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Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Scheduler.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import chisel3.experimental.dataview._ class InclusiveCacheBankScheduler(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val in = Flipped(TLBundle(params.inner.bundle)) val out = TLBundle(params.outer.bundle) // Way permissions val ways = Flipped(Vec(params.allClients, UInt(params.cache.ways.W))) val divs = Flipped(Vec(params.allClients, UInt((InclusiveCacheParameters.lfsrBits + 1).W))) // Control port val req = Flipped(Decoupled(new SinkXRequest(params))) val resp = Decoupled(new SourceXRequest(params)) }) val sourceA = Module(new SourceA(params)) val sourceB = Module(new SourceB(params)) val sourceC = Module(new SourceC(params)) val sourceD = Module(new SourceD(params)) val sourceE = Module(new SourceE(params)) val sourceX = Module(new SourceX(params)) io.out.a <> sourceA.io.a io.out.c <> sourceC.io.c io.out.e <> sourceE.io.e io.in.b <> sourceB.io.b io.in.d <> sourceD.io.d io.resp <> sourceX.io.x val sinkA = Module(new SinkA(params)) val sinkC = Module(new SinkC(params)) val sinkD = Module(new SinkD(params)) val sinkE = Module(new SinkE(params)) val sinkX = Module(new SinkX(params)) sinkA.io.a <> io.in.a sinkC.io.c <> io.in.c sinkE.io.e <> io.in.e sinkD.io.d <> io.out.d sinkX.io.x <> io.req io.out.b.ready := true.B // disconnected val directory = Module(new Directory(params)) val bankedStore = Module(new BankedStore(params)) val requests = Module(new ListBuffer(ListBufferParameters(new QueuedRequest(params), 3*params.mshrs, params.secondary, false))) val mshrs = Seq.fill(params.mshrs) { Module(new MSHR(params)) } val abc_mshrs = mshrs.init.init val bc_mshr = mshrs.init.last val c_mshr = mshrs.last val nestedwb = Wire(new NestedWriteback(params)) // Deliver messages from Sinks to MSHRs mshrs.zipWithIndex.foreach { case (m, i) => m.io.sinkc.valid := sinkC.io.resp.valid && sinkC.io.resp.bits.set === m.io.status.bits.set m.io.sinkd.valid := sinkD.io.resp.valid && sinkD.io.resp.bits.source === i.U m.io.sinke.valid := sinkE.io.resp.valid && sinkE.io.resp.bits.sink === i.U m.io.sinkc.bits := sinkC.io.resp.bits m.io.sinkd.bits := sinkD.io.resp.bits m.io.sinke.bits := sinkE.io.resp.bits m.io.nestedwb := nestedwb } // If the pre-emption BC or C MSHR have a matching set, the normal MSHR must be blocked val mshr_stall_abc = abc_mshrs.map { m => (bc_mshr.io.status.valid && m.io.status.bits.set === bc_mshr.io.status.bits.set) || ( c_mshr.io.status.valid && m.io.status.bits.set === c_mshr.io.status.bits.set) } val mshr_stall_bc = c_mshr.io.status.valid && bc_mshr.io.status.bits.set === c_mshr.io.status.bits.set val mshr_stall_c = false.B val mshr_stall = mshr_stall_abc :+ mshr_stall_bc :+ mshr_stall_c val stall_abc = (mshr_stall_abc zip abc_mshrs) map { case (s, m) => s && m.io.status.valid } if (!params.lastLevel || !params.firstLevel) params.ccover(stall_abc.reduce(_||_), "SCHEDULER_ABC_INTERLOCK", "ABC MSHR interlocked due to pre-emption") if (!params.lastLevel) params.ccover(mshr_stall_bc && bc_mshr.io.status.valid, "SCHEDULER_BC_INTERLOCK", "BC MSHR interlocked due to pre-emption") // Consider scheduling an MSHR only if all the resources it requires are available val mshr_request = Cat((mshrs zip mshr_stall).map { case (m, s) => m.io.schedule.valid && !s && (sourceA.io.req.ready || !m.io.schedule.bits.a.valid) && (sourceB.io.req.ready || !m.io.schedule.bits.b.valid) && (sourceC.io.req.ready || !m.io.schedule.bits.c.valid) && (sourceD.io.req.ready || !m.io.schedule.bits.d.valid) && (sourceE.io.req.ready || !m.io.schedule.bits.e.valid) && (sourceX.io.req.ready || !m.io.schedule.bits.x.valid) && (directory.io.write.ready || !m.io.schedule.bits.dir.valid) }.reverse) // Round-robin arbitration of MSHRs val robin_filter = RegInit(0.U(params.mshrs.W)) val robin_request = Cat(mshr_request, mshr_request & robin_filter) val mshr_selectOH2 = ~(leftOR(robin_request) << 1) & robin_request val mshr_selectOH = mshr_selectOH2(2*params.mshrs-1, params.mshrs) | mshr_selectOH2(params.mshrs-1, 0) val mshr_select = OHToUInt(mshr_selectOH) val schedule = Mux1H(mshr_selectOH, mshrs.map(_.io.schedule.bits)) val scheduleTag = Mux1H(mshr_selectOH, mshrs.map(_.io.status.bits.tag)) val scheduleSet = Mux1H(mshr_selectOH, mshrs.map(_.io.status.bits.set)) // When an MSHR wins the schedule, it has lowest priority next time when (mshr_request.orR) { robin_filter := ~rightOR(mshr_selectOH) } // Fill in which MSHR sends the request schedule.a.bits.source := mshr_select schedule.c.bits.source := Mux(schedule.c.bits.opcode(1), mshr_select, 0.U) // only set for Release[Data] not ProbeAck[Data] schedule.d.bits.sink := mshr_select sourceA.io.req.valid := schedule.a.valid sourceB.io.req.valid := schedule.b.valid sourceC.io.req.valid := schedule.c.valid sourceD.io.req.valid := schedule.d.valid sourceE.io.req.valid := schedule.e.valid sourceX.io.req.valid := schedule.x.valid sourceA.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.a.bits)) := schedule.a.bits sourceB.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.b.bits)) := schedule.b.bits sourceC.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.c.bits)) := schedule.c.bits sourceD.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.d.bits)) := schedule.d.bits sourceE.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.e.bits)) := schedule.e.bits sourceX.io.req.bits.viewAsSupertype(chiselTypeOf(schedule.x.bits)) := schedule.x.bits directory.io.write.valid := schedule.dir.valid directory.io.write.bits.viewAsSupertype(chiselTypeOf(schedule.dir.bits)) := schedule.dir.bits // Forward meta-data changes from nested transaction completion val select_c = mshr_selectOH(params.mshrs-1) val select_bc = mshr_selectOH(params.mshrs-2) nestedwb.set := Mux(select_c, c_mshr.io.status.bits.set, bc_mshr.io.status.bits.set) nestedwb.tag := Mux(select_c, c_mshr.io.status.bits.tag, bc_mshr.io.status.bits.tag) nestedwb.b_toN := select_bc && bc_mshr.io.schedule.bits.dir.valid && bc_mshr.io.schedule.bits.dir.bits.data.state === MetaData.INVALID nestedwb.b_toB := select_bc && bc_mshr.io.schedule.bits.dir.valid && bc_mshr.io.schedule.bits.dir.bits.data.state === MetaData.BRANCH nestedwb.b_clr_dirty := select_bc && bc_mshr.io.schedule.bits.dir.valid nestedwb.c_set_dirty := select_c && c_mshr.io.schedule.bits.dir.valid && c_mshr.io.schedule.bits.dir.bits.data.dirty // Pick highest priority request val request = Wire(Decoupled(new FullRequest(params))) request.valid := directory.io.ready && (sinkA.io.req.valid || sinkX.io.req.valid || sinkC.io.req.valid) request.bits := Mux(sinkC.io.req.valid, sinkC.io.req.bits, Mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits)) sinkC.io.req.ready := directory.io.ready && request.ready sinkX.io.req.ready := directory.io.ready && request.ready && !sinkC.io.req.valid sinkA.io.req.ready := directory.io.ready && request.ready && !sinkC.io.req.valid && !sinkX.io.req.valid // If no MSHR has been assigned to this set, we need to allocate one val setMatches = Cat(mshrs.map { m => m.io.status.valid && m.io.status.bits.set === request.bits.set }.reverse) val alloc = !setMatches.orR // NOTE: no matches also means no BC or C pre-emption on this set // If a same-set MSHR says that requests of this type must be blocked (for bounded time), do it val blockB = Mux1H(setMatches, mshrs.map(_.io.status.bits.blockB)) && request.bits.prio(1) val blockC = Mux1H(setMatches, mshrs.map(_.io.status.bits.blockC)) && request.bits.prio(2) // If a same-set MSHR says that requests of this type must be handled out-of-band, use special BC|C MSHR // ... these special MSHRs interlock the MSHR that said it should be pre-empted. val nestB = Mux1H(setMatches, mshrs.map(_.io.status.bits.nestB)) && request.bits.prio(1) val nestC = Mux1H(setMatches, mshrs.map(_.io.status.bits.nestC)) && request.bits.prio(2) // Prevent priority inversion; we may not queue to MSHRs beyond our level val prioFilter = Cat(request.bits.prio(2), !request.bits.prio(0), ~0.U((params.mshrs-2).W)) val lowerMatches = setMatches & prioFilter // If we match an MSHR <= our priority that neither blocks nor nests us, queue to it. val queue = lowerMatches.orR && !nestB && !nestC && !blockB && !blockC if (!params.lastLevel) { params.ccover(request.valid && blockB, "SCHEDULER_BLOCKB", "Interlock B request while resolving set conflict") params.ccover(request.valid && nestB, "SCHEDULER_NESTB", "Priority escalation from channel B") } if (!params.firstLevel) { params.ccover(request.valid && blockC, "SCHEDULER_BLOCKC", "Interlock C request while resolving set conflict") params.ccover(request.valid && nestC, "SCHEDULER_NESTC", "Priority escalation from channel C") } params.ccover(request.valid && queue, "SCHEDULER_SECONDARY", "Enqueue secondary miss") // It might happen that lowerMatches has >1 bit if the two special MSHRs are in-use // We want to Q to the highest matching priority MSHR. val lowerMatches1 = Mux(lowerMatches(params.mshrs-1), 1.U << (params.mshrs-1), Mux(lowerMatches(params.mshrs-2), 1.U << (params.mshrs-2), lowerMatches)) // If this goes to the scheduled MSHR, it may need to be bypassed // Alternatively, the MSHR may be refilled from a request queued in the ListBuffer val selected_requests = Cat(mshr_selectOH, mshr_selectOH, mshr_selectOH) & requests.io.valid val a_pop = selected_requests((0 + 1) * params.mshrs - 1, 0 * params.mshrs).orR val b_pop = selected_requests((1 + 1) * params.mshrs - 1, 1 * params.mshrs).orR val c_pop = selected_requests((2 + 1) * params.mshrs - 1, 2 * params.mshrs).orR val bypassMatches = (mshr_selectOH & lowerMatches1).orR && Mux(c_pop || request.bits.prio(2), !c_pop, Mux(b_pop || request.bits.prio(1), !b_pop, !a_pop)) val may_pop = a_pop || b_pop || c_pop val bypass = request.valid && queue && bypassMatches val will_reload = schedule.reload && (may_pop || bypass) val will_pop = schedule.reload && may_pop && !bypass params.ccover(mshr_selectOH.orR && bypass, "SCHEDULER_BYPASS", "Bypass new request directly to conflicting MSHR") params.ccover(mshr_selectOH.orR && will_reload, "SCHEDULER_RELOAD", "Back-to-back service of two requests") params.ccover(mshr_selectOH.orR && will_pop, "SCHEDULER_POP", "Service of a secondary miss") // Repeat the above logic, but without the fan-in mshrs.zipWithIndex.foreach { case (m, i) => val sel = mshr_selectOH(i) m.io.schedule.ready := sel val a_pop = requests.io.valid(params.mshrs * 0 + i) val b_pop = requests.io.valid(params.mshrs * 1 + i) val c_pop = requests.io.valid(params.mshrs * 2 + i) val bypassMatches = lowerMatches1(i) && Mux(c_pop || request.bits.prio(2), !c_pop, Mux(b_pop || request.bits.prio(1), !b_pop, !a_pop)) val may_pop = a_pop || b_pop || c_pop val bypass = request.valid && queue && bypassMatches val will_reload = m.io.schedule.bits.reload && (may_pop || bypass) m.io.allocate.bits.viewAsSupertype(chiselTypeOf(requests.io.data)) := Mux(bypass, WireInit(new QueuedRequest(params), init = request.bits), requests.io.data) m.io.allocate.bits.set := m.io.status.bits.set m.io.allocate.bits.repeat := m.io.allocate.bits.tag === m.io.status.bits.tag m.io.allocate.valid := sel && will_reload } // Determine which of the queued requests to pop (supposing will_pop) val prio_requests = ~(~requests.io.valid | (requests.io.valid >> params.mshrs) | (requests.io.valid >> 2*params.mshrs)) val pop_index = OHToUInt(Cat(mshr_selectOH, mshr_selectOH, mshr_selectOH) & prio_requests) requests.io.pop.valid := will_pop requests.io.pop.bits := pop_index // Reload from the Directory if the next MSHR operation changes tags val lb_tag_mismatch = scheduleTag =/= requests.io.data.tag val mshr_uses_directory_assuming_no_bypass = schedule.reload && may_pop && lb_tag_mismatch val mshr_uses_directory_for_lb = will_pop && lb_tag_mismatch val mshr_uses_directory = will_reload && scheduleTag =/= Mux(bypass, request.bits.tag, requests.io.data.tag) // Is there an MSHR free for this request? val mshr_validOH = Cat(mshrs.map(_.io.status.valid).reverse) val mshr_free = (~mshr_validOH & prioFilter).orR // Fanout the request to the appropriate handler (if any) val bypassQueue = schedule.reload && bypassMatches val request_alloc_cases = (alloc && !mshr_uses_directory_assuming_no_bypass && mshr_free) || (nestB && !mshr_uses_directory_assuming_no_bypass && !bc_mshr.io.status.valid && !c_mshr.io.status.valid) || (nestC && !mshr_uses_directory_assuming_no_bypass && !c_mshr.io.status.valid) request.ready := request_alloc_cases || (queue && (bypassQueue || requests.io.push.ready)) val alloc_uses_directory = request.valid && request_alloc_cases // When a request goes through, it will need to hit the Directory directory.io.read.valid := mshr_uses_directory || alloc_uses_directory directory.io.read.bits.set := Mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set) directory.io.read.bits.tag := Mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag) // Enqueue the request if not bypassed directly into an MSHR requests.io.push.valid := request.valid && queue && !bypassQueue requests.io.push.bits.data := request.bits requests.io.push.bits.index := Mux1H( request.bits.prio, Seq( OHToUInt(lowerMatches1 << params.mshrs*0), OHToUInt(lowerMatches1 << params.mshrs*1), OHToUInt(lowerMatches1 << params.mshrs*2))) val mshr_insertOH = ~(leftOR(~mshr_validOH) << 1) & ~mshr_validOH & prioFilter (mshr_insertOH.asBools zip mshrs) map { case (s, m) => when (request.valid && alloc && s && !mshr_uses_directory_assuming_no_bypass) { m.io.allocate.valid := true.B m.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits m.io.allocate.bits.repeat := false.B } } when (request.valid && nestB && !bc_mshr.io.status.valid && !c_mshr.io.status.valid && !mshr_uses_directory_assuming_no_bypass) { bc_mshr.io.allocate.valid := true.B bc_mshr.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits bc_mshr.io.allocate.bits.repeat := false.B assert (!request.bits.prio(0)) } bc_mshr.io.allocate.bits.prio(0) := false.B when (request.valid && nestC && !c_mshr.io.status.valid && !mshr_uses_directory_assuming_no_bypass) { c_mshr.io.allocate.valid := true.B c_mshr.io.allocate.bits.viewAsSupertype(chiselTypeOf(request.bits)) := request.bits c_mshr.io.allocate.bits.repeat := false.B assert (!request.bits.prio(0)) assert (!request.bits.prio(1)) } c_mshr.io.allocate.bits.prio(0) := false.B c_mshr.io.allocate.bits.prio(1) := false.B // Fanout the result of the Directory lookup val dirTarget = Mux(alloc, mshr_insertOH, Mux(nestB,(BigInt(1) << (params.mshrs-2)).U,(BigInt(1) << (params.mshrs-1)).U)) val directoryFanout = params.dirReg(RegNext(Mux(mshr_uses_directory, mshr_selectOH, Mux(alloc_uses_directory, dirTarget, 0.U)))) mshrs.zipWithIndex.foreach { case (m, i) => m.io.directory.valid := directoryFanout(i) m.io.directory.bits := directory.io.result.bits } // MSHR response meta-data fetch sinkC.io.way := Mux(bc_mshr.io.status.valid && bc_mshr.io.status.bits.set === sinkC.io.set, bc_mshr.io.status.bits.way, Mux1H(abc_mshrs.map(m => m.io.status.valid && m.io.status.bits.set === sinkC.io.set), abc_mshrs.map(_.io.status.bits.way))) sinkD.io.way := VecInit(mshrs.map(_.io.status.bits.way))(sinkD.io.source) sinkD.io.set := VecInit(mshrs.map(_.io.status.bits.set))(sinkD.io.source) // Beat buffer connections between components sinkA.io.pb_pop <> sourceD.io.pb_pop sourceD.io.pb_beat := sinkA.io.pb_beat sinkC.io.rel_pop <> sourceD.io.rel_pop sourceD.io.rel_beat := sinkC.io.rel_beat // BankedStore ports bankedStore.io.sinkC_adr <> sinkC.io.bs_adr bankedStore.io.sinkC_dat := sinkC.io.bs_dat bankedStore.io.sinkD_adr <> sinkD.io.bs_adr bankedStore.io.sinkD_dat := sinkD.io.bs_dat bankedStore.io.sourceC_adr <> sourceC.io.bs_adr bankedStore.io.sourceD_radr <> sourceD.io.bs_radr bankedStore.io.sourceD_wadr <> sourceD.io.bs_wadr bankedStore.io.sourceD_wdat := sourceD.io.bs_wdat sourceC.io.bs_dat := bankedStore.io.sourceC_dat sourceD.io.bs_rdat := bankedStore.io.sourceD_rdat // SourceD data hazard interlock sourceD.io.evict_req := sourceC.io.evict_req sourceD.io.grant_req := sinkD .io.grant_req sourceC.io.evict_safe := sourceD.io.evict_safe sinkD .io.grant_safe := sourceD.io.grant_safe private def afmt(x: AddressSet) = s"""{"base":${x.base},"mask":${x.mask}}""" private def addresses = params.inner.manager.managers.flatMap(_.address).map(afmt _).mkString(",") private def setBits = params.addressMapping.drop(params.offsetBits).take(params.setBits).mkString(",") private def tagBits = params.addressMapping.drop(params.offsetBits + params.setBits).take(params.tagBits).mkString(",") private def simple = s""""reset":"${reset.pathName}","tagBits":[${tagBits}],"setBits":[${setBits}],"blockBytes":${params.cache.blockBytes},"ways":${params.cache.ways}""" def json: String = s"""{"addresses":[${addresses}],${simple},"directory":${directory.json},"subbanks":${bankedStore.json}}""" }
module InclusiveCacheBankScheduler( // @[Scheduler.scala:27:7] input clock, // @[Scheduler.scala:27:7] input reset, // @[Scheduler.scala:27:7] output io_in_a_ready, // @[Scheduler.scala:29:14] input io_in_a_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14] input [7:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14] input [63:0] io_in_a_bits_data, // @[Scheduler.scala:29:14] input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_b_ready, // @[Scheduler.scala:29:14] output io_in_b_valid, // @[Scheduler.scala:29:14] output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14] output [5:0] io_in_b_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14] output io_in_c_ready, // @[Scheduler.scala:29:14] input io_in_c_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14] input [63:0] io_in_c_bits_data, // @[Scheduler.scala:29:14] input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_d_ready, // @[Scheduler.scala:29:14] output io_in_d_valid, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14] output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14] output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14] output io_in_d_bits_denied, // @[Scheduler.scala:29:14] output [63:0] io_in_d_bits_data, // @[Scheduler.scala:29:14] output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_e_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14] input io_out_a_ready, // @[Scheduler.scala:29:14] output io_out_a_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14] output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14] output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14] output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_out_c_ready, // @[Scheduler.scala:29:14] output io_out_c_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14] output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14] output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_d_ready, // @[Scheduler.scala:29:14] input io_out_d_valid, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14] input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_source, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14] input io_out_d_bits_denied, // @[Scheduler.scala:29:14] input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14] input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_e_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14] output io_req_ready, // @[Scheduler.scala:29:14] input io_req_valid, // @[Scheduler.scala:29:14] input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14] output io_resp_valid // @[Scheduler.scala:29:14] ); wire [10:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73] wire [10:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74] wire [10:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [10:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [10:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [10:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [10:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire request_ready; // @[Scheduler.scala:261:40] wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [9:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire [7:0] _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _requests_io_push_ready; // @[Scheduler.scala:70:24] wire [20:0] _requests_io_valid; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24] wire _requests_io_data_control; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24] wire [10:0] _requests_io_data_tag; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24] wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27] wire _directory_io_write_ready; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25] wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25] wire [7:0] _directory_io_result_bits_clients; // @[Scheduler.scala:68:25] wire [10:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25] wire [2:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25] wire _directory_io_ready; // @[Scheduler.scala:68:25] wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21] wire [10:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21] wire [9:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21] wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21] wire [2:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21] wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_source; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21] wire [9:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21] wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21] wire [9:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21] wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21] wire [10:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21] wire [10:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_set; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21] wire [9:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21] wire [63:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21] wire [63:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21] wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21] wire [10:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21] wire [9:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21] wire [63:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21] wire [7:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21] wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23] wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23] wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23] wire [9:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23] wire [9:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23] wire [2:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23] wire [63:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23] wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23] wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23] wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23] wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23] wire [9:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23] wire [9:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23] wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23] wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23] wire _mshr_request_T_22 = _mshrs_0_io_schedule_valid & ~(_mshrs_5_io_status_valid & _mshrs_0_io_status_bits_set == _mshrs_5_io_status_bits_set | _mshrs_6_io_status_valid & _mshrs_0_io_status_bits_set == _mshrs_6_io_status_bits_set) & (_sourceA_io_req_ready | ~_mshrs_0_io_schedule_bits_a_valid) & (_sourceB_io_req_ready | ~_mshrs_0_io_schedule_bits_b_valid) & (_sourceC_io_req_ready | ~_mshrs_0_io_schedule_bits_c_valid) & (_sourceD_io_req_ready | ~_mshrs_0_io_schedule_bits_d_valid) & (_sourceE_io_req_ready | ~_mshrs_0_io_schedule_bits_e_valid) & (_sourceX_io_req_ready | ~_mshrs_0_io_schedule_bits_x_valid) & (_directory_io_write_ready | ~_mshrs_0_io_schedule_bits_dir_valid); // @[Scheduler.scala:40:23, :41:23, :42:23, :43:23, :44:23, :45:23, :68:25, :71:46, :90:{30,54,86}, :91:{30,54}, :107:{25,28,31}, :108:{29,32,61}, :109:{29,32,61}, :110:{29,32,61}, :111:{29,32,61}, :112:{29,32,61}, :113:{29,32,61}, :114:{33,36}] wire _mshr_request_T_45 = _mshrs_1_io_schedule_valid & ~(_mshrs_5_io_status_valid & _mshrs_1_io_status_bits_set == _mshrs_5_io_status_bits_set | _mshrs_6_io_status_valid & _mshrs_1_io_status_bits_set == _mshrs_6_io_status_bits_set) & (_sourceA_io_req_ready | ~_mshrs_1_io_schedule_bits_a_valid) & (_sourceB_io_req_ready | ~_mshrs_1_io_schedule_bits_b_valid) & (_sourceC_io_req_ready | ~_mshrs_1_io_schedule_bits_c_valid) & (_sourceD_io_req_ready | ~_mshrs_1_io_schedule_bits_d_valid) & (_sourceE_io_req_ready | ~_mshrs_1_io_schedule_bits_e_valid) & (_sourceX_io_req_ready | ~_mshrs_1_io_schedule_bits_x_valid) & (_directory_io_write_ready | ~_mshrs_1_io_schedule_bits_dir_valid); // @[Scheduler.scala:40:23, :41:23, :42:23, :43:23, :44:23, :45:23, :68:25, :71:46, :90:{30,54,86}, :91:{30,54}, :107:{25,28,31}, :108:{29,32,61}, :109:{29,32,61}, :110:{29,32,61}, :111:{29,32,61}, :112:{29,32,61}, :113:{29,32,61}, :114:{33,36}] wire _mshr_request_T_68 = _mshrs_2_io_schedule_valid & ~(_mshrs_5_io_status_valid & _mshrs_2_io_status_bits_set == _mshrs_5_io_status_bits_set | _mshrs_6_io_status_valid & _mshrs_2_io_status_bits_set == _mshrs_6_io_status_bits_set) & (_sourceA_io_req_ready | ~_mshrs_2_io_schedule_bits_a_valid) & (_sourceB_io_req_ready | ~_mshrs_2_io_schedule_bits_b_valid) & (_sourceC_io_req_ready | ~_mshrs_2_io_schedule_bits_c_valid) & (_sourceD_io_req_ready | ~_mshrs_2_io_schedule_bits_d_valid) & (_sourceE_io_req_ready | ~_mshrs_2_io_schedule_bits_e_valid) & (_sourceX_io_req_ready | ~_mshrs_2_io_schedule_bits_x_valid) & (_directory_io_write_ready | ~_mshrs_2_io_schedule_bits_dir_valid); // @[Scheduler.scala:40:23, :41:23, :42:23, :43:23, :44:23, :45:23, :68:25, :71:46, :90:{30,54,86}, :91:{30,54}, :107:{25,28,31}, :108:{29,32,61}, :109:{29,32,61}, :110:{29,32,61}, :111:{29,32,61}, :112:{29,32,61}, :113:{29,32,61}, :114:{33,36}] wire _mshr_request_T_91 = _mshrs_3_io_schedule_valid & ~(_mshrs_5_io_status_valid & _mshrs_3_io_status_bits_set == _mshrs_5_io_status_bits_set | _mshrs_6_io_status_valid & _mshrs_3_io_status_bits_set == _mshrs_6_io_status_bits_set) & (_sourceA_io_req_ready | ~_mshrs_3_io_schedule_bits_a_valid) & (_sourceB_io_req_ready | ~_mshrs_3_io_schedule_bits_b_valid) & (_sourceC_io_req_ready | ~_mshrs_3_io_schedule_bits_c_valid) & (_sourceD_io_req_ready | ~_mshrs_3_io_schedule_bits_d_valid) & (_sourceE_io_req_ready | ~_mshrs_3_io_schedule_bits_e_valid) & (_sourceX_io_req_ready | ~_mshrs_3_io_schedule_bits_x_valid) & (_directory_io_write_ready | ~_mshrs_3_io_schedule_bits_dir_valid); // @[Scheduler.scala:40:23, :41:23, :42:23, :43:23, :44:23, :45:23, :68:25, :71:46, :90:{30,54,86}, :91:{30,54}, :107:{25,28,31}, :108:{29,32,61}, :109:{29,32,61}, :110:{29,32,61}, :111:{29,32,61}, :112:{29,32,61}, :113:{29,32,61}, :114:{33,36}] wire _mshr_request_T_114 = _mshrs_4_io_schedule_valid & ~(_mshrs_5_io_status_valid & _mshrs_4_io_status_bits_set == _mshrs_5_io_status_bits_set | _mshrs_6_io_status_valid & _mshrs_4_io_status_bits_set == _mshrs_6_io_status_bits_set) & (_sourceA_io_req_ready | ~_mshrs_4_io_schedule_bits_a_valid) & (_sourceB_io_req_ready | ~_mshrs_4_io_schedule_bits_b_valid) & (_sourceC_io_req_ready | ~_mshrs_4_io_schedule_bits_c_valid) & (_sourceD_io_req_ready | ~_mshrs_4_io_schedule_bits_d_valid) & (_sourceE_io_req_ready | ~_mshrs_4_io_schedule_bits_e_valid) & (_sourceX_io_req_ready | ~_mshrs_4_io_schedule_bits_x_valid) & (_directory_io_write_ready | ~_mshrs_4_io_schedule_bits_dir_valid); // @[Scheduler.scala:40:23, :41:23, :42:23, :43:23, :44:23, :45:23, :68:25, :71:46, :90:{30,54,86}, :91:{30,54}, :107:{25,28,31}, :108:{29,32,61}, :109:{29,32,61}, :110:{29,32,61}, :111:{29,32,61}, :112:{29,32,61}, :113:{29,32,61}, :114:{33,36}] wire _mshr_request_T_137 = _mshrs_5_io_schedule_valid & ~(_mshrs_6_io_status_valid & _mshrs_5_io_status_bits_set == _mshrs_6_io_status_bits_set) & (_sourceA_io_req_ready | ~_mshrs_5_io_schedule_bits_a_valid) & (_sourceB_io_req_ready | ~_mshrs_5_io_schedule_bits_b_valid) & (_sourceC_io_req_ready | ~_mshrs_5_io_schedule_bits_c_valid) & (_sourceD_io_req_ready | ~_mshrs_5_io_schedule_bits_d_valid) & (_sourceE_io_req_ready | ~_mshrs_5_io_schedule_bits_e_valid) & (_sourceX_io_req_ready | ~_mshrs_5_io_schedule_bits_x_valid) & (_directory_io_write_ready | ~_mshrs_5_io_schedule_bits_dir_valid); // @[Scheduler.scala:40:23, :41:23, :42:23, :43:23, :44:23, :45:23, :68:25, :71:46, :94:{28,58}, :107:{25,28,31}, :108:{29,32,61}, :109:{29,32,61}, :110:{29,32,61}, :111:{29,32,61}, :112:{29,32,61}, :113:{29,32,61}, :114:{33,36}] wire _mshr_request_T_160 = _mshrs_6_io_schedule_valid & (_sourceA_io_req_ready | ~_mshrs_6_io_schedule_bits_a_valid) & (_sourceB_io_req_ready | ~_mshrs_6_io_schedule_bits_b_valid) & (_sourceC_io_req_ready | ~_mshrs_6_io_schedule_bits_c_valid) & (_sourceD_io_req_ready | ~_mshrs_6_io_schedule_bits_d_valid) & (_sourceE_io_req_ready | ~_mshrs_6_io_schedule_bits_e_valid) & (_sourceX_io_req_ready | ~_mshrs_6_io_schedule_bits_x_valid) & (_directory_io_write_ready | ~_mshrs_6_io_schedule_bits_dir_valid); // @[Scheduler.scala:40:23, :41:23, :42:23, :43:23, :44:23, :45:23, :68:25, :71:46, :107:31, :108:{29,32,61}, :109:{29,32,61}, :110:{29,32,61}, :111:{29,32,61}, :112:{29,32,61}, :113:{29,32,61}, :114:{33,36}] wire [6:0] mshr_request = {_mshr_request_T_160, _mshr_request_T_137, _mshr_request_T_114, _mshr_request_T_91, _mshr_request_T_68, _mshr_request_T_45, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :107:{25,31}, :108:61, :109:61, :110:61, :111:61, :112:61, :113:61] reg [6:0] robin_filter; // @[Scheduler.scala:118:29] wire [6:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54] wire _GEN = _mshr_request_T_91 | _mshr_request_T_68; // @[package.scala:253:43] wire _GEN_0 = _mshr_request_T_68 | _mshr_request_T_45; // @[package.scala:253:43] wire _GEN_1 = _mshr_request_T_45 | _mshr_request_T_22; // @[package.scala:253:43] wire _GEN_2 = _mshr_request_T_22 | _robin_request_T[6]; // @[package.scala:253:43] wire [5:0] _GEN_3 = _robin_request_T[6:1] | _robin_request_T[5:0]; // @[package.scala:253:43] wire _GEN_4 = _GEN_1 | _GEN_3[5]; // @[package.scala:253:43] wire _GEN_5 = _GEN_2 | _GEN_3[4]; // @[package.scala:253:43] wire [3:0] _GEN_6 = _GEN_3[5:2] | _GEN_3[3:0]; // @[package.scala:253:43] wire _GEN_7 = _GEN_3[1] | _robin_request_T[0]; // @[package.scala:253:43] wire _GEN_8 = _GEN_6[1] | _robin_request_T[0]; // @[package.scala:253:43] wire [13:0] _GEN_9 = {~(_mshr_request_T_137 | _mshr_request_T_114 | _GEN | _GEN_4 | _GEN_8), ~(_mshr_request_T_114 | _mshr_request_T_91 | _GEN_0 | _GEN_5 | _GEN_6[0]), ~(_GEN | _GEN_1 | _GEN_6[3] | _GEN_7), ~(_GEN_0 | _GEN_2 | _GEN_6[2] | _GEN_3[0]), ~(_GEN_4 | _GEN_6[1] | _robin_request_T[0]), ~(_GEN_5 | _GEN_6[0]), ~(_GEN_6[3] | _GEN_7), ~(_GEN_6[2] | _GEN_3[0]), ~_GEN_8, ~(_GEN_6[0]), ~_GEN_7, ~(_GEN_3[0]), ~(_robin_request_T[0]), 1'h1} & {_mshr_request_T_160, _mshr_request_T_137, _mshr_request_T_114, _mshr_request_T_91, _mshr_request_T_68, _mshr_request_T_45, _mshr_request_T_22, _robin_request_T}; // @[package.scala:253:43] wire [6:0] mshr_selectOH = _GEN_9[13:7] | _GEN_9[6:0]; // @[Scheduler.scala:120:54, :121:{37,70,86}] wire [2:0] _mshr_select_T_1 = {1'h0, mshr_selectOH[6:5]} | mshr_selectOH[3:1]; // @[OneHot.scala:31:18, :32:28] wire [2:0] mshr_select = {|(mshr_selectOH[6:4]), |(_mshr_select_T_1[2:1]), _mshr_select_T_1[2] | _mshr_select_T_1[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _schedule_T_19 = mshr_selectOH[0] & _mshrs_0_io_schedule_bits_reload | mshr_selectOH[1] & _mshrs_1_io_schedule_bits_reload | mshr_selectOH[2] & _mshrs_2_io_schedule_bits_reload | mshr_selectOH[3] & _mshrs_3_io_schedule_bits_reload | mshr_selectOH[4] & _mshrs_4_io_schedule_bits_reload | mshr_selectOH[5] & _mshrs_5_io_schedule_bits_reload | mshr_selectOH[6] & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_461 = (mshr_selectOH[0] ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0) | (mshr_selectOH[1] ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0) | (mshr_selectOH[2] ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0) | (mshr_selectOH[3] ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0) | (mshr_selectOH[4] ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0) | (mshr_selectOH[5] ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0) | (mshr_selectOH[6] ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0); // @[Mux.scala:30:73, :32:36] wire [10:0] scheduleTag = (mshr_selectOH[0] ? _mshrs_0_io_status_bits_tag : 11'h0) | (mshr_selectOH[1] ? _mshrs_1_io_status_bits_tag : 11'h0) | (mshr_selectOH[2] ? _mshrs_2_io_status_bits_tag : 11'h0) | (mshr_selectOH[3] ? _mshrs_3_io_status_bits_tag : 11'h0) | (mshr_selectOH[4] ? _mshrs_4_io_status_bits_tag : 11'h0) | (mshr_selectOH[5] ? _mshrs_5_io_status_bits_tag : 11'h0) | (mshr_selectOH[6] ? _mshrs_6_io_status_bits_tag : 11'h0); // @[Mux.scala:30:73, :32:36] wire [9:0] nestedwb_set = mshr_selectOH[6] ? _mshrs_6_io_status_bits_set : _mshrs_5_io_status_bits_set; // @[Mux.scala:32:36] wire [10:0] nestedwb_tag = mshr_selectOH[6] ? _mshrs_6_io_status_bits_tag : _mshrs_5_io_status_bits_tag; // @[Mux.scala:32:36] wire nestedwb_b_clr_dirty = mshr_selectOH[5] & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:32:36] wire nestedwb_b_toN = nestedwb_b_clr_dirty & _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:{37,75,123}] wire nestedwb_b_toB = nestedwb_b_clr_dirty & _mshrs_5_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :157:37, :158:{75,123}] wire nestedwb_c_set_dirty = mshr_selectOH[6] & _mshrs_6_io_schedule_bits_dir_valid & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:32:36] wire request_valid = _directory_io_ready & (_sinkA_io_req_valid | _sinkX_io_req_valid | _sinkC_io_req_valid); // @[Scheduler.scala:54:21, :55:21, :58:21, :68:25, :164:{39,62,84}] wire request_bits_control = ~_sinkC_io_req_valid & _sinkX_io_req_valid; // @[Scheduler.scala:55:21, :58:21, :165:22] wire [2:0] request_bits_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :55:21, :58:21, :165:22, :166:22] wire [2:0] request_bits_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :55:21, :58:21, :165:22, :166:22] wire [2:0] request_bits_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :55:21, :58:21, :165:22, :166:22] wire [5:0] request_bits_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :55:21, :58:21, :165:22, :166:22] wire [10:0] request_bits_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :55:21, :58:21, :165:22, :166:22] wire [5:0] request_bits_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :55:21, :58:21, :165:22, :166:22] wire [5:0] request_bits_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :55:21, :58:21, :165:22, :166:22] wire [9:0] request_bits_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :55:21, :58:21, :165:22, :166:22] wire sinkC_io_req_ready = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :167:44, :261:40] wire _setMatches_T_1 = _mshrs_0_io_status_valid & _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :165:22, :172:{59,83}] wire _setMatches_T_3 = _mshrs_1_io_status_valid & _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :165:22, :172:{59,83}] wire _setMatches_T_5 = _mshrs_2_io_status_valid & _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :165:22, :172:{59,83}] wire _setMatches_T_7 = _mshrs_3_io_status_valid & _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :165:22, :172:{59,83}] wire _setMatches_T_9 = _mshrs_4_io_status_valid & _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :165:22, :172:{59,83}] wire _setMatches_T_11 = _mshrs_5_io_status_valid & _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :165:22, :172:{59,83}] wire _setMatches_T_13 = _mshrs_6_io_status_valid & _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :165:22, :172:{59,83}] wire [6:0] setMatches = {_setMatches_T_13, _setMatches_T_11, _setMatches_T_9, _setMatches_T_7, _setMatches_T_5, _setMatches_T_3, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}] wire alloc = setMatches == 7'h0; // @[Scheduler.scala:172:23, :173:27] wire nestC = (_setMatches_T_1 & _mshrs_0_io_status_bits_nestC | _setMatches_T_3 & _mshrs_1_io_status_bits_nestC | _setMatches_T_5 & _mshrs_2_io_status_bits_nestC | _setMatches_T_7 & _mshrs_3_io_status_bits_nestC | _setMatches_T_9 & _mshrs_4_io_status_bits_nestC | _setMatches_T_11 & _mshrs_5_io_status_bits_nestC | _setMatches_T_13 & _mshrs_6_io_status_bits_nestC) & _sinkC_io_req_valid; // @[Mux.scala:30:73] wire [6:0] prioFilter = {{2{_sinkC_io_req_valid}}, 5'h1F}; // @[Scheduler.scala:55:21, :182:23] wire [6:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33] wire queue = (|lowerMatches) & ~nestC & ~((_setMatches_T_1 & _mshrs_0_io_status_bits_blockC | _setMatches_T_3 & _mshrs_1_io_status_bits_blockC | _setMatches_T_5 & _mshrs_2_io_status_bits_blockC | _setMatches_T_7 & _mshrs_3_io_status_bits_blockC | _setMatches_T_9 & _mshrs_4_io_status_bits_blockC | _setMatches_T_11 & _mshrs_5_io_status_bits_blockC | _setMatches_T_13 & _mshrs_6_io_status_bits_blockC) & _sinkC_io_req_valid); // @[Mux.scala:30:73] wire _requests_io_push_valid_T = request_valid & queue; // @[Scheduler.scala:164:39, :185:{42,63}, :195:31] wire [6:0] lowerMatches1 = _setMatches_T_13 & _sinkC_io_req_valid ? 7'h40 : _setMatches_T_11 & _sinkC_io_req_valid ? 7'h20 : lowerMatches; // @[Scheduler.scala:55:21, :172:59, :183:33, :200:{8,21}, :201:{8,21}] wire [6:0] _a_pop_T = mshr_selectOH & _requests_io_valid[6:0]; // @[Scheduler.scala:70:24, :121:70, :206:76, :207:32] wire [6:0] _b_pop_T = mshr_selectOH & _requests_io_valid[13:7]; // @[Scheduler.scala:70:24, :121:70, :206:76, :208:32] wire [6:0] _c_pop_T = mshr_selectOH & _requests_io_valid[20:14]; // @[Scheduler.scala:70:24, :121:70, :206:76, :209:32] wire bypassMatches = (|(mshr_selectOH & lowerMatches1)) & ((|_c_pop_T) | _sinkC_io_req_valid ? ~(|_c_pop_T) : (|_b_pop_T) ? ~(|_b_pop_T) : _a_pop_T == 7'h0); // @[Scheduler.scala:55:21, :121:70, :200:8, :206:76, :207:{32,79}, :208:{32,79}, :209:{32,79}, :210:{38,55,59}, :211:{26,33,58,69,101}] wire [20:0] _GEN_10 = {_a_pop_T, _b_pop_T, _c_pop_T}; // @[Scheduler.scala:206:76, :207:{32,79}, :208:{32,79}, :209:{32,79}, :212:{23,32}] wire bypass = _requests_io_push_valid_T & bypassMatches; // @[Scheduler.scala:195:31, :210:59, :213:39] wire _mshr_uses_directory_assuming_no_bypass_T = _schedule_T_19 & (|_GEN_10); // @[Mux.scala:30:73] wire will_pop = _mshr_uses_directory_assuming_no_bypass_T & ~bypass; // @[Scheduler.scala:213:39, :215:{34,45,48}] wire bypass_1 = _requests_io_push_valid_T & lowerMatches1[0] & (_requests_io_valid[14] | _sinkC_io_req_valid ? ~(_requests_io_valid[14]) : _requests_io_valid[7] ? ~(_requests_io_valid[7]) : ~(_requests_io_valid[0])); // @[Scheduler.scala:55:21, :70:24, :195:31, :200:8, :225:34, :226:34, :227:34, :228:{38,42}, :229:{28,35,60,71,103,111}, :231:41] wire bypass_2 = _requests_io_push_valid_T & lowerMatches1[1] & (_requests_io_valid[15] | _sinkC_io_req_valid ? ~(_requests_io_valid[15]) : _requests_io_valid[8] ? ~(_requests_io_valid[8]) : ~(_requests_io_valid[1])); // @[Scheduler.scala:55:21, :70:24, :195:31, :200:8, :225:34, :226:34, :227:34, :228:{38,42}, :229:{28,35,60,71,103,111}, :231:41] wire bypass_3 = _requests_io_push_valid_T & lowerMatches1[2] & (_requests_io_valid[16] | _sinkC_io_req_valid ? ~(_requests_io_valid[16]) : _requests_io_valid[9] ? ~(_requests_io_valid[9]) : ~(_requests_io_valid[2])); // @[Scheduler.scala:55:21, :70:24, :195:31, :200:8, :225:34, :226:34, :227:34, :228:{38,42}, :229:{28,35,60,71,103,111}, :231:41] wire bypass_4 = _requests_io_push_valid_T & lowerMatches1[3] & (_requests_io_valid[17] | _sinkC_io_req_valid ? ~(_requests_io_valid[17]) : _requests_io_valid[10] ? ~(_requests_io_valid[10]) : ~(_requests_io_valid[3])); // @[Scheduler.scala:55:21, :70:24, :195:31, :200:8, :225:34, :226:34, :227:34, :228:{38,42}, :229:{28,35,60,71,103,111}, :231:41] wire bypass_5 = _requests_io_push_valid_T & lowerMatches1[4] & (_requests_io_valid[18] | _sinkC_io_req_valid ? ~(_requests_io_valid[18]) : _requests_io_valid[11] ? ~(_requests_io_valid[11]) : ~(_requests_io_valid[4])); // @[Scheduler.scala:55:21, :70:24, :195:31, :200:8, :225:34, :226:34, :227:34, :228:{38,42}, :229:{28,35,60,71,103,111}, :231:41] wire bypass_6 = _requests_io_push_valid_T & lowerMatches1[5] & (_requests_io_valid[19] | _sinkC_io_req_valid ? ~(_requests_io_valid[19]) : _requests_io_valid[12] ? ~(_requests_io_valid[12]) : ~(_requests_io_valid[5])); // @[Scheduler.scala:55:21, :70:24, :195:31, :200:8, :225:34, :226:34, :227:34, :228:{38,42}, :229:{28,35,60,71,103,111}, :231:41] wire bypass_7 = _requests_io_push_valid_T & lowerMatches1[6] & (_requests_io_valid[20] | _sinkC_io_req_valid ? ~(_requests_io_valid[20]) : _requests_io_valid[13] ? ~(_requests_io_valid[13]) : ~(_requests_io_valid[6])); // @[Scheduler.scala:55:21, :70:24, :195:31, :200:8, :225:34, :226:34, :227:34, :228:{38,42}, :229:{28,35,60,71,103,111}, :231:41] wire [19:0] _prio_requests_T = ~(_requests_io_valid[20:1]); // @[Scheduler.scala:70:24, :240:25] wire [12:0] _GEN_11 = _prio_requests_T[12:0] | _requests_io_valid[20:8]; // @[Scheduler.scala:70:24, :240:{25,44,65}] wire [19:0] prio_requests = ~{_prio_requests_T[19:13], _GEN_11[12:6], _GEN_11[5:0] | _requests_io_valid[20:15]}; // @[Scheduler.scala:70:24, :240:{23,25,44,82,103}] wire [20:0] _pop_index_T = {3{mshr_selectOH}}; // @[Scheduler.scala:121:70, :241:31] wire [4:0] pop_index_hi_1 = mshr_selectOH[6:2] & prio_requests[19:15]; // @[OneHot.scala:30:18] wire [14:0] _pop_index_T_3 = {11'h0, pop_index_hi_1[4:1]} | _pop_index_T[15:1] & prio_requests[14:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [6:0] _pop_index_T_5 = _pop_index_T_3[14:8] | _pop_index_T_3[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _pop_index_T_7 = _pop_index_T_5[6:4] | _pop_index_T_5[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73] wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:215:34, :246:37, :247:75] wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45] wire mshr_uses_directory = _schedule_T_19 & ((|_GEN_10) | bypass) & scheduleTag != (bypass ? request_bits_tag : _requests_io_data_tag); // @[Mux.scala:30:73] wire [6:0] _mshr_insertOH_T_13 = ~{_mshrs_6_io_status_valid, _mshrs_5_io_status_valid, _mshrs_4_io_status_valid, _mshrs_3_io_status_valid, _mshrs_2_io_status_valid, _mshrs_1_io_status_valid, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25, :253:20] wire bypassQueue = _schedule_T_19 & bypassMatches; // @[Mux.scala:30:73] wire request_alloc_cases = alloc & ~mshr_uses_directory_assuming_no_bypass & (|(_mshr_insertOH_T_13 & prioFilter)) | nestC & ~mshr_uses_directory_assuming_no_bypass & ~_mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :173:27, :180:70, :182:23, :247:75, :253:{20,34,48}, :258:{13,16,56}, :259:{87,112}, :260:{13,56}] assign request_ready = request_alloc_cases | queue & (bypassQueue | _requests_io_push_ready); // @[Scheduler.scala:70:24, :185:{42,63}, :256:37, :259:112, :261:{40,50,66}] wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:164:39, :259:112, :262:44] wire [2:0] _requests_io_push_bits_index_T_2 = {1'h0, lowerMatches1[6:5]} | lowerMatches1[3:1]; // @[OneHot.scala:31:18, :32:28] wire [2:0] _requests_io_push_bits_index_T_25 = {lowerMatches1[1:0], 1'h0} | lowerMatches1[5:3]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [5:0] _mshr_insertOH_T_3 = _mshr_insertOH_T_13[5:0] | {_mshr_insertOH_T_13[4:0], 1'h0}; // @[package.scala:253:{43,53}] wire [5:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | {_mshr_insertOH_T_3[3:0], 2'h0}; // @[package.scala:253:{43,53}] wire [6:0] _GEN_12 = {~(_mshr_insertOH_T_6 | {_mshr_insertOH_T_6[1:0], 4'h0}), 1'h1} & _mshr_insertOH_T_13 & prioFilter; // @[package.scala:253:{43,53}] wire _GEN_13 = request_valid & alloc; // @[Scheduler.scala:164:39, :173:27, :280:25] wire _GEN_14 = _GEN_13 & _GEN_12[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:{53,69}, :279:18, :280:{25,34,39}] wire _GEN_15 = _GEN_14 | bypass_1; // @[Scheduler.scala:228:42, :231:41, :233:72, :280:{34,39,83}, :282:70] assign mshrs_0_io_allocate_bits_tag = _GEN_15 ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :165:22, :233:72, :280:83, :282:70] wire _GEN_16 = _GEN_13 & _GEN_12[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:{53,69}, :279:18, :280:{25,34,39}] wire _GEN_17 = _GEN_16 | bypass_2; // @[Scheduler.scala:228:42, :231:41, :233:72, :280:{34,39,83}, :282:70] assign mshrs_1_io_allocate_bits_tag = _GEN_17 ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :165:22, :233:72, :280:83, :282:70] wire _GEN_18 = _GEN_13 & _GEN_12[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:{53,69}, :279:18, :280:{25,34,39}] wire _GEN_19 = _GEN_18 | bypass_3; // @[Scheduler.scala:228:42, :231:41, :233:72, :280:{34,39,83}, :282:70] assign mshrs_2_io_allocate_bits_tag = _GEN_19 ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :165:22, :233:72, :280:83, :282:70] wire _GEN_20 = _GEN_13 & _GEN_12[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:{53,69}, :279:18, :280:{25,34,39}] wire _GEN_21 = _GEN_20 | bypass_4; // @[Scheduler.scala:228:42, :231:41, :233:72, :280:{34,39,83}, :282:70] assign mshrs_3_io_allocate_bits_tag = _GEN_21 ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :165:22, :233:72, :280:83, :282:70] wire _GEN_22 = _GEN_13 & _GEN_12[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:{53,69}, :279:18, :280:{25,34,39}] wire _GEN_23 = _GEN_22 | bypass_5; // @[Scheduler.scala:228:42, :231:41, :233:72, :280:{34,39,83}, :282:70] assign mshrs_4_io_allocate_bits_tag = _GEN_23 ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :165:22, :233:72, :280:83, :282:70] wire _GEN_24 = _GEN_13 & _GEN_12[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:{53,69}, :279:18, :280:{25,34,39}] wire _GEN_25 = _GEN_24 | bypass_6; // @[Scheduler.scala:228:42, :231:41, :233:72, :280:{34,39,83}, :282:70, :287:131, :289:74] assign mshrs_5_io_allocate_bits_tag = _GEN_25 ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :165:22, :233:72, :280:83, :282:70, :287:131, :289:74] wire _GEN_26 = request_valid & nestC & ~_mshrs_6_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :164:39, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}] wire _GEN_27 = _GEN_26 | _GEN_13 & _GEN_12[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:{53,69}, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30] wire _GEN_28 = _GEN_27 | bypass_7; // @[Scheduler.scala:228:42, :231:41, :233:72, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73] assign mshrs_6_io_allocate_bits_tag = _GEN_28 ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :165:22, :233:72, :280:83, :282:70, :295:103, :297:73]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_77 | _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31] wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31] wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31] wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31] wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31] wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31] wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31] wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31] wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31] wire _source_ok_T_128 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_155 | _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46] wire _T_1759 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1759; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1759; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1827 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1827; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1827; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1827; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1692 = _T_1759 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1692 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1692 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1692 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1692 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1692 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1738 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1738 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1707 = _T_1827 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1707 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1707 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1707 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1803 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1803 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1785 = _T_1827 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1785 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1785 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1785 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }
module dataMems_449( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File tage.scala: package boom.v4.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f2_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)*l, histLength)-1, i*l) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val us = SyncReadMem(nRows, Vec(bankWidth*2, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) us.suggestName(s"tage_u_${histLength}") table.suggestName(s"tage_table_${histLength}") val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry)) val s2_req_rus = Wire(Vec(bankWidth*2, Bool())) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f2_resp(w).valid := s2_req_rhits(w) io.f2_resp(w).bits.u := Cat(s2_req_rus(w*2+1), s2_req_rus(w*2)) io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val clear_u_mask = VecInit((0 until bankWidth*2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) val wen = WireInit(doing_reset || io.update_mask.reduce(_||_)) val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid) when (RegNext(wen) && singlePorted.B) { s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry)) } .otherwise { s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry))) } when (wen) { val widx = Mux(doing_reset, reset_idx, update_idx) val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))) val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt) table.write(widx, wdata, wmask.asBools) } val update_u_mask = VecInit((0 until bankWidth*2) map {i => io.update_u_mask(i / 2)}) val update_u_wen = WireInit(doing_reset || doing_clear_u || update_u_mask.reduce(_||_)) val u_rdata = if (singlePorted) { us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid) } else { us.read(s1_hashed_idx, io.f1_req_valid) } s2_req_rus := u_rdata when (update_u_wen) { val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx)) val wdata = Mux(doing_reset || doing_clear_u, VecInit(0.U((bankWidth*2).W).asBools), VecInit(io.update_u.asUInt.asBools)) val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt)) us.write(widx, wdata, wmask.asBools) } val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_||_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag } when (io.update_mask.reduce(_||_)) { when (wrbypass_hits.reduce(_||_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048, singlePorted: Boolean = false ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc)) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f2_resps = VecInit(tables.map(_.io.f2_resp)) val f3_resps = RegNext(f2_resps) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var s2_provided = false.B var s2_provider = 0.U var s2_alt_provided = false.B var s2_alt_provider = 0.U for (i <- 0 until tageNTables) { val hit = f2_resps(i)(w).valid s2_alt_provided = s2_alt_provided || (s2_provided && hit) s2_provided = s2_provided || hit s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider) s2_provider = Mux(hit, i.U, s2_provider) } val s3_provided = RegNext(s2_provided) val s3_provider = RegNext(s2_provider) val s3_alt_provided = RegNext(s2_alt_provided) val s3_alt_provider = RegNext(s2_alt_provider) val prov = RegNext(f2_resps(s2_provider)(w).bits) val alt = RegNext(f2_resps(s2_alt_provider)(w).bits) io.resp.f3(w).taken := Mux(s3_provided, Mux(prov.ctr === 3.U || prov.ctr === 4.U, Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken), prov.ctr(2)), io.resp_in(0).f3(w).taken ) f3_meta.provider(w).valid := s3_provided f3_meta.provider(w).bits := s3_provider f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken f3_meta.provider_u(w) := prov.u f3_meta.provider_ctr(w) := prov.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }
module tage_u_4( // @[tage.scala:89:27] input [6:0] R0_addr, input R0_en, input R0_clk, output [7:0] R0_data, input [6:0] W0_addr, input W0_en, input W0_clk, input [7:0] W0_data, input [7:0] W0_mask ); tage_u_2_ext tage_u_2_ext ( // @[tage.scala:89:27] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data), .W0_mask (W0_mask) ); // @[tage.scala:89:27] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_445( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_189 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_102( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_358 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_16( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [271:0] c_sizes_set = 272'h0; // @[Monitor.scala:741:34] wire [135:0] c_opcodes_set = 136'h0; // @[Monitor.scala:740:34] wire [33:0] c_set = 34'h0; // @[Monitor.scala:738:34] wire [33:0] c_set_wo_ready = 34'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_31 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_33 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_39 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_45 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_51 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_46 = _source_ok_T_45 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_52 = _source_ok_T_51 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire _source_ok_T_57 = io_in_d_bits_source_0 == 6'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire _source_ok_T_58 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_63 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _T_1411 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1411; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1411; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1484 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1484; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1484; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1484; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [33:0] inflight; // @[Monitor.scala:614:27] reg [135:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [271:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [33:0] a_set; // @[Monitor.scala:626:34] wire [33:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [135:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [271:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [135:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [135:0] _a_opcode_lookup_T_6 = {132'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [135:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [271:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [271:0] _a_size_lookup_T_6 = {264'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [271:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[271:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1337 = _T_1411 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1337 ? _a_set_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1337 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1337 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1337 ? _a_opcodes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1337 ? _a_sizes_set_T_1[271:0] : 272'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [33:0] d_clr; // @[Monitor.scala:664:34] wire [33:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [135:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [271:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1383 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1383 & ~d_release_ack ? _d_clr_wo_ready_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1352 = _T_1484 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1352 ? _d_clr_T[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1352 ? _d_opcodes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1352 ? _d_sizes_clr_T_5[271:0] : 272'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [33:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [33:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [33:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [135:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [135:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [135:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [271:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [271:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [271:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [33:0] inflight_1; // @[Monitor.scala:726:35] wire [33:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [135:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [135:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [271:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [271:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [135:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [135:0] _c_opcode_lookup_T_6 = {132'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [135:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[135:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [271:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [271:0] _c_size_lookup_T_6 = {264'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [271:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[271:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [33:0] d_clr_1; // @[Monitor.scala:774:34] wire [33:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [135:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [271:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1455 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1455 & d_release_ack_1 ? _d_clr_wo_ready_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35] wire _T_1437 = _T_1484 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1437 ? _d_clr_T_1[33:0] : 34'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1437 ? _d_opcodes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1437 ? _d_sizes_clr_T_11[271:0] : 272'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [33:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [33:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [135:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [135:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [271:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [271:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_58( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_34( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_34 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }
module MulAddRecFNToRaw_postMul_e8_s24_22( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_10( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [7:0] _roundMask_T_5 = 8'hF; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_4 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_10 = 8'hF0; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_13 = 6'hF; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_14 = 8'h3C; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_15 = 8'h33; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_20 = 8'hCC; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_23 = 7'h33; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_24 = 8'h66; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_25 = 8'h55; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_30 = 8'hAA; // @[primitives.scala:77:20] wire [5:0] _expOut_T_4 = 6'h37; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [13:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49] wire [16:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[13]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [5:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [5:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [9:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [9:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [5:0] _roundMask_T = io_in_sExp_0[5:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [5:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1); // @[primitives.scala:52:21, :76:56] wire [11:0] _roundMask_T_2 = roundMask_shift[18:7]; // @[primitives.scala:76:56, :78:22] wire [7:0] _roundMask_T_3 = _roundMask_T_2[7:0]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_6 = _roundMask_T_3[7:4]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_7 = {4'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_8 = _roundMask_T_3[3:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_9 = {_roundMask_T_8, 4'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_11 = _roundMask_T_9 & 8'hF0; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_16 = _roundMask_T_12[7:2]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_17 = {2'h0, _roundMask_T_16 & 6'h33}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_18 = _roundMask_T_12[5:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_19 = {_roundMask_T_18, 2'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_21 = _roundMask_T_19 & 8'hCC; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_26 = _roundMask_T_22[7:1]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_27 = {1'h0, _roundMask_T_26 & 7'h55}; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_28 = _roundMask_T_22[6:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_29 = {_roundMask_T_28, 1'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_31 = _roundMask_T_29 & 8'hAA; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_33 = _roundMask_T_2[11:8]; // @[primitives.scala:77:20, :78:22] wire [1:0] _roundMask_T_34 = _roundMask_T_33[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_35 = _roundMask_T_34[0]; // @[primitives.scala:77:20] wire _roundMask_T_36 = _roundMask_T_34[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_37 = {_roundMask_T_35, _roundMask_T_36}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_38 = _roundMask_T_33[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_39 = _roundMask_T_38[0]; // @[primitives.scala:77:20] wire _roundMask_T_40 = _roundMask_T_38[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_41 = {_roundMask_T_39, _roundMask_T_40}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_42 = {_roundMask_T_37, _roundMask_T_41}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_43 = {_roundMask_T_32, _roundMask_T_42}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_44 = {_roundMask_T_43[11:1], _roundMask_T_43[0] | doShiftSigDown1}; // @[primitives.scala:77:20] wire [13:0] roundMask = {_roundMask_T_44, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [14:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [13:0] shiftedRoundMask = _shiftedRoundMask_T[14:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [13:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [13:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [13:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [13:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [13:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [11:0] _roundedSig_T_1 = _roundedSig_T[13:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [12:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 13'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [12:0] _roundedSig_T_6 = roundMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [12:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [12:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [12:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [13:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [13:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [11:0] _roundedSig_T_12 = _roundedSig_T_11[13:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [12:0] _roundedSig_T_14 = roundPosMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [12:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [12:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [12:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[12:11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [7:0] sRoundedExp = {io_in_sExp_0[6], io_in_sExp_0} + {{5{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[5:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [9:0] _common_fractOut_T = roundedSig[10:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [9:0] _common_fractOut_T_1 = roundedSig[9:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[7:4]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 8'sh8; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[12]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[6:5]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [5:0] _expOut_T_1 = _expOut_T ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [5:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [5:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [5:0] _expOut_T_5 = pegMinNonzeroMagOut ? 6'h37 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [5:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [5:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [5:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 4'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [5:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [5:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [5:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [5:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [5:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [5:0] _expOut_T_14 = {2'h0, pegMinNonzeroMagOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [5:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [5:0] _expOut_T_16 = pegMaxFiniteMagOut ? 6'h2F : 6'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [5:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [5:0] _expOut_T_18 = notNaN_isInfOut ? 6'h30 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [5:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [5:0] _expOut_T_20 = isNaNOut ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [5:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [9:0] _fractOut_T_2 = {isNaNOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [9:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [9:0] _fractOut_T_4 = {10{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [9:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [6:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_975 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_975; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_975; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1043 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1043; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_908 = _T_975 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_908 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_908 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_908 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_908 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_908 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_954 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_954 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_923 = _T_1043 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_923 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_923 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_923 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1019 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1019 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1001 = _T_1043 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1001 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1001 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1001 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_191( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File tage.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f3_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)*l, histLength)-1, i*l) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry))) val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f3_resp(w).valid := RegNext(s2_req_rhits(w)) io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w))) io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr) } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) table.write( Mux(doing_reset, reset_idx , update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))), Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools ) val update_hi_wdata = Wire(Vec(bankWidth, Bool())) hi_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)), Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata), Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val update_lo_wdata = Wire(Vec(bankWidth, Bool())) lo_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)), Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata), Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_||_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag update_hi_wdata(w) := io.update_u(w)(1) update_lo_wdata(w) := io.update_u(w)(0) } when (io.update_mask.reduce(_||_)) { when (wrbypass_hits.reduce(_||_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048 ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(io.f0_pc) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f3_resps = VecInit(tables.map(_.io.f3_resp)) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var altpred = io.resp_in(0).f3(w).taken val final_altpred = WireInit(io.resp_in(0).f3(w).taken) var provided = false.B var provider = 0.U io.resp.f3(w).taken := io.resp_in(0).f3(w).taken for (i <- 0 until tageNTables) { val hit = f3_resps(i)(w).valid val ctr = f3_resps(i)(w).bits.ctr when (hit) { io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2)) final_altpred := altpred } provided = provided || hit provider = Mux(hit, i.U, provider) altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred) } f3_meta.provider(w).valid := provided f3_meta.provider(w).bits := provider f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }
module TageTable_16( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f3_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14] output io_f3_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14] output io_f3_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14] output io_f3_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8] wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8] wire [12:0] table_MPORT_data_3; // @[tage.scala:123:8] wire [12:0] table_MPORT_data_2; // @[tage.scala:123:8] wire [12:0] table_MPORT_data_1; // @[tage.scala:123:8] wire [12:0] table_MPORT_data_0; // @[tage.scala:123:8] wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87] wire [51:0] _table_R0_data; // @[tage.scala:91:27] wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27] wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26] wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [6:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2 = io_f1_req_ghist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3 = io_f1_req_ghist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [3:0] idx_history_hist_chunks_4 = io_f1_req_ghist_0[31:28]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_1 = _idx_history_T ^ idx_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_2 = _idx_history_T_1 ^ idx_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history = {_idx_history_T_2[6:4], _idx_history_T_2[3:0] ^ idx_history_hist_chunks_4}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:162:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[10:4] ^ idx_history}; // @[frontend.scala:162:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40] wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32] wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32] wire [8:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2 = io_f1_req_ghist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [4:0] tag_history_hist_chunks_3 = io_f1_req_ghist_0[31:27]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_1 = _tag_history_T ^ tag_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history = {_tag_history_T_1[8:5], _tag_history_T_1[4:0] ^ tag_history_hist_chunks_3}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_1 = {_tag_T[28:9], _tag_T[8:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] s1_tag = _tag_T_1[8:0]; // @[tage.scala:62:{50,64}] wire [12:0] _s2_req_rtage_WIRE_2 = _table_R0_data[12:0]; // @[tage.scala:91:27, :97:87] wire [12:0] _s2_req_rtage_WIRE_4 = _table_R0_data[25:13]; // @[tage.scala:91:27, :97:87] wire [12:0] _s2_req_rtage_WIRE_6 = _table_R0_data[38:26]; // @[tage.scala:91:27, :97:87] wire [12:0] _s2_req_rtage_WIRE_8 = _table_R0_data[51:39]; // @[tage.scala:91:27, :97:87] reg [8:0] s2_tag; // @[tage.scala:95:29] wire _s2_req_rtage_T_2; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_1; // @[tage.scala:97:87] wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87] assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87] assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87] wire _s2_req_rtage_T_5; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_4; // @[tage.scala:97:87] wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87] assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87] assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87] wire _s2_req_rtage_T_8; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_7; // @[tage.scala:97:87] wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87] assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87] assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87] wire _s2_req_rtage_T_11; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_10; // @[tage.scala:97:87] wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87] assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87] assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54] wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54] wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}] wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}] wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}] wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [6:0] idx_history_hist_chunks_0_1 = io_update_hist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1_1 = io_update_hist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2_1 = io_update_hist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3_1 = io_update_hist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [3:0] idx_history_hist_chunks_4_1 = io_update_hist_0[31:28]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T_3 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_4 = _idx_history_T_3 ^ idx_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_5 = _idx_history_T_4 ^ idx_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history_1 = {_idx_history_T_5[6:4], _idx_history_T_5[3:0] ^ idx_history_hist_chunks_4_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:162:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[10:4] ^ idx_history_1}; // @[frontend.scala:162:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [8:0] tag_history_hist_chunks_0_1 = io_update_hist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1_1 = io_update_hist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2_1 = io_update_hist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [4:0] tag_history_hist_chunks_3_1 = io_update_hist_0[31:27]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T_2 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_3 = _tag_history_T_2 ^ tag_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history_1 = {_tag_history_T_3[8:5], _tag_history_T_3[4:0] ^ tag_history_hist_chunks_3_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_3 = {_tag_T_2[28:9], _tag_T_2[8:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] update_tag = _tag_T_3[8:0]; // @[tage.scala:62:{50,64}] wire [8:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [8:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [8:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [8:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26] wire [9:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102] wire [9:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102] wire [9:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102] wire [9:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102] assign table_MPORT_data_0 = doing_reset ? 13'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_1 = doing_reset ? 13'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_2 = doing_reset ? 13'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_3 = doing_reset ? 13'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90] wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90] wire _update_hi_wdata_0_T; // @[tage.scala:166:44] wire _update_hi_wdata_1_T; // @[tage.scala:166:44] wire _update_hi_wdata_2_T; // @[tage.scala:166:44] wire _update_hi_wdata_3_T; // @[tage.scala:166:44] wire update_hi_wdata_0; // @[tage.scala:127:29] wire update_hi_wdata_1; // @[tage.scala:127:29] wire update_hi_wdata_2; // @[tage.scala:127:29] wire update_hi_wdata_3; // @[tage.scala:127:29] wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21] assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}] wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80] wire [1:0] lo_1; // @[tage.scala:131:80] assign lo_1 = _GEN; // @[tage.scala:131:80] wire [1:0] lo_2; // @[tage.scala:138:80] assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80] wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80] wire [1:0] hi_5; // @[tage.scala:131:80] assign hi_5 = _GEN_0; // @[tage.scala:131:80] wire [1:0] hi_6; // @[tage.scala:138:80] assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80] wire _update_lo_wdata_0_T; // @[tage.scala:167:44] wire _update_lo_wdata_1_T; // @[tage.scala:167:44] wire _update_lo_wdata_2_T; // @[tage.scala:167:44] wire _update_lo_wdata_3_T; // @[tage.scala:167:44] wire update_lo_wdata_0; // @[tage.scala:134:29] wire update_lo_wdata_1; // @[tage.scala:134:29] wire update_lo_wdata_2; // @[tage.scala:134:29] wire update_lo_wdata_3; // @[tage.scala:134:29] wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21] assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}] reg [8:0] wrbypass_tags_0; // @[tage.scala:141:29] reg [8:0] wrbypass_tags_1; // @[tage.scala:141:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29] reg [2:0] wrbypass_0_0; // @[tage.scala:143:29] reg [2:0] wrbypass_0_1; // @[tage.scala:143:29] reg [2:0] wrbypass_0_2; // @[tage.scala:143:29] reg [2:0] wrbypass_0_3; // @[tage.scala:143:29] reg [2:0] wrbypass_1_0; // @[tage.scala:143:29] reg [2:0] wrbypass_1_1; // @[tage.scala:143:29] reg [2:0] wrbypass_1_2; // @[tage.scala:143:29] reg [2:0] wrbypass_1_3; // @[tage.scala:143:29] reg wrbypass_enq_idx; // @[tage.scala:144:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}] wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39] end else // @[tage.scala:144:33, :170:38, :171:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29] io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38] io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38] io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38] io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38] io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38] if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29] if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29] if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] end else begin // @[tage.scala:143:29, :170:38, :171:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end always @(posedge) hi_us_15 hi_us ( // @[tage.scala:89:27] .R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_hi_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}] .W0_clk (clock), .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8] .W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}] ); // @[tage.scala:89:27] lo_us_15 lo_us ( // @[tage.scala:90:27] .R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_lo_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}] .W0_clk (clock), .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8] .W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}] ); // @[tage.scala:90:27] table_15 table_0 ( // @[tage.scala:91:27] .R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_table_R0_data), .W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8] .W0_clk (clock), .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8] .W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}] ); // @[tage.scala:91:27] assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File HellaCacheArbiter.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat,log2Up} import org.chipsalliance.cde.config.Parameters class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module { val io = IO(new Bundle { val requestor = Flipped(Vec(n, new HellaCacheIO)) val mem = new HellaCacheIO }) if (n == 1) { io.mem <> io.requestor.head } else { val s1_id = Reg(UInt()) val s2_id = RegNext(s1_id) io.mem.keep_clock_enabled := io.requestor.map(_.keep_clock_enabled).reduce(_||_) io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_) io.requestor(0).req.ready := io.mem.req.ready for (i <- 1 until n) io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid for (i <- n-1 to 0 by -1) { val req = io.requestor(i).req def connect_s0() = { io.mem.req.bits := req.bits io.mem.req.bits.tag := Cat(req.bits.tag, i.U(log2Up(n).W)) s1_id := i.U } def connect_s1() = { io.mem.s1_kill := io.requestor(i).s1_kill io.mem.s1_data := io.requestor(i).s1_data } def connect_s2() = { io.mem.s2_kill := io.requestor(i).s2_kill } if (i == n-1) { connect_s0() connect_s1() connect_s2() } else { when (req.valid) { connect_s0() } when (s1_id === i.U) { connect_s1() } when (s2_id === i.U) { connect_s2() } } } io.mem.uncached_resp.foreach(_.ready := false.B) for (i <- 0 until n) { val resp = io.requestor(i).resp val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === i.U resp.valid := io.mem.resp.valid && tag_hit io.requestor(i).s2_xcpt := io.mem.s2_xcpt io.requestor(i).s2_gpa := io.mem.s2_gpa io.requestor(i).s2_gpa_is_pte := io.mem.s2_gpa_is_pte io.requestor(i).ordered := io.mem.ordered io.requestor(i).store_pending := io.mem.store_pending io.requestor(i).perf := io.mem.perf io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === i.U io.requestor(i).s2_nack_cause_raw := io.mem.s2_nack_cause_raw io.requestor(i).s2_uncached := io.mem.s2_uncached io.requestor(i).s2_paddr := io.mem.s2_paddr io.requestor(i).clock_enabled := io.mem.clock_enabled resp.bits := io.mem.resp.bits resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n) io.requestor(i).replay_next := io.mem.replay_next io.requestor(i).uncached_resp.map { uncached_resp => val uncached_tag_hit = io.mem.uncached_resp.get.bits.tag(log2Up(n)-1,0) === i.U uncached_resp.valid := io.mem.uncached_resp.get.valid && uncached_tag_hit when (uncached_resp.ready && uncached_tag_hit) { io.mem.uncached_resp.get.ready := true.B } uncached_resp.bits := io.mem.uncached_resp.get.bits uncached_resp.bits.tag := io.mem.uncached_resp.get.bits.tag >> log2Up(n) } } } }
module HellaCacheArbiter( // @[HellaCacheArbiter.scala:10:7] input clock, // @[HellaCacheArbiter.scala:10:7] input reset, // @[HellaCacheArbiter.scala:10:7] output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_0_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_0_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_0_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_0_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_0_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_0_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_1_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_1_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_requestor_1_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_1_req_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_1_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_s1_kill, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_1_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_1_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_1_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_1_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_1_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_1_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_1_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_1_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_requestor_1_keep_clock_enabled, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_req_ready, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_req_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_requestor_2_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_requestor_2_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_requestor_2_req_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_requestor_2_s1_kill, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_requestor_2_s1_data_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_requestor_2_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_nack, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_uncached, // @[HellaCacheArbiter.scala:12:14] output [31:0] io_requestor_2_s2_paddr, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_2_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_2_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_requestor_2_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_2_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_requestor_2_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_requestor_2_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_requestor_2_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_replay_next, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_requestor_2_s2_gpa, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_ordered, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_store_pending, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_acquire, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_grant, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_blocked, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] output io_requestor_2_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14] output [39:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_req_bits_tag, // @[HellaCacheArbiter.scala:12:14] output [4:0] io_mem_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_size, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_signed, // @[HellaCacheArbiter.scala:12:14] output [1:0] io_mem_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_phys, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14] output io_mem_req_bits_no_xcpt, // @[HellaCacheArbiter.scala:12:14] output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14] output [63:0] io_mem_s1_data_data, // @[HellaCacheArbiter.scala:12:14] output [7:0] io_mem_s1_data_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_uncached, // @[HellaCacheArbiter.scala:12:14] input [31:0] io_mem_s2_paddr, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14] input [4:0] io_mem_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_size, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14] input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14] input [7:0] io_mem_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14] input io_mem_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14] input [63:0] io_mem_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14] input io_mem_replay_next, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14] input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14] input [39:0] io_mem_s2_gpa, // @[HellaCacheArbiter.scala:12:14] input io_mem_ordered, // @[HellaCacheArbiter.scala:12:14] input io_mem_store_pending, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_acquire, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_grant, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_blocked, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14] input io_mem_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14] output io_mem_keep_clock_enabled // @[HellaCacheArbiter.scala:12:14] ); wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_req_bits_tag_0 = io_requestor_1_req_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_req_bits_cmd_0 = io_requestor_1_req_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_size_0 = io_requestor_1_req_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_signed_0 = io_requestor_1_req_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_req_bits_dprv_0 = io_requestor_1_req_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_dv_0 = io_requestor_1_req_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_resp_0 = io_requestor_1_req_bits_no_resp; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s1_kill_0 = io_requestor_1_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_keep_clock_enabled_0 = io_requestor_1_keep_clock_enabled; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_valid_0 = io_requestor_2_req_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_2_req_bits_addr_0 = io_requestor_2_req_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_2_req_bits_cmd_0 = io_requestor_2_req_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_req_bits_size_0 = io_requestor_2_req_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s1_kill_0 = io_requestor_2_s1_kill; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_s1_data_data_0 = io_requestor_2_s1_data_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_s1_data_mask_0 = io_requestor_2_s1_data_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala:10:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[HellaCacheArbiter.scala:10:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[HellaCacheArbiter.scala:10:7] wire io_mem_ordered_0 = io_mem_ordered; // @[HellaCacheArbiter.scala:10:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[HellaCacheArbiter.scala:10:7] wire [9:0] _io_mem_req_bits_tag_T = 10'h2; // @[HellaCacheArbiter.scala:34:35] wire [9:0] _io_mem_req_bits_tag_T_2 = 10'h0; // @[HellaCacheArbiter.scala:34:35] wire [1:0] io_requestor_2_req_bits_dprv = 2'h0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_requestor_2_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] wire [1:0] io_requestor_0_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :51:21] wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7, :12:14] wire [7:0] io_requestor_0_req_bits_tag = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:29, :50:26] wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:29, :50:26] wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:29, :50:26] wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:29, :50:26] wire [7:0] io_requestor_1_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:29, :50:26] wire [7:0] io_requestor_2_req_bits_tag = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:29, :50:26] wire [7:0] io_requestor_2_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:29, :50:26] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:29, :50:26] wire io_requestor_0_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_no_xcpt = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_dv = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_perf_release = 1'h0; // @[HellaCacheArbiter.scala:10:7] wire _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire _io_mem_keep_clock_enabled_T = io_requestor_1_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7, :23:81] wire _io_requestor_2_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64] wire _io_requestor_2_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49] wire _io_requestor_2_resp_valid_T; // @[HellaCacheArbiter.scala:61:39] wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_req_valid_T_1; // @[HellaCacheArbiter.scala:25:63] wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [31:0] io_requestor_2_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_2_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_requestor_2_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_requestor_2_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_requestor_2_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_requestor_2_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] wire _io_mem_keep_clock_enabled_T_1; // @[HellaCacheArbiter.scala:23:81] wire [7:0] io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_req_ready_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_requestor_2_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] wire io_requestor_2_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] wire [39:0] io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] wire [4:0] io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] wire [1:0] io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_bits_no_xcpt_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] wire [63:0] io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] wire [7:0] io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] wire io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] reg [1:0] s1_id; // @[HellaCacheArbiter.scala:20:20] reg [1:0] s2_id; // @[HellaCacheArbiter.scala:21:24] assign _io_mem_keep_clock_enabled_T_1 = _io_mem_keep_clock_enabled_T; // @[HellaCacheArbiter.scala:23:81] assign io_mem_keep_clock_enabled_0 = _io_mem_keep_clock_enabled_T_1; // @[HellaCacheArbiter.scala:10:7, :23:81] wire _io_mem_req_valid_T = io_requestor_0_req_valid_0 | io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign _io_mem_req_valid_T_1 = _io_mem_req_valid_T | io_requestor_2_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63] assign io_mem_req_valid_0 = _io_mem_req_valid_T_1; // @[HellaCacheArbiter.scala:10:7, :25:63] wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] wire _io_requestor_2_req_ready_T = ~io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67] assign _io_requestor_2_req_ready_T_1 = io_requestor_1_req_ready_0 & _io_requestor_2_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}] assign io_requestor_2_req_ready_0 = _io_requestor_2_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64] wire [9:0] _io_mem_req_bits_tag_T_1 = {io_requestor_1_req_bits_tag_0, 2'h1}; // @[HellaCacheArbiter.scala:10:7, :34:35, :51:21] wire _T = s1_id == 2'h1; // @[HellaCacheArbiter.scala:20:20, :51:21] wire _io_requestor_1_s2_nack_T = s2_id == 2'h1; // @[HellaCacheArbiter.scala:21:24, :51:21, :52:21, :68:58] assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_valid_0 ? io_requestor_1_req_bits_addr_0 : io_requestor_2_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_cmd_0 = io_requestor_0_req_valid_0 ? 5'h0 : io_requestor_1_req_valid_0 ? io_requestor_1_req_bits_cmd_0 : io_requestor_2_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_size_0 = io_requestor_0_req_valid_0 ? 2'h3 : io_requestor_1_req_valid_0 ? io_requestor_1_req_bits_size_0 : io_requestor_2_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26] assign io_mem_req_bits_signed_0 = ~io_requestor_0_req_valid_0 & io_requestor_1_req_valid_0 & io_requestor_1_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_dprv_0 = io_requestor_0_req_valid_0 ? 2'h1 : io_requestor_1_req_valid_0 ? io_requestor_1_req_bits_dprv_0 : 2'h0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26, :51:21] assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_dv_0 : io_requestor_1_req_valid_0 & io_requestor_1_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_phys_0 = io_requestor_0_req_valid_0 | ~io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67, :33:25, :50:26] assign io_mem_req_bits_no_resp_0 = ~io_requestor_0_req_valid_0 & io_requestor_1_req_valid_0 & io_requestor_1_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26] assign io_mem_req_bits_no_xcpt_0 = ~io_requestor_0_req_valid_0 & ~io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67, :33:25, :50:26] assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 8'h0 : io_requestor_1_req_valid_0 ? _io_mem_req_bits_tag_T_1[7:0] : 8'h2; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:{29,35}, :50:26] wire _T_2 = s1_id == 2'h0; // @[HellaCacheArbiter.scala:20:20, :51:21] assign io_mem_s1_kill_0 = _T_2 ? io_requestor_0_s1_kill_0 : _T ? io_requestor_1_s1_kill_0 : io_requestor_2_s1_kill_0; // @[HellaCacheArbiter.scala:10:7, :38:24, :51:{21,30}] assign io_mem_s1_data_data_0 = _T_2 ? 64'h0 : _T ? io_requestor_1_s1_data_data_0 : io_requestor_2_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :39:24, :50:26, :51:{21,30}] assign io_mem_s1_data_mask_0 = _T_2 | _T ? 8'h0 : io_requestor_2_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:29, :39:24, :50:26, :51:{21,30}] wire _io_requestor_0_s2_nack_T = s2_id == 2'h0; // @[HellaCacheArbiter.scala:21:24, :52:21, :68:58] wire [1:0] _tag_hit_T = io_mem_resp_bits_tag_0[1:0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire [1:0] _tag_hit_T_1 = io_mem_resp_bits_tag_0[1:0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire [1:0] _tag_hit_T_2 = io_mem_resp_bits_tag_0[1:0]; // @[HellaCacheArbiter.scala:10:7, :60:41] wire tag_hit = _tag_hit_T == 2'h0; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] wire [5:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:2]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [5:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:2]; // @[HellaCacheArbiter.scala:10:7, :74:45] wire [5:0] _io_requestor_2_resp_bits_tag_T = io_mem_resp_bits_tag_0[7:2]; // @[HellaCacheArbiter.scala:10:7, :74:45] assign io_requestor_0_resp_bits_tag_0 = {2'h0, _io_requestor_0_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_1 = _tag_hit_T_1 == 2'h1; // @[HellaCacheArbiter.scala:51:21, :60:{41,57}] assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_1_resp_bits_tag_0 = {2'h0, _io_requestor_1_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] wire tag_hit_2 = _tag_hit_T_2 == 2'h2; // @[HellaCacheArbiter.scala:60:{41,57}] assign _io_requestor_2_resp_valid_T = io_mem_resp_valid_0 & tag_hit_2; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39] assign io_requestor_2_resp_valid_0 = _io_requestor_2_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39] wire _io_requestor_2_s2_nack_T = s2_id == 2'h2; // @[HellaCacheArbiter.scala:21:24, :68:58] assign _io_requestor_2_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_2_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}] assign io_requestor_2_s2_nack_0 = _io_requestor_2_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49] assign io_requestor_2_resp_bits_tag_0 = {2'h0, _io_requestor_2_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}] always @(posedge clock) begin // @[HellaCacheArbiter.scala:10:7] s1_id <= io_requestor_0_req_valid_0 ? 2'h0 : io_requestor_1_req_valid_0 ? 2'h1 : 2'h2; // @[HellaCacheArbiter.scala:10:7, :20:20, :35:15, :50:26, :51:21] s2_id <= s1_id; // @[HellaCacheArbiter.scala:20:20, :21:24] always @(posedge) assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_replay_next = io_requestor_0_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_tlbMiss = io_requestor_0_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_replay_next = io_requestor_1_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_tlbMiss = io_requestor_1_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_req_ready = io_requestor_2_req_ready_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_nack = io_requestor_2_s2_nack_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_nack_cause_raw = io_requestor_2_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_uncached = io_requestor_2_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_paddr = io_requestor_2_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_valid = io_requestor_2_resp_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_addr = io_requestor_2_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_tag = io_requestor_2_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_cmd = io_requestor_2_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_size = io_requestor_2_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_signed = io_requestor_2_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_dprv = io_requestor_2_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_dv = io_requestor_2_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_data = io_requestor_2_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_mask = io_requestor_2_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_replay = io_requestor_2_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_has_data = io_requestor_2_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_data_word_bypass = io_requestor_2_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_data_raw = io_requestor_2_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_resp_bits_store_data = io_requestor_2_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_replay_next = io_requestor_2_replay_next_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ma_ld = io_requestor_2_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ma_st = io_requestor_2_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_pf_ld = io_requestor_2_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_pf_st = io_requestor_2_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ae_ld = io_requestor_2_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_xcpt_ae_st = io_requestor_2_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_s2_gpa = io_requestor_2_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_ordered = io_requestor_2_ordered_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_store_pending = io_requestor_2_store_pending_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_acquire = io_requestor_2_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_grant = io_requestor_2_perf_grant_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_tlbMiss = io_requestor_2_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_blocked = io_requestor_2_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_canAcceptStoreThenLoad = io_requestor_2_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_canAcceptStoreThenRMW = io_requestor_2_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_canAcceptLoadThenLoad = io_requestor_2_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_storeBufferEmptyAfterLoad = io_requestor_2_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7] assign io_requestor_2_perf_storeBufferEmptyAfterStore = io_requestor_2_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_cmd = io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_size = io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_signed = io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_phys = io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_no_resp = io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_req_bits_no_xcpt = io_mem_req_bits_no_xcpt_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_s1_data_mask = io_mem_s1_data_mask_0; // @[HellaCacheArbiter.scala:10:7] assign io_mem_keep_clock_enabled = io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File HasChipyardPRCI.scala: package chipyard.clocking import chisel3._ import scala.collection.mutable.{ArrayBuffer} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.boot.{TLTileResetCtrl} import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating || enableTileResetSetting } case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() := _) }) // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() (allClockGroupsNode :*= clockNamePrefixer :*= aggregator) // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) // 3. Synchronize reset to each clock group // 4. Clock gate the clock groups corresponding to Tiles (if desired). // 5. Add reset control registers to the tiles (if desired) // The final clock group here contains physically distinct clock domains, which some PRCI node in a // diplomatic IOBinder should drive val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = prci_ctrl_domain { if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer() } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } if (!prciParams.enableResetSynchronizers) { println(Console.RED + s""" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WARNING: DISABLING THE RESET SYNCHRONIZERS RESULTS IN A BROKEN DESIGN THAT WILL NOT BEHAVE PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) } // The chiptopClockGroupsNode shouuld be what ClockBinders attach to val chiptopClockGroupsNode = ClockGroupEphemeralNode() (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := chiptopClockGroupsNode) } File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File ResetSynchronizer.scala: // See LICENSE for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.ResetCatchAndSync /** * Synchronizes the reset of a diplomatic clock-reset pair to its accompanying clock. */ class ResetSynchronizer(implicit p: Parameters) extends LazyModule { val node = ClockAdapterNode() lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, _), (i, _)) => o.clock := i.clock o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) } } } object ResetSynchronizer { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ResetSynchronizer()).node } /** * Instantiates a reset synchronizer on all clock-reset pairs in a clock group. */ class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { val node = ClockGroupAdapterNode() lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { (node.out zip node.in).map { case ((oG, _), (iG, _)) => (oG.member.data zip iG.member.data).foreach { case (o, i) => o.clock := i.clock o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) } } } } object ClockGroupResetSynchronizer { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }
module ChipyardPRCICtrlClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_resetSynchronizer_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_resetSynchronizer_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _fragmenter_1_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34] wire [8:0] _fragmenter_1_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_1_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [12:0] _fragmenter_1_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [20:0] _fragmenter_1_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_1_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_1_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _reset_setter_auto_clock_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_clock_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_tl_in_a_ready; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_tl_in_d_valid; // @[HasChipyardPRCI.scala:78:34] wire [2:0] _reset_setter_auto_tl_in_d_bits_opcode; // @[HasChipyardPRCI.scala:78:34] wire [1:0] _reset_setter_auto_tl_in_d_bits_size; // @[HasChipyardPRCI.scala:78:34] wire [12:0] _reset_setter_auto_tl_in_d_bits_source; // @[HasChipyardPRCI.scala:78:34] wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34] wire [8:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [12:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [20:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _clock_gater_auto_clock_gater_in_1_a_ready; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_in_1_d_valid; // @[HasChipyardPRCI.scala:73:33] wire [2:0] _clock_gater_auto_clock_gater_in_1_d_bits_opcode; // @[HasChipyardPRCI.scala:73:33] wire [1:0] _clock_gater_auto_clock_gater_in_1_d_bits_size; // @[HasChipyardPRCI.scala:73:33] wire [12:0] _clock_gater_auto_clock_gater_in_1_d_bits_source; // @[HasChipyardPRCI.scala:73:33] wire [63:0] _clock_gater_auto_clock_gater_in_1_d_bits_data; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:73:33] wire _xbar_auto_anon_out_1_a_valid; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_opcode; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_param; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_size; // @[Xbar.scala:346:26] wire [8:0] _xbar_auto_anon_out_1_a_bits_source; // @[Xbar.scala:346:26] wire [20:0] _xbar_auto_anon_out_1_a_bits_address; // @[Xbar.scala:346:26] wire [7:0] _xbar_auto_anon_out_1_a_bits_mask; // @[Xbar.scala:346:26] wire [63:0] _xbar_auto_anon_out_1_a_bits_data; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_1_a_bits_corrupt; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_1_d_ready; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_a_valid; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_opcode; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_param; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_size; // @[Xbar.scala:346:26] wire [8:0] _xbar_auto_anon_out_0_a_bits_source; // @[Xbar.scala:346:26] wire [20:0] _xbar_auto_anon_out_0_a_bits_address; // @[Xbar.scala:346:26] wire [7:0] _xbar_auto_anon_out_0_a_bits_mask; // @[Xbar.scala:346:26] wire [63:0] _xbar_auto_anon_out_0_a_bits_data; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_a_bits_corrupt; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_d_ready; // @[Xbar.scala:346:26] wire auto_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_reset_setter_clock_in_member_allClocks_uncore_clock; // @[ClockDomain.scala:14:9] wire auto_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_reset_setter_clock_in_member_allClocks_uncore_reset; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [8:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [20:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_xbar_anon_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9] wire auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [8:0] auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] TLXbar_prcibus_i1_o2_a21d64s9k1z3u xbar ( // @[Xbar.scala:346:26] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (auto_xbar_anon_in_a_ready_0), .auto_anon_in_a_valid (auto_xbar_anon_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_opcode (auto_xbar_anon_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_param (auto_xbar_anon_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_size (auto_xbar_anon_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_source (auto_xbar_anon_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_address (auto_xbar_anon_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_mask (auto_xbar_anon_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_data (auto_xbar_anon_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_corrupt (auto_xbar_anon_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_anon_in_d_ready (auto_xbar_anon_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_anon_in_d_valid (auto_xbar_anon_in_d_valid_0), .auto_anon_in_d_bits_opcode (auto_xbar_anon_in_d_bits_opcode_0), .auto_anon_in_d_bits_size (auto_xbar_anon_in_d_bits_size_0), .auto_anon_in_d_bits_source (auto_xbar_anon_in_d_bits_source_0), .auto_anon_in_d_bits_data (auto_xbar_anon_in_d_bits_data_0), .auto_anon_out_1_a_ready (_fragmenter_1_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34] .auto_anon_out_1_a_valid (_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_fragmenter_1_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34] .auto_anon_out_1_d_bits_opcode (_fragmenter_1_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34] .auto_anon_out_1_d_bits_size (_fragmenter_1_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34] .auto_anon_out_1_d_bits_source (_fragmenter_1_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34] .auto_anon_out_0_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34] .auto_anon_out_0_a_valid (_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34] ); // @[Xbar.scala:346:26] ClockGroupResetSynchronizer resetSynchronizer ( // @[ResetSynchronizer.scala:46:69] .auto_in_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:73:33] .auto_in_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:73:33] .auto_out_member_allClocks_uncore_clock (auto_resetSynchronizer_out_member_allClocks_uncore_clock_0), .auto_out_member_allClocks_uncore_reset (auto_resetSynchronizer_out_member_allClocks_uncore_reset_0) ); // @[ResetSynchronizer.scala:46:69] TileClockGater clock_gater ( // @[HasChipyardPRCI.scala:73:33] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_clock_gater_in_1_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), .auto_clock_gater_in_1_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), .auto_clock_gater_in_1_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), .auto_clock_gater_in_1_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), .auto_clock_gater_in_1_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), .auto_clock_gater_in_1_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data), .auto_clock_gater_in_0_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:78:34] .auto_clock_gater_in_0_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:78:34] .auto_clock_gater_out_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), .auto_clock_gater_out_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset) ); // @[HasChipyardPRCI.scala:73:33] TLFragmenter_TileClockGater fragmenter ( // @[Fragmenter.scala:345:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready), .auto_anon_in_a_valid (_xbar_auto_anon_out_0_a_valid), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), // @[Xbar.scala:346:26] .auto_anon_in_d_ready (_xbar_auto_anon_out_0_d_ready), // @[Xbar.scala:346:26] .auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), .auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data), .auto_anon_out_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready), .auto_anon_out_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data) // @[HasChipyardPRCI.scala:73:33] ); // @[Fragmenter.scala:345:34] TileResetSetter reset_setter ( // @[HasChipyardPRCI.scala:78:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_clock_in_member_allClocks_uncore_clock (auto_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[ClockDomain.scala:14:9] .auto_clock_in_member_allClocks_uncore_reset (auto_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[ClockDomain.scala:14:9] .auto_clock_out_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), .auto_clock_out_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), .auto_tl_in_a_ready (_reset_setter_auto_tl_in_a_ready), .auto_tl_in_a_valid (_fragmenter_1_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_tl_in_d_ready (_fragmenter_1_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_tl_in_d_valid (_reset_setter_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_reset_setter_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_reset_setter_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_reset_setter_auto_tl_in_d_bits_source) ); // @[HasChipyardPRCI.scala:78:34] TLFragmenter_TileResetSetter fragmenter_1 ( // @[Fragmenter.scala:345:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_fragmenter_1_auto_anon_in_a_ready), .auto_anon_in_a_valid (_xbar_auto_anon_out_1_a_valid), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_data (_xbar_auto_anon_out_1_a_bits_data), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), // @[Xbar.scala:346:26] .auto_anon_in_d_ready (_xbar_auto_anon_out_1_d_ready), // @[Xbar.scala:346:26] .auto_anon_in_d_valid (_fragmenter_1_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_fragmenter_1_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (_fragmenter_1_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_fragmenter_1_auto_anon_in_d_bits_source), .auto_anon_out_a_ready (_reset_setter_auto_tl_in_a_ready), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_a_valid (_fragmenter_1_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_1_auto_anon_out_d_ready), .auto_anon_out_d_valid (_reset_setter_auto_tl_in_d_valid), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_d_bits_opcode (_reset_setter_auto_tl_in_d_bits_opcode), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_d_bits_size (_reset_setter_auto_tl_in_d_bits_size), // @[HasChipyardPRCI.scala:78:34] .auto_anon_out_d_bits_source (_reset_setter_auto_tl_in_d_bits_source) // @[HasChipyardPRCI.scala:78:34] ); // @[Fragmenter.scala:345:34] assign auto_resetSynchronizer_out_member_allClocks_uncore_clock = auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9] assign auto_resetSynchronizer_out_member_allClocks_uncore_reset = auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File UserYanker.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.amba.axi4 import chisel3._ import chisel3.util.{Queue, QueueIO, UIntToOH} import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.util.BundleMap /** This adapter prunes all user bit fields of the echo type from request messages, * storing them in queues and echoing them back when matching response messages are received. * * It also optionally rate limits the number of transactions that can be in flight simultaneously * per FIFO domain / A[W|R]ID. * * @param capMaxFlight is an optional maximum number of transactions that can be in flight per A[W|R]ID. */ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule { val node = AXI4AdapterNode( masterFn = { mp => mp.copy( masters = mp.masters.map { m => m.copy( maxFlight = (m.maxFlight, capMaxFlight) match { case (Some(x), Some(y)) => Some(x min y) case (Some(x), None) => Some(x) case (None, Some(y)) => Some(y) case (None, None) => None })}, echoFields = Nil)}, slaveFn = { sp => sp }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // Which fields are we stripping? val echoFields = edgeIn.master.echoFields val need_bypass = edgeOut.slave.minLatency < 1 edgeOut.master.masters.foreach { m => require (m.maxFlight.isDefined, "UserYanker needs a flight cap on each ID") } def queue(id: Int) = { val depth = edgeOut.master.masters.find(_.id.contains(id)).flatMap(_.maxFlight).getOrElse(0) if (depth == 0) { Wire(new QueueIO(BundleMap(echoFields), 1)) // unused ID => undefined value } else { Module(new Queue(BundleMap(echoFields), depth, flow=need_bypass)).io } } val rqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) } val wqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) } val arid = in.ar.bits.id val ar_ready = VecInit(rqueues.map(_.enq.ready))(arid) in .ar.ready := out.ar.ready && ar_ready out.ar.valid := in .ar.valid && ar_ready Connectable.waiveUnmatched(out.ar.bits, in.ar.bits) match { case (lhs, rhs) => lhs :<= rhs } val rid = out.r.bits.id val r_valid = VecInit(rqueues.map(_.deq.valid))(rid) val r_bits = VecInit(rqueues.map(_.deq.bits))(rid) assert (!out.r.valid || r_valid) // Q must be ready faster than the response Connectable.waiveUnmatched(in.r, out.r) match { case (lhs, rhs) => lhs :<>= rhs } in.r.bits.echo :<= r_bits val arsel = UIntToOH(arid, edgeIn.master.endId).asBools val rsel = UIntToOH(rid, edgeIn.master.endId).asBools (rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) => q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last q.deq.valid := DontCare q.deq.bits := DontCare q.enq.valid := in .ar.valid && out.ar.ready && ar q.enq.ready := DontCare q.enq.bits :<>= in.ar.bits.echo q.count := DontCare } val awid = in.aw.bits.id val aw_ready = VecInit(wqueues.map(_.enq.ready))(awid) in .aw.ready := out.aw.ready && aw_ready out.aw.valid := in .aw.valid && aw_ready Connectable.waiveUnmatched(out.aw.bits, in.aw.bits) match { case (lhs, rhs) => lhs :<>= rhs } val bid = out.b.bits.id val b_valid = VecInit(wqueues.map(_.deq.valid))(bid) val b_bits = VecInit(wqueues.map(_.deq.bits))(bid) assert (!out.b.valid || b_valid) // Q must be ready faster than the response Connectable.waiveUnmatched(in.b, out.b) match { case (lhs, rhs) => lhs :<>= rhs } in.b.bits.echo :<>= b_bits val awsel = UIntToOH(awid, edgeIn.master.endId).asBools val bsel = UIntToOH(bid, edgeIn.master.endId).asBools (wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) => q.deq.ready := out.b .valid && in .b .ready && b q.deq.valid := DontCare q.deq.bits := DontCare q.enq.valid := in .aw.valid && out.aw.ready && aw q.enq.ready := DontCare q.enq.bits :<>= in.aw.bits.echo q.count := DontCare } out.w :<>= in.w } } } object AXI4UserYanker { def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node = { val axi4yank = LazyModule(new AXI4UserYanker(capMaxFlight)) axi4yank.node } }
module AXI4UserYanker_3( // @[UserYanker.scala:36:9] input clock, // @[UserYanker.scala:36:9] input reset, // @[UserYanker.scala:36:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[UserYanker.scala:36:9] wire [6:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[UserYanker.scala:36:9] wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[UserYanker.scala:36:9] wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[UserYanker.scala:36:9] wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[UserYanker.scala:36:9] wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[UserYanker.scala:36:9] wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[UserYanker.scala:36:9] wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[UserYanker.scala:36:9] wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[UserYanker.scala:36:9] wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[UserYanker.scala:36:9] wire [3:0] auto_in_aw_bits_echo_tl_state_size_0 = auto_in_aw_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] wire [7:0] auto_in_aw_bits_echo_tl_state_source_0 = auto_in_aw_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] wire auto_in_aw_bits_echo_extra_id_0 = auto_in_aw_bits_echo_extra_id; // @[UserYanker.scala:36:9] wire auto_in_w_valid_0 = auto_in_w_valid; // @[UserYanker.scala:36:9] wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[UserYanker.scala:36:9] wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[UserYanker.scala:36:9] wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[UserYanker.scala:36:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[UserYanker.scala:36:9] wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[UserYanker.scala:36:9] wire [6:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[UserYanker.scala:36:9] wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[UserYanker.scala:36:9] wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[UserYanker.scala:36:9] wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[UserYanker.scala:36:9] wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[UserYanker.scala:36:9] wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[UserYanker.scala:36:9] wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[UserYanker.scala:36:9] wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[UserYanker.scala:36:9] wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[UserYanker.scala:36:9] wire [3:0] auto_in_ar_bits_echo_tl_state_size_0 = auto_in_ar_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] wire [7:0] auto_in_ar_bits_echo_tl_state_source_0 = auto_in_ar_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] wire auto_in_ar_bits_echo_extra_id_0 = auto_in_ar_bits_echo_extra_id; // @[UserYanker.scala:36:9] wire auto_in_r_ready_0 = auto_in_r_ready; // @[UserYanker.scala:36:9] wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[UserYanker.scala:36:9] wire auto_out_w_ready_0 = auto_out_w_ready; // @[UserYanker.scala:36:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[UserYanker.scala:36:9] wire [6:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[UserYanker.scala:36:9] wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[UserYanker.scala:36:9] wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[UserYanker.scala:36:9] wire auto_out_r_valid_0 = auto_out_r_valid; // @[UserYanker.scala:36:9] wire [6:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[UserYanker.scala:36:9] wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[UserYanker.scala:36:9] wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[UserYanker.scala:36:9] wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[UserYanker.scala:36:9] wire nodeIn_aw_ready; // @[MixedNode.scala:551:17] wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[UserYanker.scala:36:9] wire [6:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[UserYanker.scala:36:9] wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire nodeIn_aw_bits_echo_extra_id = auto_in_aw_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire nodeIn_w_ready; // @[MixedNode.scala:551:17] wire nodeIn_w_valid = auto_in_w_valid_0; // @[UserYanker.scala:36:9] wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[UserYanker.scala:36:9] wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[UserYanker.scala:36:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[UserYanker.scala:36:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_echo_extra_id; // @[MixedNode.scala:551:17] wire nodeIn_ar_ready; // @[MixedNode.scala:551:17] wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[UserYanker.scala:36:9] wire [6:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[UserYanker.scala:36:9] wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire nodeIn_ar_bits_echo_extra_id = auto_in_ar_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire nodeIn_r_ready = auto_in_r_ready_0; // @[UserYanker.scala:36:9] wire nodeIn_r_valid; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_r_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_echo_extra_id; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17] wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[UserYanker.scala:36:9] wire nodeOut_aw_valid; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17] wire nodeOut_w_ready = auto_out_w_ready_0; // @[UserYanker.scala:36:9] wire nodeOut_w_valid; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17] wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[UserYanker.scala:36:9] wire [6:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[UserYanker.scala:36:9] wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[UserYanker.scala:36:9] wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[UserYanker.scala:36:9] wire nodeOut_ar_valid; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17] wire nodeOut_r_ready; // @[MixedNode.scala:542:17] wire nodeOut_r_valid = auto_out_r_valid_0; // @[UserYanker.scala:36:9] wire [6:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[UserYanker.scala:36:9] wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[UserYanker.scala:36:9] wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[UserYanker.scala:36:9] wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[UserYanker.scala:36:9] wire auto_in_aw_ready_0; // @[UserYanker.scala:36:9] wire auto_in_w_ready_0; // @[UserYanker.scala:36:9] wire [3:0] auto_in_b_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [7:0] auto_in_b_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire auto_in_b_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire [6:0] auto_in_b_bits_id_0; // @[UserYanker.scala:36:9] wire [1:0] auto_in_b_bits_resp_0; // @[UserYanker.scala:36:9] wire auto_in_b_valid_0; // @[UserYanker.scala:36:9] wire auto_in_ar_ready_0; // @[UserYanker.scala:36:9] wire [3:0] auto_in_r_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [7:0] auto_in_r_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire auto_in_r_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire [6:0] auto_in_r_bits_id_0; // @[UserYanker.scala:36:9] wire [63:0] auto_in_r_bits_data_0; // @[UserYanker.scala:36:9] wire [1:0] auto_in_r_bits_resp_0; // @[UserYanker.scala:36:9] wire auto_in_r_bits_last_0; // @[UserYanker.scala:36:9] wire auto_in_r_valid_0; // @[UserYanker.scala:36:9] wire [6:0] auto_out_aw_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] auto_out_aw_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] auto_out_aw_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_aw_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] auto_out_aw_bits_burst_0; // @[UserYanker.scala:36:9] wire auto_out_aw_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_aw_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_aw_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_aw_bits_qos_0; // @[UserYanker.scala:36:9] wire auto_out_aw_valid_0; // @[UserYanker.scala:36:9] wire [63:0] auto_out_w_bits_data_0; // @[UserYanker.scala:36:9] wire [7:0] auto_out_w_bits_strb_0; // @[UserYanker.scala:36:9] wire auto_out_w_bits_last_0; // @[UserYanker.scala:36:9] wire auto_out_w_valid_0; // @[UserYanker.scala:36:9] wire auto_out_b_ready_0; // @[UserYanker.scala:36:9] wire [6:0] auto_out_ar_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] auto_out_ar_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] auto_out_ar_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_ar_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] auto_out_ar_bits_burst_0; // @[UserYanker.scala:36:9] wire auto_out_ar_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_ar_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_ar_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_ar_bits_qos_0; // @[UserYanker.scala:36:9] wire auto_out_ar_valid_0; // @[UserYanker.scala:36:9] wire auto_out_r_ready_0; // @[UserYanker.scala:36:9] wire _nodeIn_aw_ready_T; // @[UserYanker.scala:89:36] assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[UserYanker.scala:36:9] assign nodeOut_aw_bits_id = nodeIn_aw_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [6:0] awsel_shiftAmount = nodeIn_aw_bits_id; // @[OneHot.scala:64:49] assign nodeOut_aw_bits_addr = nodeIn_aw_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_len = nodeIn_aw_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_size = nodeIn_aw_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_burst = nodeIn_aw_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_lock = nodeIn_aw_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_cache = nodeIn_aw_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_prot = nodeIn_aw_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_qos = nodeIn_aw_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign auto_in_w_ready_0 = nodeIn_w_ready; // @[UserYanker.scala:36:9] assign nodeOut_w_valid = nodeIn_w_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_data = nodeIn_w_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_strb = nodeIn_w_bits_strb; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_last = nodeIn_w_bits_last; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[UserYanker.scala:36:9] assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[UserYanker.scala:36:9] assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[UserYanker.scala:36:9] assign auto_in_b_bits_echo_tl_state_size_0 = nodeIn_b_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] assign auto_in_b_bits_echo_tl_state_source_0 = nodeIn_b_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] assign auto_in_b_bits_echo_extra_id_0 = nodeIn_b_bits_echo_extra_id; // @[UserYanker.scala:36:9] wire _nodeIn_ar_ready_T; // @[UserYanker.scala:60:36] assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[UserYanker.scala:36:9] assign nodeOut_ar_bits_id = nodeIn_ar_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [6:0] arsel_shiftAmount = nodeIn_ar_bits_id; // @[OneHot.scala:64:49] assign nodeOut_ar_bits_addr = nodeIn_ar_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_len = nodeIn_ar_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_size = nodeIn_ar_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_burst = nodeIn_ar_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_lock = nodeIn_ar_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_cache = nodeIn_ar_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_prot = nodeIn_ar_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_qos = nodeIn_ar_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_r_valid_0 = nodeIn_r_valid; // @[UserYanker.scala:36:9] assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[UserYanker.scala:36:9] assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[UserYanker.scala:36:9] assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[UserYanker.scala:36:9] assign auto_in_r_bits_echo_tl_state_size_0 = nodeIn_r_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] assign auto_in_r_bits_echo_tl_state_source_0 = nodeIn_r_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] assign auto_in_r_bits_echo_extra_id_0 = nodeIn_r_bits_echo_extra_id; // @[UserYanker.scala:36:9] assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[UserYanker.scala:36:9] wire _nodeOut_aw_valid_T; // @[UserYanker.scala:90:36] assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[UserYanker.scala:36:9] assign nodeIn_w_ready = nodeOut_w_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_w_valid_0 = nodeOut_w_valid; // @[UserYanker.scala:36:9] assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[UserYanker.scala:36:9] assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[UserYanker.scala:36:9] assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[UserYanker.scala:36:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[UserYanker.scala:36:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_id = nodeOut_b_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [6:0] bsel_shiftAmount = nodeOut_b_bits_id; // @[OneHot.scala:64:49] assign nodeIn_b_bits_resp = nodeOut_b_bits_resp; // @[MixedNode.scala:542:17, :551:17] wire _nodeOut_ar_valid_T; // @[UserYanker.scala:61:36] assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[UserYanker.scala:36:9] assign auto_out_r_ready_0 = nodeOut_r_ready; // @[UserYanker.scala:36:9] assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_id = nodeOut_r_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [6:0] rsel_shiftAmount = nodeOut_r_bits_id; // @[OneHot.scala:64:49] assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_last = nodeOut_r_bits_last; // @[MixedNode.scala:542:17, :551:17] wire _ar_ready_WIRE_0; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_1; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_2; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_3; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_4; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_5; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_6; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_7; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_8; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_9; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_10; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_11; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_12; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_13; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_14; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_15; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_16; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_17; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_18; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_19; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_20; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_21; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_22; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_23; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_24; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_25; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_26; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_27; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_28; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_29; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_30; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_31; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_32; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_33; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_34; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_35; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_36; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_37; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_38; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_39; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_40; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_41; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_42; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_43; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_44; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_45; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_46; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_47; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_48; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_49; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_50; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_51; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_52; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_53; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_54; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_55; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_56; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_57; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_58; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_59; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_60; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_61; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_62; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_63; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_64; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_65; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_66; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_67; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_68; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_69; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_70; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_71; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_72; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_73; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_74; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_75; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_76; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_77; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_78; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_79; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_80; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_81; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_82; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_83; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_84; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_85; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_86; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_87; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_88; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_89; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_90; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_91; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_92; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_93; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_94; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_95; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_96; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_97; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_98; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_99; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_100; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_101; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_102; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_103; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_104; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_105; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_106; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_107; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_108; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_109; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_110; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_111; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_112; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_113; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_114; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_115; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_116; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_117; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_118; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_119; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_120; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_121; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_122; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_123; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_124; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_125; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_126; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_127; // @[UserYanker.scala:59:29] wire [127:0] _GEN = {{_ar_ready_WIRE_127}, {_ar_ready_WIRE_126}, {_ar_ready_WIRE_125}, {_ar_ready_WIRE_124}, {_ar_ready_WIRE_123}, {_ar_ready_WIRE_122}, {_ar_ready_WIRE_121}, {_ar_ready_WIRE_120}, {_ar_ready_WIRE_119}, {_ar_ready_WIRE_118}, {_ar_ready_WIRE_117}, {_ar_ready_WIRE_116}, {_ar_ready_WIRE_115}, {_ar_ready_WIRE_114}, {_ar_ready_WIRE_113}, {_ar_ready_WIRE_112}, {_ar_ready_WIRE_111}, {_ar_ready_WIRE_110}, {_ar_ready_WIRE_109}, {_ar_ready_WIRE_108}, {_ar_ready_WIRE_107}, {_ar_ready_WIRE_106}, {_ar_ready_WIRE_105}, {_ar_ready_WIRE_104}, {_ar_ready_WIRE_103}, {_ar_ready_WIRE_102}, {_ar_ready_WIRE_101}, {_ar_ready_WIRE_100}, {_ar_ready_WIRE_99}, {_ar_ready_WIRE_98}, {_ar_ready_WIRE_97}, {_ar_ready_WIRE_96}, {_ar_ready_WIRE_95}, {_ar_ready_WIRE_94}, {_ar_ready_WIRE_93}, {_ar_ready_WIRE_92}, {_ar_ready_WIRE_91}, {_ar_ready_WIRE_90}, {_ar_ready_WIRE_89}, {_ar_ready_WIRE_88}, {_ar_ready_WIRE_87}, {_ar_ready_WIRE_86}, {_ar_ready_WIRE_85}, {_ar_ready_WIRE_84}, {_ar_ready_WIRE_83}, {_ar_ready_WIRE_82}, {_ar_ready_WIRE_81}, {_ar_ready_WIRE_80}, {_ar_ready_WIRE_79}, {_ar_ready_WIRE_78}, {_ar_ready_WIRE_77}, {_ar_ready_WIRE_76}, {_ar_ready_WIRE_75}, {_ar_ready_WIRE_74}, {_ar_ready_WIRE_73}, {_ar_ready_WIRE_72}, {_ar_ready_WIRE_71}, {_ar_ready_WIRE_70}, {_ar_ready_WIRE_69}, {_ar_ready_WIRE_68}, {_ar_ready_WIRE_67}, {_ar_ready_WIRE_66}, {_ar_ready_WIRE_65}, {_ar_ready_WIRE_64}, {_ar_ready_WIRE_63}, {_ar_ready_WIRE_62}, {_ar_ready_WIRE_61}, {_ar_ready_WIRE_60}, {_ar_ready_WIRE_59}, {_ar_ready_WIRE_58}, {_ar_ready_WIRE_57}, {_ar_ready_WIRE_56}, {_ar_ready_WIRE_55}, {_ar_ready_WIRE_54}, {_ar_ready_WIRE_53}, {_ar_ready_WIRE_52}, {_ar_ready_WIRE_51}, {_ar_ready_WIRE_50}, {_ar_ready_WIRE_49}, {_ar_ready_WIRE_48}, {_ar_ready_WIRE_47}, {_ar_ready_WIRE_46}, {_ar_ready_WIRE_45}, {_ar_ready_WIRE_44}, {_ar_ready_WIRE_43}, {_ar_ready_WIRE_42}, {_ar_ready_WIRE_41}, {_ar_ready_WIRE_40}, {_ar_ready_WIRE_39}, {_ar_ready_WIRE_38}, {_ar_ready_WIRE_37}, {_ar_ready_WIRE_36}, {_ar_ready_WIRE_35}, {_ar_ready_WIRE_34}, {_ar_ready_WIRE_33}, {_ar_ready_WIRE_32}, {_ar_ready_WIRE_31}, {_ar_ready_WIRE_30}, {_ar_ready_WIRE_29}, {_ar_ready_WIRE_28}, {_ar_ready_WIRE_27}, {_ar_ready_WIRE_26}, {_ar_ready_WIRE_25}, {_ar_ready_WIRE_24}, {_ar_ready_WIRE_23}, {_ar_ready_WIRE_22}, {_ar_ready_WIRE_21}, {_ar_ready_WIRE_20}, {_ar_ready_WIRE_19}, {_ar_ready_WIRE_18}, {_ar_ready_WIRE_17}, {_ar_ready_WIRE_16}, {_ar_ready_WIRE_15}, {_ar_ready_WIRE_14}, {_ar_ready_WIRE_13}, {_ar_ready_WIRE_12}, {_ar_ready_WIRE_11}, {_ar_ready_WIRE_10}, {_ar_ready_WIRE_9}, {_ar_ready_WIRE_8}, {_ar_ready_WIRE_7}, {_ar_ready_WIRE_6}, {_ar_ready_WIRE_5}, {_ar_ready_WIRE_4}, {_ar_ready_WIRE_3}, {_ar_ready_WIRE_2}, {_ar_ready_WIRE_1}, {_ar_ready_WIRE_0}}; // @[UserYanker.scala:59:29, :60:36] assign _nodeIn_ar_ready_T = nodeOut_ar_ready & _GEN[nodeIn_ar_bits_id]; // @[UserYanker.scala:60:36] assign nodeIn_ar_ready = _nodeIn_ar_ready_T; // @[UserYanker.scala:60:36] assign _nodeOut_ar_valid_T = nodeIn_ar_valid & _GEN[nodeIn_ar_bits_id]; // @[UserYanker.scala:60:36, :61:36] assign nodeOut_ar_valid = _nodeOut_ar_valid_T; // @[UserYanker.scala:61:36] wire [3:0] _r_bits_WIRE_0_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_1_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_2_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_3_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_4_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_5_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_6_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_7_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_8_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_9_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_10_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_11_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_12_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_13_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_14_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_15_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_16_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_17_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_18_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_19_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_20_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_21_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_22_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_23_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_24_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_25_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_26_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_27_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_28_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_29_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_30_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_31_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_32_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_33_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_34_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_35_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_36_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_37_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_38_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_39_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_40_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_41_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_42_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_43_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_44_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_45_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_46_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_47_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_48_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_49_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_50_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_51_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_52_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_53_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_54_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_55_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_56_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_57_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_58_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_59_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_60_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_61_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_62_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_63_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_64_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_65_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_66_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_67_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_68_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_69_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_70_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_71_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_72_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_73_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_74_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_75_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_76_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_77_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_78_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_79_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_80_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_81_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_82_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_83_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_84_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_85_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_86_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_87_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_88_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_89_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_90_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_91_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_92_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_93_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_94_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_95_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_96_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_97_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_98_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_99_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_100_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_101_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_102_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_103_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_104_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_105_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_106_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_107_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_108_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_109_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_110_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_111_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_112_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_113_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_114_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_115_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_116_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_117_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_118_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_119_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_120_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_121_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_122_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_123_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_124_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_125_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_126_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_127_tl_state_size; // @[UserYanker.scala:68:27] wire [127:0][3:0] _GEN_0 = {{_r_bits_WIRE_127_tl_state_size}, {_r_bits_WIRE_126_tl_state_size}, {_r_bits_WIRE_125_tl_state_size}, {_r_bits_WIRE_124_tl_state_size}, {_r_bits_WIRE_123_tl_state_size}, {_r_bits_WIRE_122_tl_state_size}, {_r_bits_WIRE_121_tl_state_size}, {_r_bits_WIRE_120_tl_state_size}, {_r_bits_WIRE_119_tl_state_size}, {_r_bits_WIRE_118_tl_state_size}, {_r_bits_WIRE_117_tl_state_size}, {_r_bits_WIRE_116_tl_state_size}, {_r_bits_WIRE_115_tl_state_size}, {_r_bits_WIRE_114_tl_state_size}, {_r_bits_WIRE_113_tl_state_size}, {_r_bits_WIRE_112_tl_state_size}, {_r_bits_WIRE_111_tl_state_size}, {_r_bits_WIRE_110_tl_state_size}, {_r_bits_WIRE_109_tl_state_size}, {_r_bits_WIRE_108_tl_state_size}, {_r_bits_WIRE_107_tl_state_size}, {_r_bits_WIRE_106_tl_state_size}, {_r_bits_WIRE_105_tl_state_size}, {_r_bits_WIRE_104_tl_state_size}, {_r_bits_WIRE_103_tl_state_size}, {_r_bits_WIRE_102_tl_state_size}, {_r_bits_WIRE_101_tl_state_size}, {_r_bits_WIRE_100_tl_state_size}, {_r_bits_WIRE_99_tl_state_size}, {_r_bits_WIRE_98_tl_state_size}, {_r_bits_WIRE_97_tl_state_size}, {_r_bits_WIRE_96_tl_state_size}, {_r_bits_WIRE_95_tl_state_size}, {_r_bits_WIRE_94_tl_state_size}, {_r_bits_WIRE_93_tl_state_size}, {_r_bits_WIRE_92_tl_state_size}, {_r_bits_WIRE_91_tl_state_size}, {_r_bits_WIRE_90_tl_state_size}, {_r_bits_WIRE_89_tl_state_size}, {_r_bits_WIRE_88_tl_state_size}, {_r_bits_WIRE_87_tl_state_size}, {_r_bits_WIRE_86_tl_state_size}, {_r_bits_WIRE_85_tl_state_size}, {_r_bits_WIRE_84_tl_state_size}, {_r_bits_WIRE_83_tl_state_size}, {_r_bits_WIRE_82_tl_state_size}, {_r_bits_WIRE_81_tl_state_size}, {_r_bits_WIRE_80_tl_state_size}, {_r_bits_WIRE_79_tl_state_size}, {_r_bits_WIRE_78_tl_state_size}, {_r_bits_WIRE_77_tl_state_size}, {_r_bits_WIRE_76_tl_state_size}, {_r_bits_WIRE_75_tl_state_size}, {_r_bits_WIRE_74_tl_state_size}, {_r_bits_WIRE_73_tl_state_size}, {_r_bits_WIRE_72_tl_state_size}, {_r_bits_WIRE_71_tl_state_size}, {_r_bits_WIRE_70_tl_state_size}, {_r_bits_WIRE_69_tl_state_size}, {_r_bits_WIRE_68_tl_state_size}, {_r_bits_WIRE_67_tl_state_size}, {_r_bits_WIRE_66_tl_state_size}, {_r_bits_WIRE_65_tl_state_size}, {_r_bits_WIRE_64_tl_state_size}, {_r_bits_WIRE_63_tl_state_size}, {_r_bits_WIRE_62_tl_state_size}, {_r_bits_WIRE_61_tl_state_size}, {_r_bits_WIRE_60_tl_state_size}, {_r_bits_WIRE_59_tl_state_size}, {_r_bits_WIRE_58_tl_state_size}, {_r_bits_WIRE_57_tl_state_size}, {_r_bits_WIRE_56_tl_state_size}, {_r_bits_WIRE_55_tl_state_size}, {_r_bits_WIRE_54_tl_state_size}, {_r_bits_WIRE_53_tl_state_size}, {_r_bits_WIRE_52_tl_state_size}, {_r_bits_WIRE_51_tl_state_size}, {_r_bits_WIRE_50_tl_state_size}, {_r_bits_WIRE_49_tl_state_size}, {_r_bits_WIRE_48_tl_state_size}, {_r_bits_WIRE_47_tl_state_size}, {_r_bits_WIRE_46_tl_state_size}, {_r_bits_WIRE_45_tl_state_size}, {_r_bits_WIRE_44_tl_state_size}, {_r_bits_WIRE_43_tl_state_size}, {_r_bits_WIRE_42_tl_state_size}, {_r_bits_WIRE_41_tl_state_size}, {_r_bits_WIRE_40_tl_state_size}, {_r_bits_WIRE_39_tl_state_size}, {_r_bits_WIRE_38_tl_state_size}, {_r_bits_WIRE_37_tl_state_size}, {_r_bits_WIRE_36_tl_state_size}, {_r_bits_WIRE_35_tl_state_size}, {_r_bits_WIRE_34_tl_state_size}, {_r_bits_WIRE_33_tl_state_size}, {_r_bits_WIRE_32_tl_state_size}, {_r_bits_WIRE_31_tl_state_size}, {_r_bits_WIRE_30_tl_state_size}, {_r_bits_WIRE_29_tl_state_size}, {_r_bits_WIRE_28_tl_state_size}, {_r_bits_WIRE_27_tl_state_size}, {_r_bits_WIRE_26_tl_state_size}, {_r_bits_WIRE_25_tl_state_size}, {_r_bits_WIRE_24_tl_state_size}, {_r_bits_WIRE_23_tl_state_size}, {_r_bits_WIRE_22_tl_state_size}, {_r_bits_WIRE_21_tl_state_size}, {_r_bits_WIRE_20_tl_state_size}, {_r_bits_WIRE_19_tl_state_size}, {_r_bits_WIRE_18_tl_state_size}, {_r_bits_WIRE_17_tl_state_size}, {_r_bits_WIRE_16_tl_state_size}, {_r_bits_WIRE_15_tl_state_size}, {_r_bits_WIRE_14_tl_state_size}, {_r_bits_WIRE_13_tl_state_size}, {_r_bits_WIRE_12_tl_state_size}, {_r_bits_WIRE_11_tl_state_size}, {_r_bits_WIRE_10_tl_state_size}, {_r_bits_WIRE_9_tl_state_size}, {_r_bits_WIRE_8_tl_state_size}, {_r_bits_WIRE_7_tl_state_size}, {_r_bits_WIRE_6_tl_state_size}, {_r_bits_WIRE_5_tl_state_size}, {_r_bits_WIRE_4_tl_state_size}, {_r_bits_WIRE_3_tl_state_size}, {_r_bits_WIRE_2_tl_state_size}, {_r_bits_WIRE_1_tl_state_size}, {_r_bits_WIRE_0_tl_state_size}}; // @[UserYanker.scala:68:27, :73:22] assign nodeIn_r_bits_echo_tl_state_size = _GEN_0[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22] wire [7:0] _r_bits_WIRE_0_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_1_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_2_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_3_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_4_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_5_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_6_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_7_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_8_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_9_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_10_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_11_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_12_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_13_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_14_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_15_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_16_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_17_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_18_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_19_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_20_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_21_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_22_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_23_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_24_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_25_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_26_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_27_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_28_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_29_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_30_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_31_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_32_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_33_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_34_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_35_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_36_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_37_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_38_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_39_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_40_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_41_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_42_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_43_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_44_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_45_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_46_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_47_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_48_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_49_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_50_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_51_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_52_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_53_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_54_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_55_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_56_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_57_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_58_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_59_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_60_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_61_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_62_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_63_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_64_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_65_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_66_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_67_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_68_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_69_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_70_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_71_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_72_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_73_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_74_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_75_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_76_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_77_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_78_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_79_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_80_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_81_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_82_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_83_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_84_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_85_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_86_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_87_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_88_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_89_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_90_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_91_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_92_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_93_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_94_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_95_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_96_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_97_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_98_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_99_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_100_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_101_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_102_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_103_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_104_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_105_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_106_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_107_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_108_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_109_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_110_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_111_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_112_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_113_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_114_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_115_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_116_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_117_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_118_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_119_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_120_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_121_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_122_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_123_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_124_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_125_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_126_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_127_tl_state_source; // @[UserYanker.scala:68:27] wire [127:0][7:0] _GEN_1 = {{_r_bits_WIRE_127_tl_state_source}, {_r_bits_WIRE_126_tl_state_source}, {_r_bits_WIRE_125_tl_state_source}, {_r_bits_WIRE_124_tl_state_source}, {_r_bits_WIRE_123_tl_state_source}, {_r_bits_WIRE_122_tl_state_source}, {_r_bits_WIRE_121_tl_state_source}, {_r_bits_WIRE_120_tl_state_source}, {_r_bits_WIRE_119_tl_state_source}, {_r_bits_WIRE_118_tl_state_source}, {_r_bits_WIRE_117_tl_state_source}, {_r_bits_WIRE_116_tl_state_source}, {_r_bits_WIRE_115_tl_state_source}, {_r_bits_WIRE_114_tl_state_source}, {_r_bits_WIRE_113_tl_state_source}, {_r_bits_WIRE_112_tl_state_source}, {_r_bits_WIRE_111_tl_state_source}, {_r_bits_WIRE_110_tl_state_source}, {_r_bits_WIRE_109_tl_state_source}, {_r_bits_WIRE_108_tl_state_source}, {_r_bits_WIRE_107_tl_state_source}, {_r_bits_WIRE_106_tl_state_source}, {_r_bits_WIRE_105_tl_state_source}, {_r_bits_WIRE_104_tl_state_source}, {_r_bits_WIRE_103_tl_state_source}, {_r_bits_WIRE_102_tl_state_source}, {_r_bits_WIRE_101_tl_state_source}, {_r_bits_WIRE_100_tl_state_source}, {_r_bits_WIRE_99_tl_state_source}, {_r_bits_WIRE_98_tl_state_source}, {_r_bits_WIRE_97_tl_state_source}, {_r_bits_WIRE_96_tl_state_source}, {_r_bits_WIRE_95_tl_state_source}, {_r_bits_WIRE_94_tl_state_source}, {_r_bits_WIRE_93_tl_state_source}, {_r_bits_WIRE_92_tl_state_source}, {_r_bits_WIRE_91_tl_state_source}, {_r_bits_WIRE_90_tl_state_source}, {_r_bits_WIRE_89_tl_state_source}, {_r_bits_WIRE_88_tl_state_source}, {_r_bits_WIRE_87_tl_state_source}, {_r_bits_WIRE_86_tl_state_source}, {_r_bits_WIRE_85_tl_state_source}, {_r_bits_WIRE_84_tl_state_source}, {_r_bits_WIRE_83_tl_state_source}, {_r_bits_WIRE_82_tl_state_source}, {_r_bits_WIRE_81_tl_state_source}, {_r_bits_WIRE_80_tl_state_source}, {_r_bits_WIRE_79_tl_state_source}, {_r_bits_WIRE_78_tl_state_source}, {_r_bits_WIRE_77_tl_state_source}, {_r_bits_WIRE_76_tl_state_source}, {_r_bits_WIRE_75_tl_state_source}, {_r_bits_WIRE_74_tl_state_source}, {_r_bits_WIRE_73_tl_state_source}, {_r_bits_WIRE_72_tl_state_source}, {_r_bits_WIRE_71_tl_state_source}, {_r_bits_WIRE_70_tl_state_source}, {_r_bits_WIRE_69_tl_state_source}, {_r_bits_WIRE_68_tl_state_source}, {_r_bits_WIRE_67_tl_state_source}, {_r_bits_WIRE_66_tl_state_source}, {_r_bits_WIRE_65_tl_state_source}, {_r_bits_WIRE_64_tl_state_source}, {_r_bits_WIRE_63_tl_state_source}, {_r_bits_WIRE_62_tl_state_source}, {_r_bits_WIRE_61_tl_state_source}, {_r_bits_WIRE_60_tl_state_source}, {_r_bits_WIRE_59_tl_state_source}, {_r_bits_WIRE_58_tl_state_source}, {_r_bits_WIRE_57_tl_state_source}, {_r_bits_WIRE_56_tl_state_source}, {_r_bits_WIRE_55_tl_state_source}, {_r_bits_WIRE_54_tl_state_source}, {_r_bits_WIRE_53_tl_state_source}, {_r_bits_WIRE_52_tl_state_source}, {_r_bits_WIRE_51_tl_state_source}, {_r_bits_WIRE_50_tl_state_source}, {_r_bits_WIRE_49_tl_state_source}, {_r_bits_WIRE_48_tl_state_source}, {_r_bits_WIRE_47_tl_state_source}, {_r_bits_WIRE_46_tl_state_source}, {_r_bits_WIRE_45_tl_state_source}, {_r_bits_WIRE_44_tl_state_source}, {_r_bits_WIRE_43_tl_state_source}, {_r_bits_WIRE_42_tl_state_source}, {_r_bits_WIRE_41_tl_state_source}, {_r_bits_WIRE_40_tl_state_source}, {_r_bits_WIRE_39_tl_state_source}, {_r_bits_WIRE_38_tl_state_source}, {_r_bits_WIRE_37_tl_state_source}, {_r_bits_WIRE_36_tl_state_source}, {_r_bits_WIRE_35_tl_state_source}, {_r_bits_WIRE_34_tl_state_source}, {_r_bits_WIRE_33_tl_state_source}, {_r_bits_WIRE_32_tl_state_source}, {_r_bits_WIRE_31_tl_state_source}, {_r_bits_WIRE_30_tl_state_source}, {_r_bits_WIRE_29_tl_state_source}, {_r_bits_WIRE_28_tl_state_source}, {_r_bits_WIRE_27_tl_state_source}, {_r_bits_WIRE_26_tl_state_source}, {_r_bits_WIRE_25_tl_state_source}, {_r_bits_WIRE_24_tl_state_source}, {_r_bits_WIRE_23_tl_state_source}, {_r_bits_WIRE_22_tl_state_source}, {_r_bits_WIRE_21_tl_state_source}, {_r_bits_WIRE_20_tl_state_source}, {_r_bits_WIRE_19_tl_state_source}, {_r_bits_WIRE_18_tl_state_source}, {_r_bits_WIRE_17_tl_state_source}, {_r_bits_WIRE_16_tl_state_source}, {_r_bits_WIRE_15_tl_state_source}, {_r_bits_WIRE_14_tl_state_source}, {_r_bits_WIRE_13_tl_state_source}, {_r_bits_WIRE_12_tl_state_source}, {_r_bits_WIRE_11_tl_state_source}, {_r_bits_WIRE_10_tl_state_source}, {_r_bits_WIRE_9_tl_state_source}, {_r_bits_WIRE_8_tl_state_source}, {_r_bits_WIRE_7_tl_state_source}, {_r_bits_WIRE_6_tl_state_source}, {_r_bits_WIRE_5_tl_state_source}, {_r_bits_WIRE_4_tl_state_source}, {_r_bits_WIRE_3_tl_state_source}, {_r_bits_WIRE_2_tl_state_source}, {_r_bits_WIRE_1_tl_state_source}, {_r_bits_WIRE_0_tl_state_source}}; // @[UserYanker.scala:68:27, :73:22] assign nodeIn_r_bits_echo_tl_state_source = _GEN_1[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22] wire _r_bits_WIRE_0_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_1_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_2_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_3_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_4_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_5_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_6_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_7_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_8_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_9_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_10_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_11_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_12_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_13_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_14_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_15_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_16_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_17_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_18_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_19_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_20_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_21_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_22_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_23_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_24_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_25_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_26_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_27_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_28_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_29_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_30_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_31_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_32_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_33_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_34_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_35_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_36_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_37_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_38_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_39_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_40_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_41_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_42_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_43_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_44_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_45_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_46_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_47_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_48_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_49_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_50_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_51_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_52_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_53_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_54_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_55_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_56_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_57_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_58_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_59_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_60_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_61_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_62_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_63_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_64_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_65_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_66_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_67_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_68_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_69_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_70_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_71_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_72_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_73_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_74_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_75_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_76_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_77_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_78_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_79_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_80_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_81_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_82_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_83_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_84_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_85_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_86_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_87_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_88_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_89_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_90_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_91_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_92_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_93_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_94_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_95_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_96_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_97_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_98_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_99_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_100_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_101_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_102_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_103_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_104_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_105_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_106_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_107_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_108_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_109_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_110_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_111_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_112_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_113_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_114_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_115_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_116_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_117_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_118_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_119_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_120_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_121_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_122_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_123_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_124_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_125_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_126_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_127_extra_id; // @[UserYanker.scala:68:27] wire [127:0] _GEN_2 = {{_r_bits_WIRE_127_extra_id}, {_r_bits_WIRE_126_extra_id}, {_r_bits_WIRE_125_extra_id}, {_r_bits_WIRE_124_extra_id}, {_r_bits_WIRE_123_extra_id}, {_r_bits_WIRE_122_extra_id}, {_r_bits_WIRE_121_extra_id}, {_r_bits_WIRE_120_extra_id}, {_r_bits_WIRE_119_extra_id}, {_r_bits_WIRE_118_extra_id}, {_r_bits_WIRE_117_extra_id}, {_r_bits_WIRE_116_extra_id}, {_r_bits_WIRE_115_extra_id}, {_r_bits_WIRE_114_extra_id}, {_r_bits_WIRE_113_extra_id}, {_r_bits_WIRE_112_extra_id}, {_r_bits_WIRE_111_extra_id}, {_r_bits_WIRE_110_extra_id}, {_r_bits_WIRE_109_extra_id}, {_r_bits_WIRE_108_extra_id}, {_r_bits_WIRE_107_extra_id}, {_r_bits_WIRE_106_extra_id}, {_r_bits_WIRE_105_extra_id}, {_r_bits_WIRE_104_extra_id}, {_r_bits_WIRE_103_extra_id}, {_r_bits_WIRE_102_extra_id}, {_r_bits_WIRE_101_extra_id}, {_r_bits_WIRE_100_extra_id}, {_r_bits_WIRE_99_extra_id}, {_r_bits_WIRE_98_extra_id}, {_r_bits_WIRE_97_extra_id}, {_r_bits_WIRE_96_extra_id}, {_r_bits_WIRE_95_extra_id}, {_r_bits_WIRE_94_extra_id}, {_r_bits_WIRE_93_extra_id}, {_r_bits_WIRE_92_extra_id}, {_r_bits_WIRE_91_extra_id}, {_r_bits_WIRE_90_extra_id}, {_r_bits_WIRE_89_extra_id}, {_r_bits_WIRE_88_extra_id}, {_r_bits_WIRE_87_extra_id}, {_r_bits_WIRE_86_extra_id}, {_r_bits_WIRE_85_extra_id}, {_r_bits_WIRE_84_extra_id}, {_r_bits_WIRE_83_extra_id}, {_r_bits_WIRE_82_extra_id}, {_r_bits_WIRE_81_extra_id}, {_r_bits_WIRE_80_extra_id}, {_r_bits_WIRE_79_extra_id}, {_r_bits_WIRE_78_extra_id}, {_r_bits_WIRE_77_extra_id}, {_r_bits_WIRE_76_extra_id}, {_r_bits_WIRE_75_extra_id}, {_r_bits_WIRE_74_extra_id}, {_r_bits_WIRE_73_extra_id}, {_r_bits_WIRE_72_extra_id}, {_r_bits_WIRE_71_extra_id}, {_r_bits_WIRE_70_extra_id}, {_r_bits_WIRE_69_extra_id}, {_r_bits_WIRE_68_extra_id}, {_r_bits_WIRE_67_extra_id}, {_r_bits_WIRE_66_extra_id}, {_r_bits_WIRE_65_extra_id}, {_r_bits_WIRE_64_extra_id}, {_r_bits_WIRE_63_extra_id}, {_r_bits_WIRE_62_extra_id}, {_r_bits_WIRE_61_extra_id}, {_r_bits_WIRE_60_extra_id}, {_r_bits_WIRE_59_extra_id}, {_r_bits_WIRE_58_extra_id}, {_r_bits_WIRE_57_extra_id}, {_r_bits_WIRE_56_extra_id}, {_r_bits_WIRE_55_extra_id}, {_r_bits_WIRE_54_extra_id}, {_r_bits_WIRE_53_extra_id}, {_r_bits_WIRE_52_extra_id}, {_r_bits_WIRE_51_extra_id}, {_r_bits_WIRE_50_extra_id}, {_r_bits_WIRE_49_extra_id}, {_r_bits_WIRE_48_extra_id}, {_r_bits_WIRE_47_extra_id}, {_r_bits_WIRE_46_extra_id}, {_r_bits_WIRE_45_extra_id}, {_r_bits_WIRE_44_extra_id}, {_r_bits_WIRE_43_extra_id}, {_r_bits_WIRE_42_extra_id}, {_r_bits_WIRE_41_extra_id}, {_r_bits_WIRE_40_extra_id}, {_r_bits_WIRE_39_extra_id}, {_r_bits_WIRE_38_extra_id}, {_r_bits_WIRE_37_extra_id}, {_r_bits_WIRE_36_extra_id}, {_r_bits_WIRE_35_extra_id}, {_r_bits_WIRE_34_extra_id}, {_r_bits_WIRE_33_extra_id}, {_r_bits_WIRE_32_extra_id}, {_r_bits_WIRE_31_extra_id}, {_r_bits_WIRE_30_extra_id}, {_r_bits_WIRE_29_extra_id}, {_r_bits_WIRE_28_extra_id}, {_r_bits_WIRE_27_extra_id}, {_r_bits_WIRE_26_extra_id}, {_r_bits_WIRE_25_extra_id}, {_r_bits_WIRE_24_extra_id}, {_r_bits_WIRE_23_extra_id}, {_r_bits_WIRE_22_extra_id}, {_r_bits_WIRE_21_extra_id}, {_r_bits_WIRE_20_extra_id}, {_r_bits_WIRE_19_extra_id}, {_r_bits_WIRE_18_extra_id}, {_r_bits_WIRE_17_extra_id}, {_r_bits_WIRE_16_extra_id}, {_r_bits_WIRE_15_extra_id}, {_r_bits_WIRE_14_extra_id}, {_r_bits_WIRE_13_extra_id}, {_r_bits_WIRE_12_extra_id}, {_r_bits_WIRE_11_extra_id}, {_r_bits_WIRE_10_extra_id}, {_r_bits_WIRE_9_extra_id}, {_r_bits_WIRE_8_extra_id}, {_r_bits_WIRE_7_extra_id}, {_r_bits_WIRE_6_extra_id}, {_r_bits_WIRE_5_extra_id}, {_r_bits_WIRE_4_extra_id}, {_r_bits_WIRE_3_extra_id}, {_r_bits_WIRE_2_extra_id}, {_r_bits_WIRE_1_extra_id}, {_r_bits_WIRE_0_extra_id}}; // @[UserYanker.scala:68:27, :73:22] assign nodeIn_r_bits_echo_extra_id = _GEN_2[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22] wire [127:0] _arsel_T = 128'h1 << arsel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [127:0] _arsel_T_1 = _arsel_T; // @[OneHot.scala:65:{12,27}] wire arsel_0 = _arsel_T_1[0]; // @[OneHot.scala:65:27] wire arsel_1 = _arsel_T_1[1]; // @[OneHot.scala:65:27] wire arsel_2 = _arsel_T_1[2]; // @[OneHot.scala:65:27] wire arsel_3 = _arsel_T_1[3]; // @[OneHot.scala:65:27] wire arsel_4 = _arsel_T_1[4]; // @[OneHot.scala:65:27] wire arsel_5 = _arsel_T_1[5]; // @[OneHot.scala:65:27] wire arsel_6 = _arsel_T_1[6]; // @[OneHot.scala:65:27] wire arsel_7 = _arsel_T_1[7]; // @[OneHot.scala:65:27] wire arsel_8 = _arsel_T_1[8]; // @[OneHot.scala:65:27] wire arsel_9 = _arsel_T_1[9]; // @[OneHot.scala:65:27] wire arsel_10 = _arsel_T_1[10]; // @[OneHot.scala:65:27] wire arsel_11 = _arsel_T_1[11]; // @[OneHot.scala:65:27] wire arsel_12 = _arsel_T_1[12]; // @[OneHot.scala:65:27] wire arsel_13 = _arsel_T_1[13]; // @[OneHot.scala:65:27] wire arsel_14 = _arsel_T_1[14]; // @[OneHot.scala:65:27] wire arsel_15 = _arsel_T_1[15]; // @[OneHot.scala:65:27] wire arsel_16 = _arsel_T_1[16]; // @[OneHot.scala:65:27] wire arsel_17 = _arsel_T_1[17]; // @[OneHot.scala:65:27] wire arsel_18 = _arsel_T_1[18]; // @[OneHot.scala:65:27] wire arsel_19 = _arsel_T_1[19]; // @[OneHot.scala:65:27] wire arsel_20 = _arsel_T_1[20]; // @[OneHot.scala:65:27] wire arsel_21 = _arsel_T_1[21]; // @[OneHot.scala:65:27] wire arsel_22 = _arsel_T_1[22]; // @[OneHot.scala:65:27] wire arsel_23 = _arsel_T_1[23]; // @[OneHot.scala:65:27] wire arsel_24 = _arsel_T_1[24]; // @[OneHot.scala:65:27] wire arsel_25 = _arsel_T_1[25]; // @[OneHot.scala:65:27] wire arsel_26 = _arsel_T_1[26]; // @[OneHot.scala:65:27] wire arsel_27 = _arsel_T_1[27]; // @[OneHot.scala:65:27] wire arsel_28 = _arsel_T_1[28]; // @[OneHot.scala:65:27] wire arsel_29 = _arsel_T_1[29]; // @[OneHot.scala:65:27] wire arsel_30 = _arsel_T_1[30]; // @[OneHot.scala:65:27] wire arsel_31 = _arsel_T_1[31]; // @[OneHot.scala:65:27] wire arsel_32 = _arsel_T_1[32]; // @[OneHot.scala:65:27] wire arsel_33 = _arsel_T_1[33]; // @[OneHot.scala:65:27] wire arsel_34 = _arsel_T_1[34]; // @[OneHot.scala:65:27] wire arsel_35 = _arsel_T_1[35]; // @[OneHot.scala:65:27] wire arsel_36 = _arsel_T_1[36]; // @[OneHot.scala:65:27] wire arsel_37 = _arsel_T_1[37]; // @[OneHot.scala:65:27] wire arsel_38 = _arsel_T_1[38]; // @[OneHot.scala:65:27] wire arsel_39 = _arsel_T_1[39]; // @[OneHot.scala:65:27] wire arsel_40 = _arsel_T_1[40]; // @[OneHot.scala:65:27] wire arsel_41 = _arsel_T_1[41]; // @[OneHot.scala:65:27] wire arsel_42 = _arsel_T_1[42]; // @[OneHot.scala:65:27] wire arsel_43 = _arsel_T_1[43]; // @[OneHot.scala:65:27] wire arsel_44 = _arsel_T_1[44]; // @[OneHot.scala:65:27] wire arsel_45 = _arsel_T_1[45]; // @[OneHot.scala:65:27] wire arsel_46 = _arsel_T_1[46]; // @[OneHot.scala:65:27] wire arsel_47 = _arsel_T_1[47]; // @[OneHot.scala:65:27] wire arsel_48 = _arsel_T_1[48]; // @[OneHot.scala:65:27] wire arsel_49 = _arsel_T_1[49]; // @[OneHot.scala:65:27] wire arsel_50 = _arsel_T_1[50]; // @[OneHot.scala:65:27] wire arsel_51 = _arsel_T_1[51]; // @[OneHot.scala:65:27] wire arsel_52 = _arsel_T_1[52]; // @[OneHot.scala:65:27] wire arsel_53 = _arsel_T_1[53]; // @[OneHot.scala:65:27] wire arsel_54 = _arsel_T_1[54]; // @[OneHot.scala:65:27] wire arsel_55 = _arsel_T_1[55]; // @[OneHot.scala:65:27] wire arsel_56 = _arsel_T_1[56]; // @[OneHot.scala:65:27] wire arsel_57 = _arsel_T_1[57]; // @[OneHot.scala:65:27] wire arsel_58 = _arsel_T_1[58]; // @[OneHot.scala:65:27] wire arsel_59 = _arsel_T_1[59]; // @[OneHot.scala:65:27] wire arsel_60 = _arsel_T_1[60]; // @[OneHot.scala:65:27] wire arsel_61 = _arsel_T_1[61]; // @[OneHot.scala:65:27] wire arsel_62 = _arsel_T_1[62]; // @[OneHot.scala:65:27] wire arsel_63 = _arsel_T_1[63]; // @[OneHot.scala:65:27] wire arsel_64 = _arsel_T_1[64]; // @[OneHot.scala:65:27] wire arsel_65 = _arsel_T_1[65]; // @[OneHot.scala:65:27] wire arsel_66 = _arsel_T_1[66]; // @[OneHot.scala:65:27] wire arsel_67 = _arsel_T_1[67]; // @[OneHot.scala:65:27] wire arsel_68 = _arsel_T_1[68]; // @[OneHot.scala:65:27] wire arsel_69 = _arsel_T_1[69]; // @[OneHot.scala:65:27] wire arsel_70 = _arsel_T_1[70]; // @[OneHot.scala:65:27] wire arsel_71 = _arsel_T_1[71]; // @[OneHot.scala:65:27] wire arsel_72 = _arsel_T_1[72]; // @[OneHot.scala:65:27] wire arsel_73 = _arsel_T_1[73]; // @[OneHot.scala:65:27] wire arsel_74 = _arsel_T_1[74]; // @[OneHot.scala:65:27] wire arsel_75 = _arsel_T_1[75]; // @[OneHot.scala:65:27] wire arsel_76 = _arsel_T_1[76]; // @[OneHot.scala:65:27] wire arsel_77 = _arsel_T_1[77]; // @[OneHot.scala:65:27] wire arsel_78 = _arsel_T_1[78]; // @[OneHot.scala:65:27] wire arsel_79 = _arsel_T_1[79]; // @[OneHot.scala:65:27] wire arsel_80 = _arsel_T_1[80]; // @[OneHot.scala:65:27] wire arsel_81 = _arsel_T_1[81]; // @[OneHot.scala:65:27] wire arsel_82 = _arsel_T_1[82]; // @[OneHot.scala:65:27] wire arsel_83 = _arsel_T_1[83]; // @[OneHot.scala:65:27] wire arsel_84 = _arsel_T_1[84]; // @[OneHot.scala:65:27] wire arsel_85 = _arsel_T_1[85]; // @[OneHot.scala:65:27] wire arsel_86 = _arsel_T_1[86]; // @[OneHot.scala:65:27] wire arsel_87 = _arsel_T_1[87]; // @[OneHot.scala:65:27] wire arsel_88 = _arsel_T_1[88]; // @[OneHot.scala:65:27] wire arsel_89 = _arsel_T_1[89]; // @[OneHot.scala:65:27] wire arsel_90 = _arsel_T_1[90]; // @[OneHot.scala:65:27] wire arsel_91 = _arsel_T_1[91]; // @[OneHot.scala:65:27] wire arsel_92 = _arsel_T_1[92]; // @[OneHot.scala:65:27] wire arsel_93 = _arsel_T_1[93]; // @[OneHot.scala:65:27] wire arsel_94 = _arsel_T_1[94]; // @[OneHot.scala:65:27] wire arsel_95 = _arsel_T_1[95]; // @[OneHot.scala:65:27] wire arsel_96 = _arsel_T_1[96]; // @[OneHot.scala:65:27] wire arsel_97 = _arsel_T_1[97]; // @[OneHot.scala:65:27] wire arsel_98 = _arsel_T_1[98]; // @[OneHot.scala:65:27] wire arsel_99 = _arsel_T_1[99]; // @[OneHot.scala:65:27] wire arsel_100 = _arsel_T_1[100]; // @[OneHot.scala:65:27] wire arsel_101 = _arsel_T_1[101]; // @[OneHot.scala:65:27] wire arsel_102 = _arsel_T_1[102]; // @[OneHot.scala:65:27] wire arsel_103 = _arsel_T_1[103]; // @[OneHot.scala:65:27] wire arsel_104 = _arsel_T_1[104]; // @[OneHot.scala:65:27] wire arsel_105 = _arsel_T_1[105]; // @[OneHot.scala:65:27] wire arsel_106 = _arsel_T_1[106]; // @[OneHot.scala:65:27] wire arsel_107 = _arsel_T_1[107]; // @[OneHot.scala:65:27] wire arsel_108 = _arsel_T_1[108]; // @[OneHot.scala:65:27] wire arsel_109 = _arsel_T_1[109]; // @[OneHot.scala:65:27] wire arsel_110 = _arsel_T_1[110]; // @[OneHot.scala:65:27] wire arsel_111 = _arsel_T_1[111]; // @[OneHot.scala:65:27] wire arsel_112 = _arsel_T_1[112]; // @[OneHot.scala:65:27] wire arsel_113 = _arsel_T_1[113]; // @[OneHot.scala:65:27] wire arsel_114 = _arsel_T_1[114]; // @[OneHot.scala:65:27] wire arsel_115 = _arsel_T_1[115]; // @[OneHot.scala:65:27] wire arsel_116 = _arsel_T_1[116]; // @[OneHot.scala:65:27] wire arsel_117 = _arsel_T_1[117]; // @[OneHot.scala:65:27] wire arsel_118 = _arsel_T_1[118]; // @[OneHot.scala:65:27] wire arsel_119 = _arsel_T_1[119]; // @[OneHot.scala:65:27] wire arsel_120 = _arsel_T_1[120]; // @[OneHot.scala:65:27] wire arsel_121 = _arsel_T_1[121]; // @[OneHot.scala:65:27] wire arsel_122 = _arsel_T_1[122]; // @[OneHot.scala:65:27] wire arsel_123 = _arsel_T_1[123]; // @[OneHot.scala:65:27] wire arsel_124 = _arsel_T_1[124]; // @[OneHot.scala:65:27] wire arsel_125 = _arsel_T_1[125]; // @[OneHot.scala:65:27] wire arsel_126 = _arsel_T_1[126]; // @[OneHot.scala:65:27] wire arsel_127 = _arsel_T_1[127]; // @[OneHot.scala:65:27] wire [127:0] _rsel_T = 128'h1 << rsel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [127:0] _rsel_T_1 = _rsel_T; // @[OneHot.scala:65:{12,27}] wire rsel_0 = _rsel_T_1[0]; // @[OneHot.scala:65:27] wire rsel_1 = _rsel_T_1[1]; // @[OneHot.scala:65:27] wire rsel_2 = _rsel_T_1[2]; // @[OneHot.scala:65:27] wire rsel_3 = _rsel_T_1[3]; // @[OneHot.scala:65:27] wire rsel_4 = _rsel_T_1[4]; // @[OneHot.scala:65:27] wire rsel_5 = _rsel_T_1[5]; // @[OneHot.scala:65:27] wire rsel_6 = _rsel_T_1[6]; // @[OneHot.scala:65:27] wire rsel_7 = _rsel_T_1[7]; // @[OneHot.scala:65:27] wire rsel_8 = _rsel_T_1[8]; // @[OneHot.scala:65:27] wire rsel_9 = _rsel_T_1[9]; // @[OneHot.scala:65:27] wire rsel_10 = _rsel_T_1[10]; // @[OneHot.scala:65:27] wire rsel_11 = _rsel_T_1[11]; // @[OneHot.scala:65:27] wire rsel_12 = _rsel_T_1[12]; // @[OneHot.scala:65:27] wire rsel_13 = _rsel_T_1[13]; // @[OneHot.scala:65:27] wire rsel_14 = _rsel_T_1[14]; // @[OneHot.scala:65:27] wire rsel_15 = _rsel_T_1[15]; // @[OneHot.scala:65:27] wire rsel_16 = _rsel_T_1[16]; // @[OneHot.scala:65:27] wire rsel_17 = _rsel_T_1[17]; // @[OneHot.scala:65:27] wire rsel_18 = _rsel_T_1[18]; // @[OneHot.scala:65:27] wire rsel_19 = _rsel_T_1[19]; // @[OneHot.scala:65:27] wire rsel_20 = _rsel_T_1[20]; // @[OneHot.scala:65:27] wire rsel_21 = _rsel_T_1[21]; // @[OneHot.scala:65:27] wire rsel_22 = _rsel_T_1[22]; // @[OneHot.scala:65:27] wire rsel_23 = _rsel_T_1[23]; // @[OneHot.scala:65:27] wire rsel_24 = _rsel_T_1[24]; // @[OneHot.scala:65:27] wire rsel_25 = _rsel_T_1[25]; // @[OneHot.scala:65:27] wire rsel_26 = _rsel_T_1[26]; // @[OneHot.scala:65:27] wire rsel_27 = _rsel_T_1[27]; // @[OneHot.scala:65:27] wire rsel_28 = _rsel_T_1[28]; // @[OneHot.scala:65:27] wire rsel_29 = _rsel_T_1[29]; // @[OneHot.scala:65:27] wire rsel_30 = _rsel_T_1[30]; // @[OneHot.scala:65:27] wire rsel_31 = _rsel_T_1[31]; // @[OneHot.scala:65:27] wire rsel_32 = _rsel_T_1[32]; // @[OneHot.scala:65:27] wire rsel_33 = _rsel_T_1[33]; // @[OneHot.scala:65:27] wire rsel_34 = _rsel_T_1[34]; // @[OneHot.scala:65:27] wire rsel_35 = _rsel_T_1[35]; // @[OneHot.scala:65:27] wire rsel_36 = _rsel_T_1[36]; // @[OneHot.scala:65:27] wire rsel_37 = _rsel_T_1[37]; // @[OneHot.scala:65:27] wire rsel_38 = _rsel_T_1[38]; // @[OneHot.scala:65:27] wire rsel_39 = _rsel_T_1[39]; // @[OneHot.scala:65:27] wire rsel_40 = _rsel_T_1[40]; // @[OneHot.scala:65:27] wire rsel_41 = _rsel_T_1[41]; // @[OneHot.scala:65:27] wire rsel_42 = _rsel_T_1[42]; // @[OneHot.scala:65:27] wire rsel_43 = _rsel_T_1[43]; // @[OneHot.scala:65:27] wire rsel_44 = _rsel_T_1[44]; // @[OneHot.scala:65:27] wire rsel_45 = _rsel_T_1[45]; // @[OneHot.scala:65:27] wire rsel_46 = _rsel_T_1[46]; // @[OneHot.scala:65:27] wire rsel_47 = _rsel_T_1[47]; // @[OneHot.scala:65:27] wire rsel_48 = _rsel_T_1[48]; // @[OneHot.scala:65:27] wire rsel_49 = _rsel_T_1[49]; // @[OneHot.scala:65:27] wire rsel_50 = _rsel_T_1[50]; // @[OneHot.scala:65:27] wire rsel_51 = _rsel_T_1[51]; // @[OneHot.scala:65:27] wire rsel_52 = _rsel_T_1[52]; // @[OneHot.scala:65:27] wire rsel_53 = _rsel_T_1[53]; // @[OneHot.scala:65:27] wire rsel_54 = _rsel_T_1[54]; // @[OneHot.scala:65:27] wire rsel_55 = _rsel_T_1[55]; // @[OneHot.scala:65:27] wire rsel_56 = _rsel_T_1[56]; // @[OneHot.scala:65:27] wire rsel_57 = _rsel_T_1[57]; // @[OneHot.scala:65:27] wire rsel_58 = _rsel_T_1[58]; // @[OneHot.scala:65:27] wire rsel_59 = _rsel_T_1[59]; // @[OneHot.scala:65:27] wire rsel_60 = _rsel_T_1[60]; // @[OneHot.scala:65:27] wire rsel_61 = _rsel_T_1[61]; // @[OneHot.scala:65:27] wire rsel_62 = _rsel_T_1[62]; // @[OneHot.scala:65:27] wire rsel_63 = _rsel_T_1[63]; // @[OneHot.scala:65:27] wire rsel_64 = _rsel_T_1[64]; // @[OneHot.scala:65:27] wire rsel_65 = _rsel_T_1[65]; // @[OneHot.scala:65:27] wire rsel_66 = _rsel_T_1[66]; // @[OneHot.scala:65:27] wire rsel_67 = _rsel_T_1[67]; // @[OneHot.scala:65:27] wire rsel_68 = _rsel_T_1[68]; // @[OneHot.scala:65:27] wire rsel_69 = _rsel_T_1[69]; // @[OneHot.scala:65:27] wire rsel_70 = _rsel_T_1[70]; // @[OneHot.scala:65:27] wire rsel_71 = _rsel_T_1[71]; // @[OneHot.scala:65:27] wire rsel_72 = _rsel_T_1[72]; // @[OneHot.scala:65:27] wire rsel_73 = _rsel_T_1[73]; // @[OneHot.scala:65:27] wire rsel_74 = _rsel_T_1[74]; // @[OneHot.scala:65:27] wire rsel_75 = _rsel_T_1[75]; // @[OneHot.scala:65:27] wire rsel_76 = _rsel_T_1[76]; // @[OneHot.scala:65:27] wire rsel_77 = _rsel_T_1[77]; // @[OneHot.scala:65:27] wire rsel_78 = _rsel_T_1[78]; // @[OneHot.scala:65:27] wire rsel_79 = _rsel_T_1[79]; // @[OneHot.scala:65:27] wire rsel_80 = _rsel_T_1[80]; // @[OneHot.scala:65:27] wire rsel_81 = _rsel_T_1[81]; // @[OneHot.scala:65:27] wire rsel_82 = _rsel_T_1[82]; // @[OneHot.scala:65:27] wire rsel_83 = _rsel_T_1[83]; // @[OneHot.scala:65:27] wire rsel_84 = _rsel_T_1[84]; // @[OneHot.scala:65:27] wire rsel_85 = _rsel_T_1[85]; // @[OneHot.scala:65:27] wire rsel_86 = _rsel_T_1[86]; // @[OneHot.scala:65:27] wire rsel_87 = _rsel_T_1[87]; // @[OneHot.scala:65:27] wire rsel_88 = _rsel_T_1[88]; // @[OneHot.scala:65:27] wire rsel_89 = _rsel_T_1[89]; // @[OneHot.scala:65:27] wire rsel_90 = _rsel_T_1[90]; // @[OneHot.scala:65:27] wire rsel_91 = _rsel_T_1[91]; // @[OneHot.scala:65:27] wire rsel_92 = _rsel_T_1[92]; // @[OneHot.scala:65:27] wire rsel_93 = _rsel_T_1[93]; // @[OneHot.scala:65:27] wire rsel_94 = _rsel_T_1[94]; // @[OneHot.scala:65:27] wire rsel_95 = _rsel_T_1[95]; // @[OneHot.scala:65:27] wire rsel_96 = _rsel_T_1[96]; // @[OneHot.scala:65:27] wire rsel_97 = _rsel_T_1[97]; // @[OneHot.scala:65:27] wire rsel_98 = _rsel_T_1[98]; // @[OneHot.scala:65:27] wire rsel_99 = _rsel_T_1[99]; // @[OneHot.scala:65:27] wire rsel_100 = _rsel_T_1[100]; // @[OneHot.scala:65:27] wire rsel_101 = _rsel_T_1[101]; // @[OneHot.scala:65:27] wire rsel_102 = _rsel_T_1[102]; // @[OneHot.scala:65:27] wire rsel_103 = _rsel_T_1[103]; // @[OneHot.scala:65:27] wire rsel_104 = _rsel_T_1[104]; // @[OneHot.scala:65:27] wire rsel_105 = _rsel_T_1[105]; // @[OneHot.scala:65:27] wire rsel_106 = _rsel_T_1[106]; // @[OneHot.scala:65:27] wire rsel_107 = _rsel_T_1[107]; // @[OneHot.scala:65:27] wire rsel_108 = _rsel_T_1[108]; // @[OneHot.scala:65:27] wire rsel_109 = _rsel_T_1[109]; // @[OneHot.scala:65:27] wire rsel_110 = _rsel_T_1[110]; // @[OneHot.scala:65:27] wire rsel_111 = _rsel_T_1[111]; // @[OneHot.scala:65:27] wire rsel_112 = _rsel_T_1[112]; // @[OneHot.scala:65:27] wire rsel_113 = _rsel_T_1[113]; // @[OneHot.scala:65:27] wire rsel_114 = _rsel_T_1[114]; // @[OneHot.scala:65:27] wire rsel_115 = _rsel_T_1[115]; // @[OneHot.scala:65:27] wire rsel_116 = _rsel_T_1[116]; // @[OneHot.scala:65:27] wire rsel_117 = _rsel_T_1[117]; // @[OneHot.scala:65:27] wire rsel_118 = _rsel_T_1[118]; // @[OneHot.scala:65:27] wire rsel_119 = _rsel_T_1[119]; // @[OneHot.scala:65:27] wire rsel_120 = _rsel_T_1[120]; // @[OneHot.scala:65:27] wire rsel_121 = _rsel_T_1[121]; // @[OneHot.scala:65:27] wire rsel_122 = _rsel_T_1[122]; // @[OneHot.scala:65:27] wire rsel_123 = _rsel_T_1[123]; // @[OneHot.scala:65:27] wire rsel_124 = _rsel_T_1[124]; // @[OneHot.scala:65:27] wire rsel_125 = _rsel_T_1[125]; // @[OneHot.scala:65:27] wire rsel_126 = _rsel_T_1[126]; // @[OneHot.scala:65:27] wire rsel_127 = _rsel_T_1[127]; // @[OneHot.scala:65:27] wire _T_640 = nodeOut_r_valid & nodeIn_r_ready; // @[UserYanker.scala:78:37] wire _T_643 = nodeIn_ar_valid & nodeOut_ar_ready; // @[UserYanker.scala:81:37] wire _aw_ready_WIRE_0; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_1; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_2; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_3; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_4; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_5; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_6; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_7; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_8; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_9; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_10; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_11; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_12; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_13; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_14; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_15; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_16; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_17; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_18; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_19; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_20; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_21; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_22; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_23; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_24; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_25; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_26; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_27; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_28; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_29; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_30; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_31; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_32; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_33; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_34; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_35; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_36; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_37; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_38; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_39; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_40; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_41; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_42; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_43; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_44; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_45; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_46; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_47; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_48; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_49; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_50; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_51; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_52; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_53; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_54; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_55; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_56; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_57; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_58; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_59; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_60; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_61; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_62; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_63; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_64; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_65; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_66; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_67; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_68; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_69; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_70; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_71; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_72; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_73; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_74; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_75; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_76; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_77; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_78; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_79; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_80; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_81; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_82; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_83; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_84; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_85; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_86; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_87; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_88; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_89; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_90; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_91; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_92; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_93; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_94; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_95; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_96; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_97; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_98; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_99; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_100; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_101; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_102; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_103; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_104; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_105; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_106; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_107; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_108; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_109; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_110; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_111; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_112; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_113; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_114; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_115; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_116; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_117; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_118; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_119; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_120; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_121; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_122; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_123; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_124; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_125; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_126; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_127; // @[UserYanker.scala:88:29] wire [127:0] _GEN_3 = {{_aw_ready_WIRE_127}, {_aw_ready_WIRE_126}, {_aw_ready_WIRE_125}, {_aw_ready_WIRE_124}, {_aw_ready_WIRE_123}, {_aw_ready_WIRE_122}, {_aw_ready_WIRE_121}, {_aw_ready_WIRE_120}, {_aw_ready_WIRE_119}, {_aw_ready_WIRE_118}, {_aw_ready_WIRE_117}, {_aw_ready_WIRE_116}, {_aw_ready_WIRE_115}, {_aw_ready_WIRE_114}, {_aw_ready_WIRE_113}, {_aw_ready_WIRE_112}, {_aw_ready_WIRE_111}, {_aw_ready_WIRE_110}, {_aw_ready_WIRE_109}, {_aw_ready_WIRE_108}, {_aw_ready_WIRE_107}, {_aw_ready_WIRE_106}, {_aw_ready_WIRE_105}, {_aw_ready_WIRE_104}, {_aw_ready_WIRE_103}, {_aw_ready_WIRE_102}, {_aw_ready_WIRE_101}, {_aw_ready_WIRE_100}, {_aw_ready_WIRE_99}, {_aw_ready_WIRE_98}, {_aw_ready_WIRE_97}, {_aw_ready_WIRE_96}, {_aw_ready_WIRE_95}, {_aw_ready_WIRE_94}, {_aw_ready_WIRE_93}, {_aw_ready_WIRE_92}, {_aw_ready_WIRE_91}, {_aw_ready_WIRE_90}, {_aw_ready_WIRE_89}, {_aw_ready_WIRE_88}, {_aw_ready_WIRE_87}, {_aw_ready_WIRE_86}, {_aw_ready_WIRE_85}, {_aw_ready_WIRE_84}, {_aw_ready_WIRE_83}, {_aw_ready_WIRE_82}, {_aw_ready_WIRE_81}, {_aw_ready_WIRE_80}, {_aw_ready_WIRE_79}, {_aw_ready_WIRE_78}, {_aw_ready_WIRE_77}, {_aw_ready_WIRE_76}, {_aw_ready_WIRE_75}, {_aw_ready_WIRE_74}, {_aw_ready_WIRE_73}, {_aw_ready_WIRE_72}, {_aw_ready_WIRE_71}, {_aw_ready_WIRE_70}, {_aw_ready_WIRE_69}, {_aw_ready_WIRE_68}, {_aw_ready_WIRE_67}, {_aw_ready_WIRE_66}, {_aw_ready_WIRE_65}, {_aw_ready_WIRE_64}, {_aw_ready_WIRE_63}, {_aw_ready_WIRE_62}, {_aw_ready_WIRE_61}, {_aw_ready_WIRE_60}, {_aw_ready_WIRE_59}, {_aw_ready_WIRE_58}, {_aw_ready_WIRE_57}, {_aw_ready_WIRE_56}, {_aw_ready_WIRE_55}, {_aw_ready_WIRE_54}, {_aw_ready_WIRE_53}, {_aw_ready_WIRE_52}, {_aw_ready_WIRE_51}, {_aw_ready_WIRE_50}, {_aw_ready_WIRE_49}, {_aw_ready_WIRE_48}, {_aw_ready_WIRE_47}, {_aw_ready_WIRE_46}, {_aw_ready_WIRE_45}, {_aw_ready_WIRE_44}, {_aw_ready_WIRE_43}, {_aw_ready_WIRE_42}, {_aw_ready_WIRE_41}, {_aw_ready_WIRE_40}, {_aw_ready_WIRE_39}, {_aw_ready_WIRE_38}, {_aw_ready_WIRE_37}, {_aw_ready_WIRE_36}, {_aw_ready_WIRE_35}, {_aw_ready_WIRE_34}, {_aw_ready_WIRE_33}, {_aw_ready_WIRE_32}, {_aw_ready_WIRE_31}, {_aw_ready_WIRE_30}, {_aw_ready_WIRE_29}, {_aw_ready_WIRE_28}, {_aw_ready_WIRE_27}, {_aw_ready_WIRE_26}, {_aw_ready_WIRE_25}, {_aw_ready_WIRE_24}, {_aw_ready_WIRE_23}, {_aw_ready_WIRE_22}, {_aw_ready_WIRE_21}, {_aw_ready_WIRE_20}, {_aw_ready_WIRE_19}, {_aw_ready_WIRE_18}, {_aw_ready_WIRE_17}, {_aw_ready_WIRE_16}, {_aw_ready_WIRE_15}, {_aw_ready_WIRE_14}, {_aw_ready_WIRE_13}, {_aw_ready_WIRE_12}, {_aw_ready_WIRE_11}, {_aw_ready_WIRE_10}, {_aw_ready_WIRE_9}, {_aw_ready_WIRE_8}, {_aw_ready_WIRE_7}, {_aw_ready_WIRE_6}, {_aw_ready_WIRE_5}, {_aw_ready_WIRE_4}, {_aw_ready_WIRE_3}, {_aw_ready_WIRE_2}, {_aw_ready_WIRE_1}, {_aw_ready_WIRE_0}}; // @[UserYanker.scala:88:29, :89:36] assign _nodeIn_aw_ready_T = nodeOut_aw_ready & _GEN_3[nodeIn_aw_bits_id]; // @[UserYanker.scala:89:36] assign nodeIn_aw_ready = _nodeIn_aw_ready_T; // @[UserYanker.scala:89:36] assign _nodeOut_aw_valid_T = nodeIn_aw_valid & _GEN_3[nodeIn_aw_bits_id]; // @[UserYanker.scala:89:36, :90:36] assign nodeOut_aw_valid = _nodeOut_aw_valid_T; // @[UserYanker.scala:90:36] wire _r_valid_WIRE_0; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_1; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_2; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_3; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_4; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_5; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_6; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_7; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_8; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_9; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_10; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_11; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_12; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_13; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_14; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_15; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_16; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_17; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_18; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_19; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_20; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_21; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_22; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_23; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_24; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_25; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_26; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_27; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_28; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_29; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_30; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_31; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_32; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_33; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_34; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_35; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_36; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_37; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_38; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_39; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_40; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_41; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_42; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_43; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_44; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_45; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_46; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_47; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_48; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_49; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_50; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_51; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_52; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_53; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_54; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_55; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_56; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_57; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_58; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_59; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_60; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_61; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_62; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_63; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_64; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_65; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_66; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_67; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_68; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_69; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_70; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_71; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_72; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_73; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_74; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_75; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_76; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_77; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_78; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_79; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_80; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_81; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_82; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_83; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_84; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_85; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_86; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_87; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_88; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_89; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_90; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_91; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_92; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_93; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_94; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_95; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_96; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_97; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_98; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_99; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_100; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_101; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_102; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_103; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_104; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_105; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_106; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_107; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_108; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_109; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_110; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_111; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_112; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_113; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_114; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_115; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_116; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_117; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_118; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_119; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_120; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_121; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_122; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_123; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_124; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_125; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_126; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_127; // @[UserYanker.scala:67:28] wire _b_valid_WIRE_0; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_1; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_2; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_3; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_4; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_5; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_6; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_7; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_8; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_9; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_10; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_11; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_12; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_13; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_14; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_15; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_16; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_17; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_18; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_19; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_20; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_21; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_22; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_23; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_24; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_25; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_26; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_27; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_28; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_29; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_30; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_31; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_32; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_33; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_34; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_35; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_36; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_37; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_38; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_39; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_40; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_41; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_42; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_43; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_44; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_45; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_46; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_47; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_48; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_49; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_50; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_51; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_52; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_53; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_54; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_55; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_56; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_57; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_58; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_59; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_60; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_61; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_62; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_63; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_64; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_65; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_66; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_67; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_68; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_69; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_70; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_71; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_72; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_73; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_74; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_75; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_76; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_77; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_78; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_79; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_80; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_81; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_82; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_83; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_84; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_85; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_86; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_87; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_88; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_89; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_90; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_91; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_92; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_93; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_94; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_95; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_96; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_97; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_98; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_99; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_100; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_101; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_102; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_103; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_104; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_105; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_106; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_107; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_108; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_109; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_110; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_111; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_112; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_113; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_114; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_115; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_116; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_117; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_118; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_119; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_120; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_121; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_122; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_123; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_124; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_125; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_126; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_127; // @[UserYanker.scala:96:28]
Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid || io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 || nBanks == 2 || nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }
module RegisterReadXbar_3( // @[RegisterFile.scala:27:7] input clock, // @[RegisterFile.scala:27:7] output io_in_0_req_ready, // @[RegisterFile.scala:28:14] input io_in_0_req_valid, // @[RegisterFile.scala:28:14] input [6:0] io_in_0_req_bits_eg, // @[RegisterFile.scala:28:14] input io_in_0_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_0_resp, // @[RegisterFile.scala:28:14] output io_in_1_req_ready, // @[RegisterFile.scala:28:14] input io_in_1_req_valid, // @[RegisterFile.scala:28:14] input [6:0] io_in_1_req_bits_eg, // @[RegisterFile.scala:28:14] input io_in_1_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_1_resp, // @[RegisterFile.scala:28:14] output io_in_2_req_ready, // @[RegisterFile.scala:28:14] input io_in_2_req_valid, // @[RegisterFile.scala:28:14] input [6:0] io_in_2_req_bits_eg, // @[RegisterFile.scala:28:14] input io_in_2_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_2_resp, // @[RegisterFile.scala:28:14] output io_in_3_req_ready, // @[RegisterFile.scala:28:14] input io_in_3_req_valid, // @[RegisterFile.scala:28:14] input [6:0] io_in_3_req_bits_eg, // @[RegisterFile.scala:28:14] input io_in_3_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_3_resp, // @[RegisterFile.scala:28:14] output io_in_4_req_ready, // @[RegisterFile.scala:28:14] input io_in_4_req_valid, // @[RegisterFile.scala:28:14] input [6:0] io_in_4_req_bits_eg, // @[RegisterFile.scala:28:14] output [63:0] io_in_4_resp, // @[RegisterFile.scala:28:14] input io_out_0_req_ready, // @[RegisterFile.scala:28:14] output [6:0] io_out_0_req_bits_eg, // @[RegisterFile.scala:28:14] input [63:0] io_out_0_resp, // @[RegisterFile.scala:28:14] input io_out_1_req_ready, // @[RegisterFile.scala:28:14] output [6:0] io_out_1_req_bits_eg, // @[RegisterFile.scala:28:14] input [63:0] io_out_1_resp, // @[RegisterFile.scala:28:14] input io_out_2_req_ready, // @[RegisterFile.scala:28:14] output [6:0] io_out_2_req_bits_eg, // @[RegisterFile.scala:28:14] input [63:0] io_out_2_resp, // @[RegisterFile.scala:28:14] input io_out_3_req_ready, // @[RegisterFile.scala:28:14] output [6:0] io_out_3_req_bits_eg, // @[RegisterFile.scala:28:14] input [63:0] io_out_3_resp // @[RegisterFile.scala:28:14] ); wire _arbs_3_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_3_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_3_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _arbs_3_io_in_3_ready; // @[RegisterFile.scala:33:38] wire _arbs_3_io_in_4_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_3_ready; // @[RegisterFile.scala:33:38] wire _arbs_2_io_in_4_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_3_ready; // @[RegisterFile.scala:33:38] wire _arbs_1_io_in_4_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_1_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_2_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_3_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_4_ready; // @[RegisterFile.scala:33:38] wire _io_in_0_resp_T = io_in_0_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [6:0] arbs_3_io_in_0_bits_eg = {2'h0, io_in_0_req_bits_eg[6:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_0_resp_T_1 = io_in_0_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_0_resp_T_2 = io_in_0_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_1_resp_T = io_in_1_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [6:0] arbs_3_io_in_1_bits_eg = {2'h0, io_in_1_req_bits_eg[6:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_1_resp_T_1 = io_in_1_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_1_resp_T_2 = io_in_1_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_2_resp_T = io_in_2_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [6:0] arbs_3_io_in_2_bits_eg = {2'h0, io_in_2_req_bits_eg[6:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_2_resp_T_1 = io_in_2_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_2_resp_T_2 = io_in_2_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_3_resp_T = io_in_3_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [6:0] arbs_3_io_in_3_bits_eg = {2'h0, io_in_3_req_bits_eg[6:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_3_resp_T_1 = io_in_3_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_3_resp_T_2 = io_in_3_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_4_resp_T = io_in_4_req_bits_eg[1:0] == 2'h0; // @[RegisterFile.scala:41:82, :43:63] wire [6:0] arbs_3_io_in_4_bits_eg = {2'h0, io_in_4_req_bits_eg[6:2]}; // @[RegisterFile.scala:44:{32,56}] wire _io_in_4_resp_T_1 = io_in_4_req_bits_eg[1:0] == 2'h1; // @[RegisterFile.scala:41:82, :43:63] wire _io_in_4_resp_T_2 = io_in_4_req_bits_eg[1:0] == 2'h2; // @[RegisterFile.scala:41:82, :43:63] OldestRRArbiter_12 arbs_0 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_0_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & _io_in_0_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_0_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & _io_in_1_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_0_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & _io_in_2_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_in_2_bits_oldest (io_in_2_req_bits_oldest), .io_in_3_ready (_arbs_0_io_in_3_ready), .io_in_3_valid (io_in_3_req_valid & _io_in_3_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_3_bits_eg (arbs_3_io_in_3_bits_eg), // @[RegisterFile.scala:44:32] .io_in_3_bits_oldest (io_in_3_req_bits_oldest), .io_in_4_ready (_arbs_0_io_in_4_ready), .io_in_4_valid (io_in_4_req_valid & _io_in_4_resp_T), // @[RegisterFile.scala:43:{52,63}] .io_in_4_bits_eg (arbs_3_io_in_4_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_0_req_ready), .io_out_bits_eg (io_out_0_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter_12 arbs_1 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & _io_in_0_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_1_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & _io_in_1_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_1_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & _io_in_2_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_in_2_bits_oldest (io_in_2_req_bits_oldest), .io_in_3_ready (_arbs_1_io_in_3_ready), .io_in_3_valid (io_in_3_req_valid & _io_in_3_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_3_bits_eg (arbs_3_io_in_3_bits_eg), // @[RegisterFile.scala:44:32] .io_in_3_bits_oldest (io_in_3_req_bits_oldest), .io_in_4_ready (_arbs_1_io_in_4_ready), .io_in_4_valid (io_in_4_req_valid & _io_in_4_resp_T_1), // @[RegisterFile.scala:43:{52,63}] .io_in_4_bits_eg (arbs_3_io_in_4_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_1_req_ready), .io_out_bits_eg (io_out_1_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter_12 arbs_2 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_2_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & _io_in_0_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_2_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & _io_in_1_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_2_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & _io_in_2_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_in_2_bits_oldest (io_in_2_req_bits_oldest), .io_in_3_ready (_arbs_2_io_in_3_ready), .io_in_3_valid (io_in_3_req_valid & _io_in_3_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_3_bits_eg (arbs_3_io_in_3_bits_eg), // @[RegisterFile.scala:44:32] .io_in_3_bits_oldest (io_in_3_req_bits_oldest), .io_in_4_ready (_arbs_2_io_in_4_ready), .io_in_4_valid (io_in_4_req_valid & _io_in_4_resp_T_2), // @[RegisterFile.scala:43:{52,63}] .io_in_4_bits_eg (arbs_3_io_in_4_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_2_req_ready), .io_out_bits_eg (io_out_2_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter_12 arbs_3 ( // @[RegisterFile.scala:33:38] .clock (clock), .io_in_0_ready (_arbs_3_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & (&(io_in_0_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_0_bits_eg (arbs_3_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_in_1_ready (_arbs_3_io_in_1_ready), .io_in_1_valid (io_in_1_req_valid & (&(io_in_1_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_1_bits_eg (arbs_3_io_in_1_bits_eg), // @[RegisterFile.scala:44:32] .io_in_1_bits_oldest (io_in_1_req_bits_oldest), .io_in_2_ready (_arbs_3_io_in_2_ready), .io_in_2_valid (io_in_2_req_valid & (&(io_in_2_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_2_bits_eg (arbs_3_io_in_2_bits_eg), // @[RegisterFile.scala:44:32] .io_in_2_bits_oldest (io_in_2_req_bits_oldest), .io_in_3_ready (_arbs_3_io_in_3_ready), .io_in_3_valid (io_in_3_req_valid & (&(io_in_3_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_3_bits_eg (arbs_3_io_in_3_bits_eg), // @[RegisterFile.scala:44:32] .io_in_3_bits_oldest (io_in_3_req_bits_oldest), .io_in_4_ready (_arbs_3_io_in_4_ready), .io_in_4_valid (io_in_4_req_valid & (&(io_in_4_req_bits_eg[1:0]))), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_4_bits_eg (arbs_3_io_in_4_bits_eg), // @[RegisterFile.scala:44:32] .io_out_ready (io_out_3_req_ready), .io_out_bits_eg (io_out_3_req_bits_eg) ); // @[RegisterFile.scala:33:38] assign io_in_0_req_ready = _io_in_0_resp_T & _arbs_0_io_in_0_ready | _io_in_0_resp_T_1 & _arbs_1_io_in_0_ready | _io_in_0_resp_T_2 & _arbs_2_io_in_0_ready | (&(io_in_0_req_bits_eg[1:0])) & _arbs_3_io_in_0_ready; // @[Mux.scala:30:73] assign io_in_0_resp = (_io_in_0_resp_T ? io_out_0_resp : 64'h0) | (_io_in_0_resp_T_1 ? io_out_1_resp : 64'h0) | (_io_in_0_resp_T_2 ? io_out_2_resp : 64'h0) | ((&(io_in_0_req_bits_eg[1:0])) ? io_out_3_resp : 64'h0); // @[Mux.scala:30:73] assign io_in_1_req_ready = _io_in_1_resp_T & _arbs_0_io_in_1_ready | _io_in_1_resp_T_1 & _arbs_1_io_in_1_ready | _io_in_1_resp_T_2 & _arbs_2_io_in_1_ready | (&(io_in_1_req_bits_eg[1:0])) & _arbs_3_io_in_1_ready; // @[Mux.scala:30:73] assign io_in_1_resp = (_io_in_1_resp_T ? io_out_0_resp : 64'h0) | (_io_in_1_resp_T_1 ? io_out_1_resp : 64'h0) | (_io_in_1_resp_T_2 ? io_out_2_resp : 64'h0) | ((&(io_in_1_req_bits_eg[1:0])) ? io_out_3_resp : 64'h0); // @[Mux.scala:30:73] assign io_in_2_req_ready = _io_in_2_resp_T & _arbs_0_io_in_2_ready | _io_in_2_resp_T_1 & _arbs_1_io_in_2_ready | _io_in_2_resp_T_2 & _arbs_2_io_in_2_ready | (&(io_in_2_req_bits_eg[1:0])) & _arbs_3_io_in_2_ready; // @[Mux.scala:30:73] assign io_in_2_resp = (_io_in_2_resp_T ? io_out_0_resp : 64'h0) | (_io_in_2_resp_T_1 ? io_out_1_resp : 64'h0) | (_io_in_2_resp_T_2 ? io_out_2_resp : 64'h0) | ((&(io_in_2_req_bits_eg[1:0])) ? io_out_3_resp : 64'h0); // @[Mux.scala:30:73] assign io_in_3_req_ready = _io_in_3_resp_T & _arbs_0_io_in_3_ready | _io_in_3_resp_T_1 & _arbs_1_io_in_3_ready | _io_in_3_resp_T_2 & _arbs_2_io_in_3_ready | (&(io_in_3_req_bits_eg[1:0])) & _arbs_3_io_in_3_ready; // @[Mux.scala:30:73] assign io_in_3_resp = (_io_in_3_resp_T ? io_out_0_resp : 64'h0) | (_io_in_3_resp_T_1 ? io_out_1_resp : 64'h0) | (_io_in_3_resp_T_2 ? io_out_2_resp : 64'h0) | ((&(io_in_3_req_bits_eg[1:0])) ? io_out_3_resp : 64'h0); // @[Mux.scala:30:73] assign io_in_4_req_ready = _io_in_4_resp_T & _arbs_0_io_in_4_ready | _io_in_4_resp_T_1 & _arbs_1_io_in_4_ready | _io_in_4_resp_T_2 & _arbs_2_io_in_4_ready | (&(io_in_4_req_bits_eg[1:0])) & _arbs_3_io_in_4_ready; // @[Mux.scala:30:73] assign io_in_4_resp = (_io_in_4_resp_T ? io_out_0_resp : 64'h0) | (_io_in_4_resp_T_1 ? io_out_1_resp : 64'h0) | (_io_in_4_resp_T_2 ? io_out_2_resp : 64'h0) | ((&(io_in_4_req_bits_eg[1:0])) ? io_out_3_resp : 64'h0); // @[Mux.scala:30:73] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_95( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_151 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_18 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_25 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [103:0] c_opcodes_set = 104'h0; // @[Monitor.scala:740:34] wire [103:0] c_sizes_set = 104'h0; // @[Monitor.scala:741:34] wire [25:0] c_set = 26'h0; // @[Monitor.scala:738:34] wire [25:0] c_set_wo_ready = 26'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_7 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 5'h19; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = ~_source_ok_T_7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = source_ok_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_10 & _source_ok_T_11; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = io_in_a_bits_source_0 == 5'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_3 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire _source_ok_T_14 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_15 = _source_ok_T_14 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_15 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_18 = _uncommonBits_T_18[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_19 = _uncommonBits_T_19[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_20 = _uncommonBits_T_20[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_21 = _uncommonBits_T_21[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_16 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_23 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_19 = _source_ok_T_17; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_20 = source_ok_uncommonBits_2 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_21 = _source_ok_T_19 & _source_ok_T_20; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_21; // @[Parameters.scala:1138:31] wire _source_ok_T_22 = io_in_d_bits_source_0 == 5'h19; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_22; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_24 = ~_source_ok_T_23; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_26 = _source_ok_T_24; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_27 = source_ok_uncommonBits_3 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_28 = _source_ok_T_26 & _source_ok_T_27; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_2 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_d_bits_source_0 == 5'h9; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_3 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_31 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_831 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_831; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_831; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_899 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_899; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_899; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_899; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [25:0] inflight; // @[Monitor.scala:614:27] reg [103:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [103:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [25:0] a_set; // @[Monitor.scala:626:34] wire [25:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [103:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [103:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [103:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [103:0] _a_opcode_lookup_T_6 = {100'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [103:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [103:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [103:0] _a_size_lookup_T_6 = {100'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [103:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[103:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire _T_764 = _T_831 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_764 ? _a_set_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_764 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_764 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_764 ? _a_opcodes_set_T_1[103:0] : 104'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_764 ? _a_sizes_set_T_1[103:0] : 104'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [25:0] d_clr; // @[Monitor.scala:664:34] wire [25:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [103:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [103:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_810 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_810 & ~d_release_ack ? _d_clr_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire _T_779 = _T_899 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_779 ? _d_clr_T[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_779 ? _d_opcodes_clr_T_5[103:0] : 104'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_779 ? _d_sizes_clr_T_5[103:0] : 104'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [25:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [25:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [25:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [103:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [103:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [103:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [103:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [103:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [103:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [25:0] inflight_1; // @[Monitor.scala:726:35] wire [25:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [103:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [103:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [103:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [103:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [103:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [103:0] _c_opcode_lookup_T_6 = {100'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [103:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [103:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [103:0] _c_size_lookup_T_6 = {100'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [103:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[103:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [25:0] d_clr_1; // @[Monitor.scala:774:34] wire [25:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [103:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [103:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_875 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_875 & d_release_ack_1 ? _d_clr_wo_ready_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35] wire _T_857 = _T_899 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_857 ? _d_clr_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_857 ? _d_opcodes_clr_T_11[103:0] : 104'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_857 ? _d_sizes_clr_T_11[103:0] : 104'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [25:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [25:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [103:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [103:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [103:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [103:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File IdIndexer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.amba.axi4 import chisel3._ import chisel3.util.{log2Ceil, Cat} import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.diplomacy.IdRange import freechips.rocketchip.util.{ControlKey, SimpleBundleField} case object AXI4ExtraId extends ControlKey[UInt]("extra_id") case class AXI4ExtraIdField(width: Int) extends SimpleBundleField(AXI4ExtraId)(Output(UInt(width.W)), 0.U) /** This adapter limits the set of FIFO domain ids used by outbound transactions. * * Extra AWID and ARID bits from upstream transactions are stored in a User Bits field called AXI4ExtraId, * which values are expected to be echoed back to this adapter alongside any downstream response messages, * and are then prepended to the RID and BID field to restore the original identifier. * * @param idBits is the desired number of A[W|R]ID bits to be used */ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule { require (idBits >= 0, s"AXI4IdIndexer: idBits must be > 0, not $idBits") val node = AXI4AdapterNode( masterFn = { mp => // Create one new "master" per ID val masters = Array.tabulate(1 << idBits) { i => AXI4MasterParameters( name = "", id = IdRange(i, i+1), aligned = true, maxFlight = Some(0)) } // Accumulate the names of masters we squish val names = Array.fill(1 << idBits) { new scala.collection.mutable.HashSet[String]() } // Squash the information from original masters into new ID masters mp.masters.foreach { m => for (i <- m.id.start until m.id.end) { val j = i % (1 << idBits) val accumulated = masters(j) names(j) += m.name masters(j) = accumulated.copy( aligned = accumulated.aligned && m.aligned, maxFlight = accumulated.maxFlight.flatMap { o => m.maxFlight.map { n => o+n } }) } } val finalNameStrings = names.map { n => if (n.isEmpty) "(unused)" else n.toList.mkString(", ") } val bits = log2Ceil(mp.endId) - idBits val field = if (bits > 0) Seq(AXI4ExtraIdField(bits)) else Nil mp.copy( echoFields = field ++ mp.echoFields, masters = masters.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) }) }, slaveFn = { sp => sp }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // Leave everything mostly untouched Connectable.waiveUnmatched(out.ar, in.ar) match { case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll } Connectable.waiveUnmatched(out.aw, in.aw) match { case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll } Connectable.waiveUnmatched(out.w, in.w) match { case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll } Connectable.waiveUnmatched(in.b, out.b) match { case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll } Connectable.waiveUnmatched(in.r, out.r) match { case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll } val bits = log2Ceil(edgeIn.master.endId) - idBits if (bits > 0) { // (in.aX.bits.id >> idBits).width = bits > 0 out.ar.bits.echo(AXI4ExtraId) := in.ar.bits.id >> idBits out.aw.bits.echo(AXI4ExtraId) := in.aw.bits.id >> idBits // Special care is needed in case of 0 idBits, b/c .id has width 1 still if (idBits == 0) { out.ar.bits.id := 0.U out.aw.bits.id := 0.U in.r.bits.id := out.r.bits.echo(AXI4ExtraId) in.b.bits.id := out.b.bits.echo(AXI4ExtraId) } else { in.r.bits.id := Cat(out.r.bits.echo(AXI4ExtraId), out.r.bits.id) in.b.bits.id := Cat(out.b.bits.echo(AXI4ExtraId), out.b.bits.id) } } } } } object AXI4IdIndexer { def apply(idBits: Int)(implicit p: Parameters): AXI4Node = { val axi4index = LazyModule(new AXI4IdIndexer(idBits)) axi4index.node } } File ToAXI4.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField} import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp} import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1} import freechips.rocketchip.util.DataToAugmentedData class AXI4TLStateBundle(val sourceBits: Int) extends Bundle { val size = UInt(4.W) val source = UInt((sourceBits max 1).W) } case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state") case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => { x.size := 0.U x.source := 0.U }) /** TLtoAXI4IdMap serves as a record for the translation performed between id spaces. * * Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy. * Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module. */ class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry] { val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType) private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size } private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) => AXI4MasterParameters( name = tl.name, id = IdRange(start, start+size), aligned = true, maxFlight = Some(if (tl.requestFifo) tl.sourceId.size else 1), nodePath = tl.nodePath) } private val axi4IdEnd = axi4Masters.map(_.id.end).max private val axiDigits = String.valueOf(axi4IdEnd-1).length() private val tlDigits = String.valueOf(tlPort.endSourceId-1).length() protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s" val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) => TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo) } } case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = axi4Id val maxTransactionsInFlight = Some(tlId.size) } case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)( dFn = { p => AXI4MasterPortParameters( masters = (new TLtoAXI4IdMap(p)).axi4Masters, requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]), echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields, responseKeys = p.responseKeys) }, uFn = { p => TLSlavePortParameters.v1( managers = p.slaves.map { case s => TLSlaveParameters.v1( address = s.address, resources = s.resources, regionType = s.regionType, executable = s.executable, nodePath = s.nodePath, supportsGet = s.supportsRead, supportsPutFull = s.supportsWrite, supportsPutPartial = s.supportsWrite, fifoId = Some(0), mayDenyPut = true, mayDenyGet = true)}, beatBytes = p.beatBytes, minLatency = p.minLatency, responseFields = p.responseFields, requestKeys = AMBAProt +: p.requestKeys) }) // wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule { require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4") val node = TLToAXI4Node(wcorrupt) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val slaves = edgeOut.slave.slaves // All pairs of slaves must promise that they will never interleave data require (slaves(0).interleavedId.isDefined) slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) } // Construct the source=>ID mapping table val map = new TLtoAXI4IdMap(edgeIn.client) val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B)) val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id))) val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B)) var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] } map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) => for (i <- 0 until tlId.size) { val id = axi4Id.start + (if (fifo) 0 else i) sourceStall(tlId.start + i) := idStall(id) sourceTable(tlId.start + i) := id.U } if (fifo) { idCount(axi4Id.start) = Some(tlId.size) } } adapterName.foreach { n => println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n") ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""") } // We need to keep the following state from A => D: (size, source) // All of those fields could potentially require 0 bits (argh. Chisel.) // We will pack all of that extra information into the echo bits. require (log2Ceil(edgeIn.maxLgSize+1) <= 4) val a_address = edgeIn.address(in.a.bits) val a_source = in.a.bits.source val a_size = edgeIn.size(in.a.bits) val a_isPut = edgeIn.hasData(in.a.bits) val (a_first, a_last, _) = edgeIn.firstlast(in.a) val r_state = out.r.bits.echo(AXI4TLState) val r_source = r_state.source val r_size = r_state.size val b_state = out.b.bits.echo(AXI4TLState) val b_source = b_state.source val b_size = b_state.size // We need these Queues because AXI4 queues are irrevocable val depth = if (combinational) 1 else 2 val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params))) val out_w = Wire(chiselTypeOf(out.w)) out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational) val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational) // Fan out the ARW channel to AR and AW out.ar.bits := queue_arw.bits out.aw.bits := queue_arw.bits out.ar.valid := queue_arw.valid && !queue_arw.bits.wen out.aw.valid := queue_arw.valid && queue_arw.bits.wen queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready) val beatBytes = edgeIn.manager.beatBytes val maxSize = log2Ceil(beatBytes).U val doneAW = RegInit(false.B) when (in.a.fire) { doneAW := !a_last } val arw = out_arw.bits arw.wen := a_isPut arw.id := sourceTable(a_source) arw.addr := a_address arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes) arw.size := Mux(a_size >= maxSize, maxSize, a_size) arw.burst := AXI4Parameters.BURST_INCR arw.lock := 0.U // not exclusive (LR/SC unsupported b/c no forward progress guarantee) arw.cache := 0.U // do not allow AXI to modify our transactions arw.prot := AXI4Parameters.PROT_PRIVILEGED arw.qos := 0.U // no QoS Connectable.waiveUnmatched(arw.user, in.a.bits.user) match { case (lhs, rhs) => lhs :<= rhs } Connectable.waiveUnmatched(arw.echo, in.a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = arw.echo(AXI4TLState) a_extra.source := a_source a_extra.size := a_size in.a.bits.user.lift(AMBAProt).foreach { x => val prot = Wire(Vec(3, Bool())) val cache = Wire(Vec(4, Bool())) prot(0) := x.privileged prot(1) := !x.secure prot(2) := x.fetch cache(0) := x.bufferable cache(1) := x.modifiable cache(2) := x.readalloc cache(3) := x.writealloc arw.prot := Cat(prot.reverse) arw.cache := Cat(cache.reverse) } val stall = sourceStall(in.a.bits.source) && a_first in.a.ready := !stall && Mux(a_isPut, (doneAW || out_arw.ready) && out_w.ready, out_arw.ready) out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, true.B) out_w.valid := !stall && in.a.valid && a_isPut && (doneAW || out_arw.ready) out_w.bits.data := in.a.bits.data out_w.bits.strb := in.a.bits.mask out_w.bits.last := a_last out_w.bits.user.lift(AMBACorrupt).foreach { _ := in.a.bits.corrupt } // R and B => D arbitration val r_holds_d = RegInit(false.B) when (out.r.fire) { r_holds_d := !out.r.bits.last } // Give R higher priority than B, unless B has been delayed for 8 cycles val b_delay = Reg(UInt(3.W)) when (out.b.valid && !out.b.ready) { b_delay := b_delay + 1.U } .otherwise { b_delay := 0.U } val r_wins = (out.r.valid && b_delay =/= 7.U) || r_holds_d out.r.ready := in.d.ready && r_wins out.b.ready := in.d.ready && !r_wins in.d.valid := Mux(r_wins, out.r.valid, out.b.valid) // If the first beat of the AXI RRESP is RESP_DECERR, treat this as a denied // request. We must pulse extend this value as AXI is allowed to change the // value of RRESP on every beat, and ChipLink may not. val r_first = RegInit(true.B) when (out.r.fire) { r_first := out.r.bits.last } val r_denied = out.r.bits.resp === AXI4Parameters.RESP_DECERR holdUnless r_first val r_corrupt = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY val b_denied = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY val r_d = edgeIn.AccessAck(r_source, r_size, 0.U, denied = r_denied, corrupt = r_corrupt || r_denied) val b_d = edgeIn.AccessAck(b_source, b_size, denied = b_denied) Connectable.waiveUnmatched(r_d.user, out.r.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(r_d.echo, out.r.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.user, out.b.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.echo, out.b.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } in.d.bits := Mux(r_wins, r_d, b_d) in.d.bits.data := out.r.bits.data // avoid a costly Mux // We need to track if any reads or writes are inflight for a given ID. // If the opposite type arrives, we must stall until it completes. val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools val d_last = Mux(r_wins, out.r.bits.last, true.B) // If FIFO was requested, ensure that R+W ordering is preserved (a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) => // AXI does not guarantee read vs. write ordering. In particular, if we // are in the middle of receiving a read burst and then issue a write, // the write might affect the read burst. This violates FIFO behaviour. // To solve this, we must wait until the last beat of a burst, but this // means that a TileLink master which performs early source reuse can // have one more transaction inflight than we promised AXI; stall it too. val maxCount = n.getOrElse(1) val count = RegInit(0.U(log2Ceil(maxCount + 1).W)) val write = Reg(Bool()) val idle = count === 0.U val inc = as && out_arw.fire val dec = ds && d_last && in.d.fire count := count + inc.asUInt - dec.asUInt assert (!dec || count =/= 0.U) // underflow assert (!inc || count =/= maxCount.U) // overflow when (inc) { write := arw.wen } // If only one transaction can be inflight, it can't mismatch val mismatch = if (maxCount > 1) { write =/= arw.wen } else { false.B } s := (!idle && mismatch) || (count === maxCount.U) } // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B } } } object TLToAXI4 { def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0, wcorrupt: Boolean = true)(implicit p: Parameters) = { val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits, wcorrupt)) tl2axi4.node } def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = { if ( a.supports.probe && !b.supports.probe) return false if (!a.supports.probe && b.supports.probe) return true if ( a.requestFifo && !b.requestFifo ) return false if (!a.requestFifo && b.requestFifo ) return true return false } } File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File UserYanker.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.amba.axi4 import chisel3._ import chisel3.util.{Queue, QueueIO, UIntToOH} import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp} import freechips.rocketchip.util.BundleMap /** This adapter prunes all user bit fields of the echo type from request messages, * storing them in queues and echoing them back when matching response messages are received. * * It also optionally rate limits the number of transactions that can be in flight simultaneously * per FIFO domain / A[W|R]ID. * * @param capMaxFlight is an optional maximum number of transactions that can be in flight per A[W|R]ID. */ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule { val node = AXI4AdapterNode( masterFn = { mp => mp.copy( masters = mp.masters.map { m => m.copy( maxFlight = (m.maxFlight, capMaxFlight) match { case (Some(x), Some(y)) => Some(x min y) case (Some(x), None) => Some(x) case (None, Some(y)) => Some(y) case (None, None) => None })}, echoFields = Nil)}, slaveFn = { sp => sp }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // Which fields are we stripping? val echoFields = edgeIn.master.echoFields val need_bypass = edgeOut.slave.minLatency < 1 edgeOut.master.masters.foreach { m => require (m.maxFlight.isDefined, "UserYanker needs a flight cap on each ID") } def queue(id: Int) = { val depth = edgeOut.master.masters.find(_.id.contains(id)).flatMap(_.maxFlight).getOrElse(0) if (depth == 0) { Wire(new QueueIO(BundleMap(echoFields), 1)) // unused ID => undefined value } else { Module(new Queue(BundleMap(echoFields), depth, flow=need_bypass)).io } } val rqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) } val wqueues = Seq.tabulate(edgeIn.master.endId) { i => queue(i) } val arid = in.ar.bits.id val ar_ready = VecInit(rqueues.map(_.enq.ready))(arid) in .ar.ready := out.ar.ready && ar_ready out.ar.valid := in .ar.valid && ar_ready Connectable.waiveUnmatched(out.ar.bits, in.ar.bits) match { case (lhs, rhs) => lhs :<= rhs } val rid = out.r.bits.id val r_valid = VecInit(rqueues.map(_.deq.valid))(rid) val r_bits = VecInit(rqueues.map(_.deq.bits))(rid) assert (!out.r.valid || r_valid) // Q must be ready faster than the response Connectable.waiveUnmatched(in.r, out.r) match { case (lhs, rhs) => lhs :<>= rhs } in.r.bits.echo :<= r_bits val arsel = UIntToOH(arid, edgeIn.master.endId).asBools val rsel = UIntToOH(rid, edgeIn.master.endId).asBools (rqueues zip (arsel zip rsel)) foreach { case (q, (ar, r)) => q.deq.ready := out.r .valid && in .r .ready && r && out.r.bits.last q.deq.valid := DontCare q.deq.bits := DontCare q.enq.valid := in .ar.valid && out.ar.ready && ar q.enq.ready := DontCare q.enq.bits :<>= in.ar.bits.echo q.count := DontCare } val awid = in.aw.bits.id val aw_ready = VecInit(wqueues.map(_.enq.ready))(awid) in .aw.ready := out.aw.ready && aw_ready out.aw.valid := in .aw.valid && aw_ready Connectable.waiveUnmatched(out.aw.bits, in.aw.bits) match { case (lhs, rhs) => lhs :<>= rhs } val bid = out.b.bits.id val b_valid = VecInit(wqueues.map(_.deq.valid))(bid) val b_bits = VecInit(wqueues.map(_.deq.bits))(bid) assert (!out.b.valid || b_valid) // Q must be ready faster than the response Connectable.waiveUnmatched(in.b, out.b) match { case (lhs, rhs) => lhs :<>= rhs } in.b.bits.echo :<>= b_bits val awsel = UIntToOH(awid, edgeIn.master.endId).asBools val bsel = UIntToOH(bid, edgeIn.master.endId).asBools (wqueues zip (awsel zip bsel)) foreach { case (q, (aw, b)) => q.deq.ready := out.b .valid && in .b .ready && b q.deq.valid := DontCare q.deq.bits := DontCare q.enq.valid := in .aw.valid && out.aw.ready && aw q.enq.ready := DontCare q.enq.bits :<>= in.aw.bits.echo q.count := DontCare } out.w :<>= in.w } } } object AXI4UserYanker { def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node = { val axi4yank = LazyModule(new AXI4UserYanker(capMaxFlight)) axi4yank.node } }
module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_widget_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_widget_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_widget_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_axi4yank_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_axi4yank_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_axi4yank_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_axi4yank_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_axi4yank_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_axi4yank_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_axi4yank_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_axi4yank_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_axi4yank_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_axi4yank_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_axi4yank_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_axi4yank_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_axi4yank_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_axi4yank_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_axi4yank_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_axi4yank_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_axi4yank_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_r_bits_last, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [4:0] widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire _tl2axi4_auto_out_aw_valid; // @[ToAXI4.scala:301:29] wire [4:0] _tl2axi4_auto_out_aw_bits_id; // @[ToAXI4.scala:301:29] wire [31:0] _tl2axi4_auto_out_aw_bits_addr; // @[ToAXI4.scala:301:29] wire [7:0] _tl2axi4_auto_out_aw_bits_len; // @[ToAXI4.scala:301:29] wire [2:0] _tl2axi4_auto_out_aw_bits_size; // @[ToAXI4.scala:301:29] wire [1:0] _tl2axi4_auto_out_aw_bits_burst; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_aw_bits_lock; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_aw_bits_cache; // @[ToAXI4.scala:301:29] wire [2:0] _tl2axi4_auto_out_aw_bits_prot; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_aw_bits_qos; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_aw_bits_echo_tl_state_size; // @[ToAXI4.scala:301:29] wire [4:0] _tl2axi4_auto_out_aw_bits_echo_tl_state_source; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_w_valid; // @[ToAXI4.scala:301:29] wire [63:0] _tl2axi4_auto_out_w_bits_data; // @[ToAXI4.scala:301:29] wire [7:0] _tl2axi4_auto_out_w_bits_strb; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_w_bits_last; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_b_ready; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_ar_valid; // @[ToAXI4.scala:301:29] wire [4:0] _tl2axi4_auto_out_ar_bits_id; // @[ToAXI4.scala:301:29] wire [31:0] _tl2axi4_auto_out_ar_bits_addr; // @[ToAXI4.scala:301:29] wire [7:0] _tl2axi4_auto_out_ar_bits_len; // @[ToAXI4.scala:301:29] wire [2:0] _tl2axi4_auto_out_ar_bits_size; // @[ToAXI4.scala:301:29] wire [1:0] _tl2axi4_auto_out_ar_bits_burst; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_ar_bits_lock; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_ar_bits_cache; // @[ToAXI4.scala:301:29] wire [2:0] _tl2axi4_auto_out_ar_bits_prot; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_ar_bits_qos; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_ar_bits_echo_tl_state_size; // @[ToAXI4.scala:301:29] wire [4:0] _tl2axi4_auto_out_ar_bits_echo_tl_state_source; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_r_ready; // @[ToAXI4.scala:301:29] wire _axi4index_auto_in_aw_ready; // @[IdIndexer.scala:108:31] wire _axi4index_auto_in_w_ready; // @[IdIndexer.scala:108:31] wire _axi4index_auto_in_b_valid; // @[IdIndexer.scala:108:31] wire [4:0] _axi4index_auto_in_b_bits_id; // @[IdIndexer.scala:108:31] wire [1:0] _axi4index_auto_in_b_bits_resp; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_in_b_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31] wire [4:0] _axi4index_auto_in_b_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31] wire _axi4index_auto_in_ar_ready; // @[IdIndexer.scala:108:31] wire _axi4index_auto_in_r_valid; // @[IdIndexer.scala:108:31] wire [4:0] _axi4index_auto_in_r_bits_id; // @[IdIndexer.scala:108:31] wire [63:0] _axi4index_auto_in_r_bits_data; // @[IdIndexer.scala:108:31] wire [1:0] _axi4index_auto_in_r_bits_resp; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_in_r_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31] wire [4:0] _axi4index_auto_in_r_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31] wire _axi4index_auto_in_r_bits_last; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_aw_valid; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_aw_bits_id; // @[IdIndexer.scala:108:31] wire [31:0] _axi4index_auto_out_aw_bits_addr; // @[IdIndexer.scala:108:31] wire [7:0] _axi4index_auto_out_aw_bits_len; // @[IdIndexer.scala:108:31] wire [2:0] _axi4index_auto_out_aw_bits_size; // @[IdIndexer.scala:108:31] wire [1:0] _axi4index_auto_out_aw_bits_burst; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_aw_bits_lock; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_aw_bits_cache; // @[IdIndexer.scala:108:31] wire [2:0] _axi4index_auto_out_aw_bits_prot; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_aw_bits_qos; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31] wire [4:0] _axi4index_auto_out_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_aw_bits_echo_extra_id; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_w_valid; // @[IdIndexer.scala:108:31] wire [63:0] _axi4index_auto_out_w_bits_data; // @[IdIndexer.scala:108:31] wire [7:0] _axi4index_auto_out_w_bits_strb; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_w_bits_last; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_b_ready; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_ar_valid; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_ar_bits_id; // @[IdIndexer.scala:108:31] wire [31:0] _axi4index_auto_out_ar_bits_addr; // @[IdIndexer.scala:108:31] wire [7:0] _axi4index_auto_out_ar_bits_len; // @[IdIndexer.scala:108:31] wire [2:0] _axi4index_auto_out_ar_bits_size; // @[IdIndexer.scala:108:31] wire [1:0] _axi4index_auto_out_ar_bits_burst; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_ar_bits_lock; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_ar_bits_cache; // @[IdIndexer.scala:108:31] wire [2:0] _axi4index_auto_out_ar_bits_prot; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_ar_bits_qos; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31] wire [4:0] _axi4index_auto_out_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_ar_bits_echo_extra_id; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_r_ready; // @[IdIndexer.scala:108:31] wire _axi4yank_auto_in_aw_ready; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_w_ready; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_b_valid; // @[UserYanker.scala:125:30] wire [3:0] _axi4yank_auto_in_b_bits_id; // @[UserYanker.scala:125:30] wire [1:0] _axi4yank_auto_in_b_bits_resp; // @[UserYanker.scala:125:30] wire [3:0] _axi4yank_auto_in_b_bits_echo_tl_state_size; // @[UserYanker.scala:125:30] wire [4:0] _axi4yank_auto_in_b_bits_echo_tl_state_source; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_b_bits_echo_extra_id; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_ar_ready; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_r_valid; // @[UserYanker.scala:125:30] wire [3:0] _axi4yank_auto_in_r_bits_id; // @[UserYanker.scala:125:30] wire [63:0] _axi4yank_auto_in_r_bits_data; // @[UserYanker.scala:125:30] wire [1:0] _axi4yank_auto_in_r_bits_resp; // @[UserYanker.scala:125:30] wire [3:0] _axi4yank_auto_in_r_bits_echo_tl_state_size; // @[UserYanker.scala:125:30] wire [4:0] _axi4yank_auto_in_r_bits_echo_tl_state_source; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_r_bits_echo_extra_id; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_r_bits_last; // @[UserYanker.scala:125:30] wire auto_widget_anon_in_a_valid_0 = auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_opcode_0 = auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_param_0 = auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_size_0 = auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] auto_widget_anon_in_a_bits_source_0 = auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] auto_widget_anon_in_a_bits_address_0 = auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_widget_anon_in_a_bits_mask_0 = auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_widget_anon_in_a_bits_data_0 = auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_a_bits_corrupt_0 = auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_ready_0 = auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_aw_ready_0 = auto_axi4yank_out_aw_ready; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_w_ready_0 = auto_axi4yank_out_w_ready; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_b_valid_0 = auto_axi4yank_out_b_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_axi4yank_out_b_bits_id_0 = auto_axi4yank_out_b_bits_id; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_axi4yank_out_b_bits_resp_0 = auto_axi4yank_out_b_bits_resp; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_ar_ready_0 = auto_axi4yank_out_ar_ready; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_r_valid_0 = auto_axi4yank_out_r_valid; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_axi4yank_out_r_bits_id_0 = auto_axi4yank_out_r_bits_id; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_axi4yank_out_r_bits_data_0 = auto_axi4yank_out_r_bits_data; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_axi4yank_out_r_bits_resp_0 = auto_axi4yank_out_r_bits_resp; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_r_bits_last_0 = auto_axi4yank_out_r_bits_last; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_tl_out_a_ready_0 = auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_tl_out_d_valid_0 = auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_out_d_bits_opcode_0 = auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_out_d_bits_size_0 = auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] auto_tl_out_d_bits_source_0 = auto_tl_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire auto_tl_out_d_bits_denied_0 = auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_out_d_bits_data_0 = auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_out_d_bits_corrupt_0 = auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28] wire auto_tl_in_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28] wire auto_tl_out_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28] wire widget_auto_anon_in_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28] wire widget_auto_anon_out_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28] wire widget_anonOut_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28] wire widget_anonIn_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28] wire tlOut_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28] wire tlIn_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28] wire [1:0] auto_widget_anon_in_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28] wire [1:0] auto_tl_out_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28] wire [1:0] widget_auto_anon_out_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28] wire [1:0] widget_anonOut_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28] wire [1:0] widget_anonIn_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28] wire [1:0] tlOut_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28] wire [1:0] tlIn_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28] wire widget_auto_anon_in_a_valid = auto_widget_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode = auto_widget_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param = auto_widget_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_size = auto_widget_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] widget_auto_anon_in_a_bits_source = auto_widget_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address = auto_widget_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_a_bits_mask = auto_widget_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_a_bits_data = auto_widget_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_bits_corrupt = auto_widget_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready = auto_widget_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire tlIn_a_ready; // @[MixedNode.scala:551:17] wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [4:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [31:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire tlIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire tlOut_a_ready = auto_tl_out_a_ready_0; // @[MixedNode.scala:542:17] wire tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlOut_d_ready; // @[MixedNode.scala:542:17] wire tlOut_d_valid = auto_tl_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_opcode = auto_tl_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_size = auto_tl_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [4:0] tlOut_d_bits_source = auto_tl_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire tlOut_d_bits_denied = auto_tl_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [63:0] tlOut_d_bits_data = auto_tl_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire tlOut_d_bits_corrupt = auto_tl_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [4:0] auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_axi4yank_out_aw_bits_id_0; // @[LazyModuleImp.scala:138:7] wire [31:0] auto_axi4yank_out_aw_bits_addr_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_axi4yank_out_aw_bits_len_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_axi4yank_out_aw_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_axi4yank_out_aw_bits_burst_0; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_aw_bits_lock_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_axi4yank_out_aw_bits_cache_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_axi4yank_out_aw_bits_prot_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_axi4yank_out_aw_bits_qos_0; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_aw_valid_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_axi4yank_out_w_bits_data_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_axi4yank_out_w_bits_strb_0; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_w_bits_last_0; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_w_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_b_ready_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_axi4yank_out_ar_bits_id_0; // @[LazyModuleImp.scala:138:7] wire [31:0] auto_axi4yank_out_ar_bits_addr_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_axi4yank_out_ar_bits_len_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_axi4yank_out_ar_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_axi4yank_out_ar_bits_burst_0; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_ar_bits_lock_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_axi4yank_out_ar_bits_cache_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_axi4yank_out_ar_bits_prot_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_axi4yank_out_ar_bits_qos_0; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_ar_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_axi4yank_out_r_ready_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [4:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [4:0] auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [31:0] auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign auto_widget_anon_in_a_ready_0 = widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_a_bits_corrupt = widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign auto_widget_anon_in_d_valid_0 = widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_widget_anon_in_d_bits_opcode_0 = widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_widget_anon_in_d_bits_size_0 = widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_widget_anon_in_d_bits_source_0 = widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_widget_anon_in_d_bits_denied_0 = widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_widget_anon_in_d_bits_data_0 = widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_widget_anon_in_d_bits_corrupt_0 = widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_corrupt = widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_corrupt = widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_out_a_valid_0 = tlOut_a_valid; // @[MixedNode.scala:542:17] assign auto_tl_out_a_bits_opcode_0 = tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_tl_out_a_bits_param_0 = tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_tl_out_a_bits_size_0 = tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_tl_out_a_bits_source_0 = tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_tl_out_a_bits_address_0 = tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_tl_out_a_bits_mask_0 = tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_tl_out_a_bits_data_0 = tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_tl_out_a_bits_corrupt_0 = tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_tl_out_d_ready_0 = tlOut_d_ready; // @[MixedNode.scala:542:17] assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17] assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_denied_0 = tlIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_corrupt_0 = tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] AXI4UserYanker axi4yank ( // @[UserYanker.scala:125:30] .clock (clock), .reset (reset), .auto_in_aw_ready (_axi4yank_auto_in_aw_ready), .auto_in_aw_valid (_axi4index_auto_out_aw_valid), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_id (_axi4index_auto_out_aw_bits_id), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_addr (_axi4index_auto_out_aw_bits_addr), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_len (_axi4index_auto_out_aw_bits_len), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_size (_axi4index_auto_out_aw_bits_size), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_burst (_axi4index_auto_out_aw_bits_burst), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_lock (_axi4index_auto_out_aw_bits_lock), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_cache (_axi4index_auto_out_aw_bits_cache), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_prot (_axi4index_auto_out_aw_bits_prot), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_qos (_axi4index_auto_out_aw_bits_qos), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_echo_tl_state_size (_axi4index_auto_out_aw_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_echo_tl_state_source (_axi4index_auto_out_aw_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_echo_extra_id (_axi4index_auto_out_aw_bits_echo_extra_id), // @[IdIndexer.scala:108:31] .auto_in_w_ready (_axi4yank_auto_in_w_ready), .auto_in_w_valid (_axi4index_auto_out_w_valid), // @[IdIndexer.scala:108:31] .auto_in_w_bits_data (_axi4index_auto_out_w_bits_data), // @[IdIndexer.scala:108:31] .auto_in_w_bits_strb (_axi4index_auto_out_w_bits_strb), // @[IdIndexer.scala:108:31] .auto_in_w_bits_last (_axi4index_auto_out_w_bits_last), // @[IdIndexer.scala:108:31] .auto_in_b_ready (_axi4index_auto_out_b_ready), // @[IdIndexer.scala:108:31] .auto_in_b_valid (_axi4yank_auto_in_b_valid), .auto_in_b_bits_id (_axi4yank_auto_in_b_bits_id), .auto_in_b_bits_resp (_axi4yank_auto_in_b_bits_resp), .auto_in_b_bits_echo_tl_state_size (_axi4yank_auto_in_b_bits_echo_tl_state_size), .auto_in_b_bits_echo_tl_state_source (_axi4yank_auto_in_b_bits_echo_tl_state_source), .auto_in_b_bits_echo_extra_id (_axi4yank_auto_in_b_bits_echo_extra_id), .auto_in_ar_ready (_axi4yank_auto_in_ar_ready), .auto_in_ar_valid (_axi4index_auto_out_ar_valid), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_id (_axi4index_auto_out_ar_bits_id), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_addr (_axi4index_auto_out_ar_bits_addr), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_len (_axi4index_auto_out_ar_bits_len), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_size (_axi4index_auto_out_ar_bits_size), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_burst (_axi4index_auto_out_ar_bits_burst), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_lock (_axi4index_auto_out_ar_bits_lock), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_cache (_axi4index_auto_out_ar_bits_cache), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_prot (_axi4index_auto_out_ar_bits_prot), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_qos (_axi4index_auto_out_ar_bits_qos), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_echo_tl_state_size (_axi4index_auto_out_ar_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_echo_tl_state_source (_axi4index_auto_out_ar_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_echo_extra_id (_axi4index_auto_out_ar_bits_echo_extra_id), // @[IdIndexer.scala:108:31] .auto_in_r_ready (_axi4index_auto_out_r_ready), // @[IdIndexer.scala:108:31] .auto_in_r_valid (_axi4yank_auto_in_r_valid), .auto_in_r_bits_id (_axi4yank_auto_in_r_bits_id), .auto_in_r_bits_data (_axi4yank_auto_in_r_bits_data), .auto_in_r_bits_resp (_axi4yank_auto_in_r_bits_resp), .auto_in_r_bits_echo_tl_state_size (_axi4yank_auto_in_r_bits_echo_tl_state_size), .auto_in_r_bits_echo_tl_state_source (_axi4yank_auto_in_r_bits_echo_tl_state_source), .auto_in_r_bits_echo_extra_id (_axi4yank_auto_in_r_bits_echo_extra_id), .auto_in_r_bits_last (_axi4yank_auto_in_r_bits_last), .auto_out_aw_ready (auto_axi4yank_out_aw_ready_0), // @[LazyModuleImp.scala:138:7] .auto_out_aw_valid (auto_axi4yank_out_aw_valid_0), .auto_out_aw_bits_id (auto_axi4yank_out_aw_bits_id_0), .auto_out_aw_bits_addr (auto_axi4yank_out_aw_bits_addr_0), .auto_out_aw_bits_len (auto_axi4yank_out_aw_bits_len_0), .auto_out_aw_bits_size (auto_axi4yank_out_aw_bits_size_0), .auto_out_aw_bits_burst (auto_axi4yank_out_aw_bits_burst_0), .auto_out_aw_bits_lock (auto_axi4yank_out_aw_bits_lock_0), .auto_out_aw_bits_cache (auto_axi4yank_out_aw_bits_cache_0), .auto_out_aw_bits_prot (auto_axi4yank_out_aw_bits_prot_0), .auto_out_aw_bits_qos (auto_axi4yank_out_aw_bits_qos_0), .auto_out_w_ready (auto_axi4yank_out_w_ready_0), // @[LazyModuleImp.scala:138:7] .auto_out_w_valid (auto_axi4yank_out_w_valid_0), .auto_out_w_bits_data (auto_axi4yank_out_w_bits_data_0), .auto_out_w_bits_strb (auto_axi4yank_out_w_bits_strb_0), .auto_out_w_bits_last (auto_axi4yank_out_w_bits_last_0), .auto_out_b_ready (auto_axi4yank_out_b_ready_0), .auto_out_b_valid (auto_axi4yank_out_b_valid_0), // @[LazyModuleImp.scala:138:7] .auto_out_b_bits_id (auto_axi4yank_out_b_bits_id_0), // @[LazyModuleImp.scala:138:7] .auto_out_b_bits_resp (auto_axi4yank_out_b_bits_resp_0), // @[LazyModuleImp.scala:138:7] .auto_out_ar_ready (auto_axi4yank_out_ar_ready_0), // @[LazyModuleImp.scala:138:7] .auto_out_ar_valid (auto_axi4yank_out_ar_valid_0), .auto_out_ar_bits_id (auto_axi4yank_out_ar_bits_id_0), .auto_out_ar_bits_addr (auto_axi4yank_out_ar_bits_addr_0), .auto_out_ar_bits_len (auto_axi4yank_out_ar_bits_len_0), .auto_out_ar_bits_size (auto_axi4yank_out_ar_bits_size_0), .auto_out_ar_bits_burst (auto_axi4yank_out_ar_bits_burst_0), .auto_out_ar_bits_lock (auto_axi4yank_out_ar_bits_lock_0), .auto_out_ar_bits_cache (auto_axi4yank_out_ar_bits_cache_0), .auto_out_ar_bits_prot (auto_axi4yank_out_ar_bits_prot_0), .auto_out_ar_bits_qos (auto_axi4yank_out_ar_bits_qos_0), .auto_out_r_ready (auto_axi4yank_out_r_ready_0), .auto_out_r_valid (auto_axi4yank_out_r_valid_0), // @[LazyModuleImp.scala:138:7] .auto_out_r_bits_id (auto_axi4yank_out_r_bits_id_0), // @[LazyModuleImp.scala:138:7] .auto_out_r_bits_data (auto_axi4yank_out_r_bits_data_0), // @[LazyModuleImp.scala:138:7] .auto_out_r_bits_resp (auto_axi4yank_out_r_bits_resp_0), // @[LazyModuleImp.scala:138:7] .auto_out_r_bits_last (auto_axi4yank_out_r_bits_last_0) // @[LazyModuleImp.scala:138:7] ); // @[UserYanker.scala:125:30] AXI4IdIndexer axi4index ( // @[IdIndexer.scala:108:31] .clock (clock), .reset (reset), .auto_in_aw_ready (_axi4index_auto_in_aw_ready), .auto_in_aw_valid (_tl2axi4_auto_out_aw_valid), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_id (_tl2axi4_auto_out_aw_bits_id), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_addr (_tl2axi4_auto_out_aw_bits_addr), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_len (_tl2axi4_auto_out_aw_bits_len), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_size (_tl2axi4_auto_out_aw_bits_size), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_burst (_tl2axi4_auto_out_aw_bits_burst), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_lock (_tl2axi4_auto_out_aw_bits_lock), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_cache (_tl2axi4_auto_out_aw_bits_cache), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_prot (_tl2axi4_auto_out_aw_bits_prot), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_qos (_tl2axi4_auto_out_aw_bits_qos), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_echo_tl_state_size (_tl2axi4_auto_out_aw_bits_echo_tl_state_size), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_echo_tl_state_source (_tl2axi4_auto_out_aw_bits_echo_tl_state_source), // @[ToAXI4.scala:301:29] .auto_in_w_ready (_axi4index_auto_in_w_ready), .auto_in_w_valid (_tl2axi4_auto_out_w_valid), // @[ToAXI4.scala:301:29] .auto_in_w_bits_data (_tl2axi4_auto_out_w_bits_data), // @[ToAXI4.scala:301:29] .auto_in_w_bits_strb (_tl2axi4_auto_out_w_bits_strb), // @[ToAXI4.scala:301:29] .auto_in_w_bits_last (_tl2axi4_auto_out_w_bits_last), // @[ToAXI4.scala:301:29] .auto_in_b_ready (_tl2axi4_auto_out_b_ready), // @[ToAXI4.scala:301:29] .auto_in_b_valid (_axi4index_auto_in_b_valid), .auto_in_b_bits_id (_axi4index_auto_in_b_bits_id), .auto_in_b_bits_resp (_axi4index_auto_in_b_bits_resp), .auto_in_b_bits_echo_tl_state_size (_axi4index_auto_in_b_bits_echo_tl_state_size), .auto_in_b_bits_echo_tl_state_source (_axi4index_auto_in_b_bits_echo_tl_state_source), .auto_in_ar_ready (_axi4index_auto_in_ar_ready), .auto_in_ar_valid (_tl2axi4_auto_out_ar_valid), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_id (_tl2axi4_auto_out_ar_bits_id), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_addr (_tl2axi4_auto_out_ar_bits_addr), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_len (_tl2axi4_auto_out_ar_bits_len), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_size (_tl2axi4_auto_out_ar_bits_size), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_burst (_tl2axi4_auto_out_ar_bits_burst), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_lock (_tl2axi4_auto_out_ar_bits_lock), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_cache (_tl2axi4_auto_out_ar_bits_cache), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_prot (_tl2axi4_auto_out_ar_bits_prot), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_qos (_tl2axi4_auto_out_ar_bits_qos), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_echo_tl_state_size (_tl2axi4_auto_out_ar_bits_echo_tl_state_size), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_echo_tl_state_source (_tl2axi4_auto_out_ar_bits_echo_tl_state_source), // @[ToAXI4.scala:301:29] .auto_in_r_ready (_tl2axi4_auto_out_r_ready), // @[ToAXI4.scala:301:29] .auto_in_r_valid (_axi4index_auto_in_r_valid), .auto_in_r_bits_id (_axi4index_auto_in_r_bits_id), .auto_in_r_bits_data (_axi4index_auto_in_r_bits_data), .auto_in_r_bits_resp (_axi4index_auto_in_r_bits_resp), .auto_in_r_bits_echo_tl_state_size (_axi4index_auto_in_r_bits_echo_tl_state_size), .auto_in_r_bits_echo_tl_state_source (_axi4index_auto_in_r_bits_echo_tl_state_source), .auto_in_r_bits_last (_axi4index_auto_in_r_bits_last), .auto_out_aw_ready (_axi4yank_auto_in_aw_ready), // @[UserYanker.scala:125:30] .auto_out_aw_valid (_axi4index_auto_out_aw_valid), .auto_out_aw_bits_id (_axi4index_auto_out_aw_bits_id), .auto_out_aw_bits_addr (_axi4index_auto_out_aw_bits_addr), .auto_out_aw_bits_len (_axi4index_auto_out_aw_bits_len), .auto_out_aw_bits_size (_axi4index_auto_out_aw_bits_size), .auto_out_aw_bits_burst (_axi4index_auto_out_aw_bits_burst), .auto_out_aw_bits_lock (_axi4index_auto_out_aw_bits_lock), .auto_out_aw_bits_cache (_axi4index_auto_out_aw_bits_cache), .auto_out_aw_bits_prot (_axi4index_auto_out_aw_bits_prot), .auto_out_aw_bits_qos (_axi4index_auto_out_aw_bits_qos), .auto_out_aw_bits_echo_tl_state_size (_axi4index_auto_out_aw_bits_echo_tl_state_size), .auto_out_aw_bits_echo_tl_state_source (_axi4index_auto_out_aw_bits_echo_tl_state_source), .auto_out_aw_bits_echo_extra_id (_axi4index_auto_out_aw_bits_echo_extra_id), .auto_out_w_ready (_axi4yank_auto_in_w_ready), // @[UserYanker.scala:125:30] .auto_out_w_valid (_axi4index_auto_out_w_valid), .auto_out_w_bits_data (_axi4index_auto_out_w_bits_data), .auto_out_w_bits_strb (_axi4index_auto_out_w_bits_strb), .auto_out_w_bits_last (_axi4index_auto_out_w_bits_last), .auto_out_b_ready (_axi4index_auto_out_b_ready), .auto_out_b_valid (_axi4yank_auto_in_b_valid), // @[UserYanker.scala:125:30] .auto_out_b_bits_id (_axi4yank_auto_in_b_bits_id), // @[UserYanker.scala:125:30] .auto_out_b_bits_resp (_axi4yank_auto_in_b_bits_resp), // @[UserYanker.scala:125:30] .auto_out_b_bits_echo_tl_state_size (_axi4yank_auto_in_b_bits_echo_tl_state_size), // @[UserYanker.scala:125:30] .auto_out_b_bits_echo_tl_state_source (_axi4yank_auto_in_b_bits_echo_tl_state_source), // @[UserYanker.scala:125:30] .auto_out_b_bits_echo_extra_id (_axi4yank_auto_in_b_bits_echo_extra_id), // @[UserYanker.scala:125:30] .auto_out_ar_ready (_axi4yank_auto_in_ar_ready), // @[UserYanker.scala:125:30] .auto_out_ar_valid (_axi4index_auto_out_ar_valid), .auto_out_ar_bits_id (_axi4index_auto_out_ar_bits_id), .auto_out_ar_bits_addr (_axi4index_auto_out_ar_bits_addr), .auto_out_ar_bits_len (_axi4index_auto_out_ar_bits_len), .auto_out_ar_bits_size (_axi4index_auto_out_ar_bits_size), .auto_out_ar_bits_burst (_axi4index_auto_out_ar_bits_burst), .auto_out_ar_bits_lock (_axi4index_auto_out_ar_bits_lock), .auto_out_ar_bits_cache (_axi4index_auto_out_ar_bits_cache), .auto_out_ar_bits_prot (_axi4index_auto_out_ar_bits_prot), .auto_out_ar_bits_qos (_axi4index_auto_out_ar_bits_qos), .auto_out_ar_bits_echo_tl_state_size (_axi4index_auto_out_ar_bits_echo_tl_state_size), .auto_out_ar_bits_echo_tl_state_source (_axi4index_auto_out_ar_bits_echo_tl_state_source), .auto_out_ar_bits_echo_extra_id (_axi4index_auto_out_ar_bits_echo_extra_id), .auto_out_r_ready (_axi4index_auto_out_r_ready), .auto_out_r_valid (_axi4yank_auto_in_r_valid), // @[UserYanker.scala:125:30] .auto_out_r_bits_id (_axi4yank_auto_in_r_bits_id), // @[UserYanker.scala:125:30] .auto_out_r_bits_data (_axi4yank_auto_in_r_bits_data), // @[UserYanker.scala:125:30] .auto_out_r_bits_resp (_axi4yank_auto_in_r_bits_resp), // @[UserYanker.scala:125:30] .auto_out_r_bits_echo_tl_state_size (_axi4yank_auto_in_r_bits_echo_tl_state_size), // @[UserYanker.scala:125:30] .auto_out_r_bits_echo_tl_state_source (_axi4yank_auto_in_r_bits_echo_tl_state_source), // @[UserYanker.scala:125:30] .auto_out_r_bits_echo_extra_id (_axi4yank_auto_in_r_bits_echo_extra_id), // @[UserYanker.scala:125:30] .auto_out_r_bits_last (_axi4yank_auto_in_r_bits_last) // @[UserYanker.scala:125:30] ); // @[IdIndexer.scala:108:31] TLToAXI4 tl2axi4 ( // @[ToAXI4.scala:301:29] .clock (clock), .reset (reset), .auto_in_a_ready (widget_auto_anon_out_a_ready), .auto_in_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_in_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9] .auto_in_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9] .auto_in_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9] .auto_in_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9] .auto_in_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_in_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9] .auto_in_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9] .auto_in_a_bits_corrupt (widget_auto_anon_out_a_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_in_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9] .auto_in_d_valid (widget_auto_anon_out_d_valid), .auto_in_d_bits_opcode (widget_auto_anon_out_d_bits_opcode), .auto_in_d_bits_size (widget_auto_anon_out_d_bits_size), .auto_in_d_bits_source (widget_auto_anon_out_d_bits_source), .auto_in_d_bits_denied (widget_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (widget_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt), .auto_out_aw_ready (_axi4index_auto_in_aw_ready), // @[IdIndexer.scala:108:31] .auto_out_aw_valid (_tl2axi4_auto_out_aw_valid), .auto_out_aw_bits_id (_tl2axi4_auto_out_aw_bits_id), .auto_out_aw_bits_addr (_tl2axi4_auto_out_aw_bits_addr), .auto_out_aw_bits_len (_tl2axi4_auto_out_aw_bits_len), .auto_out_aw_bits_size (_tl2axi4_auto_out_aw_bits_size), .auto_out_aw_bits_burst (_tl2axi4_auto_out_aw_bits_burst), .auto_out_aw_bits_lock (_tl2axi4_auto_out_aw_bits_lock), .auto_out_aw_bits_cache (_tl2axi4_auto_out_aw_bits_cache), .auto_out_aw_bits_prot (_tl2axi4_auto_out_aw_bits_prot), .auto_out_aw_bits_qos (_tl2axi4_auto_out_aw_bits_qos), .auto_out_aw_bits_echo_tl_state_size (_tl2axi4_auto_out_aw_bits_echo_tl_state_size), .auto_out_aw_bits_echo_tl_state_source (_tl2axi4_auto_out_aw_bits_echo_tl_state_source), .auto_out_w_ready (_axi4index_auto_in_w_ready), // @[IdIndexer.scala:108:31] .auto_out_w_valid (_tl2axi4_auto_out_w_valid), .auto_out_w_bits_data (_tl2axi4_auto_out_w_bits_data), .auto_out_w_bits_strb (_tl2axi4_auto_out_w_bits_strb), .auto_out_w_bits_last (_tl2axi4_auto_out_w_bits_last), .auto_out_b_ready (_tl2axi4_auto_out_b_ready), .auto_out_b_valid (_axi4index_auto_in_b_valid), // @[IdIndexer.scala:108:31] .auto_out_b_bits_id (_axi4index_auto_in_b_bits_id), // @[IdIndexer.scala:108:31] .auto_out_b_bits_resp (_axi4index_auto_in_b_bits_resp), // @[IdIndexer.scala:108:31] .auto_out_b_bits_echo_tl_state_size (_axi4index_auto_in_b_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31] .auto_out_b_bits_echo_tl_state_source (_axi4index_auto_in_b_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31] .auto_out_ar_ready (_axi4index_auto_in_ar_ready), // @[IdIndexer.scala:108:31] .auto_out_ar_valid (_tl2axi4_auto_out_ar_valid), .auto_out_ar_bits_id (_tl2axi4_auto_out_ar_bits_id), .auto_out_ar_bits_addr (_tl2axi4_auto_out_ar_bits_addr), .auto_out_ar_bits_len (_tl2axi4_auto_out_ar_bits_len), .auto_out_ar_bits_size (_tl2axi4_auto_out_ar_bits_size), .auto_out_ar_bits_burst (_tl2axi4_auto_out_ar_bits_burst), .auto_out_ar_bits_lock (_tl2axi4_auto_out_ar_bits_lock), .auto_out_ar_bits_cache (_tl2axi4_auto_out_ar_bits_cache), .auto_out_ar_bits_prot (_tl2axi4_auto_out_ar_bits_prot), .auto_out_ar_bits_qos (_tl2axi4_auto_out_ar_bits_qos), .auto_out_ar_bits_echo_tl_state_size (_tl2axi4_auto_out_ar_bits_echo_tl_state_size), .auto_out_ar_bits_echo_tl_state_source (_tl2axi4_auto_out_ar_bits_echo_tl_state_source), .auto_out_r_ready (_tl2axi4_auto_out_r_ready), .auto_out_r_valid (_axi4index_auto_in_r_valid), // @[IdIndexer.scala:108:31] .auto_out_r_bits_id (_axi4index_auto_in_r_bits_id), // @[IdIndexer.scala:108:31] .auto_out_r_bits_data (_axi4index_auto_in_r_bits_data), // @[IdIndexer.scala:108:31] .auto_out_r_bits_resp (_axi4index_auto_in_r_bits_resp), // @[IdIndexer.scala:108:31] .auto_out_r_bits_echo_tl_state_size (_axi4index_auto_in_r_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31] .auto_out_r_bits_echo_tl_state_source (_axi4index_auto_in_r_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31] .auto_out_r_bits_last (_axi4index_auto_in_r_bits_last) // @[IdIndexer.scala:108:31] ); // @[ToAXI4.scala:301:29] assign auto_widget_anon_in_a_ready = auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_valid = auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_opcode = auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_size = auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_source = auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_denied = auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_data = auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_corrupt = auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_aw_valid = auto_axi4yank_out_aw_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_aw_bits_id = auto_axi4yank_out_aw_bits_id_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_aw_bits_addr = auto_axi4yank_out_aw_bits_addr_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_aw_bits_len = auto_axi4yank_out_aw_bits_len_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_aw_bits_size = auto_axi4yank_out_aw_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_aw_bits_burst = auto_axi4yank_out_aw_bits_burst_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_aw_bits_lock = auto_axi4yank_out_aw_bits_lock_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_aw_bits_cache = auto_axi4yank_out_aw_bits_cache_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_aw_bits_prot = auto_axi4yank_out_aw_bits_prot_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_aw_bits_qos = auto_axi4yank_out_aw_bits_qos_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_w_valid = auto_axi4yank_out_w_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_w_bits_data = auto_axi4yank_out_w_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_w_bits_strb = auto_axi4yank_out_w_bits_strb_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_w_bits_last = auto_axi4yank_out_w_bits_last_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_b_ready = auto_axi4yank_out_b_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_ar_valid = auto_axi4yank_out_ar_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_ar_bits_id = auto_axi4yank_out_ar_bits_id_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_ar_bits_addr = auto_axi4yank_out_ar_bits_addr_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_ar_bits_len = auto_axi4yank_out_ar_bits_len_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_ar_bits_size = auto_axi4yank_out_ar_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_ar_bits_burst = auto_axi4yank_out_ar_bits_burst_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_ar_bits_lock = auto_axi4yank_out_ar_bits_lock_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_ar_bits_cache = auto_axi4yank_out_ar_bits_cache_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_ar_bits_prot = auto_axi4yank_out_ar_bits_prot_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_ar_bits_qos = auto_axi4yank_out_ar_bits_qos_0; // @[LazyModuleImp.scala:138:7] assign auto_axi4yank_out_r_ready = auto_axi4yank_out_r_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_denied = auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_corrupt = auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_valid = auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_opcode = auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_param = auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_size = auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_source = auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_address = auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_mask = auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_data = auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_corrupt = auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_d_ready = auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_7 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_18 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = io_in_d_bits_source_0[2]; // @[Monitor.scala:36:7] wire _source_ok_T_8 = ~_source_ok_T_7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = io_in_d_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T = io_in_b_bits_source_0[2]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = ~_legal_source_T; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_5 = _legal_source_T_3; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [2:0] _legal_source_T_8 = {_legal_source_WIRE_1, 2'h0}; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_9 = _legal_source_T_8; // @[Mux.scala:30:73] wire [2:0] _legal_source_WIRE_1_0 = _legal_source_T_9; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = io_in_c_bits_source_0[2]; // @[Monitor.scala:36:7] wire _source_ok_T_15 = ~_source_ok_T_14; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_19 = _source_ok_T_17; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_0 = _source_ok_T_19; // @[Parameters.scala:1138:31] wire _source_ok_T_20 = io_in_c_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_20; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire _T_2479 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2479; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2479; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2553 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2553; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [2:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2550 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2550; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2550; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [4:0] inflight; // @[Monitor.scala:614:27] reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [4:0] a_set; // @[Monitor.scala:626:34] wire [4:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [19:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [5:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [5:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [5:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [5:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [5:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [19:0] _a_opcode_lookup_T_6 = {16'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [19:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [5:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [5:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [5:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [5:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [5:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {32'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [7:0] _GEN_21 = 8'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [7:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2405 = _T_2479 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2405 ? _a_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2405 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2405 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [5:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [66:0] _a_opcodes_set_T_1 = {63'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2405 ? _a_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [5:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [67:0] _a_sizes_set_T_1 = {63'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2405 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [4:0] d_clr; // @[Monitor.scala:664:34] wire [4:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [19:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2451 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [7:0] _GEN_23 = 8'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2451 & ~d_release_ack ? _d_clr_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2420 = _T_2553 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2420 ? _d_clr_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_5 = 79'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2420 ? _d_opcodes_clr_T_5[19:0] : 20'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [78:0] _d_sizes_clr_T_5 = 79'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2420 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [4:0] inflight_1; // @[Monitor.scala:726:35] reg [19:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [4:0] c_set; // @[Monitor.scala:738:34] wire [4:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [19:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [19:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [19:0] _c_opcode_lookup_T_6 = {16'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [19:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {32'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [7:0] _GEN_24 = 8'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [7:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2492 = _T_2550 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2492 ? _c_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2492 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2492 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [5:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [66:0] _c_opcodes_set_T_1 = {63'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2492 ? _c_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [5:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [67:0] _c_sizes_set_T_1 = {63'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2492 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [4:0] d_clr_1; // @[Monitor.scala:774:34] wire [4:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [19:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2523 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2523 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2505 = _T_2553 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2505 ? _d_clr_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_11 = 79'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2505 ? _d_opcodes_clr_T_11[19:0] : 20'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [78:0] _d_sizes_clr_T_11 = 79'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2505 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [4:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [4:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [19:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [19:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2559 = _T_2553 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2559 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2568 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2568 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module Router_22( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_4_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32] wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_4_0_valid; // @[Router.scala:131:24] wire _switch_io_out_4_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_4_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_4_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_4_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_4_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_3_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_4_to_15_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_4_to_15_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_4_to_15_io_out_valid; // @[Router.scala:125:13] wire _output_unit_3_to_10_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_3_to_10_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_3_to_10_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_10_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_7_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_7_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_5_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_1_to_5_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_1_to_5_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_5_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_2_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_2_io_channel_status_1_occupied; // @[Router.scala:122:13] wire [3:0] _ingress_unit_4_from_15_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_15_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_4_from_15_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_4_from_15_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_4_from_15_io_in_ready; // @[Router.scala:116:13] wire _input_unit_3_from_10_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_10_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_10_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_10_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_10_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_3_from_10_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_10_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_10_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_3_from_10_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_10_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_3_from_10_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_7_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_7_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_7_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_7_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_2_from_7_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_7_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_7_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_2_from_7_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_7_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_7_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_1_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_1_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_2_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_2_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_2_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_2_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_2_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_2_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_5_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_7_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _input_unit_3_from_10_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_4_ready & _ingress_unit_4_from_15_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module InputUnit_42( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_21( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_33 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = source_ok_uncommonBits_5 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_38 = _source_ok_T_36 & _source_ok_T_37; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_51 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_52 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_54 = _source_ok_T_53 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_60 = _source_ok_T_59 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_66 = _source_ok_T_65 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_81 = source_ok_uncommonBits_10 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_82 = _source_ok_T_80 & _source_ok_T_81; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_89 = source_ok_uncommonBits_11 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_90 = _source_ok_T_88 & _source_ok_T_89; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_8 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_103 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _T_1315 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1315; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1315; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1388 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1388; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1388; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1388; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1241 = _T_1315 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1241 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1241 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1241 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1241 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1241 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1287 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1287 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1256 = _T_1388 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1256 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1256 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1256 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1359 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1359 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1341 = _T_1388 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1341 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1341 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1341 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Serdes.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config._ class GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module { override def desiredName = s"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(t)) val out = Decoupled(new Flit(flitWidth)) val busy = Output(Bool()) }) val dataBits = t.getWidth.max(flitWidth) val dataBeats = (dataBits - 1) / flitWidth + 1 require(dataBeats >= 1) val data = Reg(Vec(dataBeats, UInt(flitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready && beat === 0.U io.out.valid := io.in.valid || beat =/= 0.U io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat)) when (io.out.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W))) data(0) := DontCare // unused, DCE this } } io.busy := io.out.valid } class GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module { override def desiredName = s"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(t) val busy = Output(Bool()) }) val dataBits = t.getWidth.max(flitWidth) val dataBeats = (dataBits - 1) / flitWidth + 1 require(dataBeats >= 1) val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready || beat =/= (dataBeats-1).U io.out.valid := io.in.valid && beat === (dataBeats-1).U io.out.bits := (if (dataBeats == 1) { io.in.bits.flit.asTypeOf(t) } else { Cat(io.in.bits.flit, data.asUInt).asTypeOf(t) }) when (io.in.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) if (dataBeats > 1) { when (beat =/= (dataBeats-1).U) { data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit } } } io.busy := beat =/= 0.U } class FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module { override def desiredName = s"FlitToPhit_f${flitWidth}_p${phitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Phit(phitWidth)) }) require(flitWidth >= phitWidth) val dataBeats = (flitWidth - 1) / phitWidth + 1 val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready && beat === 0.U io.out.valid := io.in.valid || beat =/= 0.U io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U))) when (io.out.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail } } } object FlitToPhit { def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = { val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth)) flit2phit.io.in <> flit flit2phit.io.out } } class PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module { override def desiredName = s"PhitToFlit_p${phitWidth}_f${flitWidth}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Phit(phitWidth))) val out = Decoupled(new Flit(flitWidth)) }) require(flitWidth >= phitWidth) val dataBeats = (flitWidth - 1) / phitWidth + 1 val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W))) val beat = RegInit(0.U(log2Ceil(dataBeats).W)) io.in.ready := io.out.ready || beat =/= (dataBeats-1).U io.out.valid := io.in.valid && beat === (dataBeats-1).U io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt)) when (io.in.fire) { beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U) if (dataBeats > 1) { when (beat =/= (dataBeats-1).U) { data(beat) := io.in.bits.phit } } } } object PhitToFlit { def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = { val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth)) phit2flit.io.in <> phit phit2flit.io.out } def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = { val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth)) phit2flit.io.in.valid := phit.valid phit2flit.io.in.bits := phit.bits when (phit.valid) { assert(phit2flit.io.in.ready) } val out = Wire(Valid(new Flit(flitWidth))) out.valid := phit2flit.io.out.valid out.bits := phit2flit.io.out.bits phit2flit.io.out.ready := true.B out } } class PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module { override def desiredName = s"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}" val io = IO(new Bundle { val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth)))) val out = Decoupled(new Phit(phitWidth)) }) if (channels == 1) { io.out <> io.in(0) } else { val headerWidth = log2Ceil(channels) val headerBeats = (headerWidth - 1) / phitWidth + 1 val flitBeats = (flitWidth - 1) / phitWidth + 1 val beats = headerBeats + flitBeats val beat = RegInit(0.U(log2Ceil(beats).W)) val chosen_reg = Reg(UInt(headerWidth.W)) val chosen_prio = PriorityEncoder(io.in.map(_.valid)) val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg) val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0) io.out.valid := VecInit(io.in.map(_.valid))(chosen) io.out.bits.phit := Mux(beat < headerBeats.U, chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx), VecInit(io.in.map(_.bits.phit))(chosen)) for (i <- 0 until channels) { io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U } when (io.out.fire) { beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U) when (beat === 0.U) { chosen_reg := chosen_prio } } } } class PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module { override def desiredName = s"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Phit(phitWidth))) val out = Vec(channels, Decoupled(new Phit(phitWidth))) }) if (channels == 1) { io.out(0) <> io.in } else { val headerWidth = log2Ceil(channels) val headerBeats = (headerWidth - 1) / phitWidth + 1 val flitBeats = (flitWidth - 1) / phitWidth + 1 val beats = headerBeats + flitBeats val beat = RegInit(0.U(log2Ceil(beats).W)) val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W))) val channel = channel_vec.asUInt(log2Ceil(channels)-1,0) val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0) io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel) for (c <- 0 until channels) { io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U io.out(c).bits.phit := io.in.bits.phit } when (io.in.fire) { beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U) when (beat < headerBeats.U) { channel_vec(header_idx) := io.in.bits.phit } } } } class DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module { override def desiredName = s"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Flit(flitWidth)) val credit = Flipped(Decoupled(new Flit(flitWidth))) }) val creditWidth = log2Ceil(bufferSz) require(creditWidth <= flitWidth) val credits = RegInit(0.U((creditWidth+1).W)) val credit_incr = io.out.fire val credit_decr = io.credit.fire when (credit_incr || credit_decr) { credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U) } io.out.valid := io.in.valid && credits < bufferSz.U io.out.bits.flit := io.in.bits.flit io.in.ready := io.out.ready && credits < bufferSz.U io.credit.ready := true.B } class CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module { override def desiredName = s"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}" val io = IO(new Bundle { val in = Flipped(Decoupled(new Flit(flitWidth))) val out = Decoupled(new Flit(flitWidth)) val credit = Decoupled(new Flit(flitWidth)) }) val creditWidth = log2Ceil(bufferSz) require(creditWidth <= flitWidth) val buffer = Module(new Queue(new Flit(flitWidth), bufferSz)) val credits = RegInit(0.U((creditWidth+1).W)) val credit_incr = buffer.io.deq.fire val credit_decr = io.credit.fire when (credit_incr || credit_decr) { credits := credit_incr + Mux(credit_decr, 0.U, credits) } buffer.io.enq.valid := io.in.valid buffer.io.enq.bits := io.in.bits io.in.ready := true.B when (io.in.valid) { assert(buffer.io.enq.ready) } io.out <> buffer.io.deq io.credit.valid := credits =/= 0.U io.credit.bits.flit := credits - 1.U }
module PhitToFlit_p32_f32_4( // @[Serdes.scala:103:7] input clock, // @[Serdes.scala:103:7] input reset, // @[Serdes.scala:103:7] output io_in_ready, // @[Serdes.scala:105:14] input io_in_valid, // @[Serdes.scala:105:14] input [31:0] io_in_bits_phit, // @[Serdes.scala:105:14] input io_out_ready, // @[Serdes.scala:105:14] output io_out_valid, // @[Serdes.scala:105:14] output [31:0] io_out_bits_flit // @[Serdes.scala:105:14] ); wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:103:7] wire [31:0] io_in_bits_phit_0 = io_in_bits_phit; // @[Serdes.scala:103:7] wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:103:7] wire [1:0] _beat_T_1 = 2'h1; // @[Serdes.scala:120:53] wire _io_out_valid_T = 1'h1; // @[Serdes.scala:116:39] wire _beat_T = 1'h1; // @[Serdes.scala:120:22] wire _beat_T_2 = 1'h1; // @[Serdes.scala:120:53] wire _io_in_ready_T = 1'h0; // @[Serdes.scala:115:39] wire _io_in_ready_T_1; // @[Serdes.scala:115:31] wire _beat_T_3 = 1'h0; // @[Serdes.scala:120:16] wire _io_out_valid_T_1 = io_in_valid_0; // @[Serdes.scala:103:7, :116:31] wire [31:0] io_out_bits_flit_0 = io_in_bits_phit_0; // @[Serdes.scala:103:7] assign _io_in_ready_T_1 = io_out_ready_0; // @[Serdes.scala:103:7, :115:31] wire io_in_ready_0; // @[Serdes.scala:103:7] wire io_out_valid_0; // @[Serdes.scala:103:7] assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:103:7, :115:31] assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:103:7, :116:31] assign io_in_ready = io_in_ready_0; // @[Serdes.scala:103:7] assign io_out_valid = io_out_valid_0; // @[Serdes.scala:103:7] assign io_out_bits_flit = io_out_bits_flit_0; // @[Serdes.scala:103:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_26( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_36 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File LoadSegmenter.scala: package saturn.mem import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ class LoadSegmenter(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val valid = Input(Bool()) val done = Output(Bool()) val op = Input(new VectorMemMacroOp) val compactor = Decoupled(new CompactorReq(dLenB)) val compactor_data = Input(UInt(dLen.W)) val resp = Decoupled(new Bundle { val data = UInt(dLen.W) val debug_id = UInt(debugIdSz.W) }) }) val segbuf = Module(new LoadSegmentBuffer(vParams.doubleBufferSegments)) val r_eidx = Reg(UInt(log2Ceil(maxVLMax).W)) val r_head = RegInit(true.B) val r_sidx = Reg(UInt(3.W)) val eidx = Mux(r_head, io.op.vstart, r_eidx) val sidx = Mux(r_head, io.op.segstart, r_sidx) val mem_size = io.op.elem_size val incr = (dLenB.U - (Mux(io.op.seg_nf === 0.U, eidx, sidx) << mem_size)(dLenOffBits-1,0)) >> mem_size val eidx_incr = Mux(io.op.seg_nf =/= 0.U, 1.U, incr) val sidx_incr = incr val next_eidx = eidx +& eidx_incr val next_sidx = sidx +& sidx_incr val sidx_tail = next_sidx > io.op.seg_nf val eidx_tail = next_eidx >= io.op.vl when (io.op.seg_nf === 0.U) { io.compactor.valid := io.valid && !segbuf.io.busy && io.resp.ready io.compactor.bits.head := eidx << mem_size io.compactor.bits.tail := Mux(eidx_tail, io.op.vl << mem_size, 0.U) } .otherwise { io.compactor.valid := io.valid && segbuf.io.in.ready io.compactor.bits.head := sidx << mem_size io.compactor.bits.tail := Mux(sidx_tail, (io.op.nf +& 1.U) << mem_size, 0.U) } segbuf.io.in.valid := io.valid && io.op.seg_nf =/= 0.U && io.compactor.ready segbuf.io.in.bits.eew := mem_size segbuf.io.in.bits.nf := io.op.nf segbuf.io.in.bits.data := io.compactor_data segbuf.io.in.bits.eidx := eidx segbuf.io.in.bits.sidx := sidx segbuf.io.in.bits.sidx_tail := sidx_tail segbuf.io.in.bits.tail := eidx_tail segbuf.io.in.bits.segstart := io.op.segstart segbuf.io.in.bits.debug_id := io.op.debug_id segbuf.io.out.ready := io.resp.ready io.resp.valid := Mux(segbuf.io.busy, segbuf.io.out.valid, io.compactor.ready && io.valid && io.op.seg_nf === 0.U) io.resp.bits.data := Mux(segbuf.io.busy, segbuf.io.out.bits.data, io.compactor_data) io.resp.bits.debug_id := Mux(segbuf.io.busy, segbuf.io.out.bits.debug_id, io.op.debug_id) val seg_ready = Mux(io.op.seg_nf === 0.U, !segbuf.io.busy && io.compactor.ready && io.resp.ready, segbuf.io.in.ready && io.compactor.ready && sidx_tail) when (segbuf.io.in.fire) { r_head := false.B when (r_head) { r_eidx := io.op.vstart } r_sidx := next_sidx when (next_sidx > io.op.nf) { r_sidx := 0.U } } io.done := false.B when (seg_ready && io.valid) { r_head := eidx_tail r_eidx := next_eidx io.done := eidx_tail } } File Bundles.scala: package saturn.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ class VectorMemMacroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val debug_id = UInt(debugIdSz.W) val base_offset = UInt(pgIdxBits.W) val page = UInt((paddrBits - pgIdxBits).W) val stride = UInt(pgIdxBits.W) val segstart = UInt(3.W) val segend = UInt(3.W) val vstart = UInt(log2Ceil(maxVLMax).W) val vl = UInt((1+log2Ceil(maxVLMax)).W) val mop = UInt(2.W) val vm = Bool() val nf = UInt(3.W) val idx_size = UInt(2.W) val elem_size = UInt(2.W) val whole_reg = Bool() val store = Bool() val fast_sg = Bool() def indexed = !mop.isOneOf(mopUnit, mopStrided) def seg_nf = Mux(whole_reg, 0.U, nf) def wr_nf = Mux(whole_reg, nf, 0.U) } class VectorIssueInst(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val pc = UInt(vaddrBitsExtended.W) val bits = UInt(32.W) val vconfig = new VConfig val vstart = UInt(log2Ceil(maxVLMax).W) val segstart = UInt(3.W) val segend = UInt(3.W) val rs1_data = UInt(xLen.W) val rs2_data = UInt(xLen.W) val page = UInt((paddrBits - pgIdxBits).W) val vat = UInt(vParams.vatSz.W) val rm = UInt(3.W) val emul = UInt(2.W) val fast_sg = Bool() val debug_id = UInt(debugIdSz.W) val mop = UInt(2.W) // stored separately from bits since dispatch may need to set this def opcode = bits(6,0) def store = opcode(5) def mem_idx_size = bits(13,12) def mem_elem_size = Mux(mop(0), vconfig.vtype.vsew, bits(13,12)) def vm = bits(25) def orig_mop = bits(27,26) def umop = bits(24,20) def nf = bits(31,29) def wr = orig_mop === mopUnit && umop === lumopWhole def seg_nf = Mux(wr, 0.U, nf) def wr_nf = Mux(wr, nf, 0.U) def vmu = opcode.isOneOf(opcLoad, opcStore) def rs1 = bits(19,15) def rs2 = bits(24,20) def rd = bits(11,7) def may_write_v0 = rd === 0.U && opcode =/= opcStore def funct3 = bits(14,12) def imm5 = bits(19,15) def imm5_sext = Cat(Fill(59, imm5(4)), imm5) def funct6 = bits(31,26) def writes_xrf = !vmu && ((funct3 === OPMVV && opmf6 === OPMFunct6.wrxunary0) || (funct3 === OPFVV && opff6 === OPFFunct6.wrfunary0)) def writes_frf = !vmu && (funct3 === OPFVV) def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX) def isOpm = funct3.isOneOf(OPMVV, OPMVX) def isOpf = funct3.isOneOf(OPFVV, OPFVF) def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal) def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal) def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal) } class BackendIssueInst(implicit p: Parameters) extends VectorIssueInst()(p) { val reduction = Bool() // accumulates into vd[0] val scalar_to_vd0 = Bool() // mv scalar to vd[0] val wide_vd = Bool() // vd reads/writes at 2xSEW val wide_vs2 = Bool() // vs2 reads at 2xSEW val writes_mask = Bool() // writes dest as a mask val reads_vs1_mask = Bool() // vs1 read as mask val reads_vs2_mask = Bool() // vs2 read as mask val rs1_is_rs2 = Bool() val nf_log2 = UInt(2.W) val renv1 = Bool() val renv2 = Bool() val renvd = Bool() val renvm = Bool() val wvd = Bool() } class IssueQueueInst(nSeqs: Int)(implicit p: Parameters) extends BackendIssueInst()(p) { val seq = UInt(nSeqs.W) } class VectorWrite(writeBits: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eg = UInt(log2Ceil(32 * vLen / writeBits).W) def bankId = if (vrfBankBits == 0) 0.U else eg(vrfBankBits-1,0) val data = UInt(writeBits.W) val mask = UInt(writeBits.W) } class ScalarWrite extends Bundle { val data = UInt(64.W) val fp = Bool() val size = UInt(2.W) val rd = UInt(5.W) } class VectorReadReq(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eg = UInt(log2Ceil(egsTotal).W) val oldest = Bool() } class VectorReadIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val req = Decoupled(new VectorReadReq) val resp = Input(UInt(dLen.W)) } class VectorIndexAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val ready = Output(Bool()) val valid = Input(Bool()) val vrs = Input(UInt(5.W)) val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W)) val eew = Input(UInt(2.W)) val idx = Output(UInt(64.W)) } class VectorMaskAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val ready = Output(Bool()) val valid = Input(Bool()) val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W)) val mask = Output(Bool()) } class MaskedByte(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val debug_id = UInt(debugIdSz.W) val data = UInt(8.W) val mask = Bool() } class ExecuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val eidx = UInt(log2Ceil(maxVLMax).W) val vl = UInt((1+log2Ceil(maxVLMax)).W) val rvs1_data = UInt(dLen.W) val rvs2_data = UInt(dLen.W) val rvd_data = UInt(dLen.W) val rvm_data = UInt(dLen.W) val rvs1_elem = UInt(64.W) val rvs2_elem = UInt(64.W) val rvd_elem = UInt(64.W) val rvs1_eew = UInt(2.W) val rvs2_eew = UInt(2.W) val rvd_eew = UInt(2.W) val vd_eew = UInt(2.W) val rmask = UInt(dLenB.W) val wmask = UInt(dLenB.W) val full_tail_mask = UInt(dLen.W) val wvd_eg = UInt(log2Ceil(egsTotal).W) val funct3 = UInt(3.W) def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX) def isOpm = funct3.isOneOf(OPMVV, OPMVX) def isOpf = funct3.isOneOf(OPFVV, OPFVF) def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal) def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal) def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal) def vd_eew8 = vd_eew === 0.U def vd_eew16 = vd_eew === 1.U def vd_eew32 = vd_eew === 2.U def vd_eew64 = vd_eew === 3.U val funct6 = UInt(6.W) val rs1 = UInt(5.W) val rs2 = UInt(5.W) val rd = UInt(5.W) val vm = Bool() val head = Bool() val tail = Bool() val vat = UInt(vParams.vatSz.W) val acc = Bool() val rm = UInt(3.W) def vxrm = rm(1,0) def frm = rm } class StoreDataMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val stdata = UInt(dLen.W) val stmask = UInt(dLenB.W) val debug_id = UInt(debugIdSz.W) val tail = Bool() val vat = UInt(vParams.vatSz.W) def asMaskedBytes = { val bytes = Wire(Vec(dLenB, new MaskedByte)) for (i <- 0 until dLenB) { bytes(i).data := stdata(((i+1)*8)-1,i*8) bytes(i).mask := stmask(i) bytes(i).debug_id := debug_id } bytes } } class LoadRespMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val wvd_eg = UInt(log2Ceil(egsTotal).W) val wmask = UInt(dLenB.W) val tail = Bool() val debug_id = UInt(debugIdSz.W) val vat = UInt(vParams.vatSz.W) } class PermuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val renv2 = Bool() val renvm = Bool() val rvs2_data = UInt(dLen.W) val eidx = UInt(log2Ceil(maxVLMax).W) val rvs2_eew = UInt(2.W) val rvm_data = UInt(dLen.W) val vmu = Bool() val vl = UInt((1+log2Ceil(maxVLMax)).W) val tail = Bool() } class PipeHazard(pipe_depth: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val latency = UInt(log2Ceil(pipe_depth).W) val eg = UInt(log2Ceil(egsTotal).W) def eg_oh = UIntToOH(eg) } class SequencerHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val vat = UInt(vParams.vatSz.W) val rintent = UInt(egsTotal.W) val wintent = UInt(egsTotal.W) } class InstructionHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val vat = UInt(vParams.vatSz.W) val rintent = UInt(32.W) val wintent = UInt(32.W) }
module LoadSegmenter( // @[LoadSegmenter.scala:11:7] input clock, // @[LoadSegmenter.scala:11:7] input reset, // @[LoadSegmenter.scala:11:7] input io_valid, // @[LoadSegmenter.scala:12:14] output io_done, // @[LoadSegmenter.scala:12:14] input [15:0] io_op_debug_id, // @[LoadSegmenter.scala:12:14] input [2:0] io_op_segstart, // @[LoadSegmenter.scala:12:14] input [7:0] io_op_vstart, // @[LoadSegmenter.scala:12:14] input [8:0] io_op_vl, // @[LoadSegmenter.scala:12:14] input [2:0] io_op_nf, // @[LoadSegmenter.scala:12:14] input [1:0] io_op_elem_size, // @[LoadSegmenter.scala:12:14] input io_op_whole_reg, // @[LoadSegmenter.scala:12:14] input io_compactor_ready, // @[LoadSegmenter.scala:12:14] output io_compactor_valid, // @[LoadSegmenter.scala:12:14] output [2:0] io_compactor_bits_head, // @[LoadSegmenter.scala:12:14] output [2:0] io_compactor_bits_tail, // @[LoadSegmenter.scala:12:14] input [63:0] io_compactor_data, // @[LoadSegmenter.scala:12:14] input io_resp_ready, // @[LoadSegmenter.scala:12:14] output io_resp_valid, // @[LoadSegmenter.scala:12:14] output [63:0] io_resp_bits_data, // @[LoadSegmenter.scala:12:14] output [15:0] io_resp_bits_debug_id // @[LoadSegmenter.scala:12:14] ); wire _segbuf_io_in_ready; // @[LoadSegmenter.scala:26:22] wire _segbuf_io_out_valid; // @[LoadSegmenter.scala:26:22] wire [63:0] _segbuf_io_out_bits_data; // @[LoadSegmenter.scala:26:22] wire [15:0] _segbuf_io_out_bits_debug_id; // @[LoadSegmenter.scala:26:22] wire _segbuf_io_busy; // @[LoadSegmenter.scala:26:22] reg [7:0] r_eidx; // @[LoadSegmenter.scala:28:19] reg r_head; // @[LoadSegmenter.scala:29:23] reg [2:0] r_sidx; // @[LoadSegmenter.scala:30:19] wire [7:0] eidx = r_head ? io_op_vstart : r_eidx; // @[LoadSegmenter.scala:28:19, :29:23, :31:17] wire [2:0] sidx = r_head ? io_op_segstart : r_sidx; // @[LoadSegmenter.scala:29:23, :30:19, :32:17] wire [2:0] _seg_ready_T = io_op_whole_reg ? 3'h0 : io_op_nf; // @[Bundles.scala:33:19] wire [10:0] _GEN = {9'h0, io_op_elem_size}; // @[LoadSegmenter.scala:35:64] wire [10:0] _incr_T_3 = {3'h0, (|_seg_ready_T) ? {5'h0, sidx} : eidx} << _GEN; // @[LoadSegmenter.scala:31:17, :32:17, :35:{29,43,64}] wire [3:0] incr = 4'h8 - {1'h0, _incr_T_3[2:0]} >> io_op_elem_size; // @[LoadSegmenter.scala:11:7, :35:{23,64,76,95}] wire [8:0] next_eidx = {1'h0, eidx} + {5'h0, (|_seg_ready_T) ? 4'h1 : incr}; // @[LoadSegmenter.scala:11:7, :31:17, :35:{29,95}, :36:{22,36}, :38:24, :51:56] wire [4:0] next_sidx = {2'h0, sidx} + {1'h0, incr}; // @[LoadSegmenter.scala:11:7, :32:17, :35:{23,95}, :39:24] wire sidx_tail = next_sidx > {2'h0, _seg_ready_T}; // @[LoadSegmenter.scala:35:23, :39:24, :41:29] wire eidx_tail = next_eidx >= io_op_vl; // @[LoadSegmenter.scala:38:24, :42:29] wire [10:0] _io_compactor_bits_head_T = {3'h0, eidx} << _GEN; // @[LoadSegmenter.scala:31:17, :35:64, :46:36] wire [11:0] _io_compactor_bits_tail_T = {3'h0, io_op_vl} << io_op_elem_size; // @[LoadSegmenter.scala:47:55] wire [5:0] _io_compactor_bits_head_T_1 = {3'h0, sidx} << io_op_elem_size; // @[LoadSegmenter.scala:32:17, :50:36] wire [6:0] _io_compactor_bits_tail_T_3 = {3'h0, {1'h0, io_op_nf} + 4'h1} << io_op_elem_size; // @[LoadSegmenter.scala:11:7, :51:{56,64}] wire segbuf_io_in_valid = io_valid & (|_seg_ready_T) & io_compactor_ready; // @[LoadSegmenter.scala:54:{34,50,58}] wire _GEN_0 = ((|_seg_ready_T) ? _segbuf_io_in_ready & io_compactor_ready & sidx_tail : ~_segbuf_io_busy & io_compactor_ready & io_resp_ready) & io_valid; // @[LoadSegmenter.scala:26:22, :35:43, :41:29, :74:22, :75:{5,21,43}, :76:{24,46}, :88:19] wire _GEN_1 = _segbuf_io_in_ready & segbuf_io_in_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[LoadSegmenter.scala:11:7] if (_GEN_0) // @[LoadSegmenter.scala:88:19] r_eidx <= next_eidx[7:0]; // @[LoadSegmenter.scala:28:19, :38:24, :90:12] else if (_GEN_1 & r_head) // @[Decoupled.scala:51:35] r_eidx <= io_op_vstart; // @[LoadSegmenter.scala:28:19] if (_GEN_1) // @[Decoupled.scala:51:35] r_sidx <= next_sidx > {2'h0, io_op_nf} ? 3'h0 : next_sidx[2:0]; // @[LoadSegmenter.scala:30:19, :35:23, :39:24, :82:12, :83:{21,33}, :84:14] if (reset) // @[LoadSegmenter.scala:11:7] r_head <= 1'h1; // @[LoadSegmenter.scala:11:7, :29:23] else // @[LoadSegmenter.scala:11:7] r_head <= _GEN_0 ? eidx_tail : ~_GEN_1 & r_head; // @[Decoupled.scala:51:35] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File decode.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket.Instructions32 import freechips.rocketchip.rocket.CustomInstructions._ import freechips.rocketchip.rocket.RVCExpander import freechips.rocketchip.rocket.{CSR,Causes} import freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf} import FUConstants._ import boom.v3.common._ import boom.v3.util._ // scalastyle:off /** * Abstract trait giving defaults and other relevant values to different Decode constants/ */ abstract trait DecodeConstants extends freechips.rocketchip.rocket.constants.ScalarOpConstants with freechips.rocketchip.rocket.constants.MemoryOpConstants { val xpr64 = Y // TODO inform this from xLen val DC2 = BitPat.dontCare(2) // Makes the listing below more readable def decode_default: List[BitPat] = // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd // | | | | | | | | | | | | | | | | | | | | | | | | List(N, N, X, uopX , IQT_INT, FU_X , RT_X , DC2 ,DC2 ,X, IS_X, X, X, X, X, N, M_X, DC2, X, X, N, N, X, CSR.X) val table: Array[(BitPat, List[BitPat])] } // scalastyle:on /** * Decoded control signals */ class CtrlSigs extends Bundle { val legal = Bool() val fp_val = Bool() val fp_single = Bool() val uopc = UInt(UOPC_SZ.W) val iq_type = UInt(IQT_SZ.W) val fu_code = UInt(FUC_SZ.W) val dst_type = UInt(2.W) val rs1_type = UInt(2.W) val rs2_type = UInt(2.W) val frs3_en = Bool() val imm_sel = UInt(IS_X.getWidth.W) val uses_ldq = Bool() val uses_stq = Bool() val is_amo = Bool() val is_fence = Bool() val is_fencei = Bool() val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W) val wakeup_delay = UInt(2.W) val bypassable = Bool() val is_br = Bool() val is_sys_pc2epc = Bool() val inst_unique = Bool() val flush_on_commit = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val rocc = Bool() def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decode_default, table) val sigs = Seq(legal, fp_val, fp_single, uopc, iq_type, fu_code, dst_type, rs1_type, rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo, is_fence, is_fencei, mem_cmd, wakeup_delay, bypassable, is_br, is_sys_pc2epc, inst_unique, flush_on_commit, csr_cmd) sigs zip decoder map {case(s,d) => s := d} rocc := false.B this } } // scalastyle:off /** * Decode constants for RV32 */ object X32Decode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | Instructions32.SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), Instructions32.SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), Instructions32.SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N) ) } /** * Decode constants for RV64 */ object X64Decode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | LD -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LWU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), SD -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDIW -> List(Y, N, X, uopADDIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLLIW -> List(Y, N, X, uopSLLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAIW -> List(Y, N, X, uopSRAIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLIW -> List(Y, N, X, uopSRLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDW -> List(Y, N, X, uopADDW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SUBW -> List(Y, N, X, uopSUBW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLLW -> List(Y, N, X, uopSLLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRAW -> List(Y, N, X, uopSRAW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRLW -> List(Y, N, X, uopSRLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N) ) } /** * Overall Decode constants */ object XDecode extends DecodeConstants { // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | LW -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LH -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LHU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LB -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), LBU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N), SW -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SH -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), SB -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), LUI -> List(Y, N, X, uopLUI , IQT_INT, FU_ALU , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADDI -> List(Y, N, X, uopADDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ANDI -> List(Y, N, X, uopANDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ORI -> List(Y, N, X, uopORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), XORI -> List(Y, N, X, uopXORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTI -> List(Y, N, X, uopSLTI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTIU -> List(Y, N, X, uopSLTIU, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLL -> List(Y, N, X, uopSLL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), ADD -> List(Y, N, X, uopADD , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SUB -> List(Y, N, X, uopSUB , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLT -> List(Y, N, X, uopSLT , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SLTU -> List(Y, N, X, uopSLTU , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), AND -> List(Y, N, X, uopAND , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), OR -> List(Y, N, X, uopOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), XOR -> List(Y, N, X, uopXOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRA -> List(Y, N, X, uopSRA , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), SRL -> List(Y, N, X, uopSRL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N), MUL -> List(Y, N, X, uopMUL , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULH -> List(Y, N, X, uopMULH , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULHU -> List(Y, N, X, uopMULHU, IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULHSU -> List(Y, N, X, uopMULHSU,IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), MULW -> List(Y, N, X, uopMULW , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIV -> List(Y, N, X, uopDIV , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVU -> List(Y, N, X, uopDIVU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REM -> List(Y, N, X, uopREM , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMU -> List(Y, N, X, uopREMU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVW -> List(Y, N, X, uopDIVW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), DIVUW -> List(Y, N, X, uopDIVUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMW -> List(Y, N, X, uopREMW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), REMUW -> List(Y, N, X, uopREMUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), AUIPC -> List(Y, N, X, uopAUIPC, IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), // use BRU for the PC read JAL -> List(Y, N, X, uopJAL , IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), JALR -> List(Y, N, X, uopJALR , IQT_INT, FU_JMP , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), BEQ -> List(Y, N, X, uopBEQ , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BNE -> List(Y, N, X, uopBNE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BGE -> List(Y, N, X, uopBGE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BGEU -> List(Y, N, X, uopBGEU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BLT -> List(Y, N, X, uopBLT , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), BLTU -> List(Y, N, X, uopBLTU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N), // I-type, the immediate12 holds the CSR register. CSRRW -> List(Y, N, X, uopCSRRW, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W), CSRRS -> List(Y, N, X, uopCSRRS, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S), CSRRC -> List(Y, N, X, uopCSRRC, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C), CSRRWI -> List(Y, N, X, uopCSRRWI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W), CSRRSI -> List(Y, N, X, uopCSRRSI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S), CSRRCI -> List(Y, N, X, uopCSRRCI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C), SFENCE_VMA->List(Y,N, X, uopSFENCE,IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N,M_SFENCE,0.U,N, N, N, Y, Y, CSR.N), ECALL -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I), EBREAK -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I), SRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), MRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), DRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), WFI -> List(Y, N, X, uopWFI ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I), FENCE_I -> List(Y, N, X, uopNOP , IQT_INT, FU_X , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, Y, M_X , 0.U, N, N, N, Y, Y, CSR.N), FENCE -> List(Y, N, X, uopFENCE, IQT_INT, FU_MEM , RT_X , RT_X , RT_X , N, IS_X, N, Y, N, Y, N, M_X , 0.U, N, N, N, Y, Y, CSR.N), // TODO PERF make fence higher performance // currently serializes pipeline // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec? rs1 regtype | | | uses_stq | | | // | | | micro-code | rs2 type| | | | is_amo | | | // | | | | iq-type func unit | | | | | | | is_fence | | | // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd // A-type | | | | | | | | | | | | | | | | | | | | | | | | AMOADD_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), // TODO make AMOs higherperformance AMOXOR_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N), AMOSWAP_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N), AMOAND_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N), AMOOR_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N), AMOMIN_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N), AMOMINU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N), AMOMAX_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N), AMOMAXU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N), AMOADD_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), AMOXOR_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N), AMOSWAP_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N), AMOAND_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N), AMOOR_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N), AMOMIN_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N), AMOMINU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N), AMOMAX_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N), AMOMAXU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N), LR_W -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N), LR_D -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N), SC_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N), SC_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N) ) } /** * FP Decode constants */ object FDecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( // frs3_en wakeup_delay // | imm sel | bypassable (aka, known/fixed latency) // | | uses_ldq | | is_br // is val inst? rs1 regtype | | | uses_stq | | | // | is fp inst? | rs2 type| | | | is_amo | | | // | | is dst single-prec? | | | | | | | is_fence | | | // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall // | | | | iq_type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd FLW -> List(Y, Y, Y, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N), FLD -> List(Y, Y, N, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N), FSW -> List(Y, Y, Y, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), // sort of a lie; broken into two micro-ops FSD -> List(Y, Y, N, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), FCLASS_S-> List(Y, Y, Y, uopFCLASS_S,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCLASS_D-> List(Y, Y, N, uopFCLASS_D,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_W_X -> List(Y, Y, Y, uopFMV_W_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_D_X -> List(Y, Y, N, uopFMV_D_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_X_W -> List(Y, Y, Y, uopFMV_X_W, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMV_X_D -> List(Y, Y, N, uopFMV_X_D, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJ_S -> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJ_D -> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJX_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJX_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJN_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSGNJN_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // FP to FP FCVT_S_D-> List(Y, Y, Y, uopFCVT_S_D,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_S-> List(Y, Y, N, uopFCVT_D_S,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // Int to FP FCVT_S_W-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_WU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_L-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_S_LU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_W-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_WU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_L-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_D_LU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // FP to Int FCVT_W_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_WU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_L_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_LU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_W_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_WU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_L_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FCVT_LU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), // "fp_single" is used for wb_data formatting (and debugging) FEQ_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLT_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLE_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FEQ_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLT_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FLE_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMIN_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMAX_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMIN_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMAX_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FADD_S ->List(Y, Y, Y, uopFADD_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSUB_S ->List(Y, Y, Y, uopFSUB_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMUL_S ->List(Y, Y, Y, uopFMUL_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FADD_D ->List(Y, Y, N, uopFADD_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSUB_D ->List(Y, Y, N, uopFSUB_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMUL_D ->List(Y, Y, N, uopFMUL_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMADD_S ->List(Y, Y, Y, uopFMADD_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMSUB_S ->List(Y, Y, Y, uopFMSUB_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMADD_S ->List(Y, Y, Y, uopFNMADD_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMSUB_S ->List(Y, Y, Y, uopFNMSUB_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMADD_D ->List(Y, Y, N, uopFMADD_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FMSUB_D ->List(Y, Y, N, uopFMSUB_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMADD_D ->List(Y, Y, N, uopFNMADD_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FNMSUB_D ->List(Y, Y, N, uopFNMSUB_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } /** * FP Divide SquareRoot Constants */ object FDivSqrtDecode extends DecodeConstants { val table: Array[(BitPat, List[BitPat])] = Array( // frs3_en wakeup_delay // | imm sel | bypassable (aka, known/fixed latency) // | | uses_ldq | | is_br // is val inst? rs1 regtype | | | uses_stq | | | // | is fp inst? | rs2 type| | | | is_amo | | | // | | is dst single-prec? | | | | | | | is_fence | | | // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall // | | | | iq-type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd FDIV_S ->List(Y, Y, Y, uopFDIV_S , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FDIV_D ->List(Y, Y, N, uopFDIV_D , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSQRT_S ->List(Y, Y, Y, uopFSQRT_S, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), FSQRT_D ->List(Y, Y, N, uopFSQRT_D, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } //scalastyle:on /** * RoCC initial decode */ object RoCCDecode extends DecodeConstants { // Note: We use FU_CSR since CSR instructions cannot co-execute with RoCC instructions // frs3_en wakeup_delay // is val inst? | imm sel | bypassable (aka, known/fixed latency) // | is fp inst? | | uses_ldq | | is_br // | | is single-prec rs1 regtype | | | uses_stq | | | // | | | | rs2 type| | | | is_amo | | | // | | | micro-code func unit | | | | | | | is_fence | | | // | | | | iq-type | | | | | | | | | is_fencei | | | is breakpoint or ecall? // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it) // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit // | | | | | | | | | | | | | | | | | | | | | | | csr cmd // | | | | | | | | | | | | | | | | | | | | | | | | val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | | CUSTOM0 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM0_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM1_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM2_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N), CUSTOM3_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N) ) } /** * IO bundle for the Decode unit */ class DecodeUnitIo(implicit p: Parameters) extends BoomBundle { val enq = new Bundle { val uop = Input(new MicroOp()) } val deq = new Bundle { val uop = Output(new MicroOp()) } // from CSRFile val status = Input(new freechips.rocketchip.rocket.MStatus()) val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO) val interrupt = Input(Bool()) val interrupt_cause = Input(UInt(xLen.W)) } /** * Decode unit that takes in a single instruction and generates a MicroOp. */ class DecodeUnit(implicit p: Parameters) extends BoomModule with freechips.rocketchip.rocket.constants.MemoryOpConstants { val io = IO(new DecodeUnitIo) val uop = Wire(new MicroOp()) uop := io.enq.uop var decode_table = XDecode.table if (usingFPU) decode_table ++= FDecode.table if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table if (usingRoCC) decode_table ++= RoCCDecode.table decode_table ++= (if (xLen == 64) X64Decode.table else X32Decode.table) val inst = uop.inst val cs = Wire(new CtrlSigs()).decode(inst, decode_table) // Exception Handling io.csr_decode.inst := inst val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W) val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U val system_insn = cs.csr_cmd === CSR.I val sfence = cs.uopc === uopSFENCE val cs_legal = cs.legal // dontTouch(cs_legal) val id_illegal_insn = !cs_legal || cs.fp_val && io.csr_decode.fp_illegal || // TODO check for illegal rm mode: (io.fpu.illegal_rm) cs.rocc && io.csr_decode.rocc_illegal || cs.is_amo && !io.status.isa('a'-'a') || (cs.fp_val && !cs.fp_single) && !io.status.isa('d'-'a') || csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal) || ((sfence || system_insn) && io.csr_decode.system_illegal) // cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_||_), PriorityMux(x)) val (xcpt_valid, xcpt_cause) = checkExceptions(List( (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB (uop.bp_debug_if, (CSR.debugTriggerCause).U), (uop.bp_xcpt_if, (Causes.breakpoint).U), (uop.xcpt_pf_if, (Causes.fetch_page_fault).U), (uop.xcpt_ae_if, (Causes.fetch_access).U), (id_illegal_insn, (Causes.illegal_instruction).U))) uop.exception := xcpt_valid uop.exc_cause := xcpt_cause //------------------------------------------------------------- uop.uopc := cs.uopc uop.iq_type := cs.iq_type uop.fu_code := cs.fu_code // x-registers placed in 0-31, f-registers placed in 32-63. // This allows us to straight-up compare register specifiers and not need to // verify the rtypes (e.g., bypassing in rename). uop.ldst := inst(RD_MSB,RD_LSB) uop.lrs1 := inst(RS1_MSB,RS1_LSB) uop.lrs2 := inst(RS2_MSB,RS2_LSB) uop.lrs3 := inst(RS3_MSB,RS3_LSB) uop.ldst_val := cs.dst_type =/= RT_X && !(uop.ldst === 0.U && uop.dst_rtype === RT_FIX) uop.dst_rtype := cs.dst_type uop.lrs1_rtype := cs.rs1_type uop.lrs2_rtype := cs.rs2_type uop.frs3_en := cs.frs3_en uop.ldst_is_rs1 := uop.is_sfb_shadow // SFB optimization when (uop.is_sfb_shadow && cs.rs2_type === RT_X) { uop.lrs2_rtype := RT_FIX uop.lrs2 := inst(RD_MSB,RD_LSB) uop.ldst_is_rs1 := false.B } .elsewhen (uop.is_sfb_shadow && cs.uopc === uopADD && inst(RS1_MSB,RS1_LSB) === 0.U) { uop.uopc := uopMOV uop.lrs1 := inst(RD_MSB, RD_LSB) uop.ldst_is_rs1 := true.B } when (uop.is_sfb_br) { uop.fu_code := FU_JMP } uop.fp_val := cs.fp_val uop.fp_single := cs.fp_single // TODO use this signal instead of the FPU decode's table signal? uop.mem_cmd := cs.mem_cmd uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(uop.lrs2 =/= 0.U, uop.lrs1 =/= 0.U), inst(13,12)) uop.mem_signed := !inst(14) uop.uses_ldq := cs.uses_ldq uop.uses_stq := cs.uses_stq uop.is_amo := cs.is_amo uop.is_fence := cs.is_fence uop.is_fencei := cs.is_fencei uop.is_sys_pc2epc := cs.is_sys_pc2epc uop.is_unique := cs.inst_unique uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush) uop.bypassable := cs.bypassable //------------------------------------------------------------- // immediates // repackage the immediate, and then pass the fewest number of bits around val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20)) uop.imm_packed := Cat(inst(31,25), di24_20, inst(19,12)) //------------------------------------------------------------- uop.is_br := cs.is_br uop.is_jal := (uop.uopc === uopJAL) uop.is_jalr := (uop.uopc === uopJALR) // uop.is_jump := cs.is_jal || (uop.uopc === uopJALR) // uop.is_ret := (uop.uopc === uopJALR) && // (uop.ldst === X0) && // (uop.lrs1 === RA) // uop.is_call := (uop.uopc === uopJALR || uop.uopc === uopJAL) && // (uop.ldst === RA) //------------------------------------------------------------- io.deq.uop := uop } /** * Smaller Decode unit for the Frontend to decode different * branches. * Accepts EXPANDED RVC instructions */ class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle { val is_ret = Bool() val is_call = Bool() val target = UInt(vaddrBitsExtended.W) val cfi_type = UInt(CFI_SZ.W) // Is this branch a short forwards jump? val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W)) // Is this instruction allowed to be inside a sfb? val shadowable = Bool() } class BranchDecode(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val inst = Input(UInt(32.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val out = Output(new BranchDecodeSignals) }) val bpd_csignals = freechips.rocketchip.rocket.DecodeLogic(io.inst, List[BitPat](N, N, N, N, X), //// is br? //// | is jal? //// | | is jalr? //// | | | //// | | | shadowable //// | | | | has_rs2 //// | | | | | Array[(BitPat, List[BitPat])]( JAL -> List(N, Y, N, N, X), JALR -> List(N, N, Y, N, X), BEQ -> List(Y, N, N, N, X), BNE -> List(Y, N, N, N, X), BGE -> List(Y, N, N, N, X), BGEU -> List(Y, N, N, N, X), BLT -> List(Y, N, N, N, X), BLTU -> List(Y, N, N, N, X), SLLI -> List(N, N, N, Y, N), SRLI -> List(N, N, N, Y, N), SRAI -> List(N, N, N, Y, N), ADDIW -> List(N, N, N, Y, N), SLLIW -> List(N, N, N, Y, N), SRAIW -> List(N, N, N, Y, N), SRLIW -> List(N, N, N, Y, N), ADDW -> List(N, N, N, Y, Y), SUBW -> List(N, N, N, Y, Y), SLLW -> List(N, N, N, Y, Y), SRAW -> List(N, N, N, Y, Y), SRLW -> List(N, N, N, Y, Y), LUI -> List(N, N, N, Y, N), ADDI -> List(N, N, N, Y, N), ANDI -> List(N, N, N, Y, N), ORI -> List(N, N, N, Y, N), XORI -> List(N, N, N, Y, N), SLTI -> List(N, N, N, Y, N), SLTIU -> List(N, N, N, Y, N), SLL -> List(N, N, N, Y, Y), ADD -> List(N, N, N, Y, Y), SUB -> List(N, N, N, Y, Y), SLT -> List(N, N, N, Y, Y), SLTU -> List(N, N, N, Y, Y), AND -> List(N, N, N, Y, Y), OR -> List(N, N, N, Y, Y), XOR -> List(N, N, N, Y, Y), SRA -> List(N, N, N, Y, Y), SRL -> List(N, N, N, Y, Y) )) val cs_is_br = bpd_csignals(0)(0) val cs_is_jal = bpd_csignals(1)(0) val cs_is_jalr = bpd_csignals(2)(0) val cs_is_shadowable = bpd_csignals(3)(0) val cs_has_rs2 = bpd_csignals(4)(0) io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0 io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen), ComputeJALTarget(io.pc, io.inst, xLen)) io.out.cfi_type := Mux(cs_is_jalr, CFI_JALR, Mux(cs_is_jal, CFI_JAL, Mux(cs_is_br, CFI_BR, CFI_X))) val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W)) // Is a sfb if it points forwards (offset is positive) io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U io.out.sfb_offset.bits := br_offset io.out.shadowable := cs_is_shadowable && ( !cs_has_rs2 || (GetRs1(io.inst) === GetRd(io.inst)) || (io.inst === ADD && GetRs1(io.inst) === X0) ) } /** * Track the current "branch mask", and give out the branch mask to each micro-op in Decode * (each micro-op in the machine has a branch mask which says which branches it * is being speculated under). * * @param pl_width pipeline width for the processor */ class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { // guess if the uop is a branch (we'll catch this later) val is_branch = Input(Vec(pl_width, Bool())) // lock in that it's actually a branch and will fire, so we update // the branch_masks. val will_fire = Input(Vec(pl_width, Bool())) // give out tag immediately (needed in rename) // mask can come later in the cycle val br_tag = Output(Vec(pl_width, UInt(brTagSz.W))) val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W))) // tell decoders the branch mask has filled up, but on the granularity // of an individual micro-op (so some micro-ops can go through) val is_full = Output(Vec(pl_width, Bool())) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val debug_branch_mask = Output(UInt(maxBrCount.W)) }) val branch_mask = RegInit(0.U(maxBrCount.W)) //------------------------------------------------------------- // Give out the branch tag to each branch micro-op var allocate_mask = branch_mask val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W))) for (w <- 0 until pl_width) { // TODO this is a loss of performance as we're blocking branches based on potentially fake branches io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w) // find br_tag and compute next br_mask val new_br_tag = Wire(UInt(brTagSz.W)) new_br_tag := 0.U tag_masks(w) := 0.U for (i <- maxBrCount-1 to 0 by -1) { when (~allocate_mask(i)) { new_br_tag := i.U tag_masks(w) := (1.U << i.U) } } io.br_tag(w) := new_br_tag allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask) } //------------------------------------------------------------- // Give out the branch mask to each micro-op // (kill off the bits that corresponded to branches that aren't going to fire) var curr_mask = branch_mask for (w <- 0 until pl_width) { io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask) curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask) } //------------------------------------------------------------- // Update the current branch_mask when (io.flush_pipeline) { branch_mask := 0.U } .otherwise { val mask = Mux(io.brupdate.b2.mispredict, io.brupdate.b2.uop.br_mask, ~(0.U(maxBrCount.W))) branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask } io.debug_branch_mask := branch_mask } File micro-op.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // MicroOp //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.exu.FUConstants /** * Extension to BoomBundle to add a MicroOp */ abstract trait HasBoomUOP extends BoomBundle { val uop = new MicroOp() } /** * MicroOp passing through the pipeline */ class MicroOp(implicit p: Parameters) extends BoomBundle with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val uopc = UInt(UOPC_SZ.W) // micro-op code val inst = UInt(32.W) val debug_inst = UInt(32.W) val is_rvc = Bool() val debug_pc = UInt(coreMaxAddrBits.W) val iq_type = UInt(IQT_SZ.W) // which issue unit do we use? val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use? val ctrl = new CtrlSignals // What is the next state of this uop in the issue window? useful // for the compacting queue. val iw_state = UInt(2.W) // Has operand 1 or 2 been waken speculatively by a load? // Only integer operands are speculaively woken up, // so we can ignore p3. val iw_p1_poisoned = Bool() val iw_p2_poisoned = Bool() val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst? val is_jalr = Bool() // is this a jump? (jal or jalr) val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit val is_sfb = Bool() // is this a sfb or in the shadow of a sfb val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under? val br_tag = UInt(brTagSz.W) // Index into FTQ to figure out our fetch PC. val ftq_idx = UInt(log2Ceil(ftqSz).W) // This inst straddles two fetch packets val edge_inst = Bool() // Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC. // Aligned to a cache-line size, as that is the greater fetch granularity. // TODO: Shouldn't this be aligned to fetch-width size? val pc_lob = UInt(log2Ceil(icBlockBytes).W) // Was this a branch that was predicted taken? val taken = Bool() val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode... // then translate and sign-extend in execute val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe val rob_idx = UInt(robAddrSz.W) val ldq_idx = UInt(ldqAddrSz.W) val stq_idx = UInt(stqAddrSz.W) val rxq_idx = UInt(log2Ceil(numRxqEntries).W) val pdst = UInt(maxPregSz.W) val prs1 = UInt(maxPregSz.W) val prs2 = UInt(maxPregSz.W) val prs3 = UInt(maxPregSz.W) val ppred = UInt(log2Ceil(ftqSz).W) val prs1_busy = Bool() val prs2_busy = Bool() val prs3_busy = Bool() val ppred_busy = Bool() val stale_pdst = UInt(maxPregSz.W) val exception = Bool() val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...) val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes val mem_size = UInt(2.W) val mem_signed = Bool() val is_fence = Bool() val is_fencei = Bool() val is_amo = Bool() val uses_ldq = Bool() val uses_stq = Bool() val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC. val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to // drain, clear fetcha fter it (tell ROB to un-ready until empty) val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them // Preditation def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst, // else copy rs2 to dst // logical specifiers (only used in Decode->Rename), except rollback (ldst) val ldst = UInt(lregSz.W) val lrs1 = UInt(lregSz.W) val lrs2 = UInt(lregSz.W) val lrs3 = UInt(lregSz.W) val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc. val dst_rtype = UInt(2.W) val lrs1_rtype = UInt(2.W) val lrs2_rtype = UInt(2.W) val frs3_en = Bool() // floating point information val fp_val = Bool() // is a floating-point instruction (F- or D-extension)? // If it's non-ld/st it will write back exception bits to the fcsr. val fp_single = Bool() // single-precision floating point instruction (F-extension) // frontend exception information val xcpt_pf_if = Bool() // I-TLB page fault. val xcpt_ae_if = Bool() // I$ access exception. val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr). val bp_debug_if = Bool() // Breakpoint val bp_xcpt_if = Bool() // Breakpoint // What prediction structure provides the prediction FROM this op val debug_fsrc = UInt(BSRC_SZ.W) // What prediction structure provides the prediction TO this op val debug_tsrc = UInt(BSRC_SZ.W) // Do we allocate a branch tag for this? // SFB branches don't get a mask, they get a predicate bit def allocate_brtag = (is_br && !is_sfb) || is_jalr // Does this register write-back def rf_wen = dst_rtype =/= RT_X // Is it possible for this uop to misspeculate, preventing the commit of subsequent uops? def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U } /** * Control signals within a MicroOp * * TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution */ class CtrlSignals extends Bundle() { val br_type = UInt(BR_N.getWidth.W) val op1_sel = UInt(OP1_X.getWidth.W) val op2_sel = UInt(OP2_X.getWidth.W) val imm_sel = UInt(IS_X.getWidth.W) val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W) val fcn_dw = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val is_load = Bool() // will invoke TLB address lookup val is_sta = Bool() // will invoke TLB address lookup val is_std = Bool() }
module DecodeUnit_5( // @[decode.scala:474:7] input clock, // @[decode.scala:474:7] input reset, // @[decode.scala:474:7] input [31:0] io_enq_uop_inst, // @[decode.scala:477:14] input [31:0] io_enq_uop_debug_inst, // @[decode.scala:477:14] input io_enq_uop_is_rvc, // @[decode.scala:477:14] input [39:0] io_enq_uop_debug_pc, // @[decode.scala:477:14] input io_enq_uop_is_sfb, // @[decode.scala:477:14] input [4:0] io_enq_uop_ftq_idx, // @[decode.scala:477:14] input io_enq_uop_edge_inst, // @[decode.scala:477:14] input [5:0] io_enq_uop_pc_lob, // @[decode.scala:477:14] input io_enq_uop_taken, // @[decode.scala:477:14] input io_enq_uop_xcpt_pf_if, // @[decode.scala:477:14] input io_enq_uop_xcpt_ae_if, // @[decode.scala:477:14] input io_enq_uop_bp_debug_if, // @[decode.scala:477:14] input io_enq_uop_bp_xcpt_if, // @[decode.scala:477:14] input [1:0] io_enq_uop_debug_fsrc, // @[decode.scala:477:14] output [6:0] io_deq_uop_uopc, // @[decode.scala:477:14] output [31:0] io_deq_uop_inst, // @[decode.scala:477:14] output [31:0] io_deq_uop_debug_inst, // @[decode.scala:477:14] output io_deq_uop_is_rvc, // @[decode.scala:477:14] output [39:0] io_deq_uop_debug_pc, // @[decode.scala:477:14] output [2:0] io_deq_uop_iq_type, // @[decode.scala:477:14] output [9:0] io_deq_uop_fu_code, // @[decode.scala:477:14] output io_deq_uop_is_br, // @[decode.scala:477:14] output io_deq_uop_is_jalr, // @[decode.scala:477:14] output io_deq_uop_is_jal, // @[decode.scala:477:14] output io_deq_uop_is_sfb, // @[decode.scala:477:14] output [4:0] io_deq_uop_ftq_idx, // @[decode.scala:477:14] output io_deq_uop_edge_inst, // @[decode.scala:477:14] output [5:0] io_deq_uop_pc_lob, // @[decode.scala:477:14] output io_deq_uop_taken, // @[decode.scala:477:14] output [19:0] io_deq_uop_imm_packed, // @[decode.scala:477:14] output io_deq_uop_exception, // @[decode.scala:477:14] output [63:0] io_deq_uop_exc_cause, // @[decode.scala:477:14] output io_deq_uop_bypassable, // @[decode.scala:477:14] output [4:0] io_deq_uop_mem_cmd, // @[decode.scala:477:14] output [1:0] io_deq_uop_mem_size, // @[decode.scala:477:14] output io_deq_uop_mem_signed, // @[decode.scala:477:14] output io_deq_uop_is_fence, // @[decode.scala:477:14] output io_deq_uop_is_fencei, // @[decode.scala:477:14] output io_deq_uop_is_amo, // @[decode.scala:477:14] output io_deq_uop_uses_ldq, // @[decode.scala:477:14] output io_deq_uop_uses_stq, // @[decode.scala:477:14] output io_deq_uop_is_sys_pc2epc, // @[decode.scala:477:14] output io_deq_uop_is_unique, // @[decode.scala:477:14] output io_deq_uop_flush_on_commit, // @[decode.scala:477:14] output [5:0] io_deq_uop_ldst, // @[decode.scala:477:14] output [5:0] io_deq_uop_lrs1, // @[decode.scala:477:14] output [5:0] io_deq_uop_lrs2, // @[decode.scala:477:14] output [5:0] io_deq_uop_lrs3, // @[decode.scala:477:14] output io_deq_uop_ldst_val, // @[decode.scala:477:14] output [1:0] io_deq_uop_dst_rtype, // @[decode.scala:477:14] output [1:0] io_deq_uop_lrs1_rtype, // @[decode.scala:477:14] output [1:0] io_deq_uop_lrs2_rtype, // @[decode.scala:477:14] output io_deq_uop_frs3_en, // @[decode.scala:477:14] output io_deq_uop_fp_val, // @[decode.scala:477:14] output io_deq_uop_fp_single, // @[decode.scala:477:14] output io_deq_uop_xcpt_pf_if, // @[decode.scala:477:14] output io_deq_uop_xcpt_ae_if, // @[decode.scala:477:14] output io_deq_uop_bp_debug_if, // @[decode.scala:477:14] output io_deq_uop_bp_xcpt_if, // @[decode.scala:477:14] output [1:0] io_deq_uop_debug_fsrc, // @[decode.scala:477:14] input io_status_debug, // @[decode.scala:477:14] input io_status_cease, // @[decode.scala:477:14] input io_status_wfi, // @[decode.scala:477:14] input [1:0] io_status_dprv, // @[decode.scala:477:14] input io_status_dv, // @[decode.scala:477:14] input [1:0] io_status_prv, // @[decode.scala:477:14] input io_status_v, // @[decode.scala:477:14] input io_status_sd, // @[decode.scala:477:14] input io_status_mpv, // @[decode.scala:477:14] input io_status_gva, // @[decode.scala:477:14] input io_status_tsr, // @[decode.scala:477:14] input io_status_tw, // @[decode.scala:477:14] input io_status_tvm, // @[decode.scala:477:14] input io_status_mxr, // @[decode.scala:477:14] input io_status_sum, // @[decode.scala:477:14] input io_status_mprv, // @[decode.scala:477:14] input [1:0] io_status_fs, // @[decode.scala:477:14] input [1:0] io_status_mpp, // @[decode.scala:477:14] input io_status_spp, // @[decode.scala:477:14] input io_status_mpie, // @[decode.scala:477:14] input io_status_spie, // @[decode.scala:477:14] input io_status_mie, // @[decode.scala:477:14] input io_status_sie, // @[decode.scala:477:14] output [31:0] io_csr_decode_inst, // @[decode.scala:477:14] input io_csr_decode_fp_illegal, // @[decode.scala:477:14] input io_csr_decode_fp_csr, // @[decode.scala:477:14] input io_csr_decode_read_illegal, // @[decode.scala:477:14] input io_csr_decode_write_illegal, // @[decode.scala:477:14] input io_csr_decode_write_flush, // @[decode.scala:477:14] input io_csr_decode_system_illegal, // @[decode.scala:477:14] input io_csr_decode_virtual_access_illegal, // @[decode.scala:477:14] input io_csr_decode_virtual_system_illegal, // @[decode.scala:477:14] input io_interrupt, // @[decode.scala:477:14] input [63:0] io_interrupt_cause // @[decode.scala:477:14] ); wire [31:0] io_enq_uop_inst_0 = io_enq_uop_inst; // @[decode.scala:474:7] wire [31:0] io_enq_uop_debug_inst_0 = io_enq_uop_debug_inst; // @[decode.scala:474:7] wire io_enq_uop_is_rvc_0 = io_enq_uop_is_rvc; // @[decode.scala:474:7] wire [39:0] io_enq_uop_debug_pc_0 = io_enq_uop_debug_pc; // @[decode.scala:474:7] wire io_enq_uop_is_sfb_0 = io_enq_uop_is_sfb; // @[decode.scala:474:7] wire [4:0] io_enq_uop_ftq_idx_0 = io_enq_uop_ftq_idx; // @[decode.scala:474:7] wire io_enq_uop_edge_inst_0 = io_enq_uop_edge_inst; // @[decode.scala:474:7] wire [5:0] io_enq_uop_pc_lob_0 = io_enq_uop_pc_lob; // @[decode.scala:474:7] wire io_enq_uop_taken_0 = io_enq_uop_taken; // @[decode.scala:474:7] wire io_enq_uop_xcpt_pf_if_0 = io_enq_uop_xcpt_pf_if; // @[decode.scala:474:7] wire io_enq_uop_xcpt_ae_if_0 = io_enq_uop_xcpt_ae_if; // @[decode.scala:474:7] wire io_enq_uop_bp_debug_if_0 = io_enq_uop_bp_debug_if; // @[decode.scala:474:7] wire io_enq_uop_bp_xcpt_if_0 = io_enq_uop_bp_xcpt_if; // @[decode.scala:474:7] wire [1:0] io_enq_uop_debug_fsrc_0 = io_enq_uop_debug_fsrc; // @[decode.scala:474:7] wire io_status_debug_0 = io_status_debug; // @[decode.scala:474:7] wire io_status_cease_0 = io_status_cease; // @[decode.scala:474:7] wire io_status_wfi_0 = io_status_wfi; // @[decode.scala:474:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[decode.scala:474:7] wire io_status_dv_0 = io_status_dv; // @[decode.scala:474:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[decode.scala:474:7] wire io_status_v_0 = io_status_v; // @[decode.scala:474:7] wire io_status_sd_0 = io_status_sd; // @[decode.scala:474:7] wire io_status_mpv_0 = io_status_mpv; // @[decode.scala:474:7] wire io_status_gva_0 = io_status_gva; // @[decode.scala:474:7] wire io_status_tsr_0 = io_status_tsr; // @[decode.scala:474:7] wire io_status_tw_0 = io_status_tw; // @[decode.scala:474:7] wire io_status_tvm_0 = io_status_tvm; // @[decode.scala:474:7] wire io_status_mxr_0 = io_status_mxr; // @[decode.scala:474:7] wire io_status_sum_0 = io_status_sum; // @[decode.scala:474:7] wire io_status_mprv_0 = io_status_mprv; // @[decode.scala:474:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[decode.scala:474:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[decode.scala:474:7] wire io_status_spp_0 = io_status_spp; // @[decode.scala:474:7] wire io_status_mpie_0 = io_status_mpie; // @[decode.scala:474:7] wire io_status_spie_0 = io_status_spie; // @[decode.scala:474:7] wire io_status_mie_0 = io_status_mie; // @[decode.scala:474:7] wire io_status_sie_0 = io_status_sie; // @[decode.scala:474:7] wire io_csr_decode_fp_illegal_0 = io_csr_decode_fp_illegal; // @[decode.scala:474:7] wire io_csr_decode_fp_csr_0 = io_csr_decode_fp_csr; // @[decode.scala:474:7] wire io_csr_decode_read_illegal_0 = io_csr_decode_read_illegal; // @[decode.scala:474:7] wire io_csr_decode_write_illegal_0 = io_csr_decode_write_illegal; // @[decode.scala:474:7] wire io_csr_decode_write_flush_0 = io_csr_decode_write_flush; // @[decode.scala:474:7] wire io_csr_decode_system_illegal_0 = io_csr_decode_system_illegal; // @[decode.scala:474:7] wire io_csr_decode_virtual_access_illegal_0 = io_csr_decode_virtual_access_illegal; // @[decode.scala:474:7] wire io_csr_decode_virtual_system_illegal_0 = io_csr_decode_virtual_system_illegal; // @[decode.scala:474:7] wire io_interrupt_0 = io_interrupt; // @[decode.scala:474:7] wire [63:0] io_interrupt_cause_0 = io_interrupt_cause; // @[decode.scala:474:7] wire [1:0] io_status_sxl = 2'h2; // @[decode.scala:474:7] wire [1:0] io_status_uxl = 2'h2; // @[decode.scala:474:7] wire io_csr_decode_vector_illegal = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51] wire io_csr_decode_rocc_illegal = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51] wire _id_illegal_insn_T_5 = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51] wire _id_illegal_insn_T_11 = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51] wire [7:0] io_status_zero1 = 8'h0; // @[decode.scala:474:7, :477:14] wire [22:0] io_status_zero2 = 23'h0; // @[decode.scala:474:7, :477:14] wire [31:0] io_status_isa = 32'h14112D; // @[decode.scala:474:7, :477:14] wire [5:0] io_enq_uop_ldst = 6'h0; // @[decode.scala:474:7, :477:14] wire [5:0] io_enq_uop_lrs1 = 6'h0; // @[decode.scala:474:7, :477:14] wire [5:0] io_enq_uop_lrs2 = 6'h0; // @[decode.scala:474:7, :477:14] wire [5:0] io_enq_uop_lrs3 = 6'h0; // @[decode.scala:474:7, :477:14] wire [63:0] io_enq_uop_exc_cause = 64'h0; // @[decode.scala:474:7, :477:14] wire [11:0] io_enq_uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [11:0] io_deq_uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [11:0] uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [19:0] io_enq_uop_imm_packed = 20'h0; // @[decode.scala:474:7, :477:14] wire [15:0] io_enq_uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [15:0] io_deq_uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [15:0] uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17] wire io_enq_uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ctrl_is_load = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ctrl_is_sta = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ctrl_is_std = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_iw_p1_poisoned = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_iw_p2_poisoned = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_br = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_jalr = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_jal = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_prs1_busy = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_prs2_busy = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_prs3_busy = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ppred_busy = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_exception = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_bypassable = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_mem_signed = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_fence = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_fencei = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_amo = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_uses_ldq = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_uses_stq = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_sys_pc2epc = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_is_unique = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_flush_on_commit = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_ldst_val = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_frs3_en = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_fp_val = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_fp_single = 1'h0; // @[decode.scala:474:7] wire io_enq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ctrl_is_load = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ctrl_is_sta = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ctrl_is_std = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_iw_p1_poisoned = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_iw_p2_poisoned = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_prs1_busy = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_prs2_busy = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_prs3_busy = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ppred_busy = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:474:7] wire io_deq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:474:7] wire io_status_mbe = 1'h0; // @[decode.scala:474:7] wire io_status_sbe = 1'h0; // @[decode.scala:474:7] wire io_status_sd_rv32 = 1'h0; // @[decode.scala:474:7] wire io_status_ube = 1'h0; // @[decode.scala:474:7] wire io_status_upie = 1'h0; // @[decode.scala:474:7] wire io_status_hie = 1'h0; // @[decode.scala:474:7] wire io_status_uie = 1'h0; // @[decode.scala:474:7] wire io_csr_decode_vector_csr = 1'h0; // @[decode.scala:474:7] wire uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:479:17] wire uop_ctrl_is_load = 1'h0; // @[decode.scala:479:17] wire uop_ctrl_is_sta = 1'h0; // @[decode.scala:479:17] wire uop_ctrl_is_std = 1'h0; // @[decode.scala:479:17] wire uop_iw_p1_poisoned = 1'h0; // @[decode.scala:479:17] wire uop_iw_p2_poisoned = 1'h0; // @[decode.scala:479:17] wire uop_prs1_busy = 1'h0; // @[decode.scala:479:17] wire uop_prs2_busy = 1'h0; // @[decode.scala:479:17] wire uop_prs3_busy = 1'h0; // @[decode.scala:479:17] wire uop_ppred_busy = 1'h0; // @[decode.scala:479:17] wire uop_ldst_is_rs1 = 1'h0; // @[decode.scala:479:17] wire uop_xcpt_ma_if = 1'h0; // @[decode.scala:479:17] wire cs_rocc = 1'h0; // @[decode.scala:490:16] wire _id_illegal_insn_T_3 = 1'h0; // @[decode.scala:504:13] wire _id_illegal_insn_T_6 = 1'h0; // @[decode.scala:505:18] wire _id_illegal_insn_T_7 = 1'h0; // @[decode.scala:505:15] wire _id_illegal_insn_T_12 = 1'h0; // @[decode.scala:506:37] wire _id_illegal_insn_T_13 = 1'h0; // @[decode.scala:506:34] wire _uop_ldst_is_rs1_T_2 = 1'h0; // @[micro-op.scala:110:43] wire [4:0] io_enq_uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_enq_uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_enq_uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_enq_uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_enq_uop_mem_cmd = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_deq_uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_deq_uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_deq_uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] io_deq_uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [4:0] uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_mem_size = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_dst_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_lrs1_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_lrs2_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_enq_uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_deq_uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_deq_uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_deq_uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_deq_uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_status_xs = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] io_status_vs = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [1:0] uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] io_enq_uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] io_enq_uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] io_deq_uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] io_deq_uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [3:0] uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [9:0] io_enq_uop_fu_code = 10'h0; // @[decode.scala:474:7, :477:14] wire [2:0] io_enq_uop_iq_type = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_enq_uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_enq_uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_enq_uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_deq_uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_deq_uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] io_deq_uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [2:0] uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_uopc = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_enq_uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] io_deq_uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [6:0] uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17] wire [31:0] uop_inst = io_enq_uop_inst_0; // @[decode.scala:474:7, :479:17] wire [31:0] uop_debug_inst = io_enq_uop_debug_inst_0; // @[decode.scala:474:7, :479:17] wire uop_is_rvc = io_enq_uop_is_rvc_0; // @[decode.scala:474:7, :479:17] wire [39:0] uop_debug_pc = io_enq_uop_debug_pc_0; // @[decode.scala:474:7, :479:17] wire uop_is_sfb = io_enq_uop_is_sfb_0; // @[decode.scala:474:7, :479:17] wire [4:0] uop_ftq_idx = io_enq_uop_ftq_idx_0; // @[decode.scala:474:7, :479:17] wire uop_edge_inst = io_enq_uop_edge_inst_0; // @[decode.scala:474:7, :479:17] wire [5:0] uop_pc_lob = io_enq_uop_pc_lob_0; // @[decode.scala:474:7, :479:17] wire uop_taken = io_enq_uop_taken_0; // @[decode.scala:474:7, :479:17] wire uop_xcpt_pf_if = io_enq_uop_xcpt_pf_if_0; // @[decode.scala:474:7, :479:17] wire uop_xcpt_ae_if = io_enq_uop_xcpt_ae_if_0; // @[decode.scala:474:7, :479:17] wire uop_bp_debug_if = io_enq_uop_bp_debug_if_0; // @[decode.scala:474:7, :479:17] wire uop_bp_xcpt_if = io_enq_uop_bp_xcpt_if_0; // @[decode.scala:474:7, :479:17] wire [1:0] uop_debug_fsrc = io_enq_uop_debug_fsrc_0; // @[decode.scala:474:7, :479:17] wire [6:0] uop_uopc; // @[decode.scala:479:17] wire [2:0] uop_iq_type; // @[decode.scala:479:17] wire [9:0] uop_fu_code; // @[decode.scala:479:17] wire uop_is_br; // @[decode.scala:479:17] wire uop_is_jalr; // @[decode.scala:479:17] wire uop_is_jal; // @[decode.scala:479:17] wire [19:0] uop_imm_packed; // @[decode.scala:479:17] wire uop_exception; // @[decode.scala:479:17] wire [63:0] uop_exc_cause; // @[decode.scala:479:17] wire uop_bypassable; // @[decode.scala:479:17] wire [4:0] uop_mem_cmd; // @[decode.scala:479:17] wire [1:0] uop_mem_size; // @[decode.scala:479:17] wire uop_mem_signed; // @[decode.scala:479:17] wire uop_is_fence; // @[decode.scala:479:17] wire uop_is_fencei; // @[decode.scala:479:17] wire uop_is_amo; // @[decode.scala:479:17] wire uop_uses_ldq; // @[decode.scala:479:17] wire uop_uses_stq; // @[decode.scala:479:17] wire uop_is_sys_pc2epc; // @[decode.scala:479:17] wire uop_is_unique; // @[decode.scala:479:17] wire uop_flush_on_commit; // @[decode.scala:479:17] wire [5:0] uop_ldst; // @[decode.scala:479:17] wire [5:0] uop_lrs1; // @[decode.scala:479:17] wire [5:0] uop_lrs2; // @[decode.scala:479:17] wire [5:0] uop_lrs3; // @[decode.scala:479:17] wire uop_ldst_val; // @[decode.scala:479:17] wire [1:0] uop_dst_rtype; // @[decode.scala:479:17] wire [1:0] uop_lrs1_rtype; // @[decode.scala:479:17] wire [1:0] uop_lrs2_rtype; // @[decode.scala:479:17] wire uop_frs3_en; // @[decode.scala:479:17] wire uop_fp_val; // @[decode.scala:479:17] wire uop_fp_single; // @[decode.scala:479:17] wire [6:0] io_deq_uop_uopc_0; // @[decode.scala:474:7] wire [31:0] io_deq_uop_inst_0; // @[decode.scala:474:7] wire [31:0] io_deq_uop_debug_inst_0; // @[decode.scala:474:7] wire io_deq_uop_is_rvc_0; // @[decode.scala:474:7] wire [39:0] io_deq_uop_debug_pc_0; // @[decode.scala:474:7] wire [2:0] io_deq_uop_iq_type_0; // @[decode.scala:474:7] wire [9:0] io_deq_uop_fu_code_0; // @[decode.scala:474:7] wire io_deq_uop_is_br_0; // @[decode.scala:474:7] wire io_deq_uop_is_jalr_0; // @[decode.scala:474:7] wire io_deq_uop_is_jal_0; // @[decode.scala:474:7] wire io_deq_uop_is_sfb_0; // @[decode.scala:474:7] wire [4:0] io_deq_uop_ftq_idx_0; // @[decode.scala:474:7] wire io_deq_uop_edge_inst_0; // @[decode.scala:474:7] wire [5:0] io_deq_uop_pc_lob_0; // @[decode.scala:474:7] wire io_deq_uop_taken_0; // @[decode.scala:474:7] wire [19:0] io_deq_uop_imm_packed_0; // @[decode.scala:474:7] wire io_deq_uop_exception_0; // @[decode.scala:474:7] wire [63:0] io_deq_uop_exc_cause_0; // @[decode.scala:474:7] wire io_deq_uop_bypassable_0; // @[decode.scala:474:7] wire [4:0] io_deq_uop_mem_cmd_0; // @[decode.scala:474:7] wire [1:0] io_deq_uop_mem_size_0; // @[decode.scala:474:7] wire io_deq_uop_mem_signed_0; // @[decode.scala:474:7] wire io_deq_uop_is_fence_0; // @[decode.scala:474:7] wire io_deq_uop_is_fencei_0; // @[decode.scala:474:7] wire io_deq_uop_is_amo_0; // @[decode.scala:474:7] wire io_deq_uop_uses_ldq_0; // @[decode.scala:474:7] wire io_deq_uop_uses_stq_0; // @[decode.scala:474:7] wire io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:474:7] wire io_deq_uop_is_unique_0; // @[decode.scala:474:7] wire io_deq_uop_flush_on_commit_0; // @[decode.scala:474:7] wire [5:0] io_deq_uop_ldst_0; // @[decode.scala:474:7] wire [5:0] io_deq_uop_lrs1_0; // @[decode.scala:474:7] wire [5:0] io_deq_uop_lrs2_0; // @[decode.scala:474:7] wire [5:0] io_deq_uop_lrs3_0; // @[decode.scala:474:7] wire io_deq_uop_ldst_val_0; // @[decode.scala:474:7] wire [1:0] io_deq_uop_dst_rtype_0; // @[decode.scala:474:7] wire [1:0] io_deq_uop_lrs1_rtype_0; // @[decode.scala:474:7] wire [1:0] io_deq_uop_lrs2_rtype_0; // @[decode.scala:474:7] wire io_deq_uop_frs3_en_0; // @[decode.scala:474:7] wire io_deq_uop_fp_val_0; // @[decode.scala:474:7] wire io_deq_uop_fp_single_0; // @[decode.scala:474:7] wire io_deq_uop_xcpt_pf_if_0; // @[decode.scala:474:7] wire io_deq_uop_xcpt_ae_if_0; // @[decode.scala:474:7] wire io_deq_uop_bp_debug_if_0; // @[decode.scala:474:7] wire io_deq_uop_bp_xcpt_if_0; // @[decode.scala:474:7] wire [1:0] io_deq_uop_debug_fsrc_0; // @[decode.scala:474:7] wire [31:0] io_csr_decode_inst_0; // @[decode.scala:474:7] wire [6:0] cs_uopc; // @[decode.scala:490:16] assign io_deq_uop_uopc_0 = uop_uopc; // @[decode.scala:474:7, :479:17] assign io_deq_uop_inst_0 = uop_inst; // @[decode.scala:474:7, :479:17] assign io_csr_decode_inst_0 = uop_inst; // @[decode.scala:474:7, :479:17] wire [31:0] cs_decoder_decoded_plaInput = uop_inst; // @[pla.scala:77:22] assign io_deq_uop_debug_inst_0 = uop_debug_inst; // @[decode.scala:474:7, :479:17] assign io_deq_uop_is_rvc_0 = uop_is_rvc; // @[decode.scala:474:7, :479:17] assign io_deq_uop_debug_pc_0 = uop_debug_pc; // @[decode.scala:474:7, :479:17] wire [2:0] cs_iq_type; // @[decode.scala:490:16] assign io_deq_uop_iq_type_0 = uop_iq_type; // @[decode.scala:474:7, :479:17] wire [9:0] cs_fu_code; // @[decode.scala:490:16] assign io_deq_uop_fu_code_0 = uop_fu_code; // @[decode.scala:474:7, :479:17] wire cs_is_br; // @[decode.scala:490:16] assign io_deq_uop_is_br_0 = uop_is_br; // @[decode.scala:474:7, :479:17] wire _uop_is_jalr_T; // @[decode.scala:590:35] assign io_deq_uop_is_jalr_0 = uop_is_jalr; // @[decode.scala:474:7, :479:17] wire _uop_is_jal_T; // @[decode.scala:589:35] assign io_deq_uop_is_jal_0 = uop_is_jal; // @[decode.scala:474:7, :479:17] assign io_deq_uop_is_sfb_0 = uop_is_sfb; // @[decode.scala:474:7, :479:17] assign io_deq_uop_ftq_idx_0 = uop_ftq_idx; // @[decode.scala:474:7, :479:17] assign io_deq_uop_edge_inst_0 = uop_edge_inst; // @[decode.scala:474:7, :479:17] assign io_deq_uop_pc_lob_0 = uop_pc_lob; // @[decode.scala:474:7, :479:17] assign io_deq_uop_taken_0 = uop_taken; // @[decode.scala:474:7, :479:17] wire [19:0] _uop_imm_packed_T_2; // @[decode.scala:584:24] assign io_deq_uop_imm_packed_0 = uop_imm_packed; // @[decode.scala:474:7, :479:17] wire xcpt_valid; // @[decode.scala:513:26] assign io_deq_uop_exception_0 = uop_exception; // @[decode.scala:474:7, :479:17] wire [63:0] xcpt_cause; // @[Mux.scala:50:70] assign io_deq_uop_exc_cause_0 = uop_exc_cause; // @[decode.scala:474:7, :479:17] wire cs_bypassable; // @[decode.scala:490:16] assign io_deq_uop_bypassable_0 = uop_bypassable; // @[decode.scala:474:7, :479:17] wire [4:0] cs_mem_cmd; // @[decode.scala:490:16] assign io_deq_uop_mem_cmd_0 = uop_mem_cmd; // @[decode.scala:474:7, :479:17] wire [1:0] _uop_mem_size_T_7; // @[decode.scala:566:24] assign io_deq_uop_mem_size_0 = uop_mem_size; // @[decode.scala:474:7, :479:17] wire _uop_mem_signed_T_1; // @[decode.scala:567:21] assign io_deq_uop_mem_signed_0 = uop_mem_signed; // @[decode.scala:474:7, :479:17] wire cs_is_fence; // @[decode.scala:490:16] assign io_deq_uop_is_fence_0 = uop_is_fence; // @[decode.scala:474:7, :479:17] wire cs_is_fencei; // @[decode.scala:490:16] assign io_deq_uop_is_fencei_0 = uop_is_fencei; // @[decode.scala:474:7, :479:17] wire cs_is_amo; // @[decode.scala:490:16] assign io_deq_uop_is_amo_0 = uop_is_amo; // @[decode.scala:474:7, :479:17] wire cs_uses_ldq; // @[decode.scala:490:16] assign io_deq_uop_uses_ldq_0 = uop_uses_ldq; // @[decode.scala:474:7, :479:17] wire cs_uses_stq; // @[decode.scala:490:16] assign io_deq_uop_uses_stq_0 = uop_uses_stq; // @[decode.scala:474:7, :479:17] wire cs_is_sys_pc2epc; // @[decode.scala:490:16] assign io_deq_uop_is_sys_pc2epc_0 = uop_is_sys_pc2epc; // @[decode.scala:474:7, :479:17] wire cs_inst_unique; // @[decode.scala:490:16] assign io_deq_uop_is_unique_0 = uop_is_unique; // @[decode.scala:474:7, :479:17] wire _uop_flush_on_commit_T_3; // @[decode.scala:575:45] assign io_deq_uop_flush_on_commit_0 = uop_flush_on_commit; // @[decode.scala:474:7, :479:17] assign io_deq_uop_ldst_0 = uop_ldst; // @[decode.scala:474:7, :479:17] assign io_deq_uop_lrs1_0 = uop_lrs1; // @[decode.scala:474:7, :479:17] assign io_deq_uop_lrs2_0 = uop_lrs2; // @[decode.scala:474:7, :479:17] assign io_deq_uop_lrs3_0 = uop_lrs3; // @[decode.scala:474:7, :479:17] wire _uop_ldst_val_T_5; // @[decode.scala:540:42] assign io_deq_uop_ldst_val_0 = uop_ldst_val; // @[decode.scala:474:7, :479:17] wire [1:0] cs_dst_type; // @[decode.scala:490:16] assign io_deq_uop_dst_rtype_0 = uop_dst_rtype; // @[decode.scala:474:7, :479:17] wire [1:0] cs_rs1_type; // @[decode.scala:490:16] assign io_deq_uop_lrs1_rtype_0 = uop_lrs1_rtype; // @[decode.scala:474:7, :479:17] wire [1:0] cs_rs2_type; // @[decode.scala:490:16] assign io_deq_uop_lrs2_rtype_0 = uop_lrs2_rtype; // @[decode.scala:474:7, :479:17] wire cs_frs3_en; // @[decode.scala:490:16] assign io_deq_uop_frs3_en_0 = uop_frs3_en; // @[decode.scala:474:7, :479:17] wire cs_fp_val; // @[decode.scala:490:16] assign io_deq_uop_fp_val_0 = uop_fp_val; // @[decode.scala:474:7, :479:17] wire cs_fp_single; // @[decode.scala:490:16] assign io_deq_uop_fp_single_0 = uop_fp_single; // @[decode.scala:474:7, :479:17] assign io_deq_uop_xcpt_pf_if_0 = uop_xcpt_pf_if; // @[decode.scala:474:7, :479:17] assign io_deq_uop_xcpt_ae_if_0 = uop_xcpt_ae_if; // @[decode.scala:474:7, :479:17] assign io_deq_uop_bp_debug_if_0 = uop_bp_debug_if; // @[decode.scala:474:7, :479:17] assign io_deq_uop_bp_xcpt_if_0 = uop_bp_xcpt_if; // @[decode.scala:474:7, :479:17] assign io_deq_uop_debug_fsrc_0 = uop_debug_fsrc; // @[decode.scala:474:7, :479:17] wire cs_decoder_0; // @[Decode.scala:50:77] wire cs_decoder_1; // @[Decode.scala:50:77] assign uop_fp_val = cs_fp_val; // @[decode.scala:479:17, :490:16] wire cs_decoder_2; // @[Decode.scala:50:77] assign uop_fp_single = cs_fp_single; // @[decode.scala:479:17, :490:16] wire [6:0] cs_decoder_3; // @[Decode.scala:50:77] assign uop_uopc = cs_uopc; // @[decode.scala:479:17, :490:16] wire [2:0] cs_decoder_4; // @[Decode.scala:50:77] assign uop_iq_type = cs_iq_type; // @[decode.scala:479:17, :490:16] wire [9:0] cs_decoder_5; // @[Decode.scala:50:77] assign uop_fu_code = cs_fu_code; // @[decode.scala:479:17, :490:16] wire [1:0] cs_decoder_6; // @[Decode.scala:50:77] assign uop_dst_rtype = cs_dst_type; // @[decode.scala:479:17, :490:16] wire [1:0] cs_decoder_7; // @[Decode.scala:50:77] assign uop_lrs1_rtype = cs_rs1_type; // @[decode.scala:479:17, :490:16] wire [1:0] cs_decoder_8; // @[Decode.scala:50:77] assign uop_lrs2_rtype = cs_rs2_type; // @[decode.scala:479:17, :490:16] wire cs_decoder_9; // @[Decode.scala:50:77] assign uop_frs3_en = cs_frs3_en; // @[decode.scala:479:17, :490:16] wire [2:0] cs_decoder_10; // @[Decode.scala:50:77] wire cs_decoder_11; // @[Decode.scala:50:77] assign uop_uses_ldq = cs_uses_ldq; // @[decode.scala:479:17, :490:16] wire cs_decoder_12; // @[Decode.scala:50:77] assign uop_uses_stq = cs_uses_stq; // @[decode.scala:479:17, :490:16] wire cs_decoder_13; // @[Decode.scala:50:77] assign uop_is_amo = cs_is_amo; // @[decode.scala:479:17, :490:16] wire cs_decoder_14; // @[Decode.scala:50:77] assign uop_is_fence = cs_is_fence; // @[decode.scala:479:17, :490:16] wire cs_decoder_15; // @[Decode.scala:50:77] assign uop_is_fencei = cs_is_fencei; // @[decode.scala:479:17, :490:16] wire [4:0] cs_decoder_16; // @[Decode.scala:50:77] assign uop_mem_cmd = cs_mem_cmd; // @[decode.scala:479:17, :490:16] wire [1:0] cs_decoder_17; // @[Decode.scala:50:77] wire cs_decoder_18; // @[Decode.scala:50:77] assign uop_bypassable = cs_bypassable; // @[decode.scala:479:17, :490:16] wire cs_decoder_19; // @[Decode.scala:50:77] assign uop_is_br = cs_is_br; // @[decode.scala:479:17, :490:16] wire cs_decoder_20; // @[Decode.scala:50:77] assign uop_is_sys_pc2epc = cs_is_sys_pc2epc; // @[decode.scala:479:17, :490:16] wire cs_decoder_21; // @[Decode.scala:50:77] assign uop_is_unique = cs_inst_unique; // @[decode.scala:479:17, :490:16] wire cs_decoder_22; // @[Decode.scala:50:77] wire [2:0] cs_decoder_23; // @[Decode.scala:50:77] wire cs_legal; // @[decode.scala:490:16] wire [2:0] cs_imm_sel; // @[decode.scala:490:16] wire [1:0] cs_wakeup_delay; // @[decode.scala:490:16] wire cs_flush_on_commit; // @[decode.scala:490:16] wire [2:0] cs_csr_cmd; // @[decode.scala:490:16] wire [31:0] cs_decoder_decoded_invInputs = ~cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [52:0] cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [52:0] cs_decoder_decoded; // @[pla.scala:81:23] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo = {cs_decoder_decoded_andMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi = {cs_decoder_decoded_andMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T = {cs_decoder_decoded_andMatrixOutputs_hi, cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_77_2 = &_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_1 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_1 = {cs_decoder_decoded_andMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_84_2 = &_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_2 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_2 = {cs_decoder_decoded_andMatrixOutputs_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_8_2 = &_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_3 = {cs_decoder_decoded_andMatrixOutputs_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_29_2 = &_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_4 = {cs_decoder_decoded_andMatrixOutputs_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_124_2 = &_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_5 = {cs_decoder_decoded_andMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_102_2 = &_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_6 = {cs_decoder_decoded_andMatrixOutputs_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_85_2 = &_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_26 = cs_decoder_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_7 = {cs_decoder_decoded_andMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_56_2 = &_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_8 = {cs_decoder_decoded_andMatrixOutputs_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_71_2 = &_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_130_2 = &_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_10 = {cs_decoder_decoded_andMatrixOutputs_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_34_2 = &_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_11 = {cs_decoder_decoded_andMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_163_2 = &_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_12 = {cs_decoder_decoded_andMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_48_2 = &_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_13 = {cs_decoder_decoded_andMatrixOutputs_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_110_2 = &_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_14 = {cs_decoder_decoded_andMatrixOutputs_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_170_2 = &_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_15 = {cs_decoder_decoded_andMatrixOutputs_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_5_2 = &_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_16 = {cs_decoder_decoded_andMatrixOutputs_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_75_2 = &_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_17 = {cs_decoder_decoded_andMatrixOutputs_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_12_2 = &_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_18 = {cs_decoder_decoded_andMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_35_2 = &_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_19 = {cs_decoder_decoded_andMatrixOutputs_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_30_2 = &_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_20 = {cs_decoder_decoded_andMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_24_2 = &_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_21 = {cs_decoder_decoded_andMatrixOutputs_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_144_2 = &_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_22 = {cs_decoder_decoded_andMatrixOutputs_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_28_2 = &_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_23 = {cs_decoder_decoded_andMatrixOutputs_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_126_2 = &_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [4:0] _cs_decoder_decoded_andMatrixOutputs_T_24 = {cs_decoder_decoded_andMatrixOutputs_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_162_2 = &_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_38 = cs_decoder_decoded_andMatrixOutputs_162_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53] wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_25 = {cs_decoder_decoded_andMatrixOutputs_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_1_2 = &_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_26 = {cs_decoder_decoded_andMatrixOutputs_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_17_2 = &_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_27 = {cs_decoder_decoded_andMatrixOutputs_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_98_2 = &_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_28 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_28 = {cs_decoder_decoded_andMatrixOutputs_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_27_2 = &_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_29 = {cs_decoder_decoded_andMatrixOutputs_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_105_2 = &_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_30 = {cs_decoder_decoded_andMatrixOutputs_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_122_2 = &_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_31 = {cs_decoder_decoded_andMatrixOutputs_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_38_2 = &_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_32 = {cs_decoder_decoded_andMatrixOutputs_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_165_2 = &_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_33 = {cs_decoder_decoded_andMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_19_2 = &_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_34 = {cs_decoder_decoded_andMatrixOutputs_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_118_2 = &_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_153_2 = &_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_36 = {cs_decoder_decoded_andMatrixOutputs_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_141_2 = &_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_37 = {cs_decoder_decoded_andMatrixOutputs_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_168_2 = &_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_38 = {cs_decoder_decoded_andMatrixOutputs_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_73_2 = &_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_39 = {cs_decoder_decoded_andMatrixOutputs_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_25_2 = &_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_40 = {cs_decoder_decoded_andMatrixOutputs_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_79_2 = &_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_41 = {cs_decoder_decoded_andMatrixOutputs_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_114_2 = &_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_42 = {cs_decoder_decoded_andMatrixOutputs_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_174_2 = &_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_43 = {cs_decoder_decoded_andMatrixOutputs_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_139_2 = &_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_37 = cs_decoder_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_44 = {cs_decoder_decoded_andMatrixOutputs_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_43_2 = &_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_45 = {cs_decoder_decoded_andMatrixOutputs_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_67_2 = &_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_8 = cs_decoder_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_46 = {cs_decoder_decoded_andMatrixOutputs_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_18_2 = &_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_25 = cs_decoder_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_47 = {cs_decoder_decoded_andMatrixOutputs_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_108_2 = &_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_48 = {cs_decoder_decoded_andMatrixOutputs_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_46_2 = &_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_49 = {cs_decoder_decoded_andMatrixOutputs_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_10_2 = &_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_50 = {cs_decoder_decoded_andMatrixOutputs_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_82_2 = &_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_51 = {cs_decoder_decoded_andMatrixOutputs_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_26_2 = &_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_52 = {cs_decoder_decoded_andMatrixOutputs_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_42_2 = &_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_53 = {cs_decoder_decoded_andMatrixOutputs_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_41_2 = &_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_54 = {cs_decoder_decoded_andMatrixOutputs_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_93_2 = &_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_55 = {cs_decoder_decoded_andMatrixOutputs_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_70_2 = &_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_56 = {cs_decoder_decoded_andMatrixOutputs_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_11_2 = &_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_76_2 = &_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_58 = {cs_decoder_decoded_andMatrixOutputs_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_167_2 = &_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T = cs_decoder_decoded_andMatrixOutputs_167_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_59 = {cs_decoder_decoded_andMatrixOutputs_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_152_2 = &_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_60 = {cs_decoder_decoded_andMatrixOutputs_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_96_2 = &_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_61 = {cs_decoder_decoded_andMatrixOutputs_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_125_2 = &_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_62 = {cs_decoder_decoded_andMatrixOutputs_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_40_2 = &_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_63 = {cs_decoder_decoded_andMatrixOutputs_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_169_2 = &_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_64 = {cs_decoder_decoded_andMatrixOutputs_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_69_2 = &_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_65 = {cs_decoder_decoded_andMatrixOutputs_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_3_2 = &_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_66 = {cs_decoder_decoded_andMatrixOutputs_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_16_2 = &_cs_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_67 = {cs_decoder_decoded_andMatrixOutputs_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_112_2 = &_cs_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_68 = {cs_decoder_decoded_andMatrixOutputs_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_160_2 = &_cs_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_69 = {cs_decoder_decoded_andMatrixOutputs_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_101_2 = &_cs_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_70 = {cs_decoder_decoded_andMatrixOutputs_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_15_2 = &_cs_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_23 = cs_decoder_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_71 = {cs_decoder_decoded_andMatrixOutputs_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_23_2 = &_cs_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_72 = {cs_decoder_decoded_andMatrixOutputs_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_173_2 = &_cs_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_73 = {cs_decoder_decoded_andMatrixOutputs_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_137_2 = &_cs_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_1 = cs_decoder_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_74 = {cs_decoder_decoded_andMatrixOutputs_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_20_2 = &_cs_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_75 = {cs_decoder_decoded_andMatrixOutputs_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_54_2 = &_cs_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_76 = {cs_decoder_decoded_andMatrixOutputs_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_97_2 = &_cs_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_77 = {cs_decoder_decoded_andMatrixOutputs_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_157_2 = &_cs_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_78 = {cs_decoder_decoded_andMatrixOutputs_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_145_2 = &_cs_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_79 = {cs_decoder_decoded_andMatrixOutputs_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_134_2 = &_cs_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_80 = {cs_decoder_decoded_andMatrixOutputs_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_128_2 = &_cs_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_81 = {cs_decoder_decoded_andMatrixOutputs_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_142_2 = &_cs_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_117_2 = &_cs_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_83 = {cs_decoder_decoded_andMatrixOutputs_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_53_2 = &_cs_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_84 = {cs_decoder_decoded_andMatrixOutputs_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_166_2 = &_cs_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_85 = {cs_decoder_decoded_andMatrixOutputs_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_21_2 = &_cs_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_86 = {cs_decoder_decoded_andMatrixOutputs_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_65_2 = &_cs_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_87 = {cs_decoder_decoded_andMatrixOutputs_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_52_2 = &_cs_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_88 = {cs_decoder_decoded_andMatrixOutputs_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_57_2 = &_cs_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_74_2 = &_cs_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_90 = {cs_decoder_decoded_andMatrixOutputs_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_91_2 = &_cs_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_91 = {cs_decoder_decoded_andMatrixOutputs_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_104_2 = &_cs_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_92 = {cs_decoder_decoded_andMatrixOutputs_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_68_2 = &_cs_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_93 = {cs_decoder_decoded_andMatrixOutputs_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_94_2 = &_cs_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_94 = {cs_decoder_decoded_andMatrixOutputs_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_151_2 = &_cs_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_95 = {cs_decoder_decoded_andMatrixOutputs_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_2_2 = &_cs_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_96 = {cs_decoder_decoded_andMatrixOutputs_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_156_2 = &_cs_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_97 = {cs_decoder_decoded_andMatrixOutputs_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_154_2 = &_cs_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_98 = {cs_decoder_decoded_andMatrixOutputs_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_148_2 = &_cs_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_99 = {cs_decoder_decoded_andMatrixOutputs_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_89_2 = &_cs_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_100 = {cs_decoder_decoded_andMatrixOutputs_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_55_2 = &_cs_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_101 = {cs_decoder_decoded_andMatrixOutputs_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_116_2 = &_cs_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_102 = {cs_decoder_decoded_andMatrixOutputs_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_131_2 = &_cs_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_103 = {cs_decoder_decoded_andMatrixOutputs_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_172_2 = &_cs_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_104 = {cs_decoder_decoded_andMatrixOutputs_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_72_2 = &_cs_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_105 = {cs_decoder_decoded_andMatrixOutputs_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_81_2 = &_cs_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_106 = {cs_decoder_decoded_andMatrixOutputs_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_6_2 = &_cs_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_59 = cs_decoder_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_107 = {cs_decoder_decoded_andMatrixOutputs_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_143_2 = &_cs_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_108 = {cs_decoder_decoded_andMatrixOutputs_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_66_2 = &_cs_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_109 = {cs_decoder_decoded_andMatrixOutputs_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_63_2 = &_cs_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_110 = {cs_decoder_decoded_andMatrixOutputs_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_161_2 = &_cs_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_111 = {cs_decoder_decoded_andMatrixOutputs_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_132_2 = &_cs_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_112 = {cs_decoder_decoded_andMatrixOutputs_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_133_2 = &_cs_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_113 = {cs_decoder_decoded_andMatrixOutputs_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_147_2 = &_cs_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_114 = {cs_decoder_decoded_andMatrixOutputs_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_129_2 = &_cs_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_115 = {cs_decoder_decoded_andMatrixOutputs_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_100_2 = &_cs_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_116 = {cs_decoder_decoded_andMatrixOutputs_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_119_2 = &_cs_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_117 = {cs_decoder_decoded_andMatrixOutputs_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_150_2 = &_cs_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_118 = {cs_decoder_decoded_andMatrixOutputs_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_121_2 = &_cs_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_119 = {cs_decoder_decoded_andMatrixOutputs_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_158_2 = &_cs_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_120 = {cs_decoder_decoded_andMatrixOutputs_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_49_2 = &_cs_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_121 = {cs_decoder_decoded_andMatrixOutputs_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_50_2 = &_cs_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_122 = {cs_decoder_decoded_andMatrixOutputs_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_45_2 = &_cs_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_123 = {cs_decoder_decoded_andMatrixOutputs_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_135_2 = &_cs_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_124 = {cs_decoder_decoded_andMatrixOutputs_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_140_2 = &_cs_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_122 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_125 = {cs_decoder_decoded_andMatrixOutputs_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_95_2 = &_cs_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_123 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_126 = {cs_decoder_decoded_andMatrixOutputs_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_115_2 = &_cs_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_127 = {cs_decoder_decoded_andMatrixOutputs_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_60_2 = &_cs_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _cs_decoder_decoded_orMatrixOutputs_T_24 = cs_decoder_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_128 = {cs_decoder_decoded_andMatrixOutputs_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_7_2 = &_cs_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_129 = {cs_decoder_decoded_andMatrixOutputs_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_14_2 = &_cs_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_130 = {cs_decoder_decoded_andMatrixOutputs_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_92_2 = &_cs_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_131 = {cs_decoder_decoded_andMatrixOutputs_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_78_2 = &_cs_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_132 = {cs_decoder_decoded_andMatrixOutputs_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_47_2 = &_cs_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_130 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_133 = {cs_decoder_decoded_andMatrixOutputs_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_4_2 = &_cs_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_131 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_134 = {cs_decoder_decoded_andMatrixOutputs_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_123_2 = &_cs_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_132 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_135 = {cs_decoder_decoded_andMatrixOutputs_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_107_2 = &_cs_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_133 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_136 = {cs_decoder_decoded_andMatrixOutputs_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_33_2 = &_cs_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_134 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_137 = {cs_decoder_decoded_andMatrixOutputs_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_88_2 = &_cs_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_135 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_138 = {cs_decoder_decoded_andMatrixOutputs_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_87_2 = &_cs_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_136 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_139 = {cs_decoder_decoded_andMatrixOutputs_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_37_2 = &_cs_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_137 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_140 = {cs_decoder_decoded_andMatrixOutputs_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_22_2 = &_cs_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_138 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_141 = {cs_decoder_decoded_andMatrixOutputs_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_58_2 = &_cs_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_139 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_142 = {cs_decoder_decoded_andMatrixOutputs_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_62_2 = &_cs_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_140 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_143 = {cs_decoder_decoded_andMatrixOutputs_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_9_2 = &_cs_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_141 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_144 = {cs_decoder_decoded_andMatrixOutputs_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_64_2 = &_cs_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_142 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_145 = {cs_decoder_decoded_andMatrixOutputs_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_146_2 = &_cs_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_143 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_146, cs_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_146 = {cs_decoder_decoded_andMatrixOutputs_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_113_2 = &_cs_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_144 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_147, cs_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_147 = {cs_decoder_decoded_andMatrixOutputs_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_80_2 = &_cs_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_145 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_148, cs_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_148 = {cs_decoder_decoded_andMatrixOutputs_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_44_2 = &_cs_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_146 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_149, cs_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_149 = {cs_decoder_decoded_andMatrixOutputs_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_159_2 = &_cs_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_147 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_150, cs_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_150 = {cs_decoder_decoded_andMatrixOutputs_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_0_2 = &_cs_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_148 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_151, cs_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_151 = {cs_decoder_decoded_andMatrixOutputs_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_99_2 = &_cs_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_149 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_152, cs_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_152 = {cs_decoder_decoded_andMatrixOutputs_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_13_2 = &_cs_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_150 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_153, cs_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_153 = {cs_decoder_decoded_andMatrixOutputs_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_120_2 = &_cs_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_151 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_154, cs_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_154 = {cs_decoder_decoded_andMatrixOutputs_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_171_2 = &_cs_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_152 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_155, cs_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_155 = {cs_decoder_decoded_andMatrixOutputs_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_109_2 = &_cs_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_153 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_156, cs_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_156 = {cs_decoder_decoded_andMatrixOutputs_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_59_2 = &_cs_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_154 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_157, cs_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_157 = {cs_decoder_decoded_andMatrixOutputs_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_106_2 = &_cs_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_155 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:90:45, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_158, cs_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_158 = {cs_decoder_decoded_andMatrixOutputs_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_155_2 = &_cs_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_156 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_159, cs_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_159 = {cs_decoder_decoded_andMatrixOutputs_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_149_2 = &_cs_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_157 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_160, cs_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_160 = {cs_decoder_decoded_andMatrixOutputs_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_136_2 = &_cs_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_158 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_161, cs_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_161 = {cs_decoder_decoded_andMatrixOutputs_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_31_2 = &_cs_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_159 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_162, cs_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_162 = {cs_decoder_decoded_andMatrixOutputs_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_90_2 = &_cs_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_160 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_163, cs_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_163 = {cs_decoder_decoded_andMatrixOutputs_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_39_2 = &_cs_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_161 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_164, cs_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_164 = {cs_decoder_decoded_andMatrixOutputs_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_83_2 = &_cs_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_162 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_165, cs_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_165 = {cs_decoder_decoded_andMatrixOutputs_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_103_2 = &_cs_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_163 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_166, cs_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_166 = {cs_decoder_decoded_andMatrixOutputs_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_138_2 = &_cs_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_164 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_167, cs_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_167 = {cs_decoder_decoded_andMatrixOutputs_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_86_2 = &_cs_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_165 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_168, cs_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_168 = {cs_decoder_decoded_andMatrixOutputs_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_111_2 = &_cs_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_169 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_166 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_169 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_169 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_169, cs_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_169 = {cs_decoder_decoded_andMatrixOutputs_hi_169, cs_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_32_2 = &_cs_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_169 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_170 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_169, cs_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_167 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_170 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_170 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_170, cs_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_170 = {cs_decoder_decoded_andMatrixOutputs_hi_170, cs_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_127_2 = &_cs_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_170 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_171 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_170, cs_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_168 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_171 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_171 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_171, cs_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_171 = {cs_decoder_decoded_andMatrixOutputs_hi_171, cs_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_164_2 = &_cs_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_171 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_172 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_171, cs_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_169 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_172 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_172 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_172, cs_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_172 = {cs_decoder_decoded_andMatrixOutputs_hi_172, cs_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_61_2 = &_cs_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_172 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_173 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_172, cs_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_170 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_173 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_173 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_173, cs_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_173 = {cs_decoder_decoded_andMatrixOutputs_hi_173, cs_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_36_2 = &_cs_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107}; // @[pla.scala:91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_173 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_174 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_173, cs_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_171 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:91:29, :98:53] wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174}; // @[pla.scala:91:29, :98:53] wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_174 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_174 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_174, cs_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_174 = {cs_decoder_decoded_andMatrixOutputs_hi_174, cs_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire cs_decoder_decoded_andMatrixOutputs_51_2 = &_cs_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire [1:0] _GEN = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_13; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_13 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo = {cs_decoder_decoded_orMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_0 = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi = _GEN_0; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_14; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_14 = _GEN_0; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_2 = {cs_decoder_decoded_orMatrixOutputs_hi, cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_3 = |_cs_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_1 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = _GEN_1; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = _GEN_1; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_2 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = _GEN_2; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_2; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_4 = {cs_decoder_decoded_orMatrixOutputs_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_5 = |_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_6 = {cs_decoder_decoded_orMatrixOutputs_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_7 = |_cs_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_10 = |_cs_decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_3 = {cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = _GEN_3; // @[pla.scala:114:19] wire [1:0] _GEN_4 = {cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = _GEN_4; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = _GEN_4; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_5 = {cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_5; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = _GEN_5; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_11 = {cs_decoder_decoded_orMatrixOutputs_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_12 = |_cs_decoder_decoded_orMatrixOutputs_T_11; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_6 = {cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = _GEN_6; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_139_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_7 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = _GEN_7; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = _GEN_7; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_124_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_8 = {cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [14:0] _cs_decoder_decoded_orMatrixOutputs_T_13 = {cs_decoder_decoded_orMatrixOutputs_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_14 = |_cs_decoder_decoded_orMatrixOutputs_T_13; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_5 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_9; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_18 = _GEN_9; // @[pla.scala:114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_15 = {cs_decoder_decoded_orMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_16 = |_cs_decoder_decoded_orMatrixOutputs_T_15; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_17 = {cs_decoder_decoded_orMatrixOutputs_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_18 = |_cs_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_19 = {cs_decoder_decoded_orMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_20 = |_cs_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_21 = {cs_decoder_decoded_orMatrixOutputs_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_22 = |_cs_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_10 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_27 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_7 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_12; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_12 = _GEN_10; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_16; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_16 = _GEN_10; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_28 = |_cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_29 = {cs_decoder_decoded_orMatrixOutputs_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_30 = |_cs_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_40_2, cs_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_31 = {cs_decoder_decoded_orMatrixOutputs_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_32 = |_cs_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_33 = {cs_decoder_decoded_orMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_34 = |_cs_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_35 = {cs_decoder_decoded_orMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_36 = |_cs_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_11 = {cs_decoder_decoded_andMatrixOutputs_4_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = _GEN_11; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = _GEN_11; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_12 = {cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_6; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = _GEN_12; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = _GEN_12; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_39 = {cs_decoder_decoded_orMatrixOutputs_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_40 = |_cs_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_59_2, cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = _GEN_13; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = _GEN_13; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_14 = {cs_decoder_decoded_andMatrixOutputs_137_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = _GEN_14; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = _GEN_14; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] _GEN_15 = {cs_decoder_decoded_andMatrixOutputs_167_2, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = _GEN_15; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = _GEN_15; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = _GEN_16; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_16; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [24:0] _cs_decoder_decoded_orMatrixOutputs_T_41 = {cs_decoder_decoded_orMatrixOutputs_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_42 = |_cs_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_17 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = _GEN_17; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_43 = {cs_decoder_decoded_orMatrixOutputs_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_44 = |_cs_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_45 = {cs_decoder_decoded_orMatrixOutputs_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_46 = |_cs_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_18 = {cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_7 = _GEN_18; // @[pla.scala:114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_66 = _GEN_18; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_19 = {cs_decoder_decoded_andMatrixOutputs_1_2, cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = _GEN_19; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_19; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_47 = {cs_decoder_decoded_orMatrixOutputs_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_48 = |_cs_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_20 = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_20; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_20; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_6_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_16_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = _GEN_21; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = _GEN_21; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_22; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = _GEN_22; // @[pla.scala:114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_5_2, cs_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_49 = {cs_decoder_decoded_orMatrixOutputs_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_50 = |_cs_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_144_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_170_2, cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [12:0] _cs_decoder_decoded_orMatrixOutputs_T_51 = {cs_decoder_decoded_orMatrixOutputs_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_52 = |_cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_53 = {cs_decoder_decoded_orMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_54 = |_cs_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_55 = {cs_decoder_decoded_orMatrixOutputs_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_56 = |_cs_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_148_2, cs_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_58 = |_cs_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_60 = {cs_decoder_decoded_orMatrixOutputs_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_61 = |_cs_decoder_decoded_orMatrixOutputs_T_60; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_37_2, cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_62 = {cs_decoder_decoded_orMatrixOutputs_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_63 = |_cs_decoder_decoded_orMatrixOutputs_T_62; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_23 = {cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:19] assign _cs_decoder_decoded_orMatrixOutputs_T_64 = _GEN_23; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = _GEN_23; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_65 = |_cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:{19,36}] wire _cs_decoder_decoded_orMatrixOutputs_T_67 = |_cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_24 = {cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_19; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_19 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_13; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_13 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_24; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_101_2, cs_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_68 = {cs_decoder_decoded_orMatrixOutputs_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_69 = |_cs_decoder_decoded_orMatrixOutputs_T_68; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_25; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_125_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [17:0] _cs_decoder_decoded_orMatrixOutputs_T_70 = {cs_decoder_decoded_orMatrixOutputs_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_71 = |_cs_decoder_decoded_orMatrixOutputs_T_70; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [7:0] _cs_decoder_decoded_orMatrixOutputs_T_72 = {cs_decoder_decoded_orMatrixOutputs_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_73 = |_cs_decoder_decoded_orMatrixOutputs_T_72; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_74 = {cs_decoder_decoded_orMatrixOutputs_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_75 = |_cs_decoder_decoded_orMatrixOutputs_T_74; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_61_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_80_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_62_2, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] _GEN_26 = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = _GEN_26; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_150_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_151_2, cs_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [17:0] cs_decoder_decoded_orMatrixOutputs_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_76_2, cs_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_165_2, cs_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_8_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] cs_decoder_decoded_orMatrixOutputs_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [36:0] _cs_decoder_decoded_orMatrixOutputs_T_76 = {cs_decoder_decoded_orMatrixOutputs_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_77 = |_cs_decoder_decoded_orMatrixOutputs_T_76; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_72_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_52_2, cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_20_2, cs_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_160_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_41_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_10_2, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_27 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = _GEN_27; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [33:0] _cs_decoder_decoded_orMatrixOutputs_T_78 = {cs_decoder_decoded_orMatrixOutputs_hi_29, cs_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_79 = |_cs_decoder_decoded_orMatrixOutputs_T_78; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_148_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_42_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] _GEN_28 = {cs_decoder_decoded_andMatrixOutputs_27_2, cs_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = _GEN_28; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_28; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_30_2, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_130_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [27:0] _cs_decoder_decoded_orMatrixOutputs_T_80 = {cs_decoder_decoded_orMatrixOutputs_hi_30, cs_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_81 = |_cs_decoder_decoded_orMatrixOutputs_T_80; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_59_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_22_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_129_2, cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_66_2, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] _GEN_29 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_82 = {cs_decoder_decoded_orMatrixOutputs_hi_31, cs_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_83 = |_cs_decoder_decoded_orMatrixOutputs_T_82; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_136_2, cs_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_146_2, cs_decoder_decoded_andMatrixOutputs_113_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_154_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] cs_decoder_decoded_orMatrixOutputs_hi_32 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_24, cs_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [20:0] _cs_decoder_decoded_orMatrixOutputs_T_84 = {cs_decoder_decoded_orMatrixOutputs_hi_32, cs_decoder_decoded_orMatrixOutputs_lo_27}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_85 = |_cs_decoder_decoded_orMatrixOutputs_T_84; // @[pla.scala:114:{19,36}] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_55_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_139_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19] wire [11:0] cs_decoder_decoded_orMatrixOutputs_hi_33 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_25, cs_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [23:0] _cs_decoder_decoded_orMatrixOutputs_T_86 = {cs_decoder_decoded_orMatrixOutputs_hi_33, cs_decoder_decoded_orMatrixOutputs_lo_28}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_87 = |_cs_decoder_decoded_orMatrixOutputs_T_86; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_31_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_29 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_147_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19] wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_34 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_26, cs_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:114:19] wire [17:0] _cs_decoder_decoded_orMatrixOutputs_T_88 = {cs_decoder_decoded_orMatrixOutputs_hi_34, cs_decoder_decoded_orMatrixOutputs_lo_29}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_89 = |_cs_decoder_decoded_orMatrixOutputs_T_88; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_111_2, cs_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_171_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_30 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_lo_21}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_107_2, cs_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_35 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_27, cs_decoder_decoded_orMatrixOutputs_hi_lo_22}; // @[pla.scala:114:19] wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_90 = {cs_decoder_decoded_orMatrixOutputs_hi_35, cs_decoder_decoded_orMatrixOutputs_lo_30}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_91 = |_cs_decoder_decoded_orMatrixOutputs_T_90; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_90_2, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_31 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_lo_22}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_36 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_28, cs_decoder_decoded_orMatrixOutputs_hi_lo_23}; // @[pla.scala:114:19] wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_92 = {cs_decoder_decoded_orMatrixOutputs_hi_36, cs_decoder_decoded_orMatrixOutputs_lo_31}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_93 = |_cs_decoder_decoded_orMatrixOutputs_T_92; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_95_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19] wire [19:0] cs_decoder_decoded_orMatrixOutputs_lo_32 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_lo_23}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_70_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_114_2, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_170_2, cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [10:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19] wire [20:0] cs_decoder_decoded_orMatrixOutputs_hi_37 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_29, cs_decoder_decoded_orMatrixOutputs_hi_lo_24}; // @[pla.scala:114:19] wire [40:0] _cs_decoder_decoded_orMatrixOutputs_T_94 = {cs_decoder_decoded_orMatrixOutputs_hi_37, cs_decoder_decoded_orMatrixOutputs_lo_32}; // @[pla.scala:114:19] wire _cs_decoder_decoded_orMatrixOutputs_T_95 = |_cs_decoder_decoded_orMatrixOutputs_T_94; // @[pla.scala:114:{19,36}] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_3, _cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_8, _cs_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_14, _cs_decoder_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_10}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_18, _cs_decoder_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_22, _cs_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36] wire [12:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_25, _cs_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_23}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_30, _cs_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_36, _cs_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_38, _cs_decoder_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {_cs_decoder_decoded_orMatrixOutputs_T_42, _cs_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36] wire [12:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:102:36] wire [25:0] cs_decoder_decoded_orMatrixOutputs_lo_33 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_lo_24}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_48, _cs_decoder_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_54, _cs_decoder_decoded_orMatrixOutputs_T_52}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_59, _cs_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_63, _cs_decoder_decoded_orMatrixOutputs_T_61}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_67, _cs_decoder_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36] wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_73, _cs_decoder_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_69}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_77, _cs_decoder_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_81, _cs_decoder_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_87, _cs_decoder_decoded_orMatrixOutputs_T_85}; // @[pla.scala:102:36, :114:36] wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_83}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_91, _cs_decoder_decoded_orMatrixOutputs_T_89}; // @[pla.scala:102:36, :114:36] wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {_cs_decoder_decoded_orMatrixOutputs_T_95, _cs_decoder_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36] wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:102:36] wire [26:0] cs_decoder_decoded_orMatrixOutputs_hi_38 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_30, cs_decoder_decoded_orMatrixOutputs_hi_lo_25}; // @[pla.scala:102:36] wire [52:0] cs_decoder_decoded_orMatrixOutputs = {cs_decoder_decoded_orMatrixOutputs_hi_38, cs_decoder_decoded_orMatrixOutputs_lo_33}; // @[pla.scala:102:36] wire _cs_decoder_decoded_invMatrixOutputs_T = cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_1 = cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_2 = cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_3 = cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_4 = cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_5 = cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_6 = cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_7 = cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_8 = cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_9 = cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_10 = cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_11 = cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_12 = cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_13 = cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_14 = cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_15 = cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_16 = cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_17 = cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_18 = cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_19 = cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_20 = cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_21 = cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_22 = cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_23 = cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_24 = cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_25 = cs_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_26 = cs_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_27 = cs_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_28 = cs_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_29 = cs_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_30 = ~_cs_decoder_decoded_invMatrixOutputs_T_29; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_31 = cs_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_32 = cs_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_33 = cs_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_34 = cs_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_35 = cs_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_36 = cs_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_37 = cs_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_38 = cs_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_39 = cs_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_40 = cs_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_41 = cs_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :123:56] wire _cs_decoder_decoded_invMatrixOutputs_T_42 = ~_cs_decoder_decoded_invMatrixOutputs_T_41; // @[pla.scala:123:{40,56}] wire _cs_decoder_decoded_invMatrixOutputs_T_43 = cs_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_44 = cs_decoder_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_45 = cs_decoder_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_46 = cs_decoder_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_47 = cs_decoder_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_48 = cs_decoder_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_49 = cs_decoder_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_50 = cs_decoder_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_51 = cs_decoder_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_52 = cs_decoder_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_53 = cs_decoder_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _cs_decoder_decoded_invMatrixOutputs_T_54 = cs_decoder_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_2, _cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_5, _cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [5:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_8, _cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_10, _cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_12, _cs_decoder_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [12:0] cs_decoder_decoded_invMatrixOutputs_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_15, _cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_18, _cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [5:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_21, _cs_decoder_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_23, _cs_decoder_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_25, _cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [12:0] cs_decoder_decoded_invMatrixOutputs_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [25:0] cs_decoder_decoded_invMatrixOutputs_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_28, _cs_decoder_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_32, _cs_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :123:40] wire [5:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_35, _cs_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_37, _cs_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_39, _cs_decoder_decoded_invMatrixOutputs_T_38}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [12:0] cs_decoder_decoded_invMatrixOutputs_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_43, _cs_decoder_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_45, _cs_decoder_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_47, _cs_decoder_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_50, _cs_decoder_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_52, _cs_decoder_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31] wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_54, _cs_decoder_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [13:0] cs_decoder_decoded_invMatrixOutputs_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [26:0] cs_decoder_decoded_invMatrixOutputs_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded_invMatrixOutputs = {cs_decoder_decoded_invMatrixOutputs_hi, cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign cs_decoder_decoded = cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign cs_decoder_0 = cs_decoder_decoded[52]; // @[pla.scala:81:23] assign cs_legal = cs_decoder_0; // @[Decode.scala:50:77] assign cs_decoder_1 = cs_decoder_decoded[51]; // @[pla.scala:81:23] assign cs_fp_val = cs_decoder_1; // @[Decode.scala:50:77] assign cs_decoder_2 = cs_decoder_decoded[50]; // @[pla.scala:81:23] assign cs_fp_single = cs_decoder_2; // @[Decode.scala:50:77] assign cs_decoder_3 = cs_decoder_decoded[49:43]; // @[pla.scala:81:23] assign cs_uopc = cs_decoder_3; // @[Decode.scala:50:77] assign cs_decoder_4 = cs_decoder_decoded[42:40]; // @[pla.scala:81:23] assign cs_iq_type = cs_decoder_4; // @[Decode.scala:50:77] assign cs_decoder_5 = cs_decoder_decoded[39:30]; // @[pla.scala:81:23] assign cs_fu_code = cs_decoder_5; // @[Decode.scala:50:77] assign cs_decoder_6 = cs_decoder_decoded[29:28]; // @[pla.scala:81:23] assign cs_dst_type = cs_decoder_6; // @[Decode.scala:50:77] assign cs_decoder_7 = cs_decoder_decoded[27:26]; // @[pla.scala:81:23] assign cs_rs1_type = cs_decoder_7; // @[Decode.scala:50:77] assign cs_decoder_8 = cs_decoder_decoded[25:24]; // @[pla.scala:81:23] assign cs_rs2_type = cs_decoder_8; // @[Decode.scala:50:77] assign cs_decoder_9 = cs_decoder_decoded[23]; // @[pla.scala:81:23] assign cs_frs3_en = cs_decoder_9; // @[Decode.scala:50:77] assign cs_decoder_10 = cs_decoder_decoded[22:20]; // @[pla.scala:81:23] assign cs_imm_sel = cs_decoder_10; // @[Decode.scala:50:77] assign cs_decoder_11 = cs_decoder_decoded[19]; // @[pla.scala:81:23] assign cs_uses_ldq = cs_decoder_11; // @[Decode.scala:50:77] assign cs_decoder_12 = cs_decoder_decoded[18]; // @[pla.scala:81:23] assign cs_uses_stq = cs_decoder_12; // @[Decode.scala:50:77] assign cs_decoder_13 = cs_decoder_decoded[17]; // @[pla.scala:81:23] assign cs_is_amo = cs_decoder_13; // @[Decode.scala:50:77] assign cs_decoder_14 = cs_decoder_decoded[16]; // @[pla.scala:81:23] assign cs_is_fence = cs_decoder_14; // @[Decode.scala:50:77] assign cs_decoder_15 = cs_decoder_decoded[15]; // @[pla.scala:81:23] assign cs_is_fencei = cs_decoder_15; // @[Decode.scala:50:77] assign cs_decoder_16 = cs_decoder_decoded[14:10]; // @[pla.scala:81:23] assign cs_mem_cmd = cs_decoder_16; // @[Decode.scala:50:77] assign cs_decoder_17 = cs_decoder_decoded[9:8]; // @[pla.scala:81:23] assign cs_wakeup_delay = cs_decoder_17; // @[Decode.scala:50:77] assign cs_decoder_18 = cs_decoder_decoded[7]; // @[pla.scala:81:23] assign cs_bypassable = cs_decoder_18; // @[Decode.scala:50:77] assign cs_decoder_19 = cs_decoder_decoded[6]; // @[pla.scala:81:23] assign cs_is_br = cs_decoder_19; // @[Decode.scala:50:77] assign cs_decoder_20 = cs_decoder_decoded[5]; // @[pla.scala:81:23] assign cs_is_sys_pc2epc = cs_decoder_20; // @[Decode.scala:50:77] assign cs_decoder_21 = cs_decoder_decoded[4]; // @[pla.scala:81:23] assign cs_inst_unique = cs_decoder_21; // @[Decode.scala:50:77] assign cs_decoder_22 = cs_decoder_decoded[3]; // @[pla.scala:81:23] assign cs_flush_on_commit = cs_decoder_22; // @[Decode.scala:50:77] assign cs_decoder_23 = cs_decoder_decoded[2:0]; // @[pla.scala:81:23] assign cs_csr_cmd = cs_decoder_23; // @[Decode.scala:50:77] wire _GEN_30 = cs_csr_cmd == 3'h6; // @[package.scala:16:47] wire _csr_en_T; // @[package.scala:16:47] assign _csr_en_T = _GEN_30; // @[package.scala:16:47] wire _csr_ren_T; // @[package.scala:16:47] assign _csr_ren_T = _GEN_30; // @[package.scala:16:47] wire _csr_en_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_en_T_2 = cs_csr_cmd == 3'h5; // @[package.scala:16:47] wire _csr_en_T_3 = _csr_en_T | _csr_en_T_1; // @[package.scala:16:47, :81:59] wire csr_en = _csr_en_T_3 | _csr_en_T_2; // @[package.scala:16:47, :81:59] wire _csr_ren_T_1 = &cs_csr_cmd; // @[package.scala:16:47] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _csr_ren_T_3 = ~(|uop_lrs1); // @[decode.scala:479:17, :495:62] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[package.scala:81:59] wire system_insn = cs_csr_cmd == 3'h4; // @[decode.scala:490:16, :496:32] wire sfence = cs_uopc == 7'h6B; // @[decode.scala:490:16, :497:24] wire _id_illegal_insn_T = ~cs_legal; // @[decode.scala:490:16, :502:25] wire _id_illegal_insn_T_1 = cs_fp_val & io_csr_decode_fp_illegal_0; // @[decode.scala:474:7, :490:16, :503:15] wire _id_illegal_insn_T_2 = _id_illegal_insn_T | _id_illegal_insn_T_1; // @[decode.scala:502:{25,35}, :503:15] wire _id_illegal_insn_T_4 = _id_illegal_insn_T_2; // @[decode.scala:502:35, :503:43] wire _id_illegal_insn_T_8 = _id_illegal_insn_T_4; // @[decode.scala:503:43, :504:43] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_8; // @[decode.scala:504:43, :505:43] wire _id_illegal_insn_T_9 = ~cs_fp_single; // @[decode.scala:490:16, :506:19] wire _id_illegal_insn_T_10 = cs_fp_val & _id_illegal_insn_T_9; // @[decode.scala:490:16, :506:{16,19}] wire _id_illegal_insn_T_15 = ~csr_ren; // @[decode.scala:495:50, :507:46] wire _id_illegal_insn_T_16 = _id_illegal_insn_T_15 & io_csr_decode_write_illegal_0; // @[decode.scala:474:7, :507:{46,55}] wire _id_illegal_insn_T_17 = io_csr_decode_read_illegal_0 | _id_illegal_insn_T_16; // @[decode.scala:474:7, :507:{43,55}] wire _id_illegal_insn_T_18 = csr_en & _id_illegal_insn_T_17; // @[package.scala:81:59] wire _id_illegal_insn_T_19 = _id_illegal_insn_T_14 | _id_illegal_insn_T_18; // @[decode.scala:505:43, :506:61, :507:12] wire _id_illegal_insn_T_20 = sfence | system_insn; // @[decode.scala:496:32, :497:24, :508:14] wire _id_illegal_insn_T_21 = _id_illegal_insn_T_20 & io_csr_decode_system_illegal_0; // @[decode.scala:474:7, :508:{14,30}] wire id_illegal_insn = _id_illegal_insn_T_19 | _id_illegal_insn_T_21; // @[decode.scala:506:61, :507:87, :508:30] wire _T_1 = io_interrupt_0 & ~io_enq_uop_is_sfb_0; // @[decode.scala:474:7, :516:{19,22}] assign xcpt_valid = _T_1 | uop_bp_debug_if | uop_bp_xcpt_if | uop_xcpt_pf_if | uop_xcpt_ae_if | id_illegal_insn; // @[decode.scala:479:17, :507:87, :513:26, :516:19] assign uop_exception = xcpt_valid; // @[decode.scala:479:17, :513:26] assign xcpt_cause = _T_1 ? io_interrupt_cause_0 : {60'h0, uop_bp_debug_if ? 4'hE : uop_bp_xcpt_if ? 4'h3 : uop_xcpt_pf_if ? 4'hC : {2'h0, uop_xcpt_ae_if ? 2'h1 : 2'h2}}; // @[Mux.scala:50:70] assign uop_exc_cause = xcpt_cause; // @[Mux.scala:50:70] wire [4:0] _uop_ldst_T = uop_inst[11:7]; // @[decode.scala:479:17, :535:25] wire [4:0] _uop_lrs2_T_1 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :550:28] wire [4:0] _uop_lrs1_T_1 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :554:28] wire [4:0] _di24_20_T_3 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :583:69] assign uop_ldst = {1'h0, _uop_ldst_T}; // @[decode.scala:479:17, :535:{18,25}] wire [4:0] _uop_lrs1_T = uop_inst[19:15]; // @[decode.scala:479:17, :536:25] assign uop_lrs1 = {1'h0, _uop_lrs1_T}; // @[decode.scala:479:17, :536:{18,25}] wire [4:0] _uop_lrs2_T = uop_inst[24:20]; // @[decode.scala:479:17, :537:25] wire [4:0] _di24_20_T_4 = uop_inst[24:20]; // @[decode.scala:479:17, :537:25, :583:81] assign uop_lrs2 = {1'h0, _uop_lrs2_T}; // @[decode.scala:479:17, :537:{18,25}] wire [4:0] _uop_lrs3_T = uop_inst[31:27]; // @[decode.scala:479:17, :538:25] assign uop_lrs3 = {1'h0, _uop_lrs3_T}; // @[decode.scala:479:17, :538:{18,25}] wire _uop_ldst_val_T = cs_dst_type != 2'h2; // @[decode.scala:490:16, :540:33] wire _uop_ldst_val_T_1 = uop_ldst == 6'h0; // @[decode.scala:474:7, :477:14, :479:17, :540:56] wire _uop_ldst_val_T_2 = uop_dst_rtype == 2'h0; // @[decode.scala:474:7, :477:14, :479:17, :540:81] wire _uop_ldst_val_T_3 = _uop_ldst_val_T_1 & _uop_ldst_val_T_2; // @[decode.scala:540:{56,64,81}] wire _uop_ldst_val_T_4 = ~_uop_ldst_val_T_3; // @[decode.scala:540:{45,64}] assign _uop_ldst_val_T_5 = _uop_ldst_val_T & _uop_ldst_val_T_4; // @[decode.scala:540:{33,42,45}] assign uop_ldst_val = _uop_ldst_val_T_5; // @[decode.scala:479:17, :540:42] wire _uop_ldst_is_rs1_T = ~uop_is_br; // @[decode.scala:479:17] wire _uop_ldst_is_rs1_T_1 = _uop_ldst_is_rs1_T & uop_is_sfb; // @[decode.scala:479:17] wire _uop_mem_size_T = cs_mem_cmd == 5'h14; // @[package.scala:16:47] wire _uop_mem_size_T_1 = cs_mem_cmd == 5'h5; // @[package.scala:16:47] wire _uop_mem_size_T_2 = _uop_mem_size_T | _uop_mem_size_T_1; // @[package.scala:16:47, :81:59] wire _uop_mem_size_T_3 = |uop_lrs2; // @[decode.scala:479:17, :566:81] wire _uop_mem_size_T_4 = |uop_lrs1; // @[decode.scala:479:17, :495:62, :566:99] wire [1:0] _uop_mem_size_T_5 = {_uop_mem_size_T_3, _uop_mem_size_T_4}; // @[decode.scala:566:{71,81,99}] wire [1:0] _uop_mem_size_T_6 = uop_inst[13:12]; // @[decode.scala:479:17, :566:113] assign _uop_mem_size_T_7 = _uop_mem_size_T_2 ? _uop_mem_size_T_5 : _uop_mem_size_T_6; // @[package.scala:81:59] assign uop_mem_size = _uop_mem_size_T_7; // @[decode.scala:479:17, :566:24] wire _uop_mem_signed_T = uop_inst[14]; // @[decode.scala:479:17, :567:26] assign _uop_mem_signed_T_1 = ~_uop_mem_signed_T; // @[decode.scala:567:{21,26}] assign uop_mem_signed = _uop_mem_signed_T_1; // @[decode.scala:479:17, :567:21] wire _uop_flush_on_commit_T = ~csr_ren; // @[decode.scala:495:50, :507:46, :575:59] wire _uop_flush_on_commit_T_1 = csr_en & _uop_flush_on_commit_T; // @[package.scala:81:59] wire _uop_flush_on_commit_T_2 = _uop_flush_on_commit_T_1 & io_csr_decode_write_flush_0; // @[decode.scala:474:7, :575:{56,68}] assign _uop_flush_on_commit_T_3 = cs_flush_on_commit | _uop_flush_on_commit_T_2; // @[decode.scala:490:16, :575:{45,68}] assign uop_flush_on_commit = _uop_flush_on_commit_T_3; // @[decode.scala:479:17, :575:45] wire _di24_20_T = cs_imm_sel == 3'h2; // @[decode.scala:490:16, :583:32] wire _di24_20_T_1 = cs_imm_sel == 3'h1; // @[decode.scala:490:16, :583:55] wire _di24_20_T_2 = _di24_20_T | _di24_20_T_1; // @[decode.scala:583:{32,41,55}] wire [4:0] di24_20 = _di24_20_T_2 ? _di24_20_T_3 : _di24_20_T_4; // @[decode.scala:583:{20,41,69,81}] wire [6:0] _uop_imm_packed_T = uop_inst[31:25]; // @[decode.scala:479:17, :584:29] wire [7:0] _uop_imm_packed_T_1 = uop_inst[19:12]; // @[decode.scala:479:17, :584:51] wire [11:0] uop_imm_packed_hi = {_uop_imm_packed_T, di24_20}; // @[decode.scala:583:20, :584:{24,29}] assign _uop_imm_packed_T_2 = {uop_imm_packed_hi, _uop_imm_packed_T_1}; // @[decode.scala:584:{24,51}] assign uop_imm_packed = _uop_imm_packed_T_2; // @[decode.scala:479:17, :584:24] assign _uop_is_jal_T = uop_uopc == 7'h25; // @[decode.scala:479:17, :589:35] assign uop_is_jal = _uop_is_jal_T; // @[decode.scala:479:17, :589:35] assign _uop_is_jalr_T = uop_uopc == 7'h26; // @[decode.scala:479:17, :590:35] assign uop_is_jalr = _uop_is_jalr_T; // @[decode.scala:479:17, :590:35] assign io_deq_uop_uopc = io_deq_uop_uopc_0; // @[decode.scala:474:7] assign io_deq_uop_inst = io_deq_uop_inst_0; // @[decode.scala:474:7] assign io_deq_uop_debug_inst = io_deq_uop_debug_inst_0; // @[decode.scala:474:7] assign io_deq_uop_is_rvc = io_deq_uop_is_rvc_0; // @[decode.scala:474:7] assign io_deq_uop_debug_pc = io_deq_uop_debug_pc_0; // @[decode.scala:474:7] assign io_deq_uop_iq_type = io_deq_uop_iq_type_0; // @[decode.scala:474:7] assign io_deq_uop_fu_code = io_deq_uop_fu_code_0; // @[decode.scala:474:7] assign io_deq_uop_is_br = io_deq_uop_is_br_0; // @[decode.scala:474:7] assign io_deq_uop_is_jalr = io_deq_uop_is_jalr_0; // @[decode.scala:474:7] assign io_deq_uop_is_jal = io_deq_uop_is_jal_0; // @[decode.scala:474:7] assign io_deq_uop_is_sfb = io_deq_uop_is_sfb_0; // @[decode.scala:474:7] assign io_deq_uop_ftq_idx = io_deq_uop_ftq_idx_0; // @[decode.scala:474:7] assign io_deq_uop_edge_inst = io_deq_uop_edge_inst_0; // @[decode.scala:474:7] assign io_deq_uop_pc_lob = io_deq_uop_pc_lob_0; // @[decode.scala:474:7] assign io_deq_uop_taken = io_deq_uop_taken_0; // @[decode.scala:474:7] assign io_deq_uop_imm_packed = io_deq_uop_imm_packed_0; // @[decode.scala:474:7] assign io_deq_uop_exception = io_deq_uop_exception_0; // @[decode.scala:474:7] assign io_deq_uop_exc_cause = io_deq_uop_exc_cause_0; // @[decode.scala:474:7] assign io_deq_uop_bypassable = io_deq_uop_bypassable_0; // @[decode.scala:474:7] assign io_deq_uop_mem_cmd = io_deq_uop_mem_cmd_0; // @[decode.scala:474:7] assign io_deq_uop_mem_size = io_deq_uop_mem_size_0; // @[decode.scala:474:7] assign io_deq_uop_mem_signed = io_deq_uop_mem_signed_0; // @[decode.scala:474:7] assign io_deq_uop_is_fence = io_deq_uop_is_fence_0; // @[decode.scala:474:7] assign io_deq_uop_is_fencei = io_deq_uop_is_fencei_0; // @[decode.scala:474:7] assign io_deq_uop_is_amo = io_deq_uop_is_amo_0; // @[decode.scala:474:7] assign io_deq_uop_uses_ldq = io_deq_uop_uses_ldq_0; // @[decode.scala:474:7] assign io_deq_uop_uses_stq = io_deq_uop_uses_stq_0; // @[decode.scala:474:7] assign io_deq_uop_is_sys_pc2epc = io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:474:7] assign io_deq_uop_is_unique = io_deq_uop_is_unique_0; // @[decode.scala:474:7] assign io_deq_uop_flush_on_commit = io_deq_uop_flush_on_commit_0; // @[decode.scala:474:7] assign io_deq_uop_ldst = io_deq_uop_ldst_0; // @[decode.scala:474:7] assign io_deq_uop_lrs1 = io_deq_uop_lrs1_0; // @[decode.scala:474:7] assign io_deq_uop_lrs2 = io_deq_uop_lrs2_0; // @[decode.scala:474:7] assign io_deq_uop_lrs3 = io_deq_uop_lrs3_0; // @[decode.scala:474:7] assign io_deq_uop_ldst_val = io_deq_uop_ldst_val_0; // @[decode.scala:474:7] assign io_deq_uop_dst_rtype = io_deq_uop_dst_rtype_0; // @[decode.scala:474:7] assign io_deq_uop_lrs1_rtype = io_deq_uop_lrs1_rtype_0; // @[decode.scala:474:7] assign io_deq_uop_lrs2_rtype = io_deq_uop_lrs2_rtype_0; // @[decode.scala:474:7] assign io_deq_uop_frs3_en = io_deq_uop_frs3_en_0; // @[decode.scala:474:7] assign io_deq_uop_fp_val = io_deq_uop_fp_val_0; // @[decode.scala:474:7] assign io_deq_uop_fp_single = io_deq_uop_fp_single_0; // @[decode.scala:474:7] assign io_deq_uop_xcpt_pf_if = io_deq_uop_xcpt_pf_if_0; // @[decode.scala:474:7] assign io_deq_uop_xcpt_ae_if = io_deq_uop_xcpt_ae_if_0; // @[decode.scala:474:7] assign io_deq_uop_bp_debug_if = io_deq_uop_bp_debug_if_0; // @[decode.scala:474:7] assign io_deq_uop_bp_xcpt_if = io_deq_uop_bp_xcpt_if_0; // @[decode.scala:474:7] assign io_deq_uop_debug_fsrc = io_deq_uop_debug_fsrc_0; // @[decode.scala:474:7] assign io_csr_decode_inst = io_csr_decode_inst_0; // @[decode.scala:474:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_14( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [5:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [5:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26] reg in_flight_10; // @[Monitor.scala:16:26] reg in_flight_11; // @[Monitor.scala:16:26] reg in_flight_12; // @[Monitor.scala:16:26] reg in_flight_13; // @[Monitor.scala:16:26] reg in_flight_14; // @[Monitor.scala:16:26] reg in_flight_15; // @[Monitor.scala:16:26] reg in_flight_16; // @[Monitor.scala:16:26] reg in_flight_17; // @[Monitor.scala:16:26] reg in_flight_18; // @[Monitor.scala:16:26] reg in_flight_19; // @[Monitor.scala:16:26] reg in_flight_20; // @[Monitor.scala:16:26] reg in_flight_21; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 5'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 5'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 5'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 5'h3; // @[Monitor.scala:21:46] wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 5'h4; // @[Monitor.scala:21:46] wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 5'h5; // @[Monitor.scala:21:46] wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 5'h6; // @[Monitor.scala:21:46] wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 5'h7; // @[Monitor.scala:21:46] wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 5'h8; // @[Monitor.scala:21:46] wire _GEN_8 = io_in_flit_0_bits_virt_channel_id == 5'h9; // @[Monitor.scala:21:46] wire _GEN_9 = io_in_flit_0_bits_virt_channel_id == 5'hA; // @[Monitor.scala:21:46] wire _GEN_10 = io_in_flit_0_bits_virt_channel_id == 5'hB; // @[Monitor.scala:21:46] wire _GEN_11 = io_in_flit_0_bits_virt_channel_id == 5'hE; // @[Monitor.scala:21:46] wire _GEN_12 = io_in_flit_0_bits_virt_channel_id == 5'hF; // @[Monitor.scala:21:46] wire _GEN_13 = io_in_flit_0_bits_virt_channel_id == 5'h12; // @[Monitor.scala:21:46] wire _GEN_14 = io_in_flit_0_bits_virt_channel_id == 5'h13; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [511:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [511:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [511:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [511:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [511:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [511:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire io_in_b_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire [511:0] io_in_b_bits_data = 512'h0; // @[Monitor.scala:36:7] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [5:0] b_first_beats1 = 6'h0; // @[Edges.scala:221:14] wire [5:0] b_first_count = 6'h0; // @[Edges.scala:234:25] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [5:0] _mask_sizeOH_T = {2'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [5:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[5:0]; // @[OneHot.scala:65:{12,27}] wire [5:0] mask_sizeOH = {_mask_sizeOH_T_2[5:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h5; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_sub_size = mask_sizeOH[5]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_sub_bit = io_in_a_bits_address_0[5]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_4_2 = mask_sub_sub_sub_sub_2_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_4 = mask_sub_sub_sub_size & mask_sub_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_4_1 = mask_sub_sub_sub_sub_2_1 | _mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_5_2 = mask_sub_sub_sub_sub_2_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_5 = mask_sub_sub_sub_size & mask_sub_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_5_1 = mask_sub_sub_sub_sub_2_1 | _mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_6_2 = mask_sub_sub_sub_sub_3_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_6 = mask_sub_sub_sub_size & mask_sub_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_6_1 = mask_sub_sub_sub_sub_3_1 | _mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_7_2 = mask_sub_sub_sub_sub_3_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_7 = mask_sub_sub_sub_size & mask_sub_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_7_1 = mask_sub_sub_sub_sub_3_1 | _mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_8_2 = mask_sub_sub_sub_4_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_8 = mask_sub_sub_size & mask_sub_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_8_1 = mask_sub_sub_sub_4_1 | _mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_9_2 = mask_sub_sub_sub_4_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_9 = mask_sub_sub_size & mask_sub_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_9_1 = mask_sub_sub_sub_4_1 | _mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_10_2 = mask_sub_sub_sub_5_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_10 = mask_sub_sub_size & mask_sub_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_10_1 = mask_sub_sub_sub_5_1 | _mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_11_2 = mask_sub_sub_sub_5_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_11 = mask_sub_sub_size & mask_sub_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_11_1 = mask_sub_sub_sub_5_1 | _mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_12_2 = mask_sub_sub_sub_6_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_12 = mask_sub_sub_size & mask_sub_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_12_1 = mask_sub_sub_sub_6_1 | _mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_13_2 = mask_sub_sub_sub_6_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_13 = mask_sub_sub_size & mask_sub_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_13_1 = mask_sub_sub_sub_6_1 | _mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_14_2 = mask_sub_sub_sub_7_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_14 = mask_sub_sub_size & mask_sub_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_14_1 = mask_sub_sub_sub_7_1 | _mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_15_2 = mask_sub_sub_sub_7_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_15 = mask_sub_sub_size & mask_sub_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_15_1 = mask_sub_sub_sub_7_1 | _mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_sub_16_2 = mask_sub_sub_8_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_16 = mask_sub_size & mask_sub_16_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_16_1 = mask_sub_sub_8_1 | _mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_sub_17_2 = mask_sub_sub_8_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_17 = mask_sub_size & mask_sub_17_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_17_1 = mask_sub_sub_8_1 | _mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_sub_18_2 = mask_sub_sub_9_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_18 = mask_sub_size & mask_sub_18_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_18_1 = mask_sub_sub_9_1 | _mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_sub_19_2 = mask_sub_sub_9_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_19 = mask_sub_size & mask_sub_19_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_19_1 = mask_sub_sub_9_1 | _mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_sub_20_2 = mask_sub_sub_10_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_20 = mask_sub_size & mask_sub_20_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_20_1 = mask_sub_sub_10_1 | _mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_sub_21_2 = mask_sub_sub_10_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_21 = mask_sub_size & mask_sub_21_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_21_1 = mask_sub_sub_10_1 | _mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_sub_22_2 = mask_sub_sub_11_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_22 = mask_sub_size & mask_sub_22_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_22_1 = mask_sub_sub_11_1 | _mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_sub_23_2 = mask_sub_sub_11_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_23 = mask_sub_size & mask_sub_23_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_23_1 = mask_sub_sub_11_1 | _mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_sub_24_2 = mask_sub_sub_12_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_24 = mask_sub_size & mask_sub_24_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_24_1 = mask_sub_sub_12_1 | _mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_sub_25_2 = mask_sub_sub_12_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_25 = mask_sub_size & mask_sub_25_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_25_1 = mask_sub_sub_12_1 | _mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_sub_26_2 = mask_sub_sub_13_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_26 = mask_sub_size & mask_sub_26_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_26_1 = mask_sub_sub_13_1 | _mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_sub_27_2 = mask_sub_sub_13_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_27 = mask_sub_size & mask_sub_27_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_27_1 = mask_sub_sub_13_1 | _mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_sub_28_2 = mask_sub_sub_14_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_28 = mask_sub_size & mask_sub_28_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_28_1 = mask_sub_sub_14_1 | _mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_sub_29_2 = mask_sub_sub_14_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_29 = mask_sub_size & mask_sub_29_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_29_1 = mask_sub_sub_14_1 | _mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_sub_30_2 = mask_sub_sub_15_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_30 = mask_sub_size & mask_sub_30_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_30_1 = mask_sub_sub_15_1 | _mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_sub_31_2 = mask_sub_sub_15_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_31 = mask_sub_size & mask_sub_31_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_31_1 = mask_sub_sub_15_1 | _mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire mask_eq_32 = mask_sub_16_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_32 = mask_size & mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_32 = mask_sub_16_1 | _mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire mask_eq_33 = mask_sub_16_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_33 = mask_size & mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_33 = mask_sub_16_1 | _mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire mask_eq_34 = mask_sub_17_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_34 = mask_size & mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_34 = mask_sub_17_1 | _mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire mask_eq_35 = mask_sub_17_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_35 = mask_size & mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_35 = mask_sub_17_1 | _mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire mask_eq_36 = mask_sub_18_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_36 = mask_size & mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_36 = mask_sub_18_1 | _mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire mask_eq_37 = mask_sub_18_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_37 = mask_size & mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_37 = mask_sub_18_1 | _mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire mask_eq_38 = mask_sub_19_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_38 = mask_size & mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_38 = mask_sub_19_1 | _mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire mask_eq_39 = mask_sub_19_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_39 = mask_size & mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_39 = mask_sub_19_1 | _mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire mask_eq_40 = mask_sub_20_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_40 = mask_size & mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_40 = mask_sub_20_1 | _mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire mask_eq_41 = mask_sub_20_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_41 = mask_size & mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_41 = mask_sub_20_1 | _mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire mask_eq_42 = mask_sub_21_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_42 = mask_size & mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_42 = mask_sub_21_1 | _mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire mask_eq_43 = mask_sub_21_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_43 = mask_size & mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_43 = mask_sub_21_1 | _mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire mask_eq_44 = mask_sub_22_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_44 = mask_size & mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_44 = mask_sub_22_1 | _mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire mask_eq_45 = mask_sub_22_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_45 = mask_size & mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_45 = mask_sub_22_1 | _mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire mask_eq_46 = mask_sub_23_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_46 = mask_size & mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_46 = mask_sub_23_1 | _mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire mask_eq_47 = mask_sub_23_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_47 = mask_size & mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_47 = mask_sub_23_1 | _mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire mask_eq_48 = mask_sub_24_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_48 = mask_size & mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_48 = mask_sub_24_1 | _mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire mask_eq_49 = mask_sub_24_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_49 = mask_size & mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_49 = mask_sub_24_1 | _mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire mask_eq_50 = mask_sub_25_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_50 = mask_size & mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_50 = mask_sub_25_1 | _mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire mask_eq_51 = mask_sub_25_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_51 = mask_size & mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_51 = mask_sub_25_1 | _mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire mask_eq_52 = mask_sub_26_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_52 = mask_size & mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_52 = mask_sub_26_1 | _mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire mask_eq_53 = mask_sub_26_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_53 = mask_size & mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_53 = mask_sub_26_1 | _mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire mask_eq_54 = mask_sub_27_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_54 = mask_size & mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_54 = mask_sub_27_1 | _mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire mask_eq_55 = mask_sub_27_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_55 = mask_size & mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_55 = mask_sub_27_1 | _mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire mask_eq_56 = mask_sub_28_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_56 = mask_size & mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_56 = mask_sub_28_1 | _mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire mask_eq_57 = mask_sub_28_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_57 = mask_size & mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_57 = mask_sub_28_1 | _mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire mask_eq_58 = mask_sub_29_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_58 = mask_size & mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_58 = mask_sub_29_1 | _mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire mask_eq_59 = mask_sub_29_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_59 = mask_size & mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_59 = mask_sub_29_1 | _mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire mask_eq_60 = mask_sub_30_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_60 = mask_size & mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_60 = mask_sub_30_1 | _mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire mask_eq_61 = mask_sub_30_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_61 = mask_size & mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_61 = mask_sub_30_1 | _mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire mask_eq_62 = mask_sub_31_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_62 = mask_size & mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_62 = mask_sub_31_1 | _mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire mask_eq_63 = mask_sub_31_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_63 = mask_size & mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_63 = mask_sub_31_1 | _mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo_lo = {mask_lo_lo_lo_lo_hi, mask_lo_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo_hi = {mask_lo_lo_lo_hi_hi, mask_lo_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi_lo = {mask_lo_lo_hi_lo_hi, mask_lo_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi_hi = {mask_lo_lo_hi_hi_hi, mask_lo_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo_lo = {mask_lo_hi_lo_lo_hi, mask_lo_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo_hi = {mask_lo_hi_lo_hi_hi, mask_lo_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi_lo = {mask_lo_hi_hi_lo_hi, mask_lo_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi_hi = {mask_lo_hi_hi_hi_hi, mask_lo_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo_lo = {mask_acc_33, mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_lo_hi = {mask_acc_35, mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo_lo = {mask_hi_lo_lo_lo_hi, mask_hi_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_hi_lo = {mask_acc_37, mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi_hi = {mask_acc_39, mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo_hi = {mask_hi_lo_lo_hi_hi, mask_hi_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo_lo = {mask_acc_41, mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_lo_hi = {mask_acc_43, mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi_lo = {mask_hi_lo_hi_lo_hi, mask_hi_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_hi_lo = {mask_acc_45, mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi_hi = {mask_acc_47, mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi_hi = {mask_hi_lo_hi_hi_hi, mask_hi_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo_lo = {mask_acc_49, mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_lo_hi = {mask_acc_51, mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo_lo = {mask_hi_hi_lo_lo_hi, mask_hi_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_hi_lo = {mask_acc_53, mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi_hi = {mask_acc_55, mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo_hi = {mask_hi_hi_lo_hi_hi, mask_hi_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo_lo = {mask_acc_57, mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_lo_hi = {mask_acc_59, mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi_lo = {mask_hi_hi_hi_lo_hi, mask_hi_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_hi_lo = {mask_acc_61, mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi_hi = {mask_acc_63, mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi_hi = {mask_hi_hi_hi_hi_hi, mask_hi_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [63:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [5:0] _mask_sizeOH_T_3 = {2'h0, io_in_b_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_4 = 8'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [5:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[5:0]; // @[OneHot.scala:65:{12,27}] wire [5:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[5:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h5; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_sub_size_1 = mask_sizeOH_1[5]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_sub_bit_1 = io_in_b_bits_address_0[5]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_sub_1_2_1 = mask_sub_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_sub_0_2_1 = mask_sub_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_sub_sub_size_1 & mask_sub_sub_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_sub_0_1_1 = mask_sub_sub_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_sub_sub_size_1 & mask_sub_sub_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_sub_1_1_1 = mask_sub_sub_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_sub_size_1 = mask_sizeOH_1[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit_1 = io_in_b_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2_1 = mask_sub_sub_sub_sub_sub_0_2_1 & mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T_4 = mask_sub_sub_sub_sub_size_1 & mask_sub_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1_1 = mask_sub_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_1_2_1 = mask_sub_sub_sub_sub_sub_0_2_1 & mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_sub_acc_T_5 = mask_sub_sub_sub_sub_size_1 & mask_sub_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1_1 = mask_sub_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_2_2_1 = mask_sub_sub_sub_sub_sub_1_2_1 & mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T_6 = mask_sub_sub_sub_sub_size_1 & mask_sub_sub_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_2_1_1 = mask_sub_sub_sub_sub_sub_1_1_1 | _mask_sub_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_sub_3_2_1 = mask_sub_sub_sub_sub_sub_1_2_1 & mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_sub_acc_T_7 = mask_sub_sub_sub_sub_size_1 & mask_sub_sub_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_3_1_1 = mask_sub_sub_sub_sub_sub_1_1_1 | _mask_sub_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_size_1 = mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_sub_0_2_1 & mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_8 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1_1 = mask_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_sub_0_2_1 & mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_9 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1_1 = mask_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2_1 = mask_sub_sub_sub_sub_1_2_1 & mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_10 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1_1 = mask_sub_sub_sub_sub_1_1_1 | _mask_sub_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2_1 = mask_sub_sub_sub_sub_1_2_1 & mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_11 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1_1 = mask_sub_sub_sub_sub_1_1_1 | _mask_sub_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_4_2_1 = mask_sub_sub_sub_sub_2_2_1 & mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_12 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_4_1_1 = mask_sub_sub_sub_sub_2_1_1 | _mask_sub_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_5_2_1 = mask_sub_sub_sub_sub_2_2_1 & mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_13 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_5_1_1 = mask_sub_sub_sub_sub_2_1_1 | _mask_sub_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_6_2_1 = mask_sub_sub_sub_sub_3_2_1 & mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_14 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_6_1_1 = mask_sub_sub_sub_sub_3_1_1 | _mask_sub_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_7_2_1 = mask_sub_sub_sub_sub_3_2_1 & mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_15 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_7_1_1 = mask_sub_sub_sub_sub_3_1_1 | _mask_sub_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_16 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_17 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_18 = mask_sub_sub_size_1 & mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1_1 = mask_sub_sub_sub_1_1_1 | _mask_sub_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_19 = mask_sub_sub_size_1 & mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1_1 = mask_sub_sub_sub_1_1_1 | _mask_sub_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2_1 = mask_sub_sub_sub_2_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_20 = mask_sub_sub_size_1 & mask_sub_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1_1 = mask_sub_sub_sub_2_1_1 | _mask_sub_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2_1 = mask_sub_sub_sub_2_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_21 = mask_sub_sub_size_1 & mask_sub_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1_1 = mask_sub_sub_sub_2_1_1 | _mask_sub_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2_1 = mask_sub_sub_sub_3_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_22 = mask_sub_sub_size_1 & mask_sub_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1_1 = mask_sub_sub_sub_3_1_1 | _mask_sub_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2_1 = mask_sub_sub_sub_3_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_23 = mask_sub_sub_size_1 & mask_sub_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1_1 = mask_sub_sub_sub_3_1_1 | _mask_sub_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_8_2_1 = mask_sub_sub_sub_4_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_24 = mask_sub_sub_size_1 & mask_sub_sub_8_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_8_1_1 = mask_sub_sub_sub_4_1_1 | _mask_sub_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_9_2_1 = mask_sub_sub_sub_4_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_25 = mask_sub_sub_size_1 & mask_sub_sub_9_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_9_1_1 = mask_sub_sub_sub_4_1_1 | _mask_sub_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_10_2_1 = mask_sub_sub_sub_5_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_26 = mask_sub_sub_size_1 & mask_sub_sub_10_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_10_1_1 = mask_sub_sub_sub_5_1_1 | _mask_sub_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_11_2_1 = mask_sub_sub_sub_5_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_27 = mask_sub_sub_size_1 & mask_sub_sub_11_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_11_1_1 = mask_sub_sub_sub_5_1_1 | _mask_sub_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_12_2_1 = mask_sub_sub_sub_6_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_28 = mask_sub_sub_size_1 & mask_sub_sub_12_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_12_1_1 = mask_sub_sub_sub_6_1_1 | _mask_sub_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_13_2_1 = mask_sub_sub_sub_6_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_29 = mask_sub_sub_size_1 & mask_sub_sub_13_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_13_1_1 = mask_sub_sub_sub_6_1_1 | _mask_sub_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_14_2_1 = mask_sub_sub_sub_7_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_30 = mask_sub_sub_size_1 & mask_sub_sub_14_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_14_1_1 = mask_sub_sub_sub_7_1_1 | _mask_sub_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_15_2_1 = mask_sub_sub_sub_7_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_31 = mask_sub_sub_size_1 & mask_sub_sub_15_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_15_1_1 = mask_sub_sub_sub_7_1_1 | _mask_sub_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_32 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_33 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_34 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_35 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_36 = mask_sub_size_1 & mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1_1 = mask_sub_sub_2_1_1 | _mask_sub_acc_T_36; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_37 = mask_sub_size_1 & mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1_1 = mask_sub_sub_2_1_1 | _mask_sub_acc_T_37; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_38 = mask_sub_size_1 & mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1_1 = mask_sub_sub_3_1_1 | _mask_sub_acc_T_38; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_39 = mask_sub_size_1 & mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1_1 = mask_sub_sub_3_1_1 | _mask_sub_acc_T_39; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2_1 = mask_sub_sub_4_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_40 = mask_sub_size_1 & mask_sub_8_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1_1 = mask_sub_sub_4_1_1 | _mask_sub_acc_T_40; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2_1 = mask_sub_sub_4_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_41 = mask_sub_size_1 & mask_sub_9_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1_1 = mask_sub_sub_4_1_1 | _mask_sub_acc_T_41; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2_1 = mask_sub_sub_5_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_42 = mask_sub_size_1 & mask_sub_10_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1_1 = mask_sub_sub_5_1_1 | _mask_sub_acc_T_42; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2_1 = mask_sub_sub_5_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_43 = mask_sub_size_1 & mask_sub_11_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1_1 = mask_sub_sub_5_1_1 | _mask_sub_acc_T_43; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2_1 = mask_sub_sub_6_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_44 = mask_sub_size_1 & mask_sub_12_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1_1 = mask_sub_sub_6_1_1 | _mask_sub_acc_T_44; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2_1 = mask_sub_sub_6_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_45 = mask_sub_size_1 & mask_sub_13_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1_1 = mask_sub_sub_6_1_1 | _mask_sub_acc_T_45; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2_1 = mask_sub_sub_7_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_46 = mask_sub_size_1 & mask_sub_14_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1_1 = mask_sub_sub_7_1_1 | _mask_sub_acc_T_46; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2_1 = mask_sub_sub_7_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_47 = mask_sub_size_1 & mask_sub_15_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1_1 = mask_sub_sub_7_1_1 | _mask_sub_acc_T_47; // @[Misc.scala:215:{29,38}] wire mask_sub_16_2_1 = mask_sub_sub_8_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_48 = mask_sub_size_1 & mask_sub_16_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_16_1_1 = mask_sub_sub_8_1_1 | _mask_sub_acc_T_48; // @[Misc.scala:215:{29,38}] wire mask_sub_17_2_1 = mask_sub_sub_8_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_49 = mask_sub_size_1 & mask_sub_17_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_17_1_1 = mask_sub_sub_8_1_1 | _mask_sub_acc_T_49; // @[Misc.scala:215:{29,38}] wire mask_sub_18_2_1 = mask_sub_sub_9_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_50 = mask_sub_size_1 & mask_sub_18_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_18_1_1 = mask_sub_sub_9_1_1 | _mask_sub_acc_T_50; // @[Misc.scala:215:{29,38}] wire mask_sub_19_2_1 = mask_sub_sub_9_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_51 = mask_sub_size_1 & mask_sub_19_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_19_1_1 = mask_sub_sub_9_1_1 | _mask_sub_acc_T_51; // @[Misc.scala:215:{29,38}] wire mask_sub_20_2_1 = mask_sub_sub_10_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_52 = mask_sub_size_1 & mask_sub_20_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_20_1_1 = mask_sub_sub_10_1_1 | _mask_sub_acc_T_52; // @[Misc.scala:215:{29,38}] wire mask_sub_21_2_1 = mask_sub_sub_10_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_53 = mask_sub_size_1 & mask_sub_21_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_21_1_1 = mask_sub_sub_10_1_1 | _mask_sub_acc_T_53; // @[Misc.scala:215:{29,38}] wire mask_sub_22_2_1 = mask_sub_sub_11_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_54 = mask_sub_size_1 & mask_sub_22_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_22_1_1 = mask_sub_sub_11_1_1 | _mask_sub_acc_T_54; // @[Misc.scala:215:{29,38}] wire mask_sub_23_2_1 = mask_sub_sub_11_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_55 = mask_sub_size_1 & mask_sub_23_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_23_1_1 = mask_sub_sub_11_1_1 | _mask_sub_acc_T_55; // @[Misc.scala:215:{29,38}] wire mask_sub_24_2_1 = mask_sub_sub_12_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_56 = mask_sub_size_1 & mask_sub_24_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_24_1_1 = mask_sub_sub_12_1_1 | _mask_sub_acc_T_56; // @[Misc.scala:215:{29,38}] wire mask_sub_25_2_1 = mask_sub_sub_12_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_57 = mask_sub_size_1 & mask_sub_25_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_25_1_1 = mask_sub_sub_12_1_1 | _mask_sub_acc_T_57; // @[Misc.scala:215:{29,38}] wire mask_sub_26_2_1 = mask_sub_sub_13_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_58 = mask_sub_size_1 & mask_sub_26_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_26_1_1 = mask_sub_sub_13_1_1 | _mask_sub_acc_T_58; // @[Misc.scala:215:{29,38}] wire mask_sub_27_2_1 = mask_sub_sub_13_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_59 = mask_sub_size_1 & mask_sub_27_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_27_1_1 = mask_sub_sub_13_1_1 | _mask_sub_acc_T_59; // @[Misc.scala:215:{29,38}] wire mask_sub_28_2_1 = mask_sub_sub_14_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_60 = mask_sub_size_1 & mask_sub_28_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_28_1_1 = mask_sub_sub_14_1_1 | _mask_sub_acc_T_60; // @[Misc.scala:215:{29,38}] wire mask_sub_29_2_1 = mask_sub_sub_14_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_61 = mask_sub_size_1 & mask_sub_29_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_29_1_1 = mask_sub_sub_14_1_1 | _mask_sub_acc_T_61; // @[Misc.scala:215:{29,38}] wire mask_sub_30_2_1 = mask_sub_sub_15_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_62 = mask_sub_size_1 & mask_sub_30_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_30_1_1 = mask_sub_sub_15_1_1 | _mask_sub_acc_T_62; // @[Misc.scala:215:{29,38}] wire mask_sub_31_2_1 = mask_sub_sub_15_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_63 = mask_sub_size_1 & mask_sub_31_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_31_1_1 = mask_sub_sub_15_1_1 | _mask_sub_acc_T_63; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_64 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_64 = mask_size_1 & mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_64 = mask_sub_0_1_1 | _mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire mask_eq_65 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_65 = mask_size_1 & mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_65 = mask_sub_0_1_1 | _mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire mask_eq_66 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_66 = mask_size_1 & mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_66 = mask_sub_1_1_1 | _mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire mask_eq_67 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_67 = mask_size_1 & mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_67 = mask_sub_1_1_1 | _mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire mask_eq_68 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_68 = mask_size_1 & mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_68 = mask_sub_2_1_1 | _mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire mask_eq_69 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_69 = mask_size_1 & mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_69 = mask_sub_2_1_1 | _mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire mask_eq_70 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_70 = mask_size_1 & mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_70 = mask_sub_3_1_1 | _mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire mask_eq_71 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_71 = mask_size_1 & mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_71 = mask_sub_3_1_1 | _mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire mask_eq_72 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_72 = mask_size_1 & mask_eq_72; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_72 = mask_sub_4_1_1 | _mask_acc_T_72; // @[Misc.scala:215:{29,38}] wire mask_eq_73 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_73 = mask_size_1 & mask_eq_73; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_73 = mask_sub_4_1_1 | _mask_acc_T_73; // @[Misc.scala:215:{29,38}] wire mask_eq_74 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_74 = mask_size_1 & mask_eq_74; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_74 = mask_sub_5_1_1 | _mask_acc_T_74; // @[Misc.scala:215:{29,38}] wire mask_eq_75 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_75 = mask_size_1 & mask_eq_75; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_75 = mask_sub_5_1_1 | _mask_acc_T_75; // @[Misc.scala:215:{29,38}] wire mask_eq_76 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_76 = mask_size_1 & mask_eq_76; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_76 = mask_sub_6_1_1 | _mask_acc_T_76; // @[Misc.scala:215:{29,38}] wire mask_eq_77 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_77 = mask_size_1 & mask_eq_77; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_77 = mask_sub_6_1_1 | _mask_acc_T_77; // @[Misc.scala:215:{29,38}] wire mask_eq_78 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_78 = mask_size_1 & mask_eq_78; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_78 = mask_sub_7_1_1 | _mask_acc_T_78; // @[Misc.scala:215:{29,38}] wire mask_eq_79 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_79 = mask_size_1 & mask_eq_79; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_79 = mask_sub_7_1_1 | _mask_acc_T_79; // @[Misc.scala:215:{29,38}] wire mask_eq_80 = mask_sub_8_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_80 = mask_size_1 & mask_eq_80; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_80 = mask_sub_8_1_1 | _mask_acc_T_80; // @[Misc.scala:215:{29,38}] wire mask_eq_81 = mask_sub_8_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_81 = mask_size_1 & mask_eq_81; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_81 = mask_sub_8_1_1 | _mask_acc_T_81; // @[Misc.scala:215:{29,38}] wire mask_eq_82 = mask_sub_9_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_82 = mask_size_1 & mask_eq_82; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_82 = mask_sub_9_1_1 | _mask_acc_T_82; // @[Misc.scala:215:{29,38}] wire mask_eq_83 = mask_sub_9_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_83 = mask_size_1 & mask_eq_83; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_83 = mask_sub_9_1_1 | _mask_acc_T_83; // @[Misc.scala:215:{29,38}] wire mask_eq_84 = mask_sub_10_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_84 = mask_size_1 & mask_eq_84; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_84 = mask_sub_10_1_1 | _mask_acc_T_84; // @[Misc.scala:215:{29,38}] wire mask_eq_85 = mask_sub_10_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_85 = mask_size_1 & mask_eq_85; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_85 = mask_sub_10_1_1 | _mask_acc_T_85; // @[Misc.scala:215:{29,38}] wire mask_eq_86 = mask_sub_11_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_86 = mask_size_1 & mask_eq_86; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_86 = mask_sub_11_1_1 | _mask_acc_T_86; // @[Misc.scala:215:{29,38}] wire mask_eq_87 = mask_sub_11_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_87 = mask_size_1 & mask_eq_87; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_87 = mask_sub_11_1_1 | _mask_acc_T_87; // @[Misc.scala:215:{29,38}] wire mask_eq_88 = mask_sub_12_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_88 = mask_size_1 & mask_eq_88; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_88 = mask_sub_12_1_1 | _mask_acc_T_88; // @[Misc.scala:215:{29,38}] wire mask_eq_89 = mask_sub_12_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_89 = mask_size_1 & mask_eq_89; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_89 = mask_sub_12_1_1 | _mask_acc_T_89; // @[Misc.scala:215:{29,38}] wire mask_eq_90 = mask_sub_13_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_90 = mask_size_1 & mask_eq_90; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_90 = mask_sub_13_1_1 | _mask_acc_T_90; // @[Misc.scala:215:{29,38}] wire mask_eq_91 = mask_sub_13_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_91 = mask_size_1 & mask_eq_91; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_91 = mask_sub_13_1_1 | _mask_acc_T_91; // @[Misc.scala:215:{29,38}] wire mask_eq_92 = mask_sub_14_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_92 = mask_size_1 & mask_eq_92; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_92 = mask_sub_14_1_1 | _mask_acc_T_92; // @[Misc.scala:215:{29,38}] wire mask_eq_93 = mask_sub_14_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_93 = mask_size_1 & mask_eq_93; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_93 = mask_sub_14_1_1 | _mask_acc_T_93; // @[Misc.scala:215:{29,38}] wire mask_eq_94 = mask_sub_15_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_94 = mask_size_1 & mask_eq_94; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_94 = mask_sub_15_1_1 | _mask_acc_T_94; // @[Misc.scala:215:{29,38}] wire mask_eq_95 = mask_sub_15_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_95 = mask_size_1 & mask_eq_95; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_95 = mask_sub_15_1_1 | _mask_acc_T_95; // @[Misc.scala:215:{29,38}] wire mask_eq_96 = mask_sub_16_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_96 = mask_size_1 & mask_eq_96; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_96 = mask_sub_16_1_1 | _mask_acc_T_96; // @[Misc.scala:215:{29,38}] wire mask_eq_97 = mask_sub_16_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_97 = mask_size_1 & mask_eq_97; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_97 = mask_sub_16_1_1 | _mask_acc_T_97; // @[Misc.scala:215:{29,38}] wire mask_eq_98 = mask_sub_17_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_98 = mask_size_1 & mask_eq_98; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_98 = mask_sub_17_1_1 | _mask_acc_T_98; // @[Misc.scala:215:{29,38}] wire mask_eq_99 = mask_sub_17_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_99 = mask_size_1 & mask_eq_99; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_99 = mask_sub_17_1_1 | _mask_acc_T_99; // @[Misc.scala:215:{29,38}] wire mask_eq_100 = mask_sub_18_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_100 = mask_size_1 & mask_eq_100; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_100 = mask_sub_18_1_1 | _mask_acc_T_100; // @[Misc.scala:215:{29,38}] wire mask_eq_101 = mask_sub_18_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_101 = mask_size_1 & mask_eq_101; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_101 = mask_sub_18_1_1 | _mask_acc_T_101; // @[Misc.scala:215:{29,38}] wire mask_eq_102 = mask_sub_19_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_102 = mask_size_1 & mask_eq_102; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_102 = mask_sub_19_1_1 | _mask_acc_T_102; // @[Misc.scala:215:{29,38}] wire mask_eq_103 = mask_sub_19_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_103 = mask_size_1 & mask_eq_103; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_103 = mask_sub_19_1_1 | _mask_acc_T_103; // @[Misc.scala:215:{29,38}] wire mask_eq_104 = mask_sub_20_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_104 = mask_size_1 & mask_eq_104; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_104 = mask_sub_20_1_1 | _mask_acc_T_104; // @[Misc.scala:215:{29,38}] wire mask_eq_105 = mask_sub_20_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_105 = mask_size_1 & mask_eq_105; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_105 = mask_sub_20_1_1 | _mask_acc_T_105; // @[Misc.scala:215:{29,38}] wire mask_eq_106 = mask_sub_21_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_106 = mask_size_1 & mask_eq_106; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_106 = mask_sub_21_1_1 | _mask_acc_T_106; // @[Misc.scala:215:{29,38}] wire mask_eq_107 = mask_sub_21_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_107 = mask_size_1 & mask_eq_107; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_107 = mask_sub_21_1_1 | _mask_acc_T_107; // @[Misc.scala:215:{29,38}] wire mask_eq_108 = mask_sub_22_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_108 = mask_size_1 & mask_eq_108; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_108 = mask_sub_22_1_1 | _mask_acc_T_108; // @[Misc.scala:215:{29,38}] wire mask_eq_109 = mask_sub_22_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_109 = mask_size_1 & mask_eq_109; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_109 = mask_sub_22_1_1 | _mask_acc_T_109; // @[Misc.scala:215:{29,38}] wire mask_eq_110 = mask_sub_23_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_110 = mask_size_1 & mask_eq_110; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_110 = mask_sub_23_1_1 | _mask_acc_T_110; // @[Misc.scala:215:{29,38}] wire mask_eq_111 = mask_sub_23_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_111 = mask_size_1 & mask_eq_111; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_111 = mask_sub_23_1_1 | _mask_acc_T_111; // @[Misc.scala:215:{29,38}] wire mask_eq_112 = mask_sub_24_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_112 = mask_size_1 & mask_eq_112; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_112 = mask_sub_24_1_1 | _mask_acc_T_112; // @[Misc.scala:215:{29,38}] wire mask_eq_113 = mask_sub_24_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_113 = mask_size_1 & mask_eq_113; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_113 = mask_sub_24_1_1 | _mask_acc_T_113; // @[Misc.scala:215:{29,38}] wire mask_eq_114 = mask_sub_25_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_114 = mask_size_1 & mask_eq_114; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_114 = mask_sub_25_1_1 | _mask_acc_T_114; // @[Misc.scala:215:{29,38}] wire mask_eq_115 = mask_sub_25_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_115 = mask_size_1 & mask_eq_115; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_115 = mask_sub_25_1_1 | _mask_acc_T_115; // @[Misc.scala:215:{29,38}] wire mask_eq_116 = mask_sub_26_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_116 = mask_size_1 & mask_eq_116; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_116 = mask_sub_26_1_1 | _mask_acc_T_116; // @[Misc.scala:215:{29,38}] wire mask_eq_117 = mask_sub_26_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_117 = mask_size_1 & mask_eq_117; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_117 = mask_sub_26_1_1 | _mask_acc_T_117; // @[Misc.scala:215:{29,38}] wire mask_eq_118 = mask_sub_27_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_118 = mask_size_1 & mask_eq_118; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_118 = mask_sub_27_1_1 | _mask_acc_T_118; // @[Misc.scala:215:{29,38}] wire mask_eq_119 = mask_sub_27_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_119 = mask_size_1 & mask_eq_119; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_119 = mask_sub_27_1_1 | _mask_acc_T_119; // @[Misc.scala:215:{29,38}] wire mask_eq_120 = mask_sub_28_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_120 = mask_size_1 & mask_eq_120; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_120 = mask_sub_28_1_1 | _mask_acc_T_120; // @[Misc.scala:215:{29,38}] wire mask_eq_121 = mask_sub_28_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_121 = mask_size_1 & mask_eq_121; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_121 = mask_sub_28_1_1 | _mask_acc_T_121; // @[Misc.scala:215:{29,38}] wire mask_eq_122 = mask_sub_29_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_122 = mask_size_1 & mask_eq_122; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_122 = mask_sub_29_1_1 | _mask_acc_T_122; // @[Misc.scala:215:{29,38}] wire mask_eq_123 = mask_sub_29_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_123 = mask_size_1 & mask_eq_123; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_123 = mask_sub_29_1_1 | _mask_acc_T_123; // @[Misc.scala:215:{29,38}] wire mask_eq_124 = mask_sub_30_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_124 = mask_size_1 & mask_eq_124; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_124 = mask_sub_30_1_1 | _mask_acc_T_124; // @[Misc.scala:215:{29,38}] wire mask_eq_125 = mask_sub_30_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_125 = mask_size_1 & mask_eq_125; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_125 = mask_sub_30_1_1 | _mask_acc_T_125; // @[Misc.scala:215:{29,38}] wire mask_eq_126 = mask_sub_31_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_126 = mask_size_1 & mask_eq_126; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_126 = mask_sub_31_1_1 | _mask_acc_T_126; // @[Misc.scala:215:{29,38}] wire mask_eq_127 = mask_sub_31_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_127 = mask_size_1 & mask_eq_127; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_127 = mask_sub_31_1_1 | _mask_acc_T_127; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo_lo_1 = {mask_acc_65, mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_lo_hi_1 = {mask_acc_67, mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo_lo_1 = {mask_lo_lo_lo_lo_hi_1, mask_lo_lo_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_hi_lo_1 = {mask_acc_69, mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi_hi_1 = {mask_acc_71, mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo_hi_1 = {mask_lo_lo_lo_hi_hi_1, mask_lo_lo_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_lo_1 = {mask_lo_lo_lo_hi_1, mask_lo_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo_lo_1 = {mask_acc_73, mask_acc_72}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_lo_hi_1 = {mask_acc_75, mask_acc_74}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi_lo_1 = {mask_lo_lo_hi_lo_hi_1, mask_lo_lo_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_hi_lo_1 = {mask_acc_77, mask_acc_76}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi_hi_1 = {mask_acc_79, mask_acc_78}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi_hi_1 = {mask_lo_lo_hi_hi_hi_1, mask_lo_lo_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo_hi_1 = {mask_lo_lo_hi_hi_1, mask_lo_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_lo_lo_1 = {mask_lo_lo_hi_1, mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo_lo_1 = {mask_acc_81, mask_acc_80}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_lo_hi_1 = {mask_acc_83, mask_acc_82}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo_lo_1 = {mask_lo_hi_lo_lo_hi_1, mask_lo_hi_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_hi_lo_1 = {mask_acc_85, mask_acc_84}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi_hi_1 = {mask_acc_87, mask_acc_86}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo_hi_1 = {mask_lo_hi_lo_hi_hi_1, mask_lo_hi_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_lo_1 = {mask_lo_hi_lo_hi_1, mask_lo_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo_lo_1 = {mask_acc_89, mask_acc_88}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_lo_hi_1 = {mask_acc_91, mask_acc_90}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi_lo_1 = {mask_lo_hi_hi_lo_hi_1, mask_lo_hi_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_hi_lo_1 = {mask_acc_93, mask_acc_92}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi_hi_1 = {mask_acc_95, mask_acc_94}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi_hi_1 = {mask_lo_hi_hi_hi_hi_1, mask_lo_hi_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi_hi_1 = {mask_lo_hi_hi_hi_1, mask_lo_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_lo_hi_1 = {mask_lo_hi_hi_1, mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [31:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo_lo_1 = {mask_acc_97, mask_acc_96}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_lo_hi_1 = {mask_acc_99, mask_acc_98}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo_lo_1 = {mask_hi_lo_lo_lo_hi_1, mask_hi_lo_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_hi_lo_1 = {mask_acc_101, mask_acc_100}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi_hi_1 = {mask_acc_103, mask_acc_102}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo_hi_1 = {mask_hi_lo_lo_hi_hi_1, mask_hi_lo_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_lo_1 = {mask_hi_lo_lo_hi_1, mask_hi_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo_lo_1 = {mask_acc_105, mask_acc_104}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_lo_hi_1 = {mask_acc_107, mask_acc_106}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi_lo_1 = {mask_hi_lo_hi_lo_hi_1, mask_hi_lo_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_hi_lo_1 = {mask_acc_109, mask_acc_108}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi_hi_1 = {mask_acc_111, mask_acc_110}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi_hi_1 = {mask_hi_lo_hi_hi_hi_1, mask_hi_lo_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo_hi_1 = {mask_hi_lo_hi_hi_1, mask_hi_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_hi_lo_1 = {mask_hi_lo_hi_1, mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo_lo_1 = {mask_acc_113, mask_acc_112}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_lo_hi_1 = {mask_acc_115, mask_acc_114}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo_lo_1 = {mask_hi_hi_lo_lo_hi_1, mask_hi_hi_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_hi_lo_1 = {mask_acc_117, mask_acc_116}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi_hi_1 = {mask_acc_119, mask_acc_118}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo_hi_1 = {mask_hi_hi_lo_hi_hi_1, mask_hi_hi_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_lo_1 = {mask_hi_hi_lo_hi_1, mask_hi_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo_lo_1 = {mask_acc_121, mask_acc_120}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_lo_hi_1 = {mask_acc_123, mask_acc_122}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi_lo_1 = {mask_hi_hi_hi_lo_hi_1, mask_hi_hi_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_hi_lo_1 = {mask_acc_125, mask_acc_124}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi_hi_1 = {mask_acc_127, mask_acc_126}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi_hi_1 = {mask_hi_hi_hi_hi_hi_1, mask_hi_hi_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi_hi_1 = {mask_hi_hi_hi_hi_1, mask_hi_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_hi_hi_1 = {mask_hi_hi_hi_1, mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [31:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [63:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2317 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2317; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2317; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [5:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:6]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [5:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 6'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [5:0] a_first_counter; // @[Edges.scala:229:27] wire [6:0] _a_first_counter1_T = {1'h0, a_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] a_first_counter1 = _a_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [5:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2391 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2391; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2391; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2391; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2391; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:6]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [5:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T = {1'h0, d_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1 = _d_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [5:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:6]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [5:0] b_first_counter; // @[Edges.scala:229:27] wire [6:0] _b_first_counter1_T = {1'h0, b_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] b_first_counter1 = _b_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire [5:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] _b_first_counter_T = b_first ? 6'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2388 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2388; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2388; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [5:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:6]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [5:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 6'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [5:0] c_first_counter; // @[Edges.scala:229:27] wire [6:0] _c_first_counter1_T = {1'h0, c_first_counter} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] c_first_counter1 = _c_first_counter1_T[5:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 6'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 6'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [5:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [5:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [5:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:6]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [5:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 6'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [5:0] a_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] a_first_counter1_1 = _a_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_1 = _d_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_19 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_20 = 2'h1 << _GEN_19; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_2243 = _T_2317 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2243 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2243 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2243 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2243 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2243 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46] wire _T_2289 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_2289 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_2391 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [5:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:6]; // @[package.scala:243:46] wire [5:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 6'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [5:0] c_first_counter_1; // @[Edges.scala:229:27] wire [6:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] c_first_counter1_1 = _c_first_counter1_T_1[5:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 6'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [5:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_2; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_2 = _d_first_counter1_T_2[5:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire c_set; // @[Monitor.scala:738:34] wire c_set_wo_ready; // @[Monitor.scala:739:34] wire [3:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [7:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_22 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_23 = 2'h1 << _GEN_22; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 & _c_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_2330 = _T_2388 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2330 & _c_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2330 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2330 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2330 ? _c_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2330 ? _c_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2361 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2361 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_2391 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = {inflight_1[1], inflight_1[0] | c_set}; // @[Monitor.scala:726:35, :738:34, :814:35] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [5:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:6]; // @[package.scala:243:46] wire [5:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 6'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [5:0] d_first_counter_3; // @[Edges.scala:229:27] wire [6:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 7'h1; // @[Edges.scala:229:27, :230:28] wire [5:0] d_first_counter1_3 = _d_first_counter1_T_3[5:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 6'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 6'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 6'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [5:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [5:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [5:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2397 = _T_2391 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_24 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_24; // @[OneHot.scala:58:35] assign d_set = _T_2397 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2406 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign e_clr = _T_2406 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File rename-maptable.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Rename Map Table //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import boom.v3.common._ import boom.v3.util._ import org.chipsalliance.cde.config.Parameters class MapReq(val lregSz: Int) extends Bundle { val lrs1 = UInt(lregSz.W) val lrs2 = UInt(lregSz.W) val lrs3 = UInt(lregSz.W) val ldst = UInt(lregSz.W) } class MapResp(val pregSz: Int) extends Bundle { val prs1 = UInt(pregSz.W) val prs2 = UInt(pregSz.W) val prs3 = UInt(pregSz.W) val stale_pdst = UInt(pregSz.W) } class RemapReq(val lregSz: Int, val pregSz: Int) extends Bundle { val ldst = UInt(lregSz.W) val pdst = UInt(pregSz.W) val valid = Bool() } class RenameMapTable( val plWidth: Int, val numLregs: Int, val numPregs: Int, val bypass: Boolean, val float: Boolean) (implicit p: Parameters) extends BoomModule { val pregSz = log2Ceil(numPregs) val io = IO(new BoomBundle()(p) { // Logical sources -> physical sources. val map_reqs = Input(Vec(plWidth, new MapReq(lregSz))) val map_resps = Output(Vec(plWidth, new MapResp(pregSz))) // Remapping an ldst to a newly allocated pdst? val remap_reqs = Input(Vec(plWidth, new RemapReq(lregSz, pregSz))) // Dispatching branches: need to take snapshots of table state. val ren_br_tags = Input(Vec(plWidth, Valid(UInt(brTagSz.W)))) // Signals for restoring state following misspeculation. val brupdate = Input(new BrUpdateInfo) val rollback = Input(Bool()) }) // The map table register array and its branch snapshots. val map_table = RegInit(VecInit(Seq.fill(numLregs){0.U(pregSz.W)})) val br_snapshots = Reg(Vec(maxBrCount, Vec(numLregs, UInt(pregSz.W)))) // The intermediate states of the map table following modification by each pipeline slot. val remap_table = Wire(Vec(plWidth+1, Vec(numLregs, UInt(pregSz.W)))) // Uops requesting changes to the map table. val remap_pdsts = io.remap_reqs map (_.pdst) val remap_ldsts_oh = io.remap_reqs map (req => UIntToOH(req.ldst) & Fill(numLregs, req.valid.asUInt)) // Figure out the new mappings seen by each pipeline slot. for (i <- 0 until numLregs) { if (i == 0 && !float) { for (j <- 0 until plWidth+1) { remap_table(j)(i) := 0.U } } else { val remapped_row = (remap_ldsts_oh.map(ldst => ldst(i)) zip remap_pdsts) .scanLeft(map_table(i)) {case (pdst, (ldst, new_pdst)) => Mux(ldst, new_pdst, pdst)} for (j <- 0 until plWidth+1) { remap_table(j)(i) := remapped_row(j) } } } // Create snapshots of new mappings. for (i <- 0 until plWidth) { when (io.ren_br_tags(i).valid) { br_snapshots(io.ren_br_tags(i).bits) := remap_table(i+1) } } when (io.brupdate.b2.mispredict) { // Restore the map table to a branch snapshot. map_table := br_snapshots(io.brupdate.b2.uop.br_tag) } .otherwise { // Update mappings. map_table := remap_table(plWidth) } // Read out mappings. for (i <- 0 until plWidth) { io.map_resps(i).prs1 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs1)) ((p,k) => Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs1, io.remap_reqs(k).pdst, p)) io.map_resps(i).prs2 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs2)) ((p,k) => Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs2, io.remap_reqs(k).pdst, p)) io.map_resps(i).prs3 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs3)) ((p,k) => Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs3, io.remap_reqs(k).pdst, p)) io.map_resps(i).stale_pdst := (0 until i).foldLeft(map_table(io.map_reqs(i).ldst)) ((p,k) => Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).ldst, io.remap_reqs(k).pdst, p)) if (!float) io.map_resps(i).prs3 := DontCare } // Don't flag the creation of duplicate 'p0' mappings during rollback. // These cases may occur soon after reset, as all maptable entries are initialized to 'p0'. io.remap_reqs map (req => (req.pdst, req.valid)) foreach {case (p,r) => assert (!r || !map_table.contains(p) || p === 0.U && io.rollback, "[maptable] Trying to write a duplicate mapping.")} }
module RenameMapTable( // @[rename-maptable.scala:43:7] input clock, // @[rename-maptable.scala:43:7] input reset, // @[rename-maptable.scala:43:7] input [5:0] io_map_reqs_0_lrs1, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_0_lrs2, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_0_lrs3, // @[rename-maptable.scala:53:14] input [5:0] io_map_reqs_0_ldst, // @[rename-maptable.scala:53:14] output [5:0] io_map_resps_0_prs1, // @[rename-maptable.scala:53:14] output [5:0] io_map_resps_0_prs2, // @[rename-maptable.scala:53:14] output [5:0] io_map_resps_0_stale_pdst, // @[rename-maptable.scala:53:14] input [5:0] io_remap_reqs_0_ldst, // @[rename-maptable.scala:53:14] input [5:0] io_remap_reqs_0_pdst, // @[rename-maptable.scala:53:14] input io_remap_reqs_0_valid, // @[rename-maptable.scala:53:14] input io_ren_br_tags_0_valid, // @[rename-maptable.scala:53:14] input [2:0] io_ren_br_tags_0_bits, // @[rename-maptable.scala:53:14] input [7:0] io_brupdate_b1_resolve_mask, // @[rename-maptable.scala:53:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[rename-maptable.scala:53:14] input [6:0] io_brupdate_b2_uop_uopc, // @[rename-maptable.scala:53:14] input [31:0] io_brupdate_b2_uop_inst, // @[rename-maptable.scala:53:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_rvc, // @[rename-maptable.scala:53:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[rename-maptable.scala:53:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[rename-maptable.scala:53:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[rename-maptable.scala:53:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_ctrl_is_load, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_ctrl_is_std, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_br, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_jalr, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_jal, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_sfb, // @[rename-maptable.scala:53:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[rename-maptable.scala:53:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_edge_inst, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_taken, // @[rename-maptable.scala:53:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[rename-maptable.scala:53:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[rename-maptable.scala:53:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_pdst, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_prs1, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_prs2, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_prs3, // @[rename-maptable.scala:53:14] input [3:0] io_brupdate_b2_uop_ppred, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_prs1_busy, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_prs2_busy, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_prs3_busy, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_ppred_busy, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_exception, // @[rename-maptable.scala:53:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_bypassable, // @[rename-maptable.scala:53:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_mem_signed, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_fence, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_fencei, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_amo, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_uses_ldq, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_uses_stq, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_is_unique, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_flush_on_commit, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_ldst, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[rename-maptable.scala:53:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_ldst_val, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_frs3_en, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_val, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_fp_single, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_bp_debug_if, // @[rename-maptable.scala:53:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[rename-maptable.scala:53:14] input io_brupdate_b2_valid, // @[rename-maptable.scala:53:14] input io_brupdate_b2_mispredict, // @[rename-maptable.scala:53:14] input io_brupdate_b2_taken, // @[rename-maptable.scala:53:14] input [2:0] io_brupdate_b2_cfi_type, // @[rename-maptable.scala:53:14] input [1:0] io_brupdate_b2_pc_sel, // @[rename-maptable.scala:53:14] input [39:0] io_brupdate_b2_jalr_target, // @[rename-maptable.scala:53:14] input [20:0] io_brupdate_b2_target_offset, // @[rename-maptable.scala:53:14] input io_rollback // @[rename-maptable.scala:53:14] ); wire [5:0] io_map_reqs_0_lrs1_0 = io_map_reqs_0_lrs1; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_0_lrs2_0 = io_map_reqs_0_lrs2; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_0_lrs3_0 = io_map_reqs_0_lrs3; // @[rename-maptable.scala:43:7] wire [5:0] io_map_reqs_0_ldst_0 = io_map_reqs_0_ldst; // @[rename-maptable.scala:43:7] wire [5:0] io_remap_reqs_0_ldst_0 = io_remap_reqs_0_ldst; // @[rename-maptable.scala:43:7] wire [5:0] io_remap_reqs_0_pdst_0 = io_remap_reqs_0_pdst; // @[rename-maptable.scala:43:7] wire io_remap_reqs_0_valid_0 = io_remap_reqs_0_valid; // @[rename-maptable.scala:43:7] wire io_ren_br_tags_0_valid_0 = io_ren_br_tags_0_valid; // @[rename-maptable.scala:43:7] wire [2:0] io_ren_br_tags_0_bits_0 = io_ren_br_tags_0_bits; // @[rename-maptable.scala:43:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rename-maptable.scala:43:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rename-maptable.scala:43:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[rename-maptable.scala:43:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rename-maptable.scala:43:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rename-maptable.scala:43:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[rename-maptable.scala:43:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[rename-maptable.scala:43:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[rename-maptable.scala:43:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rename-maptable.scala:43:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rename-maptable.scala:43:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rename-maptable.scala:43:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rename-maptable.scala:43:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[rename-maptable.scala:43:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rename-maptable.scala:43:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rename-maptable.scala:43:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[rename-maptable.scala:43:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rename-maptable.scala:43:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rename-maptable.scala:43:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rename-maptable.scala:43:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rename-maptable.scala:43:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rename-maptable.scala:43:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rename-maptable.scala:43:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rename-maptable.scala:43:7] wire io_rollback_0 = io_rollback; // @[rename-maptable.scala:43:7] wire [5:0] io_map_resps_0_prs3 = 6'h0; // @[rename-maptable.scala:43:7] wire [5:0] _map_table_WIRE_0 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_1 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_2 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_3 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_4 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_5 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_6 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_7 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_8 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_9 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_10 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_11 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_12 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_13 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_14 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_15 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_16 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_17 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_18 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_19 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_20 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_21 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_22 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_23 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_24 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_25 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_26 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_27 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_28 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_29 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_30 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] _map_table_WIRE_31 = 6'h0; // @[rename-maptable.scala:70:34] wire [5:0] remap_table_0_0 = 6'h0; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_0 = 6'h0; // @[rename-maptable.scala:74:25] wire [5:0] io_map_resps_0_prs1_0; // @[rename-maptable.scala:43:7] wire [5:0] io_map_resps_0_prs2_0; // @[rename-maptable.scala:43:7] wire [5:0] io_map_resps_0_stale_pdst_0; // @[rename-maptable.scala:43:7] reg [5:0] map_table_0; // @[rename-maptable.scala:70:26] reg [5:0] map_table_1; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_1 = map_table_1; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_2; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_2 = map_table_2; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_3; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_3 = map_table_3; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_4; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_4 = map_table_4; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_5; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_5 = map_table_5; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_6; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_6 = map_table_6; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_7; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_7 = map_table_7; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_8; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_8 = map_table_8; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_9; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_9 = map_table_9; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_10; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_10 = map_table_10; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_11; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_11 = map_table_11; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_12; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_12 = map_table_12; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_13; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_13 = map_table_13; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_14; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_14 = map_table_14; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_15; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_15 = map_table_15; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_16; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_16 = map_table_16; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_17; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_17 = map_table_17; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_18; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_18 = map_table_18; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_19; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_19 = map_table_19; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_20; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_20 = map_table_20; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_21; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_21 = map_table_21; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_22; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_22 = map_table_22; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_23; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_23 = map_table_23; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_24; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_24 = map_table_24; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_25; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_25 = map_table_25; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_26; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_26 = map_table_26; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_27; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_27 = map_table_27; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_28; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_28 = map_table_28; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_29; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_29 = map_table_29; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_30; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_30 = map_table_30; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] map_table_31; // @[rename-maptable.scala:70:26] wire [5:0] remap_table_0_31 = map_table_31; // @[rename-maptable.scala:70:26, :74:25] reg [5:0] br_snapshots_0_1; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_2; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_3; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_4; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_5; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_6; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_7; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_8; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_9; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_10; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_11; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_12; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_13; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_14; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_15; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_16; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_17; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_18; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_19; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_20; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_21; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_22; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_23; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_24; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_25; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_26; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_27; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_28; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_29; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_30; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_0_31; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_1; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_2; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_3; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_4; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_5; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_6; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_7; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_8; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_9; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_10; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_11; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_12; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_13; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_14; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_15; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_16; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_17; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_18; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_19; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_20; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_21; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_22; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_23; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_24; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_25; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_26; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_27; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_28; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_29; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_30; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_1_31; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_1; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_2; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_3; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_4; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_5; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_6; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_7; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_8; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_9; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_10; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_11; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_12; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_13; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_14; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_15; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_16; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_17; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_18; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_19; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_20; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_21; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_22; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_23; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_24; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_25; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_26; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_27; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_28; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_29; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_30; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_2_31; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_1; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_2; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_3; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_4; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_5; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_6; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_7; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_8; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_9; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_10; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_11; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_12; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_13; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_14; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_15; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_16; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_17; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_18; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_19; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_20; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_21; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_22; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_23; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_24; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_25; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_26; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_27; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_28; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_29; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_30; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_3_31; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_1; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_2; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_3; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_4; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_5; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_6; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_7; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_8; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_9; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_10; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_11; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_12; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_13; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_14; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_15; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_16; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_17; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_18; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_19; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_20; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_21; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_22; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_23; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_24; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_25; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_26; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_27; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_28; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_29; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_30; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_4_31; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_1; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_2; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_3; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_4; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_5; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_6; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_7; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_8; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_9; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_10; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_11; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_12; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_13; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_14; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_15; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_16; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_17; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_18; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_19; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_20; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_21; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_22; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_23; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_24; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_25; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_26; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_27; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_28; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_29; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_30; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_5_31; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_1; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_2; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_3; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_4; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_5; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_6; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_7; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_8; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_9; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_10; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_11; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_12; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_13; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_14; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_15; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_16; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_17; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_18; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_19; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_20; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_21; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_22; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_23; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_24; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_25; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_26; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_27; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_28; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_29; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_30; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_6_31; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_1; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_2; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_3; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_4; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_5; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_6; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_7; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_8; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_9; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_10; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_11; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_12; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_13; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_14; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_15; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_16; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_17; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_18; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_19; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_20; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_21; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_22; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_23; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_24; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_25; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_26; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_27; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_28; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_29; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_30; // @[rename-maptable.scala:71:25] reg [5:0] br_snapshots_7_31; // @[rename-maptable.scala:71:25] wire [5:0] remapped_row_1; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_1; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_2; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_3; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_4; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_5; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_6; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_7; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_8; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_9; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_10; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_11; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_12; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_13; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_14; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_15; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_16; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_17; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_18; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_19; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_20; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_21; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_22; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_23; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_24; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_25; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_26; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_27; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_28; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_29; // @[rename-maptable.scala:88:70] wire [5:0] remapped_row_1_30; // @[rename-maptable.scala:88:70] wire [5:0] remap_table_1_1; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_2; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_3; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_4; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_5; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_6; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_7; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_8; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_9; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_10; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_11; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_12; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_13; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_14; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_15; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_16; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_17; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_18; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_19; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_20; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_21; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_22; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_23; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_24; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_25; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_26; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_27; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_28; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_29; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_30; // @[rename-maptable.scala:74:25] wire [5:0] remap_table_1_31; // @[rename-maptable.scala:74:25] wire [63:0] _remap_ldsts_oh_T = 64'h1 << io_remap_reqs_0_ldst_0; // @[OneHot.scala:58:35] wire [31:0] _remap_ldsts_oh_T_1 = {32{io_remap_reqs_0_valid_0}}; // @[rename-maptable.scala:43:7, :78:75] wire [63:0] remap_ldsts_oh_0 = {32'h0, _remap_ldsts_oh_T[31:0] & _remap_ldsts_oh_T_1}; // @[OneHot.scala:58:35] wire _remapped_row_T = remap_ldsts_oh_0[1]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1 = _remapped_row_T ? io_remap_reqs_0_pdst_0 : map_table_1; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_1 = remapped_row_1; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_1 = remap_ldsts_oh_0[2]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_1 = _remapped_row_T_1 ? io_remap_reqs_0_pdst_0 : map_table_2; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_2 = remapped_row_1_1; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_2 = remap_ldsts_oh_0[3]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_2 = _remapped_row_T_2 ? io_remap_reqs_0_pdst_0 : map_table_3; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_3 = remapped_row_1_2; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_3 = remap_ldsts_oh_0[4]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_3 = _remapped_row_T_3 ? io_remap_reqs_0_pdst_0 : map_table_4; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_4 = remapped_row_1_3; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_4 = remap_ldsts_oh_0[5]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_4 = _remapped_row_T_4 ? io_remap_reqs_0_pdst_0 : map_table_5; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_5 = remapped_row_1_4; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_5 = remap_ldsts_oh_0[6]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_5 = _remapped_row_T_5 ? io_remap_reqs_0_pdst_0 : map_table_6; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_6 = remapped_row_1_5; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_6 = remap_ldsts_oh_0[7]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_6 = _remapped_row_T_6 ? io_remap_reqs_0_pdst_0 : map_table_7; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_7 = remapped_row_1_6; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_7 = remap_ldsts_oh_0[8]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_7 = _remapped_row_T_7 ? io_remap_reqs_0_pdst_0 : map_table_8; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_8 = remapped_row_1_7; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_8 = remap_ldsts_oh_0[9]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_8 = _remapped_row_T_8 ? io_remap_reqs_0_pdst_0 : map_table_9; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_9 = remapped_row_1_8; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_9 = remap_ldsts_oh_0[10]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_9 = _remapped_row_T_9 ? io_remap_reqs_0_pdst_0 : map_table_10; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_10 = remapped_row_1_9; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_10 = remap_ldsts_oh_0[11]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_10 = _remapped_row_T_10 ? io_remap_reqs_0_pdst_0 : map_table_11; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_11 = remapped_row_1_10; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_11 = remap_ldsts_oh_0[12]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_11 = _remapped_row_T_11 ? io_remap_reqs_0_pdst_0 : map_table_12; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_12 = remapped_row_1_11; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_12 = remap_ldsts_oh_0[13]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_12 = _remapped_row_T_12 ? io_remap_reqs_0_pdst_0 : map_table_13; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_13 = remapped_row_1_12; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_13 = remap_ldsts_oh_0[14]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_13 = _remapped_row_T_13 ? io_remap_reqs_0_pdst_0 : map_table_14; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_14 = remapped_row_1_13; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_14 = remap_ldsts_oh_0[15]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_14 = _remapped_row_T_14 ? io_remap_reqs_0_pdst_0 : map_table_15; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_15 = remapped_row_1_14; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_15 = remap_ldsts_oh_0[16]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_15 = _remapped_row_T_15 ? io_remap_reqs_0_pdst_0 : map_table_16; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_16 = remapped_row_1_15; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_16 = remap_ldsts_oh_0[17]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_16 = _remapped_row_T_16 ? io_remap_reqs_0_pdst_0 : map_table_17; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_17 = remapped_row_1_16; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_17 = remap_ldsts_oh_0[18]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_17 = _remapped_row_T_17 ? io_remap_reqs_0_pdst_0 : map_table_18; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_18 = remapped_row_1_17; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_18 = remap_ldsts_oh_0[19]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_18 = _remapped_row_T_18 ? io_remap_reqs_0_pdst_0 : map_table_19; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_19 = remapped_row_1_18; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_19 = remap_ldsts_oh_0[20]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_19 = _remapped_row_T_19 ? io_remap_reqs_0_pdst_0 : map_table_20; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_20 = remapped_row_1_19; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_20 = remap_ldsts_oh_0[21]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_20 = _remapped_row_T_20 ? io_remap_reqs_0_pdst_0 : map_table_21; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_21 = remapped_row_1_20; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_21 = remap_ldsts_oh_0[22]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_21 = _remapped_row_T_21 ? io_remap_reqs_0_pdst_0 : map_table_22; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_22 = remapped_row_1_21; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_22 = remap_ldsts_oh_0[23]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_22 = _remapped_row_T_22 ? io_remap_reqs_0_pdst_0 : map_table_23; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_23 = remapped_row_1_22; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_23 = remap_ldsts_oh_0[24]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_23 = _remapped_row_T_23 ? io_remap_reqs_0_pdst_0 : map_table_24; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_24 = remapped_row_1_23; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_24 = remap_ldsts_oh_0[25]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_24 = _remapped_row_T_24 ? io_remap_reqs_0_pdst_0 : map_table_25; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_25 = remapped_row_1_24; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_25 = remap_ldsts_oh_0[26]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_25 = _remapped_row_T_25 ? io_remap_reqs_0_pdst_0 : map_table_26; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_26 = remapped_row_1_25; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_26 = remap_ldsts_oh_0[27]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_26 = _remapped_row_T_26 ? io_remap_reqs_0_pdst_0 : map_table_27; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_27 = remapped_row_1_26; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_27 = remap_ldsts_oh_0[28]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_27 = _remapped_row_T_27 ? io_remap_reqs_0_pdst_0 : map_table_28; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_28 = remapped_row_1_27; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_28 = remap_ldsts_oh_0[29]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_28 = _remapped_row_T_28 ? io_remap_reqs_0_pdst_0 : map_table_29; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_29 = remapped_row_1_28; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_29 = remap_ldsts_oh_0[30]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_29 = _remapped_row_T_29 ? io_remap_reqs_0_pdst_0 : map_table_30; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_30 = remapped_row_1_29; // @[rename-maptable.scala:74:25, :88:70] wire _remapped_row_T_30 = remap_ldsts_oh_0[31]; // @[rename-maptable.scala:78:69, :87:58] assign remapped_row_1_30 = _remapped_row_T_30 ? io_remap_reqs_0_pdst_0 : map_table_31; // @[rename-maptable.scala:43:7, :70:26, :87:58, :88:70] assign remap_table_1_31 = remapped_row_1_30; // @[rename-maptable.scala:74:25, :88:70] wire [4:0] _io_map_resps_0_prs1_T = io_map_reqs_0_lrs1_0[4:0]; // @[rename-maptable.scala:43:7] wire [31:0][5:0] _GEN = {{map_table_31}, {map_table_30}, {map_table_29}, {map_table_28}, {map_table_27}, {map_table_26}, {map_table_25}, {map_table_24}, {map_table_23}, {map_table_22}, {map_table_21}, {map_table_20}, {map_table_19}, {map_table_18}, {map_table_17}, {map_table_16}, {map_table_15}, {map_table_14}, {map_table_13}, {map_table_12}, {map_table_11}, {map_table_10}, {map_table_9}, {map_table_8}, {map_table_7}, {map_table_6}, {map_table_5}, {map_table_4}, {map_table_3}, {map_table_2}, {map_table_1}, {map_table_0}}; // @[rename-maptable.scala:70:26, :113:32] assign io_map_resps_0_prs1_0 = _GEN[_io_map_resps_0_prs1_T]; // @[rename-maptable.scala:43:7, :113:32] wire [4:0] _io_map_resps_0_prs2_T = io_map_reqs_0_lrs2_0[4:0]; // @[rename-maptable.scala:43:7] assign io_map_resps_0_prs2_0 = _GEN[_io_map_resps_0_prs2_T]; // @[rename-maptable.scala:43:7, :113:32, :115:32] wire [4:0] _io_map_resps_0_prs3_T = io_map_reqs_0_lrs3_0[4:0]; // @[rename-maptable.scala:43:7] wire [4:0] _io_map_resps_0_stale_pdst_T = io_map_reqs_0_ldst_0[4:0]; // @[rename-maptable.scala:43:7] assign io_map_resps_0_stale_pdst_0 = _GEN[_io_map_resps_0_stale_pdst_T]; // @[rename-maptable.scala:43:7, :113:32, :119:32]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }
module MulAddRecFNToRaw_postMul_e8_s24_49( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48] wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49] wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17] assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body || !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body || !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLEToNoC( // @[TilelinkAdapters.scala:191:7] input clock, // @[TilelinkAdapters.scala:191:7] input reset, // @[TilelinkAdapters.scala:191:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output [5:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] reg [7:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25] reg is_body; // @[TilelinkAdapters.scala:39:24] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:191:7] if (reset) begin // @[TilelinkAdapters.scala:191:7] head_counter <= 8'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :191:7] end else begin // @[TilelinkAdapters.scala:191:7] if (io_flit_ready & _q_io_deq_valid) // @[Decoupled.scala:51:35] head_counter <= head ? 8'h0 : head_counter - 8'h1; // @[Edges.scala:229:27, :230:28, :231:25, :236:21] is_body <= ~_GEN & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File SinkX.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ class SinkXRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val address = UInt(params.inner.bundle.addressBits.W) } class SinkX(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Decoupled(new FullRequest(params)) val x = Flipped(Decoupled(new SinkXRequest(params))) }) val x = Queue(io.x, 1) val (tag, set, offset) = params.parseAddress(x.bits.address) x.ready := io.req.ready io.req.valid := x.valid params.ccover(x.valid && !x.ready, "SINKX_STALL", "Backpressure when accepting a control message") io.req.bits.prio := VecInit(1.U(3.W).asBools) // same prio as A io.req.bits.control:= true.B io.req.bits.opcode := 0.U io.req.bits.param := 0.U io.req.bits.size := params.offsetBits.U // The source does not matter, because a flush command never allocates a way. // However, it must be a legal source, otherwise assertions might spuriously fire. io.req.bits.source := params.inner.client.clients.map(_.sourceId.start).min.U io.req.bits.offset := 0.U io.req.bits.set := set io.req.bits.tag := tag io.req.bits.put := 0.U } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module SinkX( // @[SinkX.scala:28:7] input clock, // @[SinkX.scala:28:7] input reset, // @[SinkX.scala:28:7] input io_req_ready, // @[SinkX.scala:30:14] output io_req_valid, // @[SinkX.scala:30:14] output [12:0] io_req_bits_tag, // @[SinkX.scala:30:14] output [9:0] io_req_bits_set, // @[SinkX.scala:30:14] output io_x_ready, // @[SinkX.scala:30:14] input io_x_valid, // @[SinkX.scala:30:14] input [31:0] io_x_bits_address // @[SinkX.scala:30:14] ); wire [31:0] _x_q_io_deq_bits_address; // @[Decoupled.scala:362:21] wire io_req_ready_0 = io_req_ready; // @[SinkX.scala:28:7] wire io_x_valid_0 = io_x_valid; // @[SinkX.scala:28:7] wire [31:0] io_x_bits_address_0 = io_x_bits_address; // @[SinkX.scala:28:7] wire [5:0] io_req_bits_source = 6'h0; // @[SinkX.scala:28:7] wire [5:0] io_req_bits_offset = 6'h0; // @[SinkX.scala:28:7] wire [5:0] io_req_bits_put = 6'h0; // @[SinkX.scala:28:7] wire [2:0] io_req_bits_size = 3'h6; // @[SinkX.scala:28:7] wire [2:0] io_req_bits_opcode = 3'h0; // @[SinkX.scala:28:7] wire [2:0] io_req_bits_param = 3'h0; // @[SinkX.scala:28:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkX.scala:28:7] wire io_req_bits_prio_2 = 1'h0; // @[SinkX.scala:28:7] wire io_req_bits_prio_0 = 1'h1; // @[SinkX.scala:28:7] wire io_req_bits_control = 1'h1; // @[SinkX.scala:28:7] wire [12:0] tag_1; // @[Parameters.scala:217:9] wire [9:0] set_1; // @[Parameters.scala:217:28] wire [12:0] io_req_bits_tag_0; // @[SinkX.scala:28:7] wire [9:0] io_req_bits_set_0; // @[SinkX.scala:28:7] wire io_req_valid_0; // @[SinkX.scala:28:7] wire io_x_ready_0; // @[SinkX.scala:28:7] wire _offset_T = _x_q_io_deq_bits_address[0]; // @[Decoupled.scala:362:21] wire _offset_T_1 = _x_q_io_deq_bits_address[1]; // @[Decoupled.scala:362:21] wire _offset_T_2 = _x_q_io_deq_bits_address[2]; // @[Decoupled.scala:362:21] wire _offset_T_3 = _x_q_io_deq_bits_address[3]; // @[Decoupled.scala:362:21] wire _offset_T_4 = _x_q_io_deq_bits_address[4]; // @[Decoupled.scala:362:21] wire _offset_T_5 = _x_q_io_deq_bits_address[5]; // @[Decoupled.scala:362:21] wire _offset_T_6 = _x_q_io_deq_bits_address[6]; // @[Decoupled.scala:362:21] wire _offset_T_7 = _x_q_io_deq_bits_address[7]; // @[Decoupled.scala:362:21] wire _offset_T_8 = _x_q_io_deq_bits_address[8]; // @[Decoupled.scala:362:21] wire _offset_T_9 = _x_q_io_deq_bits_address[9]; // @[Decoupled.scala:362:21] wire _offset_T_10 = _x_q_io_deq_bits_address[10]; // @[Decoupled.scala:362:21] wire _offset_T_11 = _x_q_io_deq_bits_address[11]; // @[Decoupled.scala:362:21] wire _offset_T_12 = _x_q_io_deq_bits_address[12]; // @[Decoupled.scala:362:21] wire _offset_T_13 = _x_q_io_deq_bits_address[13]; // @[Decoupled.scala:362:21] wire _offset_T_14 = _x_q_io_deq_bits_address[14]; // @[Decoupled.scala:362:21] wire _offset_T_15 = _x_q_io_deq_bits_address[15]; // @[Decoupled.scala:362:21] wire _offset_T_16 = _x_q_io_deq_bits_address[16]; // @[Decoupled.scala:362:21] wire _offset_T_17 = _x_q_io_deq_bits_address[17]; // @[Decoupled.scala:362:21] wire _offset_T_18 = _x_q_io_deq_bits_address[18]; // @[Decoupled.scala:362:21] wire _offset_T_19 = _x_q_io_deq_bits_address[19]; // @[Decoupled.scala:362:21] wire _offset_T_20 = _x_q_io_deq_bits_address[20]; // @[Decoupled.scala:362:21] wire _offset_T_21 = _x_q_io_deq_bits_address[21]; // @[Decoupled.scala:362:21] wire _offset_T_22 = _x_q_io_deq_bits_address[22]; // @[Decoupled.scala:362:21] wire _offset_T_23 = _x_q_io_deq_bits_address[23]; // @[Decoupled.scala:362:21] wire _offset_T_24 = _x_q_io_deq_bits_address[24]; // @[Decoupled.scala:362:21] wire _offset_T_25 = _x_q_io_deq_bits_address[25]; // @[Decoupled.scala:362:21] wire _offset_T_26 = _x_q_io_deq_bits_address[26]; // @[Decoupled.scala:362:21] wire _offset_T_27 = _x_q_io_deq_bits_address[27]; // @[Decoupled.scala:362:21] wire _offset_T_28 = _x_q_io_deq_bits_address[31]; // @[Decoupled.scala:362:21] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_lo = {_offset_T_22, _offset_T_21}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_24, _offset_T_23}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, offset_hi_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_26, _offset_T_25}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_28, _offset_T_27}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [7:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [14:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [28:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [22:0] set = offset[28:6]; // @[Parameters.scala:214:21, :215:22] wire [12:0] tag = set[22:10]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkX.scala:28:7] assign set_1 = set[9:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkX.scala:28:7] wire [5:0] offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] Queue1_SinkXRequest x_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (io_x_ready_0), .io_enq_valid (io_x_valid_0), // @[SinkX.scala:28:7] .io_enq_bits_address (io_x_bits_address_0), // @[SinkX.scala:28:7] .io_deq_ready (io_req_ready_0), // @[SinkX.scala:28:7] .io_deq_valid (io_req_valid_0), .io_deq_bits_address (_x_q_io_deq_bits_address) ); // @[Decoupled.scala:362:21] assign io_req_valid = io_req_valid_0; // @[SinkX.scala:28:7] assign io_req_bits_tag = io_req_bits_tag_0; // @[SinkX.scala:28:7] assign io_req_bits_set = io_req_bits_set_0; // @[SinkX.scala:28:7] assign io_x_ready = io_x_ready_0; // @[SinkX.scala:28:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FunctionalUnit.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns.{VectorInstruction} abstract class FunctionalUnitIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams { val iss = new Bundle { val valid = Input(Bool()) val op = Input(new ExecuteMicroOp) val ready = Output(Bool()) } val scalar_write = Decoupled(new ScalarWrite) val set_vxsat = Output(Bool()) val set_fflags = Output(Valid(UInt(5.W))) } class PipelinedFunctionalUnitIO(depth: Int)(implicit p: Parameters) extends FunctionalUnitIO { val write = Valid(new VectorWrite(dLen)) val pipe = Input(Vec(depth, Valid(new ExecuteMicroOp))) val pipe0_stall = Output(Bool()) } class IterativeFunctionalUnitIO(implicit p: Parameters) extends FunctionalUnitIO { val write = Decoupled(new VectorWrite(dLen)) val hazard = Output(Valid(new PipeHazard(10))) val acc = Output(Bool()) val tail = Output(Bool()) val busy = Output(Bool()) } trait FunctionalUnitFactory { def insns: Seq[VectorInstruction] def generate(implicit p: Parameters): FunctionalUnit } abstract class FunctionalUnit(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io: FunctionalUnitIO } abstract class PipelinedFunctionalUnit(val depth: Int)(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new PipelinedFunctionalUnitIO(depth)) require (depth > 0) def narrow2_expand(bits: Seq[UInt], eew: UInt, upper: Bool, sext: Bool): Vec[UInt] = { val narrow_eew = (0 until 3).map { eew => Wire(Vec(dLenB >> (eew + 1), UInt((16 << eew).W))) } for (eew <- 0 until 3) { val in_vec = bits.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq for (i <- 0 until dLenB >> (eew + 1)) { val lo = Mux(upper, in_vec(i + (dLenB >> (eew + 1))), in_vec(i)) val hi = Fill(16 << eew, lo((8 << eew)-1) && sext) narrow_eew(eew)(i) := Cat(hi, lo) } } VecInit(narrow_eew.map(_.asUInt))(eew).asTypeOf(Vec(dLenB, UInt(8.W))) } } abstract class IterativeFunctionalUnit(implicit p: Parameters) extends FunctionalUnit()(p) { val io = IO(new IterativeFunctionalUnitIO) val valid = RegInit(false.B) val op = Reg(new ExecuteMicroOp) val last = Wire(Bool()) io.busy := valid io.hazard.bits.latency := DontCare when (io.iss.valid && io.iss.ready) { valid := true.B op := io.iss.op } .elsewhen (last) { valid := false.B } } File BitwisePipe.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns._ case object BitwisePipeFactory extends FunctionalUnitFactory { def insns = Seq( AND.VV, AND.VX, AND.VI, OR.VV, OR.VX, OR.VI, XOR.VV, XOR.VX, XOR.VI, MANDNOT.VV, MAND.VV, MOR.VV, MXOR.VV, MORNOT.VV, MNAND.VV, MNOR.VV, MXNOR.VV, REDAND.VV, REDOR.VV, REDXOR.VV, // Zvbb ANDN.VV, ANDN.VX ) def generate(implicit p: Parameters) = new BitwisePipe()(p) } class BitwisePipe(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) { val supported_insns = BitwisePipeFactory.insns val ctrl = new VectorDecoder(io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, 0.U, 0.U, supported_insns, Seq(BWAnd, BWOr, BWXor, BWInvOut, BWInv1)) io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched val in1 = Mux(ctrl.bool(BWInv1), ~io.pipe(0).bits.rvs1_data, io.pipe(0).bits.rvs1_data) val in2 = io.pipe(0).bits.rvs2_data val op = Mux1H(Seq( (ctrl.bool(BWAnd), (in1 & in2)), (ctrl.bool(BWOr) , (in1 | in2)), (ctrl.bool(BWXor), (in1 ^ in2)) )) val out = Mux(ctrl.bool(BWInvOut), ~op, op) io.pipe0_stall := false.B io.write.valid := io.pipe(0).valid io.write.bits.eg := io.pipe(0).bits.wvd_eg io.write.bits.mask := Mux(io.pipe(0).bits.isOpm && !io.pipe(0).bits.acc, io.pipe(0).bits.full_tail_mask, FillInterleaved(8, io.pipe(0).bits.wmask)) io.write.bits.data := out io.set_vxsat := false.B io.set_fflags.valid := false.B io.set_fflags.bits := DontCare io.scalar_write.valid := false.B io.scalar_write.bits := DontCare }
module BitwisePipe( // @[BitwisePipe.scala:23:7] input [2:0] io_iss_op_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_iss_op_funct6, // @[FunctionalUnit.scala:49:14] output io_iss_ready, // @[FunctionalUnit.scala:49:14] output io_write_valid, // @[FunctionalUnit.scala:49:14] output [6:0] io_write_bits_eg, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_data, // @[FunctionalUnit.scala:49:14] output [63:0] io_write_bits_mask, // @[FunctionalUnit.scala:49:14] input io_pipe_0_valid, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs1_data, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_rvs2_data, // @[FunctionalUnit.scala:49:14] input [7:0] io_pipe_0_bits_wmask, // @[FunctionalUnit.scala:49:14] input [63:0] io_pipe_0_bits_full_tail_mask, // @[FunctionalUnit.scala:49:14] input [6:0] io_pipe_0_bits_wvd_eg, // @[FunctionalUnit.scala:49:14] input [2:0] io_pipe_0_bits_funct3, // @[FunctionalUnit.scala:49:14] input [5:0] io_pipe_0_bits_funct6, // @[FunctionalUnit.scala:49:14] input io_pipe_0_bits_acc // @[FunctionalUnit.scala:49:14] ); wire [3:0] _GEN = ~(io_pipe_0_bits_funct6[3:0]); // @[pla.scala:78:21] wire [2:0] _decode_andMatrixOutputs_T = {_GEN[0], _GEN[1], _GEN[2]}; // @[pla.scala:78:21, :91:29, :98:53] wire [2:0] _decode_andMatrixOutputs_T_7 = {_GEN[0], _GEN[1], io_pipe_0_bits_funct6[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [2:0] _GEN_0 = ~io_iss_op_funct3; // @[pla.scala:78:21] wire [4:0] _GEN_1 = ~(io_iss_op_funct6[5:1]); // @[pla.scala:78:21] wire [63:0] in1 = {64{|{&_decode_andMatrixOutputs_T, &{_GEN[3], ~(io_pipe_0_bits_funct3[1])}, &_decode_andMatrixOutputs_T_7}}} ^ io_pipe_0_bits_rvs1_data; // @[pla.scala:78:21, :91:29, :98:{53,70}, :114:{19,36}] assign io_iss_ready = |{&{io_iss_op_funct6[0], _GEN_1[0], _GEN_1[1], _GEN_1[3], _GEN_1[4], _GEN_0[0], _GEN_0[1]}, &{io_iss_op_funct6[0], _GEN_1[0], _GEN_1[1], _GEN_1[2], _GEN_1[3], _GEN_1[4], _GEN_0[0], _GEN_0[2]}, &{io_iss_op_funct6[1], _GEN_1[1], io_iss_op_funct6[3], _GEN_1[3], _GEN_1[4], _GEN_0[0], _GEN_0[1]}, &{io_iss_op_funct6[1], _GEN_1[1], _GEN_1[2], _GEN_1[3], _GEN_1[4], _GEN_0[0], io_iss_op_funct3[1], _GEN_0[2]}, &{io_iss_op_funct6[3], io_iss_op_funct6[4], _GEN_1[4], _GEN_0[0], io_iss_op_funct3[1], _GEN_0[2]}, &{io_iss_op_funct6[0], _GEN_1[1], io_iss_op_funct6[3], _GEN_1[3], _GEN_1[4], io_iss_op_funct3[0], io_iss_op_funct3[1], _GEN_0[2]}, &{io_iss_op_funct6[1], _GEN_1[1], io_iss_op_funct6[3], _GEN_1[3], _GEN_1[4], io_iss_op_funct3[0], io_iss_op_funct3[1], _GEN_0[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_write_valid = io_pipe_0_valid; // @[BitwisePipe.scala:23:7] assign io_write_bits_eg = io_pipe_0_bits_wvd_eg; // @[BitwisePipe.scala:23:7] assign io_write_bits_data = {64{|{&{io_pipe_0_bits_funct6[0], io_pipe_0_bits_funct6[2]}, &{io_pipe_0_bits_funct6[1], io_pipe_0_bits_funct6[2]}}}} ^ (((|{&_decode_andMatrixOutputs_T, &{io_pipe_0_bits_funct6[0], _GEN[1]}}) ? in1 & io_pipe_0_bits_rvs2_data : 64'h0) | ((|{&{_GEN[0], io_pipe_0_bits_funct6[1]}, &_decode_andMatrixOutputs_T_7}) ? in1 | io_pipe_0_bits_rvs2_data : 64'h0) | ((&{io_pipe_0_bits_funct6[0], io_pipe_0_bits_funct6[1]}) ? in1 ^ io_pipe_0_bits_rvs2_data : 64'h0)); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_write_bits_mask = (io_pipe_0_bits_funct3 == 3'h2 | io_pipe_0_bits_funct3 == 3'h6) & ~io_pipe_0_bits_acc ? io_pipe_0_bits_full_tail_mask : {{8{io_pipe_0_bits_wmask[7]}}, {8{io_pipe_0_bits_wmask[6]}}, {8{io_pipe_0_bits_wmask[5]}}, {8{io_pipe_0_bits_wmask[4]}}, {8{io_pipe_0_bits_wmask[3]}}, {8{io_pipe_0_bits_wmask[2]}}, {8{io_pipe_0_bits_wmask[1]}}, {8{io_pipe_0_bits_wmask[0]}}}; // @[BitwisePipe.scala:23:7, :42:{28,51,54}, :44:20] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }
module PriorityQueueStage_253( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File BTB.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.HasCoreParameters import freechips.rocketchip.util._ case class BHTParams( nEntries: Int = 512, counterLength: Int = 1, historyLength: Int = 8, historyBits: Int = 3) case class BTBParams( nEntries: Int = 28, nMatchBits: Int = 14, nPages: Int = 6, nRAS: Int = 6, bhtParams: Option[BHTParams] = Some(BHTParams()), updatesOutOfOrder: Boolean = false) trait HasBtbParameters extends HasCoreParameters { this: InstanceId => val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0)) val matchBits = btbParams.nMatchBits max log2Ceil(p(CacheBlockBytes) * tileParams.icache.get.nSets) val entries = btbParams.nEntries val updatesOutOfOrder = btbParams.updatesOutOfOrder val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages } abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters { Annotated.params(this, btbParams) } abstract class BtbBundle(implicit val p: Parameters) extends Bundle with HasBtbParameters class RAS(nras: Int) { def push(addr: UInt): Unit = { when (count < nras.U) { count := count + 1.U } val nextPos = Mux((isPow2(nras)).B || pos < (nras-1).U, pos+1.U, 0.U) stack(nextPos) := addr pos := nextPos } def peek: UInt = stack(pos) def pop(): Unit = when (!isEmpty) { count := count - 1.U pos := Mux((isPow2(nras)).B || pos > 0.U, pos-1.U, (nras-1).U) } def clear(): Unit = count := 0.U def isEmpty: Bool = count === 0.U private val count = RegInit(0.U(log2Up(nras+1).W)) private val pos = RegInit(0.U(log2Up(nras).W)) private val stack = Reg(Vec(nras, UInt())) } class BHTResp(implicit p: Parameters) extends BtbBundle()(p) { val history = UInt(btbParams.bhtParams.map(_.historyLength).getOrElse(1).W) val value = UInt(btbParams.bhtParams.map(_.counterLength).getOrElse(1).W) def taken = value(0) def strongly_taken = value === 1.U } // BHT contains table of 2-bit counters and a global history register. // The BHT only predicts and updates when there is a BTB hit. // The global history: // - updated speculatively in fetch (if there's a BTB hit). // - on a mispredict, the history register is reset (again, only if BTB hit). // The counter table: // - each counter corresponds with the address of the fetch packet ("fetch pc"). // - updated when a branch resolves (and BTB was a hit for that branch). // The updating branch must provide its "fetch pc". class BHT(params: BHTParams)(implicit val p: Parameters) extends HasCoreParameters { def index(addr: UInt, history: UInt) = { def hashHistory(hist: UInt) = if (params.historyLength == params.historyBits) hist else { val k = math.sqrt(3)/2 val i = BigDecimal(k * math.pow(2, params.historyLength)).toBigInt (i.U * hist)(params.historyLength-1, params.historyLength-params.historyBits) } def hashAddr(addr: UInt) = { val hi = addr >> log2Ceil(fetchBytes) hi(log2Ceil(params.nEntries)-1, 0) ^ (hi >> log2Ceil(params.nEntries))(1, 0) } hashAddr(addr) ^ (hashHistory(history) << (log2Up(params.nEntries) - params.historyBits)) } def get(addr: UInt): BHTResp = { val res = Wire(new BHTResp) res.value := Mux(resetting, 0.U, table(index(addr, history))) res.history := history res } def updateTable(addr: UInt, d: BHTResp, taken: Bool): Unit = { wen := true.B when (!resetting) { waddr := index(addr, d.history) wdata := (params.counterLength match { case 1 => taken case 2 => Cat(taken ^ d.value(0), d.value === 1.U || d.value(1) && taken) }) } } def resetHistory(d: BHTResp): Unit = { history := d.history } def updateHistory(addr: UInt, d: BHTResp, taken: Bool): Unit = { history := Cat(taken, d.history >> 1) } def advanceHistory(taken: Bool): Unit = { history := Cat(taken, history >> 1) } private val table = Mem(params.nEntries, UInt(params.counterLength.W)) val history = RegInit(0.U(params.historyLength.W)) private val reset_waddr = RegInit(0.U((params.nEntries.log2+1).W)) private val resetting = !reset_waddr(params.nEntries.log2) private val wen = WireInit(resetting) private val waddr = WireInit(reset_waddr) private val wdata = WireInit(0.U) when (resetting) { reset_waddr := reset_waddr + 1.U } when (wen) { table(waddr) := wdata } } object CFIType { def SZ = 2 def apply() = UInt(SZ.W) def branch = 0.U def jump = 1.U def call = 2.U def ret = 3.U } // BTB update occurs during branch resolution (and only on a mispredict). // - "pc" is what future fetch PCs will tag match against. // - "br_pc" is the PC of the branch instruction. class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) { val prediction = new BTBResp val pc = UInt(vaddrBits.W) val target = UInt(vaddrBits.W) val taken = Bool() val isValid = Bool() val br_pc = UInt(vaddrBits.W) val cfiType = CFIType() } // BHT update occurs during branch resolution on all conditional branches. // - "pc" is what future fetch PCs will tag match against. class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) { val prediction = new BHTResp val pc = UInt(vaddrBits.W) val branch = Bool() val taken = Bool() val mispredict = Bool() } class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) { val cfiType = CFIType() val returnAddr = UInt(vaddrBits.W) } // - "bridx" is the low-order PC bits of the predicted branch (after // shifting off the lowest log(inst_bytes) bits off). // - "mask" provides a mask of valid instructions (instructions are // masked off by the predicted taken branch from the BTB). class BTBResp(implicit p: Parameters) extends BtbBundle()(p) { val cfiType = CFIType() val taken = Bool() val mask = Bits(fetchWidth.W) val bridx = Bits(log2Up(fetchWidth).W) val target = UInt(vaddrBits.W) val entry = UInt(log2Up(entries + 1).W) val bht = new BHTResp } class BTBReq(implicit p: Parameters) extends BtbBundle()(p) { val addr = UInt(vaddrBits.W) } // fully-associative branch target buffer // Higher-performance processors may cause BTB updates to occur out-of-order, // which requires an extra CAM port for updates (to ensure no duplicates get // placed in BTB). class BTB(implicit p: Parameters) extends BtbModule { val io = IO(new Bundle { val req = Flipped(Valid(new BTBReq)) val resp = Valid(new BTBResp) val btb_update = Flipped(Valid(new BTBUpdate)) val bht_update = Flipped(Valid(new BHTUpdate)) val bht_advance = Flipped(Valid(new BTBResp)) val ras_update = Flipped(Valid(new RASUpdate)) val ras_head = Valid(UInt(vaddrBits.W)) val flush = Input(Bool()) }) val idxs = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W))) val idxPages = Reg(Vec(entries, UInt(log2Up(nPages).W))) val tgts = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W))) val tgtPages = Reg(Vec(entries, UInt(log2Up(nPages).W))) val pages = Reg(Vec(nPages, UInt((vaddrBits - matchBits).W))) val pageValid = RegInit(0.U(nPages.W)) val pagesMasked = (pageValid.asBools zip pages).map { case (v, p) => Mux(v, p, 0.U) } val isValid = RegInit(0.U(entries.W)) val cfiType = Reg(Vec(entries, CFIType())) val brIdx = Reg(Vec(entries, UInt(log2Up(fetchWidth).W))) private def page(addr: UInt) = addr >> matchBits private def pageMatch(addr: UInt) = { val p = page(addr) pageValid & pages.map(_ === p).asUInt } private def idxMatch(addr: UInt) = { val idx = addr(matchBits-1, log2Up(coreInstBytes)) idxs.map(_ === idx).asUInt & isValid } val r_btb_update = Pipe(io.btb_update) val update_target = io.req.bits.addr val pageHit = pageMatch(io.req.bits.addr) val idxHit = idxMatch(io.req.bits.addr) val updatePageHit = pageMatch(r_btb_update.bits.pc) val (updateHit, updateHitAddr) = if (updatesOutOfOrder) { val updateHits = (pageHit << 1)(Mux1H(idxMatch(r_btb_update.bits.pc), idxPages)) (updateHits.orR, OHToUInt(updateHits)) } else (r_btb_update.bits.prediction.entry < entries.U, r_btb_update.bits.prediction.entry) val useUpdatePageHit = updatePageHit.orR val usePageHit = pageHit.orR val doIdxPageRepl = !useUpdatePageHit val nextPageRepl = RegInit(0.U(log2Ceil(nPages).W)) val idxPageRepl = Cat(pageHit(nPages-2,0), pageHit(nPages-1)) | Mux(usePageHit, 0.U, UIntToOH(nextPageRepl)) val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl) val idxPageUpdate = OHToUInt(idxPageUpdateOH) val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, 0.U) val samePage = page(r_btb_update.bits.pc) === page(update_target) val doTgtPageRepl = !samePage && !usePageHit val tgtPageRepl = Mux(samePage, idxPageUpdateOH, Cat(idxPageUpdateOH(nPages-2,0), idxPageUpdateOH(nPages-1))) val tgtPageUpdate = OHToUInt(pageHit | Mux(usePageHit, 0.U, tgtPageRepl)) val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, 0.U) when (r_btb_update.valid && (doIdxPageRepl || doTgtPageRepl)) { val both = doIdxPageRepl && doTgtPageRepl val next = nextPageRepl + Mux[UInt](both, 2.U, 1.U) nextPageRepl := Mux(next >= nPages.U, next(0), next) } val repl = new PseudoLRU(entries) val waddr = Mux(updateHit, updateHitAddr, repl.way) val r_resp = Pipe(io.resp) when (r_resp.valid && r_resp.bits.taken || r_btb_update.valid) { repl.access(Mux(r_btb_update.valid, waddr, r_resp.bits.entry)) } when (r_btb_update.valid) { val mask = UIntToOH(waddr) idxs(waddr) := r_btb_update.bits.pc(matchBits-1, log2Up(coreInstBytes)) tgts(waddr) := update_target(matchBits-1, log2Up(coreInstBytes)) idxPages(waddr) := idxPageUpdate +& 1.U // the +1 corresponds to the <<1 on io.resp.valid tgtPages(waddr) := tgtPageUpdate cfiType(waddr) := r_btb_update.bits.cfiType isValid := Mux(r_btb_update.bits.isValid, isValid | mask, isValid & ~mask) if (fetchWidth > 1) brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(coreInstBytes) require(nPages % 2 == 0) val idxWritesEven = !idxPageUpdate(0) def writeBank(i: Int, mod: Int, en: UInt, data: UInt) = for (i <- i until nPages by mod) when (en(i)) { pages(i) := data } writeBank(0, 2, Mux(idxWritesEven, idxPageReplEn, tgtPageReplEn), Mux(idxWritesEven, page(r_btb_update.bits.pc), page(update_target))) writeBank(1, 2, Mux(idxWritesEven, tgtPageReplEn, idxPageReplEn), Mux(idxWritesEven, page(update_target), page(r_btb_update.bits.pc))) pageValid := pageValid | tgtPageReplEn | idxPageReplEn } io.resp.valid := (pageHit << 1)(Mux1H(idxHit, idxPages)) io.resp.bits.taken := true.B io.resp.bits.target := Cat(pagesMasked(Mux1H(idxHit, tgtPages)), Mux1H(idxHit, tgts) << log2Up(coreInstBytes)) io.resp.bits.entry := OHToUInt(idxHit) io.resp.bits.bridx := (if (fetchWidth > 1) Mux1H(idxHit, brIdx) else 0.U) io.resp.bits.mask := Cat((1.U << ~Mux(io.resp.bits.taken, ~io.resp.bits.bridx, 0.U))-1.U, 1.U) io.resp.bits.cfiType := Mux1H(idxHit, cfiType) // if multiple entries for same PC land in BTB, zap them when (PopCountAtLeast(idxHit, 2)) { isValid := isValid & ~idxHit } when (io.flush) { isValid := 0.U } if (btbParams.bhtParams.nonEmpty) { val bht = new BHT(Annotated.params(this, btbParams.bhtParams.get)) val isBranch = (idxHit & cfiType.map(_ === CFIType.branch).asUInt).orR val res = bht.get(io.req.bits.addr) when (io.bht_advance.valid) { bht.advanceHistory(io.bht_advance.bits.bht.taken) } when (io.bht_update.valid) { when (io.bht_update.bits.branch) { bht.updateTable(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken) when (io.bht_update.bits.mispredict) { bht.updateHistory(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken) } }.elsewhen (io.bht_update.bits.mispredict) { bht.resetHistory(io.bht_update.bits.prediction) } } when (!res.taken && isBranch) { io.resp.bits.taken := false.B } io.resp.bits.bht := res } if (btbParams.nRAS > 0) { val ras = new RAS(btbParams.nRAS) val doPeek = (idxHit & cfiType.map(_ === CFIType.ret).asUInt).orR io.ras_head.valid := !ras.isEmpty io.ras_head.bits := ras.peek when (!ras.isEmpty && doPeek) { io.resp.bits.target := ras.peek } when (io.ras_update.valid) { when (io.ras_update.bits.cfiType === CFIType.call) { ras.push(io.ras_update.bits.returnAddr) }.elsewhen (io.ras_update.bits.cfiType === CFIType.ret) { ras.pop() } } } }
module BTB_7( // @[BTB.scala:187:7] input clock, // @[BTB.scala:187:7] input reset, // @[BTB.scala:187:7] input io_req_valid, // @[BTB.scala:188:14] input [38:0] io_req_bits_addr, // @[BTB.scala:188:14] output io_resp_valid, // @[BTB.scala:188:14] output [1:0] io_resp_bits_cfiType, // @[BTB.scala:188:14] output io_resp_bits_taken, // @[BTB.scala:188:14] output [1:0] io_resp_bits_mask, // @[BTB.scala:188:14] output io_resp_bits_bridx, // @[BTB.scala:188:14] output [38:0] io_resp_bits_target, // @[BTB.scala:188:14] output [4:0] io_resp_bits_entry, // @[BTB.scala:188:14] output [7:0] io_resp_bits_bht_history, // @[BTB.scala:188:14] output io_resp_bits_bht_value, // @[BTB.scala:188:14] input io_btb_update_valid, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_prediction_cfiType, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_taken, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_prediction_mask, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_bridx, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_prediction_target, // @[BTB.scala:188:14] input [4:0] io_btb_update_bits_prediction_entry, // @[BTB.scala:188:14] input [7:0] io_btb_update_bits_prediction_bht_history, // @[BTB.scala:188:14] input io_btb_update_bits_prediction_bht_value, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_pc, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_target, // @[BTB.scala:188:14] input io_btb_update_bits_isValid, // @[BTB.scala:188:14] input [38:0] io_btb_update_bits_br_pc, // @[BTB.scala:188:14] input [1:0] io_btb_update_bits_cfiType, // @[BTB.scala:188:14] input io_bht_update_valid, // @[BTB.scala:188:14] input [7:0] io_bht_update_bits_prediction_history, // @[BTB.scala:188:14] input io_bht_update_bits_prediction_value, // @[BTB.scala:188:14] input [38:0] io_bht_update_bits_pc, // @[BTB.scala:188:14] input io_bht_update_bits_branch, // @[BTB.scala:188:14] input io_bht_update_bits_taken, // @[BTB.scala:188:14] input io_bht_update_bits_mispredict, // @[BTB.scala:188:14] input io_bht_advance_valid, // @[BTB.scala:188:14] input [1:0] io_bht_advance_bits_cfiType, // @[BTB.scala:188:14] input io_bht_advance_bits_taken, // @[BTB.scala:188:14] input [1:0] io_bht_advance_bits_mask, // @[BTB.scala:188:14] input io_bht_advance_bits_bridx, // @[BTB.scala:188:14] input [38:0] io_bht_advance_bits_target, // @[BTB.scala:188:14] input [4:0] io_bht_advance_bits_entry, // @[BTB.scala:188:14] input [7:0] io_bht_advance_bits_bht_history, // @[BTB.scala:188:14] input io_bht_advance_bits_bht_value, // @[BTB.scala:188:14] input io_ras_update_valid, // @[BTB.scala:188:14] input [1:0] io_ras_update_bits_cfiType, // @[BTB.scala:188:14] input [38:0] io_ras_update_bits_returnAddr, // @[BTB.scala:188:14] output io_ras_head_valid, // @[BTB.scala:188:14] output [38:0] io_ras_head_bits, // @[BTB.scala:188:14] input io_flush // @[BTB.scala:188:14] ); wire _table_ext_R0_data; // @[BTB.scala:116:26] wire io_req_valid_0 = io_req_valid; // @[BTB.scala:187:7] wire [38:0] io_req_bits_addr_0 = io_req_bits_addr; // @[BTB.scala:187:7] wire io_btb_update_valid_0 = io_btb_update_valid; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_prediction_cfiType_0 = io_btb_update_bits_prediction_cfiType; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_taken_0 = io_btb_update_bits_prediction_taken; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_prediction_mask_0 = io_btb_update_bits_prediction_mask; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_bridx_0 = io_btb_update_bits_prediction_bridx; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_prediction_target_0 = io_btb_update_bits_prediction_target; // @[BTB.scala:187:7] wire [4:0] io_btb_update_bits_prediction_entry_0 = io_btb_update_bits_prediction_entry; // @[BTB.scala:187:7] wire [7:0] io_btb_update_bits_prediction_bht_history_0 = io_btb_update_bits_prediction_bht_history; // @[BTB.scala:187:7] wire io_btb_update_bits_prediction_bht_value_0 = io_btb_update_bits_prediction_bht_value; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_pc_0 = io_btb_update_bits_pc; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_target_0 = io_btb_update_bits_target; // @[BTB.scala:187:7] wire io_btb_update_bits_isValid_0 = io_btb_update_bits_isValid; // @[BTB.scala:187:7] wire [38:0] io_btb_update_bits_br_pc_0 = io_btb_update_bits_br_pc; // @[BTB.scala:187:7] wire [1:0] io_btb_update_bits_cfiType_0 = io_btb_update_bits_cfiType; // @[BTB.scala:187:7] wire io_bht_update_valid_0 = io_bht_update_valid; // @[BTB.scala:187:7] wire [7:0] io_bht_update_bits_prediction_history_0 = io_bht_update_bits_prediction_history; // @[BTB.scala:187:7] wire io_bht_update_bits_prediction_value_0 = io_bht_update_bits_prediction_value; // @[BTB.scala:187:7] wire [38:0] io_bht_update_bits_pc_0 = io_bht_update_bits_pc; // @[BTB.scala:187:7] wire io_bht_update_bits_branch_0 = io_bht_update_bits_branch; // @[BTB.scala:187:7] wire io_bht_update_bits_taken_0 = io_bht_update_bits_taken; // @[BTB.scala:187:7] wire io_bht_update_bits_mispredict_0 = io_bht_update_bits_mispredict; // @[BTB.scala:187:7] wire io_bht_advance_valid_0 = io_bht_advance_valid; // @[BTB.scala:187:7] wire [1:0] io_bht_advance_bits_cfiType_0 = io_bht_advance_bits_cfiType; // @[BTB.scala:187:7] wire io_bht_advance_bits_taken_0 = io_bht_advance_bits_taken; // @[BTB.scala:187:7] wire [1:0] io_bht_advance_bits_mask_0 = io_bht_advance_bits_mask; // @[BTB.scala:187:7] wire io_bht_advance_bits_bridx_0 = io_bht_advance_bits_bridx; // @[BTB.scala:187:7] wire [38:0] io_bht_advance_bits_target_0 = io_bht_advance_bits_target; // @[BTB.scala:187:7] wire [4:0] io_bht_advance_bits_entry_0 = io_bht_advance_bits_entry; // @[BTB.scala:187:7] wire [7:0] io_bht_advance_bits_bht_history_0 = io_bht_advance_bits_bht_history; // @[BTB.scala:187:7] wire io_bht_advance_bits_bht_value_0 = io_bht_advance_bits_bht_value; // @[BTB.scala:187:7] wire io_ras_update_valid_0 = io_ras_update_valid; // @[BTB.scala:187:7] wire [1:0] io_ras_update_bits_cfiType_0 = io_ras_update_bits_cfiType; // @[BTB.scala:187:7] wire [38:0] io_ras_update_bits_returnAddr_0 = io_ras_update_bits_returnAddr; // @[BTB.scala:187:7] wire io_flush_0 = io_flush; // @[BTB.scala:187:7] wire io_btb_update_bits_taken = 1'h0; // @[BTB.scala:187:7] wire r_btb_update_bits_taken = 1'h0; // @[Valid.scala:135:21] wire _io_resp_valid_T_85; // @[BTB.scala:287:34] wire [1:0] _io_resp_bits_cfiType_WIRE; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_WIRE; // @[Mux.scala:30:73] wire [4:0] _io_resp_bits_entry_T_12; // @[OneHot.scala:32:10] wire [7:0] res_history; // @[BTB.scala:91:19] wire res_value; // @[BTB.scala:91:19] wire _io_ras_head_valid_T_1; // @[BTB.scala:327:26] wire [7:0] io_resp_bits_bht_history_0; // @[BTB.scala:187:7] wire io_resp_bits_bht_value_0; // @[BTB.scala:187:7] wire [1:0] io_resp_bits_cfiType_0; // @[BTB.scala:187:7] wire io_resp_bits_taken_0; // @[BTB.scala:187:7] wire [1:0] io_resp_bits_mask_0; // @[BTB.scala:187:7] wire io_resp_bits_bridx_0; // @[BTB.scala:187:7] wire [38:0] io_resp_bits_target_0; // @[BTB.scala:187:7] wire [4:0] io_resp_bits_entry_0; // @[BTB.scala:187:7] wire io_resp_valid_0; // @[BTB.scala:187:7] wire io_ras_head_valid_0; // @[BTB.scala:187:7] wire [38:0] io_ras_head_bits_0; // @[BTB.scala:187:7] reg [12:0] idxs_0; // @[BTB.scala:199:17] reg [12:0] idxs_1; // @[BTB.scala:199:17] reg [12:0] idxs_2; // @[BTB.scala:199:17] reg [12:0] idxs_3; // @[BTB.scala:199:17] reg [12:0] idxs_4; // @[BTB.scala:199:17] reg [12:0] idxs_5; // @[BTB.scala:199:17] reg [12:0] idxs_6; // @[BTB.scala:199:17] reg [12:0] idxs_7; // @[BTB.scala:199:17] reg [12:0] idxs_8; // @[BTB.scala:199:17] reg [12:0] idxs_9; // @[BTB.scala:199:17] reg [12:0] idxs_10; // @[BTB.scala:199:17] reg [12:0] idxs_11; // @[BTB.scala:199:17] reg [12:0] idxs_12; // @[BTB.scala:199:17] reg [12:0] idxs_13; // @[BTB.scala:199:17] reg [12:0] idxs_14; // @[BTB.scala:199:17] reg [12:0] idxs_15; // @[BTB.scala:199:17] reg [12:0] idxs_16; // @[BTB.scala:199:17] reg [12:0] idxs_17; // @[BTB.scala:199:17] reg [12:0] idxs_18; // @[BTB.scala:199:17] reg [12:0] idxs_19; // @[BTB.scala:199:17] reg [12:0] idxs_20; // @[BTB.scala:199:17] reg [12:0] idxs_21; // @[BTB.scala:199:17] reg [12:0] idxs_22; // @[BTB.scala:199:17] reg [12:0] idxs_23; // @[BTB.scala:199:17] reg [12:0] idxs_24; // @[BTB.scala:199:17] reg [12:0] idxs_25; // @[BTB.scala:199:17] reg [12:0] idxs_26; // @[BTB.scala:199:17] reg [12:0] idxs_27; // @[BTB.scala:199:17] reg [2:0] idxPages_0; // @[BTB.scala:200:21] reg [2:0] idxPages_1; // @[BTB.scala:200:21] reg [2:0] idxPages_2; // @[BTB.scala:200:21] reg [2:0] idxPages_3; // @[BTB.scala:200:21] reg [2:0] idxPages_4; // @[BTB.scala:200:21] reg [2:0] idxPages_5; // @[BTB.scala:200:21] reg [2:0] idxPages_6; // @[BTB.scala:200:21] reg [2:0] idxPages_7; // @[BTB.scala:200:21] reg [2:0] idxPages_8; // @[BTB.scala:200:21] reg [2:0] idxPages_9; // @[BTB.scala:200:21] reg [2:0] idxPages_10; // @[BTB.scala:200:21] reg [2:0] idxPages_11; // @[BTB.scala:200:21] reg [2:0] idxPages_12; // @[BTB.scala:200:21] reg [2:0] idxPages_13; // @[BTB.scala:200:21] reg [2:0] idxPages_14; // @[BTB.scala:200:21] reg [2:0] idxPages_15; // @[BTB.scala:200:21] reg [2:0] idxPages_16; // @[BTB.scala:200:21] reg [2:0] idxPages_17; // @[BTB.scala:200:21] reg [2:0] idxPages_18; // @[BTB.scala:200:21] reg [2:0] idxPages_19; // @[BTB.scala:200:21] reg [2:0] idxPages_20; // @[BTB.scala:200:21] reg [2:0] idxPages_21; // @[BTB.scala:200:21] reg [2:0] idxPages_22; // @[BTB.scala:200:21] reg [2:0] idxPages_23; // @[BTB.scala:200:21] reg [2:0] idxPages_24; // @[BTB.scala:200:21] reg [2:0] idxPages_25; // @[BTB.scala:200:21] reg [2:0] idxPages_26; // @[BTB.scala:200:21] reg [2:0] idxPages_27; // @[BTB.scala:200:21] reg [12:0] tgts_0; // @[BTB.scala:201:17] reg [12:0] tgts_1; // @[BTB.scala:201:17] reg [12:0] tgts_2; // @[BTB.scala:201:17] reg [12:0] tgts_3; // @[BTB.scala:201:17] reg [12:0] tgts_4; // @[BTB.scala:201:17] reg [12:0] tgts_5; // @[BTB.scala:201:17] reg [12:0] tgts_6; // @[BTB.scala:201:17] reg [12:0] tgts_7; // @[BTB.scala:201:17] reg [12:0] tgts_8; // @[BTB.scala:201:17] reg [12:0] tgts_9; // @[BTB.scala:201:17] reg [12:0] tgts_10; // @[BTB.scala:201:17] reg [12:0] tgts_11; // @[BTB.scala:201:17] reg [12:0] tgts_12; // @[BTB.scala:201:17] reg [12:0] tgts_13; // @[BTB.scala:201:17] reg [12:0] tgts_14; // @[BTB.scala:201:17] reg [12:0] tgts_15; // @[BTB.scala:201:17] reg [12:0] tgts_16; // @[BTB.scala:201:17] reg [12:0] tgts_17; // @[BTB.scala:201:17] reg [12:0] tgts_18; // @[BTB.scala:201:17] reg [12:0] tgts_19; // @[BTB.scala:201:17] reg [12:0] tgts_20; // @[BTB.scala:201:17] reg [12:0] tgts_21; // @[BTB.scala:201:17] reg [12:0] tgts_22; // @[BTB.scala:201:17] reg [12:0] tgts_23; // @[BTB.scala:201:17] reg [12:0] tgts_24; // @[BTB.scala:201:17] reg [12:0] tgts_25; // @[BTB.scala:201:17] reg [12:0] tgts_26; // @[BTB.scala:201:17] reg [12:0] tgts_27; // @[BTB.scala:201:17] reg [2:0] tgtPages_0; // @[BTB.scala:202:21] reg [2:0] tgtPages_1; // @[BTB.scala:202:21] reg [2:0] tgtPages_2; // @[BTB.scala:202:21] reg [2:0] tgtPages_3; // @[BTB.scala:202:21] reg [2:0] tgtPages_4; // @[BTB.scala:202:21] reg [2:0] tgtPages_5; // @[BTB.scala:202:21] reg [2:0] tgtPages_6; // @[BTB.scala:202:21] reg [2:0] tgtPages_7; // @[BTB.scala:202:21] reg [2:0] tgtPages_8; // @[BTB.scala:202:21] reg [2:0] tgtPages_9; // @[BTB.scala:202:21] reg [2:0] tgtPages_10; // @[BTB.scala:202:21] reg [2:0] tgtPages_11; // @[BTB.scala:202:21] reg [2:0] tgtPages_12; // @[BTB.scala:202:21] reg [2:0] tgtPages_13; // @[BTB.scala:202:21] reg [2:0] tgtPages_14; // @[BTB.scala:202:21] reg [2:0] tgtPages_15; // @[BTB.scala:202:21] reg [2:0] tgtPages_16; // @[BTB.scala:202:21] reg [2:0] tgtPages_17; // @[BTB.scala:202:21] reg [2:0] tgtPages_18; // @[BTB.scala:202:21] reg [2:0] tgtPages_19; // @[BTB.scala:202:21] reg [2:0] tgtPages_20; // @[BTB.scala:202:21] reg [2:0] tgtPages_21; // @[BTB.scala:202:21] reg [2:0] tgtPages_22; // @[BTB.scala:202:21] reg [2:0] tgtPages_23; // @[BTB.scala:202:21] reg [2:0] tgtPages_24; // @[BTB.scala:202:21] reg [2:0] tgtPages_25; // @[BTB.scala:202:21] reg [2:0] tgtPages_26; // @[BTB.scala:202:21] reg [2:0] tgtPages_27; // @[BTB.scala:202:21] reg [24:0] pages_0; // @[BTB.scala:203:18] reg [24:0] pages_1; // @[BTB.scala:203:18] reg [24:0] pages_2; // @[BTB.scala:203:18] reg [24:0] pages_3; // @[BTB.scala:203:18] reg [24:0] pages_4; // @[BTB.scala:203:18] reg [24:0] pages_5; // @[BTB.scala:203:18] reg [5:0] pageValid; // @[BTB.scala:204:26] wire _pagesMasked_T = pageValid[0]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_1 = pageValid[1]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_2 = pageValid[2]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_3 = pageValid[3]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_4 = pageValid[4]; // @[BTB.scala:204:26, :205:32] wire _pagesMasked_T_5 = pageValid[5]; // @[BTB.scala:204:26, :205:32] wire [24:0] pagesMasked_0 = _pagesMasked_T ? pages_0 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_1 = _pagesMasked_T_1 ? pages_1 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_2 = _pagesMasked_T_2 ? pages_2 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_3 = _pagesMasked_T_3 ? pages_3 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_4 = _pagesMasked_T_4 ? pages_4 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] wire [24:0] pagesMasked_5 = _pagesMasked_T_5 ? pages_5 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}] reg [27:0] isValid; // @[BTB.scala:207:24] reg [1:0] cfiType_0; // @[BTB.scala:208:20] reg [1:0] cfiType_1; // @[BTB.scala:208:20] reg [1:0] cfiType_2; // @[BTB.scala:208:20] reg [1:0] cfiType_3; // @[BTB.scala:208:20] reg [1:0] cfiType_4; // @[BTB.scala:208:20] reg [1:0] cfiType_5; // @[BTB.scala:208:20] reg [1:0] cfiType_6; // @[BTB.scala:208:20] reg [1:0] cfiType_7; // @[BTB.scala:208:20] reg [1:0] cfiType_8; // @[BTB.scala:208:20] reg [1:0] cfiType_9; // @[BTB.scala:208:20] reg [1:0] cfiType_10; // @[BTB.scala:208:20] reg [1:0] cfiType_11; // @[BTB.scala:208:20] reg [1:0] cfiType_12; // @[BTB.scala:208:20] reg [1:0] cfiType_13; // @[BTB.scala:208:20] reg [1:0] cfiType_14; // @[BTB.scala:208:20] reg [1:0] cfiType_15; // @[BTB.scala:208:20] reg [1:0] cfiType_16; // @[BTB.scala:208:20] reg [1:0] cfiType_17; // @[BTB.scala:208:20] reg [1:0] cfiType_18; // @[BTB.scala:208:20] reg [1:0] cfiType_19; // @[BTB.scala:208:20] reg [1:0] cfiType_20; // @[BTB.scala:208:20] reg [1:0] cfiType_21; // @[BTB.scala:208:20] reg [1:0] cfiType_22; // @[BTB.scala:208:20] reg [1:0] cfiType_23; // @[BTB.scala:208:20] reg [1:0] cfiType_24; // @[BTB.scala:208:20] reg [1:0] cfiType_25; // @[BTB.scala:208:20] reg [1:0] cfiType_26; // @[BTB.scala:208:20] reg [1:0] cfiType_27; // @[BTB.scala:208:20] reg brIdx_0; // @[BTB.scala:209:18] reg brIdx_1; // @[BTB.scala:209:18] reg brIdx_2; // @[BTB.scala:209:18] reg brIdx_3; // @[BTB.scala:209:18] reg brIdx_4; // @[BTB.scala:209:18] reg brIdx_5; // @[BTB.scala:209:18] reg brIdx_6; // @[BTB.scala:209:18] reg brIdx_7; // @[BTB.scala:209:18] reg brIdx_8; // @[BTB.scala:209:18] reg brIdx_9; // @[BTB.scala:209:18] reg brIdx_10; // @[BTB.scala:209:18] reg brIdx_11; // @[BTB.scala:209:18] reg brIdx_12; // @[BTB.scala:209:18] reg brIdx_13; // @[BTB.scala:209:18] reg brIdx_14; // @[BTB.scala:209:18] reg brIdx_15; // @[BTB.scala:209:18] reg brIdx_16; // @[BTB.scala:209:18] reg brIdx_17; // @[BTB.scala:209:18] reg brIdx_18; // @[BTB.scala:209:18] reg brIdx_19; // @[BTB.scala:209:18] reg brIdx_20; // @[BTB.scala:209:18] reg brIdx_21; // @[BTB.scala:209:18] reg brIdx_22; // @[BTB.scala:209:18] reg brIdx_23; // @[BTB.scala:209:18] reg brIdx_24; // @[BTB.scala:209:18] reg brIdx_25; // @[BTB.scala:209:18] reg brIdx_26; // @[BTB.scala:209:18] reg brIdx_27; // @[BTB.scala:209:18] reg r_btb_update_pipe_v; // @[Valid.scala:141:24] wire r_btb_update_valid = r_btb_update_pipe_v; // @[Valid.scala:135:21, :141:24] reg [1:0] r_btb_update_pipe_b_prediction_cfiType; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_prediction_cfiType = r_btb_update_pipe_b_prediction_cfiType; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_taken; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_taken = r_btb_update_pipe_b_prediction_taken; // @[Valid.scala:135:21, :142:26] reg [1:0] r_btb_update_pipe_b_prediction_mask; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_prediction_mask = r_btb_update_pipe_b_prediction_mask; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_bridx; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_bridx = r_btb_update_pipe_b_prediction_bridx; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_prediction_target; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_prediction_target = r_btb_update_pipe_b_prediction_target; // @[Valid.scala:135:21, :142:26] reg [4:0] r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:142:26] wire [4:0] r_btb_update_bits_prediction_entry = r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:135:21, :142:26] reg [7:0] r_btb_update_pipe_b_prediction_bht_history; // @[Valid.scala:142:26] wire [7:0] r_btb_update_bits_prediction_bht_history = r_btb_update_pipe_b_prediction_bht_history; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_prediction_bht_value; // @[Valid.scala:142:26] wire r_btb_update_bits_prediction_bht_value = r_btb_update_pipe_b_prediction_bht_value; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_pc; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_pc = r_btb_update_pipe_b_pc; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_target; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_target = r_btb_update_pipe_b_target; // @[Valid.scala:135:21, :142:26] reg r_btb_update_pipe_b_isValid; // @[Valid.scala:142:26] wire r_btb_update_bits_isValid = r_btb_update_pipe_b_isValid; // @[Valid.scala:135:21, :142:26] reg [38:0] r_btb_update_pipe_b_br_pc; // @[Valid.scala:142:26] wire [38:0] r_btb_update_bits_br_pc = r_btb_update_pipe_b_br_pc; // @[Valid.scala:135:21, :142:26] reg [1:0] r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26] wire [1:0] r_btb_update_bits_cfiType = r_btb_update_pipe_b_cfiType; // @[Valid.scala:135:21, :142:26] wire [24:0] pageHit_p = io_req_bits_addr_0[38:14]; // @[BTB.scala:187:7, :211:39] wire [24:0] _samePage_T_1 = io_req_bits_addr_0[38:14]; // @[BTB.scala:187:7, :211:39] wire _pageHit_T = pages_0 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_1 = pages_1 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_2 = pages_2 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_3 = pages_3 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_4 = pages_4 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _pageHit_T_5 = pages_5 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire [1:0] pageHit_lo_hi = {_pageHit_T_2, _pageHit_T_1}; // @[package.scala:45:27] wire [2:0] pageHit_lo = {pageHit_lo_hi, _pageHit_T}; // @[package.scala:45:27] wire [1:0] pageHit_hi_hi = {_pageHit_T_5, _pageHit_T_4}; // @[package.scala:45:27] wire [2:0] pageHit_hi = {pageHit_hi_hi, _pageHit_T_3}; // @[package.scala:45:27] wire [5:0] _pageHit_T_6 = {pageHit_hi, pageHit_lo}; // @[package.scala:45:27] wire [5:0] pageHit = pageValid & _pageHit_T_6; // @[package.scala:45:27] wire [12:0] idxHit_idx = io_req_bits_addr_0[13:1]; // @[BTB.scala:187:7, :217:19] wire [12:0] _tgts_T = io_req_bits_addr_0[13:1]; // @[BTB.scala:187:7, :217:19, :265:33] wire _idxHit_T = idxs_0 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_1 = idxs_1 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_2 = idxs_2 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_3 = idxs_3 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_4 = idxs_4 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_5 = idxs_5 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_6 = idxs_6 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_7 = idxs_7 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_8 = idxs_8 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_9 = idxs_9 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_10 = idxs_10 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_11 = idxs_11 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_12 = idxs_12 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_13 = idxs_13 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_14 = idxs_14 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_15 = idxs_15 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_16 = idxs_16 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_17 = idxs_17 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_18 = idxs_18 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_19 = idxs_19 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_20 = idxs_20 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_21 = idxs_21 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_22 = idxs_22 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_23 = idxs_23 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_24 = idxs_24 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_25 = idxs_25 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_26 = idxs_26 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire _idxHit_T_27 = idxs_27 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16] wire [1:0] idxHit_lo_lo_lo_hi = {_idxHit_T_2, _idxHit_T_1}; // @[package.scala:45:27] wire [2:0] idxHit_lo_lo_lo = {idxHit_lo_lo_lo_hi, _idxHit_T}; // @[package.scala:45:27] wire [1:0] idxHit_lo_lo_hi_lo = {_idxHit_T_4, _idxHit_T_3}; // @[package.scala:45:27] wire [1:0] idxHit_lo_lo_hi_hi = {_idxHit_T_6, _idxHit_T_5}; // @[package.scala:45:27] wire [3:0] idxHit_lo_lo_hi = {idxHit_lo_lo_hi_hi, idxHit_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_lo_lo = {idxHit_lo_lo_hi, idxHit_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_lo_hi = {_idxHit_T_9, _idxHit_T_8}; // @[package.scala:45:27] wire [2:0] idxHit_lo_hi_lo = {idxHit_lo_hi_lo_hi, _idxHit_T_7}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_hi_lo = {_idxHit_T_11, _idxHit_T_10}; // @[package.scala:45:27] wire [1:0] idxHit_lo_hi_hi_hi = {_idxHit_T_13, _idxHit_T_12}; // @[package.scala:45:27] wire [3:0] idxHit_lo_hi_hi = {idxHit_lo_hi_hi_hi, idxHit_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_lo_hi = {idxHit_lo_hi_hi, idxHit_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] idxHit_lo = {idxHit_lo_hi, idxHit_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_lo_hi = {_idxHit_T_16, _idxHit_T_15}; // @[package.scala:45:27] wire [2:0] idxHit_hi_lo_lo = {idxHit_hi_lo_lo_hi, _idxHit_T_14}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_hi_lo = {_idxHit_T_18, _idxHit_T_17}; // @[package.scala:45:27] wire [1:0] idxHit_hi_lo_hi_hi = {_idxHit_T_20, _idxHit_T_19}; // @[package.scala:45:27] wire [3:0] idxHit_hi_lo_hi = {idxHit_hi_lo_hi_hi, idxHit_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_hi_lo = {idxHit_hi_lo_hi, idxHit_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_lo_hi = {_idxHit_T_23, _idxHit_T_22}; // @[package.scala:45:27] wire [2:0] idxHit_hi_hi_lo = {idxHit_hi_hi_lo_hi, _idxHit_T_21}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_hi_lo = {_idxHit_T_25, _idxHit_T_24}; // @[package.scala:45:27] wire [1:0] idxHit_hi_hi_hi_hi = {_idxHit_T_27, _idxHit_T_26}; // @[package.scala:45:27] wire [3:0] idxHit_hi_hi_hi = {idxHit_hi_hi_hi_hi, idxHit_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] idxHit_hi_hi = {idxHit_hi_hi_hi, idxHit_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] idxHit_hi = {idxHit_hi_hi, idxHit_hi_lo}; // @[package.scala:45:27] wire [27:0] _idxHit_T_28 = {idxHit_hi, idxHit_lo}; // @[package.scala:45:27] wire [27:0] idxHit = _idxHit_T_28 & isValid; // @[package.scala:45:27] wire [24:0] updatePageHit_p = r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21] wire [24:0] _samePage_T = r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21] wire _updatePageHit_T = pages_0 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_1 = pages_1 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_2 = pages_2 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_3 = pages_3 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_4 = pages_4 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire _updatePageHit_T_5 = pages_5 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29] wire [1:0] updatePageHit_lo_hi = {_updatePageHit_T_2, _updatePageHit_T_1}; // @[package.scala:45:27] wire [2:0] updatePageHit_lo = {updatePageHit_lo_hi, _updatePageHit_T}; // @[package.scala:45:27] wire [1:0] updatePageHit_hi_hi = {_updatePageHit_T_5, _updatePageHit_T_4}; // @[package.scala:45:27] wire [2:0] updatePageHit_hi = {updatePageHit_hi_hi, _updatePageHit_T_3}; // @[package.scala:45:27] wire [5:0] _updatePageHit_T_6 = {updatePageHit_hi, updatePageHit_lo}; // @[package.scala:45:27] wire [5:0] updatePageHit = pageValid & _updatePageHit_T_6; // @[package.scala:45:27] wire updateHit = r_btb_update_bits_prediction_entry[4:2] != 3'h7; // @[Valid.scala:135:21] wire useUpdatePageHit = |updatePageHit; // @[BTB.scala:214:15, :234:40] wire usePageHit = |pageHit; // @[BTB.scala:214:15, :235:28] wire doIdxPageRepl = ~useUpdatePageHit; // @[BTB.scala:234:40, :236:23] reg [2:0] nextPageRepl; // @[BTB.scala:237:29] wire [4:0] _idxPageRepl_T = pageHit[4:0]; // @[BTB.scala:214:15, :238:32] wire _idxPageRepl_T_1 = pageHit[5]; // @[BTB.scala:214:15, :238:53] wire [5:0] _idxPageRepl_T_2 = {_idxPageRepl_T, _idxPageRepl_T_1}; // @[BTB.scala:238:{24,32,53}] wire [7:0] _idxPageRepl_T_3 = 8'h1 << nextPageRepl; // @[OneHot.scala:58:35] wire [7:0] _idxPageRepl_T_4 = usePageHit ? 8'h0 : _idxPageRepl_T_3; // @[OneHot.scala:58:35] wire [7:0] idxPageRepl = {2'h0, _idxPageRepl_T_2} | _idxPageRepl_T_4; // @[BTB.scala:238:{24,65,70}] wire [7:0] idxPageUpdateOH = useUpdatePageHit ? {2'h0, updatePageHit} : idxPageRepl; // @[BTB.scala:214:15, :234:40, :238:65, :239:28] wire [3:0] idxPageUpdate_hi = idxPageUpdateOH[7:4]; // @[OneHot.scala:30:18] wire [3:0] idxPageUpdate_lo = idxPageUpdateOH[3:0]; // @[OneHot.scala:31:18] wire _idxPageUpdate_T = |idxPageUpdate_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _idxPageUpdate_T_1 = idxPageUpdate_hi | idxPageUpdate_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] idxPageUpdate_hi_1 = _idxPageUpdate_T_1[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] idxPageUpdate_lo_1 = _idxPageUpdate_T_1[1:0]; // @[OneHot.scala:31:18, :32:28] wire _idxPageUpdate_T_2 = |idxPageUpdate_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _idxPageUpdate_T_3 = idxPageUpdate_hi_1 | idxPageUpdate_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _idxPageUpdate_T_4 = _idxPageUpdate_T_3[1]; // @[OneHot.scala:32:28] wire [1:0] _idxPageUpdate_T_5 = {_idxPageUpdate_T_2, _idxPageUpdate_T_4}; // @[OneHot.scala:32:{10,14}] wire [2:0] idxPageUpdate = {_idxPageUpdate_T, _idxPageUpdate_T_5}; // @[OneHot.scala:32:{10,14}] wire [7:0] idxPageReplEn = doIdxPageRepl ? idxPageRepl : 8'h0; // @[BTB.scala:236:23, :238:65, :241:26] wire samePage = _samePage_T == _samePage_T_1; // @[BTB.scala:211:39, :243:45] wire _doTgtPageRepl_T = ~samePage; // @[BTB.scala:243:45, :244:23] wire _doTgtPageRepl_T_1 = ~usePageHit; // @[BTB.scala:235:28, :244:36] wire doTgtPageRepl = _doTgtPageRepl_T & _doTgtPageRepl_T_1; // @[BTB.scala:244:{23,33,36}] wire [4:0] _tgtPageRepl_T = idxPageUpdateOH[4:0]; // @[BTB.scala:239:28, :245:71] wire _tgtPageRepl_T_1 = idxPageUpdateOH[5]; // @[BTB.scala:239:28, :245:100] wire [5:0] _tgtPageRepl_T_2 = {_tgtPageRepl_T, _tgtPageRepl_T_1}; // @[BTB.scala:245:{55,71,100}] wire [7:0] tgtPageRepl = samePage ? idxPageUpdateOH : {2'h0, _tgtPageRepl_T_2}; // @[BTB.scala:239:28, :243:45, :245:{24,55}] wire [7:0] _tgtPageUpdate_T = usePageHit ? 8'h0 : tgtPageRepl; // @[BTB.scala:235:28, :245:24, :246:45] wire [7:0] _tgtPageUpdate_T_1 = {2'h0, pageHit} | _tgtPageUpdate_T; // @[BTB.scala:214:15, :246:{40,45}] wire [3:0] tgtPageUpdate_hi = _tgtPageUpdate_T_1[7:4]; // @[OneHot.scala:30:18] wire [3:0] tgtPageUpdate_lo = _tgtPageUpdate_T_1[3:0]; // @[OneHot.scala:31:18] wire _tgtPageUpdate_T_2 = |tgtPageUpdate_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _tgtPageUpdate_T_3 = tgtPageUpdate_hi | tgtPageUpdate_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] tgtPageUpdate_hi_1 = _tgtPageUpdate_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] tgtPageUpdate_lo_1 = _tgtPageUpdate_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _tgtPageUpdate_T_4 = |tgtPageUpdate_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _tgtPageUpdate_T_5 = tgtPageUpdate_hi_1 | tgtPageUpdate_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _tgtPageUpdate_T_6 = _tgtPageUpdate_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _tgtPageUpdate_T_7 = {_tgtPageUpdate_T_4, _tgtPageUpdate_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] tgtPageUpdate = {_tgtPageUpdate_T_2, _tgtPageUpdate_T_7}; // @[OneHot.scala:32:{10,14}] wire [7:0] tgtPageReplEn = doTgtPageRepl ? tgtPageRepl : 8'h0; // @[BTB.scala:244:33, :245:24, :247:26] wire both = doIdxPageRepl & doTgtPageRepl; // @[BTB.scala:236:23, :244:33, :250:30] wire [1:0] _next_T = both ? 2'h2 : 2'h1; // @[BTB.scala:250:30, :251:40, :292:33] wire [3:0] _next_T_1 = {1'h0, nextPageRepl} + {2'h0, _next_T}; // @[BTB.scala:237:29, :251:{29,40}] wire [2:0] next = _next_T_1[2:0]; // @[BTB.scala:251:29] wire _nextPageRepl_T = next > 3'h5; // @[BTB.scala:251:29, :252:30] wire _nextPageRepl_T_1 = next[0]; // @[BTB.scala:251:29, :252:47] wire [2:0] _nextPageRepl_T_2 = _nextPageRepl_T ? {2'h0, _nextPageRepl_T_1} : next; // @[BTB.scala:251:29, :252:{24,30,47}] reg [26:0] state_reg; // @[Replacement.scala:168:70] wire waddr_left_subtree_older = state_reg[26]; // @[Replacement.scala:168:70, :243:38] wire [10:0] waddr_left_subtree_state = state_reg[25:15]; // @[package.scala:163:13] wire [10:0] state_reg_left_subtree_state = state_reg[25:15]; // @[package.scala:163:13] wire [14:0] waddr_right_subtree_state = state_reg[14:0]; // @[Replacement.scala:168:70, :245:38] wire [14:0] state_reg_right_subtree_state = state_reg[14:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire waddr_left_subtree_older_1 = waddr_left_subtree_state[10]; // @[package.scala:163:13] wire [2:0] waddr_left_subtree_state_1 = waddr_left_subtree_state[9:7]; // @[package.scala:163:13] wire [6:0] waddr_right_subtree_state_1 = waddr_left_subtree_state[6:0]; // @[package.scala:163:13] wire waddr_left_subtree_older_2 = waddr_left_subtree_state_1[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_2 = waddr_left_subtree_state_1[1]; // @[package.scala:163:13] wire _waddr_T = waddr_left_subtree_state_2; // @[package.scala:163:13] wire waddr_right_subtree_state_2 = waddr_left_subtree_state_1[0]; // @[package.scala:163:13] wire _waddr_T_1 = waddr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_2 = waddr_left_subtree_older_2 ? _waddr_T : _waddr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_3 = {waddr_left_subtree_older_2, _waddr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_3 = waddr_right_subtree_state_1[6]; // @[Replacement.scala:243:38, :245:38] wire [2:0] waddr_left_subtree_state_3 = waddr_right_subtree_state_1[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_3 = waddr_right_subtree_state_1[2:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_4 = waddr_left_subtree_state_3[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_4 = waddr_left_subtree_state_3[1]; // @[package.scala:163:13] wire _waddr_T_4 = waddr_left_subtree_state_4; // @[package.scala:163:13] wire waddr_right_subtree_state_4 = waddr_left_subtree_state_3[0]; // @[package.scala:163:13] wire _waddr_T_5 = waddr_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_6 = waddr_left_subtree_older_4 ? _waddr_T_4 : _waddr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_7 = {waddr_left_subtree_older_4, _waddr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_5 = waddr_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_5 = waddr_right_subtree_state_3[1]; // @[package.scala:163:13] wire _waddr_T_8 = waddr_left_subtree_state_5; // @[package.scala:163:13] wire waddr_right_subtree_state_5 = waddr_right_subtree_state_3[0]; // @[Replacement.scala:245:38] wire _waddr_T_9 = waddr_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_10 = waddr_left_subtree_older_5 ? _waddr_T_8 : _waddr_T_9; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_11 = {waddr_left_subtree_older_5, _waddr_T_10}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_12 = waddr_left_subtree_older_3 ? _waddr_T_7 : _waddr_T_11; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_13 = {waddr_left_subtree_older_3, _waddr_T_12}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_14 = waddr_left_subtree_older_1 ? {1'h0, _waddr_T_3} : _waddr_T_13; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_15 = {waddr_left_subtree_older_1, _waddr_T_14}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_6 = waddr_right_subtree_state[14]; // @[Replacement.scala:243:38, :245:38] wire [6:0] waddr_left_subtree_state_6 = waddr_right_subtree_state[13:7]; // @[package.scala:163:13] wire [6:0] waddr_right_subtree_state_6 = waddr_right_subtree_state[6:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_7 = waddr_left_subtree_state_6[6]; // @[package.scala:163:13] wire [2:0] waddr_left_subtree_state_7 = waddr_left_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_7 = waddr_left_subtree_state_6[2:0]; // @[package.scala:163:13] wire waddr_left_subtree_older_8 = waddr_left_subtree_state_7[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_8 = waddr_left_subtree_state_7[1]; // @[package.scala:163:13] wire _waddr_T_16 = waddr_left_subtree_state_8; // @[package.scala:163:13] wire waddr_right_subtree_state_8 = waddr_left_subtree_state_7[0]; // @[package.scala:163:13] wire _waddr_T_17 = waddr_right_subtree_state_8; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_18 = waddr_left_subtree_older_8 ? _waddr_T_16 : _waddr_T_17; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_19 = {waddr_left_subtree_older_8, _waddr_T_18}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_9 = waddr_right_subtree_state_7[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_9 = waddr_right_subtree_state_7[1]; // @[package.scala:163:13] wire _waddr_T_20 = waddr_left_subtree_state_9; // @[package.scala:163:13] wire waddr_right_subtree_state_9 = waddr_right_subtree_state_7[0]; // @[Replacement.scala:245:38] wire _waddr_T_21 = waddr_right_subtree_state_9; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_22 = waddr_left_subtree_older_9 ? _waddr_T_20 : _waddr_T_21; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_23 = {waddr_left_subtree_older_9, _waddr_T_22}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_24 = waddr_left_subtree_older_7 ? _waddr_T_19 : _waddr_T_23; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_25 = {waddr_left_subtree_older_7, _waddr_T_24}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_10 = waddr_right_subtree_state_6[6]; // @[Replacement.scala:243:38, :245:38] wire [2:0] waddr_left_subtree_state_10 = waddr_right_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] waddr_right_subtree_state_10 = waddr_right_subtree_state_6[2:0]; // @[Replacement.scala:245:38] wire waddr_left_subtree_older_11 = waddr_left_subtree_state_10[2]; // @[package.scala:163:13] wire waddr_left_subtree_state_11 = waddr_left_subtree_state_10[1]; // @[package.scala:163:13] wire _waddr_T_26 = waddr_left_subtree_state_11; // @[package.scala:163:13] wire waddr_right_subtree_state_11 = waddr_left_subtree_state_10[0]; // @[package.scala:163:13] wire _waddr_T_27 = waddr_right_subtree_state_11; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_28 = waddr_left_subtree_older_11 ? _waddr_T_26 : _waddr_T_27; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_29 = {waddr_left_subtree_older_11, _waddr_T_28}; // @[Replacement.scala:243:38, :249:12, :250:16] wire waddr_left_subtree_older_12 = waddr_right_subtree_state_10[2]; // @[Replacement.scala:243:38, :245:38] wire waddr_left_subtree_state_12 = waddr_right_subtree_state_10[1]; // @[package.scala:163:13] wire _waddr_T_30 = waddr_left_subtree_state_12; // @[package.scala:163:13] wire waddr_right_subtree_state_12 = waddr_right_subtree_state_10[0]; // @[Replacement.scala:245:38] wire _waddr_T_31 = waddr_right_subtree_state_12; // @[Replacement.scala:245:38, :262:12] wire _waddr_T_32 = waddr_left_subtree_older_12 ? _waddr_T_30 : _waddr_T_31; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _waddr_T_33 = {waddr_left_subtree_older_12, _waddr_T_32}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _waddr_T_34 = waddr_left_subtree_older_10 ? _waddr_T_29 : _waddr_T_33; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_35 = {waddr_left_subtree_older_10, _waddr_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _waddr_T_36 = waddr_left_subtree_older_6 ? _waddr_T_25 : _waddr_T_35; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_37 = {waddr_left_subtree_older_6, _waddr_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [3:0] _waddr_T_38 = waddr_left_subtree_older ? _waddr_T_15 : _waddr_T_37; // @[Replacement.scala:243:38, :249:12, :250:16] wire [4:0] _waddr_T_39 = {waddr_left_subtree_older, _waddr_T_38}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [4:0] waddr = updateHit ? r_btb_update_bits_prediction_entry : _waddr_T_39; // @[Valid.scala:135:21] reg r_resp_pipe_v; // @[Valid.scala:141:24] wire r_resp_valid = r_resp_pipe_v; // @[Valid.scala:135:21, :141:24] reg [1:0] r_resp_pipe_b_cfiType; // @[Valid.scala:142:26] wire [1:0] r_resp_bits_cfiType = r_resp_pipe_b_cfiType; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_taken; // @[Valid.scala:142:26] wire r_resp_bits_taken = r_resp_pipe_b_taken; // @[Valid.scala:135:21, :142:26] reg [1:0] r_resp_pipe_b_mask; // @[Valid.scala:142:26] wire [1:0] r_resp_bits_mask = r_resp_pipe_b_mask; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_bridx; // @[Valid.scala:142:26] wire r_resp_bits_bridx = r_resp_pipe_b_bridx; // @[Valid.scala:135:21, :142:26] reg [38:0] r_resp_pipe_b_target; // @[Valid.scala:142:26] wire [38:0] r_resp_bits_target = r_resp_pipe_b_target; // @[Valid.scala:135:21, :142:26] reg [4:0] r_resp_pipe_b_entry; // @[Valid.scala:142:26] wire [4:0] r_resp_bits_entry = r_resp_pipe_b_entry; // @[Valid.scala:135:21, :142:26] reg [7:0] r_resp_pipe_b_bht_history; // @[Valid.scala:142:26] wire [7:0] r_resp_bits_bht_history = r_resp_pipe_b_bht_history; // @[Valid.scala:135:21, :142:26] reg r_resp_pipe_b_bht_value; // @[Valid.scala:142:26] wire r_resp_bits_bht_value = r_resp_pipe_b_bht_value; // @[Valid.scala:135:21, :142:26] wire [4:0] state_reg_touch_way_sized = r_btb_update_valid ? waddr : r_resp_bits_entry; // @[Valid.scala:135:21] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[4]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0] _state_reg_T = state_reg_touch_way_sized[3:0]; // @[package.scala:163:13] wire [3:0] _state_reg_T_39 = state_reg_touch_way_sized[3:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[3]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_1 = state_reg_left_subtree_state[9:7]; // @[package.scala:163:13] wire [6:0] state_reg_right_subtree_state_1 = state_reg_left_subtree_state[6:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_1 = _state_reg_T[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_2 = _state_reg_T_1[1]; // @[package.scala:163:13] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_2 = state_reg_left_subtree_state_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = state_reg_left_subtree_state_1[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1[0]; // @[package.scala:163:13] wire _state_reg_T_6 = _state_reg_T_1[0]; // @[package.scala:163:13] wire _state_reg_T_3 = _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_4 = ~_state_reg_T_3; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_5 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_4; // @[package.scala:163:13] wire _state_reg_T_7 = _state_reg_T_6; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_8 = ~_state_reg_T_7; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_9 = state_reg_set_left_older_2 ? _state_reg_T_8 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_2, _state_reg_T_5}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_10 = {state_reg_hi, _state_reg_T_9}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_11 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_10; // @[package.scala:163:13] wire [2:0] _state_reg_T_12 = _state_reg_T[2:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_3 = _state_reg_T_12[2]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_3 = state_reg_right_subtree_state_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_3 = state_reg_right_subtree_state_1[2:0]; // @[Replacement.scala:198:38] wire [1:0] _state_reg_T_13 = _state_reg_T_12[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_24 = _state_reg_T_12[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_4 = _state_reg_T_13[1]; // @[package.scala:163:13] wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13] wire _state_reg_T_14 = _state_reg_T_13[0]; // @[package.scala:163:13] wire _state_reg_T_18 = _state_reg_T_13[0]; // @[package.scala:163:13] wire _state_reg_T_15 = _state_reg_T_14; // @[package.scala:163:13] wire _state_reg_T_16 = ~_state_reg_T_15; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_17 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_16; // @[package.scala:163:13] wire _state_reg_T_19 = _state_reg_T_18; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_20 = ~_state_reg_T_19; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_21 = state_reg_set_left_older_4 ? _state_reg_T_20 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_4, _state_reg_T_17}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_22 = {state_reg_hi_1, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_23 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_22; // @[package.scala:163:13] wire _state_reg_set_left_older_T_5 = _state_reg_T_24[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38] wire _state_reg_T_25 = _state_reg_T_24[0]; // @[package.scala:163:13] wire _state_reg_T_29 = _state_reg_T_24[0]; // @[package.scala:163:13] wire _state_reg_T_26 = _state_reg_T_25; // @[package.scala:163:13] wire _state_reg_T_27 = ~_state_reg_T_26; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_28 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_27; // @[package.scala:163:13] wire _state_reg_T_30 = _state_reg_T_29; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_31 = ~_state_reg_T_30; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_32 = state_reg_set_left_older_5 ? _state_reg_T_31 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_2 = {state_reg_set_left_older_5, _state_reg_T_28}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_33 = {state_reg_hi_2, _state_reg_T_32}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_34 = state_reg_set_left_older_3 ? _state_reg_T_33 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_3 = {state_reg_set_left_older_3, _state_reg_T_23}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_35 = {state_reg_hi_3, _state_reg_T_34}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_36 = state_reg_set_left_older_1 ? _state_reg_T_35 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_4 = {state_reg_set_left_older_1, _state_reg_T_11}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [10:0] _state_reg_T_37 = {state_reg_hi_4, _state_reg_T_36}; // @[Replacement.scala:202:12, :206:16] wire [10:0] _state_reg_T_38 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_37; // @[package.scala:163:13] wire _state_reg_set_left_older_T_6 = _state_reg_T_39[3]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}] wire [6:0] state_reg_left_subtree_state_6 = state_reg_right_subtree_state[13:7]; // @[package.scala:163:13] wire [6:0] state_reg_right_subtree_state_6 = state_reg_right_subtree_state[6:0]; // @[Replacement.scala:198:38] wire [2:0] _state_reg_T_40 = _state_reg_T_39[2:0]; // @[package.scala:163:13] wire [2:0] _state_reg_T_65 = _state_reg_T_39[2:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_7 = _state_reg_T_40[2]; // @[package.scala:163:13] wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[2:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_41 = _state_reg_T_40[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_52 = _state_reg_T_40[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_8 = _state_reg_T_41[1]; // @[package.scala:163:13] wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_8 = state_reg_left_subtree_state_7[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_8 = state_reg_left_subtree_state_7[0]; // @[package.scala:163:13] wire _state_reg_T_42 = _state_reg_T_41[0]; // @[package.scala:163:13] wire _state_reg_T_46 = _state_reg_T_41[0]; // @[package.scala:163:13] wire _state_reg_T_43 = _state_reg_T_42; // @[package.scala:163:13] wire _state_reg_T_44 = ~_state_reg_T_43; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_45 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_44; // @[package.scala:163:13] wire _state_reg_T_47 = _state_reg_T_46; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_48 = ~_state_reg_T_47; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_49 = state_reg_set_left_older_8 ? _state_reg_T_48 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_5 = {state_reg_set_left_older_8, _state_reg_T_45}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_50 = {state_reg_hi_5, _state_reg_T_49}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_51 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_50; // @[package.scala:163:13] wire _state_reg_set_left_older_T_9 = _state_reg_T_52[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_9 = ~_state_reg_set_left_older_T_9; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_9 = state_reg_right_subtree_state_7[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_9 = state_reg_right_subtree_state_7[0]; // @[Replacement.scala:198:38] wire _state_reg_T_53 = _state_reg_T_52[0]; // @[package.scala:163:13] wire _state_reg_T_57 = _state_reg_T_52[0]; // @[package.scala:163:13] wire _state_reg_T_54 = _state_reg_T_53; // @[package.scala:163:13] wire _state_reg_T_55 = ~_state_reg_T_54; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_56 = state_reg_set_left_older_9 ? state_reg_left_subtree_state_9 : _state_reg_T_55; // @[package.scala:163:13] wire _state_reg_T_58 = _state_reg_T_57; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_59 = ~_state_reg_T_58; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_60 = state_reg_set_left_older_9 ? _state_reg_T_59 : state_reg_right_subtree_state_9; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_9, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_61 = {state_reg_hi_6, _state_reg_T_60}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_62 = state_reg_set_left_older_7 ? _state_reg_T_61 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_7 = {state_reg_set_left_older_7, _state_reg_T_51}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_63 = {state_reg_hi_7, _state_reg_T_62}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_64 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_63; // @[package.scala:163:13] wire _state_reg_set_left_older_T_10 = _state_reg_T_65[2]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_10 = ~_state_reg_set_left_older_T_10; // @[Replacement.scala:196:{33,43}] wire [2:0] state_reg_left_subtree_state_10 = state_reg_right_subtree_state_6[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_right_subtree_state_10 = state_reg_right_subtree_state_6[2:0]; // @[Replacement.scala:198:38] wire [1:0] _state_reg_T_66 = _state_reg_T_65[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_77 = _state_reg_T_65[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_11 = _state_reg_T_66[1]; // @[package.scala:163:13] wire state_reg_set_left_older_11 = ~_state_reg_set_left_older_T_11; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_11 = state_reg_left_subtree_state_10[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_11 = state_reg_left_subtree_state_10[0]; // @[package.scala:163:13] wire _state_reg_T_67 = _state_reg_T_66[0]; // @[package.scala:163:13] wire _state_reg_T_71 = _state_reg_T_66[0]; // @[package.scala:163:13] wire _state_reg_T_68 = _state_reg_T_67; // @[package.scala:163:13] wire _state_reg_T_69 = ~_state_reg_T_68; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_70 = state_reg_set_left_older_11 ? state_reg_left_subtree_state_11 : _state_reg_T_69; // @[package.scala:163:13] wire _state_reg_T_72 = _state_reg_T_71; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_73 = ~_state_reg_T_72; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_74 = state_reg_set_left_older_11 ? _state_reg_T_73 : state_reg_right_subtree_state_11; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_8 = {state_reg_set_left_older_11, _state_reg_T_70}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_75 = {state_reg_hi_8, _state_reg_T_74}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_76 = state_reg_set_left_older_10 ? state_reg_left_subtree_state_10 : _state_reg_T_75; // @[package.scala:163:13] wire _state_reg_set_left_older_T_12 = _state_reg_T_77[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_12 = ~_state_reg_set_left_older_T_12; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_12 = state_reg_right_subtree_state_10[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_12 = state_reg_right_subtree_state_10[0]; // @[Replacement.scala:198:38] wire _state_reg_T_78 = _state_reg_T_77[0]; // @[package.scala:163:13] wire _state_reg_T_82 = _state_reg_T_77[0]; // @[package.scala:163:13] wire _state_reg_T_79 = _state_reg_T_78; // @[package.scala:163:13] wire _state_reg_T_80 = ~_state_reg_T_79; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_81 = state_reg_set_left_older_12 ? state_reg_left_subtree_state_12 : _state_reg_T_80; // @[package.scala:163:13] wire _state_reg_T_83 = _state_reg_T_82; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_84 = ~_state_reg_T_83; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_85 = state_reg_set_left_older_12 ? _state_reg_T_84 : state_reg_right_subtree_state_12; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_9 = {state_reg_set_left_older_12, _state_reg_T_81}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_86 = {state_reg_hi_9, _state_reg_T_85}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_87 = state_reg_set_left_older_10 ? _state_reg_T_86 : state_reg_right_subtree_state_10; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_10 = {state_reg_set_left_older_10, _state_reg_T_76}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_88 = {state_reg_hi_10, _state_reg_T_87}; // @[Replacement.scala:202:12, :206:16] wire [6:0] _state_reg_T_89 = state_reg_set_left_older_6 ? _state_reg_T_88 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [7:0] state_reg_hi_11 = {state_reg_set_left_older_6, _state_reg_T_64}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [14:0] _state_reg_T_90 = {state_reg_hi_11, _state_reg_T_89}; // @[Replacement.scala:202:12, :206:16] wire [14:0] _state_reg_T_91 = state_reg_set_left_older ? _state_reg_T_90 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [11:0] state_reg_hi_12 = {state_reg_set_left_older, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [26:0] _state_reg_T_92 = {state_reg_hi_12, _state_reg_T_91}; // @[Replacement.scala:202:12, :206:16] wire [31:0] mask = 32'h1 << waddr; // @[OneHot.scala:58:35] wire [12:0] _idxs_T = r_btb_update_bits_pc[13:1]; // @[Valid.scala:135:21] wire [3:0] _idxPages_T = {1'h0, idxPageUpdate} + 4'h1; // @[OneHot.scala:32:10] wire [31:0] _isValid_T = {4'h0, isValid} | mask; // @[OneHot.scala:32:14, :58:35] wire [31:0] _isValid_T_1 = ~mask; // @[OneHot.scala:58:35] wire [31:0] _isValid_T_2 = {4'h0, _isValid_T_1[27:0] & isValid}; // @[OneHot.scala:32:14] wire [31:0] _isValid_T_3 = r_btb_update_bits_isValid ? _isValid_T : _isValid_T_2; // @[Valid.scala:135:21] wire [37:0] _brIdx_T = r_btb_update_bits_br_pc[38:1]; // @[Valid.scala:135:21] wire _idxWritesEven_T = idxPageUpdate[0]; // @[OneHot.scala:32:10] wire idxWritesEven = ~_idxWritesEven_T; // @[BTB.scala:274:{25,39}] wire [7:0] _pageValid_T = {2'h0, pageValid} | tgtPageReplEn; // @[BTB.scala:204:26, :247:26, :284:28] wire [7:0] _pageValid_T_1 = _pageValid_T | idxPageReplEn; // @[BTB.scala:241:26, :284:{28,44}] wire [6:0] _io_resp_valid_T = {pageHit, 1'h0}; // @[BTB.scala:214:15, :287:29] wire _io_resp_valid_T_1 = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_97 = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T = idxHit[0]; // @[Mux.scala:32:36] wire _io_resp_valid_T_2 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_98 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_1 = idxHit[1]; // @[Mux.scala:32:36] wire _io_resp_valid_T_3 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_99 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_2 = idxHit[2]; // @[Mux.scala:32:36] wire _io_resp_valid_T_4 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_100 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_3 = idxHit[3]; // @[Mux.scala:32:36] wire _io_resp_valid_T_5 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_101 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_4 = idxHit[4]; // @[Mux.scala:32:36] wire _io_resp_valid_T_6 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_102 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_5 = idxHit[5]; // @[Mux.scala:32:36] wire _io_resp_valid_T_7 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_103 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_6 = idxHit[6]; // @[Mux.scala:32:36] wire _io_resp_valid_T_8 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_104 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_7 = idxHit[7]; // @[Mux.scala:32:36] wire _io_resp_valid_T_9 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_105 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_8 = idxHit[8]; // @[Mux.scala:32:36] wire _io_resp_valid_T_10 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_106 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_9 = idxHit[9]; // @[Mux.scala:32:36] wire _io_resp_valid_T_11 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_107 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_10 = idxHit[10]; // @[Mux.scala:32:36] wire _io_resp_valid_T_12 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_108 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_11 = idxHit[11]; // @[Mux.scala:32:36] wire _io_resp_valid_T_13 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_109 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_12 = idxHit[12]; // @[Mux.scala:32:36] wire _io_resp_valid_T_14 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_110 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_13 = idxHit[13]; // @[Mux.scala:32:36] wire _io_resp_valid_T_15 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_111 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_14 = idxHit[14]; // @[Mux.scala:32:36] wire _io_resp_valid_T_16 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_112 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_15 = idxHit[15]; // @[Mux.scala:32:36] wire _io_resp_valid_T_17 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_113 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_16 = idxHit[16]; // @[Mux.scala:32:36] wire _io_resp_valid_T_18 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_114 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_17 = idxHit[17]; // @[Mux.scala:32:36] wire _io_resp_valid_T_19 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_115 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_18 = idxHit[18]; // @[Mux.scala:32:36] wire _io_resp_valid_T_20 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_116 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_19 = idxHit[19]; // @[Mux.scala:32:36] wire _io_resp_valid_T_21 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_117 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_20 = idxHit[20]; // @[Mux.scala:32:36] wire _io_resp_valid_T_22 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_118 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_21 = idxHit[21]; // @[Mux.scala:32:36] wire _io_resp_valid_T_23 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_119 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_22 = idxHit[22]; // @[Mux.scala:32:36] wire _io_resp_valid_T_24 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_120 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_23 = idxHit[23]; // @[Mux.scala:32:36] wire _io_resp_valid_T_25 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_121 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_24 = idxHit[24]; // @[Mux.scala:32:36] wire _io_resp_valid_T_26 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_122 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_25 = idxHit[25]; // @[Mux.scala:32:36] wire _io_resp_valid_T_27 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_123 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_26 = idxHit[26]; // @[Mux.scala:32:36] wire _io_resp_valid_T_28 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_target_T_124 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_bridx_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire _io_resp_bits_cfiType_T_27 = idxHit[27]; // @[Mux.scala:32:36] wire [2:0] _io_resp_valid_T_29 = _io_resp_valid_T_1 ? idxPages_0 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_30 = _io_resp_valid_T_2 ? idxPages_1 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_31 = _io_resp_valid_T_3 ? idxPages_2 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_32 = _io_resp_valid_T_4 ? idxPages_3 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_33 = _io_resp_valid_T_5 ? idxPages_4 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_34 = _io_resp_valid_T_6 ? idxPages_5 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_35 = _io_resp_valid_T_7 ? idxPages_6 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_36 = _io_resp_valid_T_8 ? idxPages_7 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_37 = _io_resp_valid_T_9 ? idxPages_8 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_38 = _io_resp_valid_T_10 ? idxPages_9 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_39 = _io_resp_valid_T_11 ? idxPages_10 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_40 = _io_resp_valid_T_12 ? idxPages_11 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_41 = _io_resp_valid_T_13 ? idxPages_12 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_42 = _io_resp_valid_T_14 ? idxPages_13 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_43 = _io_resp_valid_T_15 ? idxPages_14 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_44 = _io_resp_valid_T_16 ? idxPages_15 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_45 = _io_resp_valid_T_17 ? idxPages_16 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_46 = _io_resp_valid_T_18 ? idxPages_17 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_47 = _io_resp_valid_T_19 ? idxPages_18 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_48 = _io_resp_valid_T_20 ? idxPages_19 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_49 = _io_resp_valid_T_21 ? idxPages_20 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_50 = _io_resp_valid_T_22 ? idxPages_21 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_51 = _io_resp_valid_T_23 ? idxPages_22 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_52 = _io_resp_valid_T_24 ? idxPages_23 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_53 = _io_resp_valid_T_25 ? idxPages_24 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_54 = _io_resp_valid_T_26 ? idxPages_25 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_55 = _io_resp_valid_T_27 ? idxPages_26 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_56 = _io_resp_valid_T_28 ? idxPages_27 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_valid_T_57 = _io_resp_valid_T_29 | _io_resp_valid_T_30; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_58 = _io_resp_valid_T_57 | _io_resp_valid_T_31; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_59 = _io_resp_valid_T_58 | _io_resp_valid_T_32; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_60 = _io_resp_valid_T_59 | _io_resp_valid_T_33; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_61 = _io_resp_valid_T_60 | _io_resp_valid_T_34; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_62 = _io_resp_valid_T_61 | _io_resp_valid_T_35; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_63 = _io_resp_valid_T_62 | _io_resp_valid_T_36; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_64 = _io_resp_valid_T_63 | _io_resp_valid_T_37; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_65 = _io_resp_valid_T_64 | _io_resp_valid_T_38; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_66 = _io_resp_valid_T_65 | _io_resp_valid_T_39; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_67 = _io_resp_valid_T_66 | _io_resp_valid_T_40; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_68 = _io_resp_valid_T_67 | _io_resp_valid_T_41; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_69 = _io_resp_valid_T_68 | _io_resp_valid_T_42; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_70 = _io_resp_valid_T_69 | _io_resp_valid_T_43; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_71 = _io_resp_valid_T_70 | _io_resp_valid_T_44; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_72 = _io_resp_valid_T_71 | _io_resp_valid_T_45; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_73 = _io_resp_valid_T_72 | _io_resp_valid_T_46; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_74 = _io_resp_valid_T_73 | _io_resp_valid_T_47; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_75 = _io_resp_valid_T_74 | _io_resp_valid_T_48; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_76 = _io_resp_valid_T_75 | _io_resp_valid_T_49; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_77 = _io_resp_valid_T_76 | _io_resp_valid_T_50; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_78 = _io_resp_valid_T_77 | _io_resp_valid_T_51; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_79 = _io_resp_valid_T_78 | _io_resp_valid_T_52; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_80 = _io_resp_valid_T_79 | _io_resp_valid_T_53; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_81 = _io_resp_valid_T_80 | _io_resp_valid_T_54; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_82 = _io_resp_valid_T_81 | _io_resp_valid_T_55; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_T_83 = _io_resp_valid_T_82 | _io_resp_valid_T_56; // @[Mux.scala:30:73] wire [2:0] _io_resp_valid_WIRE = _io_resp_valid_T_83; // @[Mux.scala:30:73] wire [6:0] _io_resp_valid_T_84 = _io_resp_valid_T >> _io_resp_valid_WIRE; // @[Mux.scala:30:73] assign _io_resp_valid_T_85 = _io_resp_valid_T_84[0]; // @[BTB.scala:287:34] assign io_resp_valid_0 = _io_resp_valid_T_85; // @[BTB.scala:187:7, :287:34] wire [2:0] _io_resp_bits_target_T_28 = _io_resp_bits_target_T ? tgtPages_0 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_29 = _io_resp_bits_target_T_1 ? tgtPages_1 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_30 = _io_resp_bits_target_T_2 ? tgtPages_2 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_31 = _io_resp_bits_target_T_3 ? tgtPages_3 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_32 = _io_resp_bits_target_T_4 ? tgtPages_4 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_33 = _io_resp_bits_target_T_5 ? tgtPages_5 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_34 = _io_resp_bits_target_T_6 ? tgtPages_6 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_35 = _io_resp_bits_target_T_7 ? tgtPages_7 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_36 = _io_resp_bits_target_T_8 ? tgtPages_8 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_37 = _io_resp_bits_target_T_9 ? tgtPages_9 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_38 = _io_resp_bits_target_T_10 ? tgtPages_10 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_39 = _io_resp_bits_target_T_11 ? tgtPages_11 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_40 = _io_resp_bits_target_T_12 ? tgtPages_12 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_41 = _io_resp_bits_target_T_13 ? tgtPages_13 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_42 = _io_resp_bits_target_T_14 ? tgtPages_14 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_43 = _io_resp_bits_target_T_15 ? tgtPages_15 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_44 = _io_resp_bits_target_T_16 ? tgtPages_16 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_45 = _io_resp_bits_target_T_17 ? tgtPages_17 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_46 = _io_resp_bits_target_T_18 ? tgtPages_18 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_47 = _io_resp_bits_target_T_19 ? tgtPages_19 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_48 = _io_resp_bits_target_T_20 ? tgtPages_20 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_49 = _io_resp_bits_target_T_21 ? tgtPages_21 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_50 = _io_resp_bits_target_T_22 ? tgtPages_22 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_51 = _io_resp_bits_target_T_23 ? tgtPages_23 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_52 = _io_resp_bits_target_T_24 ? tgtPages_24 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_53 = _io_resp_bits_target_T_25 ? tgtPages_25 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_54 = _io_resp_bits_target_T_26 ? tgtPages_26 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_55 = _io_resp_bits_target_T_27 ? tgtPages_27 : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _io_resp_bits_target_T_56 = _io_resp_bits_target_T_28 | _io_resp_bits_target_T_29; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_57 = _io_resp_bits_target_T_56 | _io_resp_bits_target_T_30; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_58 = _io_resp_bits_target_T_57 | _io_resp_bits_target_T_31; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_59 = _io_resp_bits_target_T_58 | _io_resp_bits_target_T_32; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_60 = _io_resp_bits_target_T_59 | _io_resp_bits_target_T_33; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_61 = _io_resp_bits_target_T_60 | _io_resp_bits_target_T_34; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_62 = _io_resp_bits_target_T_61 | _io_resp_bits_target_T_35; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_63 = _io_resp_bits_target_T_62 | _io_resp_bits_target_T_36; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_64 = _io_resp_bits_target_T_63 | _io_resp_bits_target_T_37; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_65 = _io_resp_bits_target_T_64 | _io_resp_bits_target_T_38; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_66 = _io_resp_bits_target_T_65 | _io_resp_bits_target_T_39; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_67 = _io_resp_bits_target_T_66 | _io_resp_bits_target_T_40; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_68 = _io_resp_bits_target_T_67 | _io_resp_bits_target_T_41; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_69 = _io_resp_bits_target_T_68 | _io_resp_bits_target_T_42; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_70 = _io_resp_bits_target_T_69 | _io_resp_bits_target_T_43; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_71 = _io_resp_bits_target_T_70 | _io_resp_bits_target_T_44; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_72 = _io_resp_bits_target_T_71 | _io_resp_bits_target_T_45; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_73 = _io_resp_bits_target_T_72 | _io_resp_bits_target_T_46; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_74 = _io_resp_bits_target_T_73 | _io_resp_bits_target_T_47; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_75 = _io_resp_bits_target_T_74 | _io_resp_bits_target_T_48; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_76 = _io_resp_bits_target_T_75 | _io_resp_bits_target_T_49; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_77 = _io_resp_bits_target_T_76 | _io_resp_bits_target_T_50; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_78 = _io_resp_bits_target_T_77 | _io_resp_bits_target_T_51; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_79 = _io_resp_bits_target_T_78 | _io_resp_bits_target_T_52; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_80 = _io_resp_bits_target_T_79 | _io_resp_bits_target_T_53; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_81 = _io_resp_bits_target_T_80 | _io_resp_bits_target_T_54; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_T_82 = _io_resp_bits_target_T_81 | _io_resp_bits_target_T_55; // @[Mux.scala:30:73] wire [2:0] _io_resp_bits_target_WIRE = _io_resp_bits_target_T_82; // @[Mux.scala:30:73] wire _io_resp_bits_target_T_83 = _io_resp_bits_target_WIRE == 3'h1; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_84 = _io_resp_bits_target_T_83 ? pagesMasked_1 : pagesMasked_0; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_85 = _io_resp_bits_target_WIRE == 3'h2; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_86 = _io_resp_bits_target_T_85 ? pagesMasked_2 : _io_resp_bits_target_T_84; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_87 = _io_resp_bits_target_WIRE == 3'h3; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_88 = _io_resp_bits_target_T_87 ? pagesMasked_3 : _io_resp_bits_target_T_86; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_89 = _io_resp_bits_target_WIRE == 3'h4; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_90 = _io_resp_bits_target_T_89 ? pagesMasked_4 : _io_resp_bits_target_T_88; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_91 = _io_resp_bits_target_WIRE == 3'h5; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_92 = _io_resp_bits_target_T_91 ? pagesMasked_5 : _io_resp_bits_target_T_90; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_93 = _io_resp_bits_target_WIRE == 3'h6; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_94 = _io_resp_bits_target_T_93 ? pagesMasked_4 : _io_resp_bits_target_T_92; // @[package.scala:39:{76,86}] wire _io_resp_bits_target_T_95 = &_io_resp_bits_target_WIRE; // @[Mux.scala:30:73] wire [24:0] _io_resp_bits_target_T_96 = _io_resp_bits_target_T_95 ? pagesMasked_5 : _io_resp_bits_target_T_94; // @[package.scala:39:{76,86}] wire [12:0] _io_resp_bits_target_T_125 = _io_resp_bits_target_T_97 ? tgts_0 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_126 = _io_resp_bits_target_T_98 ? tgts_1 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_127 = _io_resp_bits_target_T_99 ? tgts_2 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_128 = _io_resp_bits_target_T_100 ? tgts_3 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_129 = _io_resp_bits_target_T_101 ? tgts_4 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_130 = _io_resp_bits_target_T_102 ? tgts_5 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_131 = _io_resp_bits_target_T_103 ? tgts_6 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_132 = _io_resp_bits_target_T_104 ? tgts_7 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_133 = _io_resp_bits_target_T_105 ? tgts_8 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_134 = _io_resp_bits_target_T_106 ? tgts_9 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_135 = _io_resp_bits_target_T_107 ? tgts_10 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_136 = _io_resp_bits_target_T_108 ? tgts_11 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_137 = _io_resp_bits_target_T_109 ? tgts_12 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_138 = _io_resp_bits_target_T_110 ? tgts_13 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_139 = _io_resp_bits_target_T_111 ? tgts_14 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_140 = _io_resp_bits_target_T_112 ? tgts_15 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_141 = _io_resp_bits_target_T_113 ? tgts_16 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_142 = _io_resp_bits_target_T_114 ? tgts_17 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_143 = _io_resp_bits_target_T_115 ? tgts_18 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_144 = _io_resp_bits_target_T_116 ? tgts_19 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_145 = _io_resp_bits_target_T_117 ? tgts_20 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_146 = _io_resp_bits_target_T_118 ? tgts_21 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_147 = _io_resp_bits_target_T_119 ? tgts_22 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_148 = _io_resp_bits_target_T_120 ? tgts_23 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_149 = _io_resp_bits_target_T_121 ? tgts_24 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_150 = _io_resp_bits_target_T_122 ? tgts_25 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_151 = _io_resp_bits_target_T_123 ? tgts_26 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_152 = _io_resp_bits_target_T_124 ? tgts_27 : 13'h0; // @[Mux.scala:30:73, :32:36] wire [12:0] _io_resp_bits_target_T_153 = _io_resp_bits_target_T_125 | _io_resp_bits_target_T_126; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_154 = _io_resp_bits_target_T_153 | _io_resp_bits_target_T_127; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_155 = _io_resp_bits_target_T_154 | _io_resp_bits_target_T_128; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_156 = _io_resp_bits_target_T_155 | _io_resp_bits_target_T_129; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_157 = _io_resp_bits_target_T_156 | _io_resp_bits_target_T_130; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_158 = _io_resp_bits_target_T_157 | _io_resp_bits_target_T_131; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_159 = _io_resp_bits_target_T_158 | _io_resp_bits_target_T_132; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_160 = _io_resp_bits_target_T_159 | _io_resp_bits_target_T_133; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_161 = _io_resp_bits_target_T_160 | _io_resp_bits_target_T_134; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_162 = _io_resp_bits_target_T_161 | _io_resp_bits_target_T_135; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_163 = _io_resp_bits_target_T_162 | _io_resp_bits_target_T_136; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_164 = _io_resp_bits_target_T_163 | _io_resp_bits_target_T_137; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_165 = _io_resp_bits_target_T_164 | _io_resp_bits_target_T_138; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_166 = _io_resp_bits_target_T_165 | _io_resp_bits_target_T_139; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_167 = _io_resp_bits_target_T_166 | _io_resp_bits_target_T_140; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_168 = _io_resp_bits_target_T_167 | _io_resp_bits_target_T_141; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_169 = _io_resp_bits_target_T_168 | _io_resp_bits_target_T_142; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_170 = _io_resp_bits_target_T_169 | _io_resp_bits_target_T_143; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_171 = _io_resp_bits_target_T_170 | _io_resp_bits_target_T_144; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_172 = _io_resp_bits_target_T_171 | _io_resp_bits_target_T_145; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_173 = _io_resp_bits_target_T_172 | _io_resp_bits_target_T_146; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_174 = _io_resp_bits_target_T_173 | _io_resp_bits_target_T_147; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_175 = _io_resp_bits_target_T_174 | _io_resp_bits_target_T_148; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_176 = _io_resp_bits_target_T_175 | _io_resp_bits_target_T_149; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_177 = _io_resp_bits_target_T_176 | _io_resp_bits_target_T_150; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_178 = _io_resp_bits_target_T_177 | _io_resp_bits_target_T_151; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_T_179 = _io_resp_bits_target_T_178 | _io_resp_bits_target_T_152; // @[Mux.scala:30:73] wire [12:0] _io_resp_bits_target_WIRE_1 = _io_resp_bits_target_T_179; // @[Mux.scala:30:73] wire [13:0] _io_resp_bits_target_T_180 = {_io_resp_bits_target_WIRE_1, 1'h0}; // @[Mux.scala:30:73] wire [38:0] _io_resp_bits_target_T_181 = {_io_resp_bits_target_T_96, _io_resp_bits_target_T_180}; // @[package.scala:39:76] wire [11:0] io_resp_bits_entry_hi = idxHit[27:16]; // @[OneHot.scala:30:18] wire [15:0] io_resp_bits_entry_lo = idxHit[15:0]; // @[OneHot.scala:31:18] wire _io_resp_bits_entry_T = |io_resp_bits_entry_hi; // @[OneHot.scala:30:18, :32:14] wire [15:0] _io_resp_bits_entry_T_1 = {4'h0, io_resp_bits_entry_hi} | io_resp_bits_entry_lo; // @[OneHot.scala:30:18, :31:18, :32:{14,28}] wire [7:0] io_resp_bits_entry_hi_1 = _io_resp_bits_entry_T_1[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] io_resp_bits_entry_lo_1 = _io_resp_bits_entry_T_1[7:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_2 = |io_resp_bits_entry_hi_1; // @[OneHot.scala:30:18, :32:14] wire [7:0] _io_resp_bits_entry_T_3 = io_resp_bits_entry_hi_1 | io_resp_bits_entry_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] io_resp_bits_entry_hi_2 = _io_resp_bits_entry_T_3[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] io_resp_bits_entry_lo_2 = _io_resp_bits_entry_T_3[3:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_4 = |io_resp_bits_entry_hi_2; // @[OneHot.scala:30:18, :32:14] wire [3:0] _io_resp_bits_entry_T_5 = io_resp_bits_entry_hi_2 | io_resp_bits_entry_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] io_resp_bits_entry_hi_3 = _io_resp_bits_entry_T_5[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] io_resp_bits_entry_lo_3 = _io_resp_bits_entry_T_5[1:0]; // @[OneHot.scala:31:18, :32:28] wire _io_resp_bits_entry_T_6 = |io_resp_bits_entry_hi_3; // @[OneHot.scala:30:18, :32:14] wire [1:0] _io_resp_bits_entry_T_7 = io_resp_bits_entry_hi_3 | io_resp_bits_entry_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _io_resp_bits_entry_T_8 = _io_resp_bits_entry_T_7[1]; // @[OneHot.scala:32:28] wire [1:0] _io_resp_bits_entry_T_9 = {_io_resp_bits_entry_T_6, _io_resp_bits_entry_T_8}; // @[OneHot.scala:32:{10,14}] wire [2:0] _io_resp_bits_entry_T_10 = {_io_resp_bits_entry_T_4, _io_resp_bits_entry_T_9}; // @[OneHot.scala:32:{10,14}] wire [3:0] _io_resp_bits_entry_T_11 = {_io_resp_bits_entry_T_2, _io_resp_bits_entry_T_10}; // @[OneHot.scala:32:{10,14}] assign _io_resp_bits_entry_T_12 = {_io_resp_bits_entry_T, _io_resp_bits_entry_T_11}; // @[OneHot.scala:32:{10,14}] assign io_resp_bits_entry_0 = _io_resp_bits_entry_T_12; // @[OneHot.scala:32:10] wire _io_resp_bits_bridx_T_28 = _io_resp_bits_bridx_T & brIdx_0; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_29 = _io_resp_bits_bridx_T_1 & brIdx_1; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_30 = _io_resp_bits_bridx_T_2 & brIdx_2; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_31 = _io_resp_bits_bridx_T_3 & brIdx_3; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_32 = _io_resp_bits_bridx_T_4 & brIdx_4; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_33 = _io_resp_bits_bridx_T_5 & brIdx_5; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_34 = _io_resp_bits_bridx_T_6 & brIdx_6; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_35 = _io_resp_bits_bridx_T_7 & brIdx_7; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_36 = _io_resp_bits_bridx_T_8 & brIdx_8; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_37 = _io_resp_bits_bridx_T_9 & brIdx_9; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_38 = _io_resp_bits_bridx_T_10 & brIdx_10; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_39 = _io_resp_bits_bridx_T_11 & brIdx_11; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_40 = _io_resp_bits_bridx_T_12 & brIdx_12; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_41 = _io_resp_bits_bridx_T_13 & brIdx_13; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_42 = _io_resp_bits_bridx_T_14 & brIdx_14; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_43 = _io_resp_bits_bridx_T_15 & brIdx_15; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_44 = _io_resp_bits_bridx_T_16 & brIdx_16; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_45 = _io_resp_bits_bridx_T_17 & brIdx_17; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_46 = _io_resp_bits_bridx_T_18 & brIdx_18; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_47 = _io_resp_bits_bridx_T_19 & brIdx_19; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_48 = _io_resp_bits_bridx_T_20 & brIdx_20; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_49 = _io_resp_bits_bridx_T_21 & brIdx_21; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_50 = _io_resp_bits_bridx_T_22 & brIdx_22; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_51 = _io_resp_bits_bridx_T_23 & brIdx_23; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_52 = _io_resp_bits_bridx_T_24 & brIdx_24; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_53 = _io_resp_bits_bridx_T_25 & brIdx_25; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_54 = _io_resp_bits_bridx_T_26 & brIdx_26; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_55 = _io_resp_bits_bridx_T_27 & brIdx_27; // @[Mux.scala:30:73, :32:36] wire _io_resp_bits_bridx_T_56 = _io_resp_bits_bridx_T_28 | _io_resp_bits_bridx_T_29; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_57 = _io_resp_bits_bridx_T_56 | _io_resp_bits_bridx_T_30; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_58 = _io_resp_bits_bridx_T_57 | _io_resp_bits_bridx_T_31; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_59 = _io_resp_bits_bridx_T_58 | _io_resp_bits_bridx_T_32; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_60 = _io_resp_bits_bridx_T_59 | _io_resp_bits_bridx_T_33; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_61 = _io_resp_bits_bridx_T_60 | _io_resp_bits_bridx_T_34; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_62 = _io_resp_bits_bridx_T_61 | _io_resp_bits_bridx_T_35; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_63 = _io_resp_bits_bridx_T_62 | _io_resp_bits_bridx_T_36; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_64 = _io_resp_bits_bridx_T_63 | _io_resp_bits_bridx_T_37; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_65 = _io_resp_bits_bridx_T_64 | _io_resp_bits_bridx_T_38; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_66 = _io_resp_bits_bridx_T_65 | _io_resp_bits_bridx_T_39; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_67 = _io_resp_bits_bridx_T_66 | _io_resp_bits_bridx_T_40; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_68 = _io_resp_bits_bridx_T_67 | _io_resp_bits_bridx_T_41; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_69 = _io_resp_bits_bridx_T_68 | _io_resp_bits_bridx_T_42; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_70 = _io_resp_bits_bridx_T_69 | _io_resp_bits_bridx_T_43; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_71 = _io_resp_bits_bridx_T_70 | _io_resp_bits_bridx_T_44; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_72 = _io_resp_bits_bridx_T_71 | _io_resp_bits_bridx_T_45; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_73 = _io_resp_bits_bridx_T_72 | _io_resp_bits_bridx_T_46; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_74 = _io_resp_bits_bridx_T_73 | _io_resp_bits_bridx_T_47; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_75 = _io_resp_bits_bridx_T_74 | _io_resp_bits_bridx_T_48; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_76 = _io_resp_bits_bridx_T_75 | _io_resp_bits_bridx_T_49; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_77 = _io_resp_bits_bridx_T_76 | _io_resp_bits_bridx_T_50; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_78 = _io_resp_bits_bridx_T_77 | _io_resp_bits_bridx_T_51; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_79 = _io_resp_bits_bridx_T_78 | _io_resp_bits_bridx_T_52; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_80 = _io_resp_bits_bridx_T_79 | _io_resp_bits_bridx_T_53; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_81 = _io_resp_bits_bridx_T_80 | _io_resp_bits_bridx_T_54; // @[Mux.scala:30:73] wire _io_resp_bits_bridx_T_82 = _io_resp_bits_bridx_T_81 | _io_resp_bits_bridx_T_55; // @[Mux.scala:30:73] assign _io_resp_bits_bridx_WIRE = _io_resp_bits_bridx_T_82; // @[Mux.scala:30:73] assign io_resp_bits_bridx_0 = _io_resp_bits_bridx_WIRE; // @[Mux.scala:30:73] wire _io_resp_bits_mask_T = ~io_resp_bits_bridx_0; // @[BTB.scala:187:7, :292:61] wire _io_resp_bits_mask_T_1 = io_resp_bits_taken_0 & _io_resp_bits_mask_T; // @[BTB.scala:187:7, :292:{40,61}] wire _io_resp_bits_mask_T_2 = ~_io_resp_bits_mask_T_1; // @[BTB.scala:292:{36,40}] wire [1:0] _io_resp_bits_mask_T_3 = 2'h1 << _io_resp_bits_mask_T_2; // @[BTB.scala:292:{33,36}] wire [2:0] _io_resp_bits_mask_T_4 = {1'h0, _io_resp_bits_mask_T_3} - 3'h1; // @[BTB.scala:292:{33,87}] wire [1:0] _io_resp_bits_mask_T_5 = _io_resp_bits_mask_T_4[1:0]; // @[BTB.scala:292:87] wire [2:0] _io_resp_bits_mask_T_6 = {_io_resp_bits_mask_T_5, 1'h1}; // @[BTB.scala:187:7, :292:{27,87}] assign io_resp_bits_mask_0 = _io_resp_bits_mask_T_6[1:0]; // @[BTB.scala:187:7, :292:{21,27}] wire [1:0] _io_resp_bits_cfiType_T_28 = _io_resp_bits_cfiType_T ? cfiType_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_29 = _io_resp_bits_cfiType_T_1 ? cfiType_1 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_30 = _io_resp_bits_cfiType_T_2 ? cfiType_2 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_31 = _io_resp_bits_cfiType_T_3 ? cfiType_3 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_32 = _io_resp_bits_cfiType_T_4 ? cfiType_4 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_33 = _io_resp_bits_cfiType_T_5 ? cfiType_5 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_34 = _io_resp_bits_cfiType_T_6 ? cfiType_6 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_35 = _io_resp_bits_cfiType_T_7 ? cfiType_7 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_36 = _io_resp_bits_cfiType_T_8 ? cfiType_8 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_37 = _io_resp_bits_cfiType_T_9 ? cfiType_9 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_38 = _io_resp_bits_cfiType_T_10 ? cfiType_10 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_39 = _io_resp_bits_cfiType_T_11 ? cfiType_11 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_40 = _io_resp_bits_cfiType_T_12 ? cfiType_12 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_41 = _io_resp_bits_cfiType_T_13 ? cfiType_13 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_42 = _io_resp_bits_cfiType_T_14 ? cfiType_14 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_43 = _io_resp_bits_cfiType_T_15 ? cfiType_15 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_44 = _io_resp_bits_cfiType_T_16 ? cfiType_16 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_45 = _io_resp_bits_cfiType_T_17 ? cfiType_17 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_46 = _io_resp_bits_cfiType_T_18 ? cfiType_18 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_47 = _io_resp_bits_cfiType_T_19 ? cfiType_19 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_48 = _io_resp_bits_cfiType_T_20 ? cfiType_20 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_49 = _io_resp_bits_cfiType_T_21 ? cfiType_21 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_50 = _io_resp_bits_cfiType_T_22 ? cfiType_22 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_51 = _io_resp_bits_cfiType_T_23 ? cfiType_23 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_52 = _io_resp_bits_cfiType_T_24 ? cfiType_24 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_53 = _io_resp_bits_cfiType_T_25 ? cfiType_25 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_54 = _io_resp_bits_cfiType_T_26 ? cfiType_26 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_55 = _io_resp_bits_cfiType_T_27 ? cfiType_27 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _io_resp_bits_cfiType_T_56 = _io_resp_bits_cfiType_T_28 | _io_resp_bits_cfiType_T_29; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_57 = _io_resp_bits_cfiType_T_56 | _io_resp_bits_cfiType_T_30; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_58 = _io_resp_bits_cfiType_T_57 | _io_resp_bits_cfiType_T_31; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_59 = _io_resp_bits_cfiType_T_58 | _io_resp_bits_cfiType_T_32; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_60 = _io_resp_bits_cfiType_T_59 | _io_resp_bits_cfiType_T_33; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_61 = _io_resp_bits_cfiType_T_60 | _io_resp_bits_cfiType_T_34; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_62 = _io_resp_bits_cfiType_T_61 | _io_resp_bits_cfiType_T_35; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_63 = _io_resp_bits_cfiType_T_62 | _io_resp_bits_cfiType_T_36; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_64 = _io_resp_bits_cfiType_T_63 | _io_resp_bits_cfiType_T_37; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_65 = _io_resp_bits_cfiType_T_64 | _io_resp_bits_cfiType_T_38; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_66 = _io_resp_bits_cfiType_T_65 | _io_resp_bits_cfiType_T_39; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_67 = _io_resp_bits_cfiType_T_66 | _io_resp_bits_cfiType_T_40; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_68 = _io_resp_bits_cfiType_T_67 | _io_resp_bits_cfiType_T_41; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_69 = _io_resp_bits_cfiType_T_68 | _io_resp_bits_cfiType_T_42; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_70 = _io_resp_bits_cfiType_T_69 | _io_resp_bits_cfiType_T_43; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_71 = _io_resp_bits_cfiType_T_70 | _io_resp_bits_cfiType_T_44; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_72 = _io_resp_bits_cfiType_T_71 | _io_resp_bits_cfiType_T_45; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_73 = _io_resp_bits_cfiType_T_72 | _io_resp_bits_cfiType_T_46; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_74 = _io_resp_bits_cfiType_T_73 | _io_resp_bits_cfiType_T_47; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_75 = _io_resp_bits_cfiType_T_74 | _io_resp_bits_cfiType_T_48; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_76 = _io_resp_bits_cfiType_T_75 | _io_resp_bits_cfiType_T_49; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_77 = _io_resp_bits_cfiType_T_76 | _io_resp_bits_cfiType_T_50; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_78 = _io_resp_bits_cfiType_T_77 | _io_resp_bits_cfiType_T_51; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_79 = _io_resp_bits_cfiType_T_78 | _io_resp_bits_cfiType_T_52; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_80 = _io_resp_bits_cfiType_T_79 | _io_resp_bits_cfiType_T_53; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_81 = _io_resp_bits_cfiType_T_80 | _io_resp_bits_cfiType_T_54; // @[Mux.scala:30:73] wire [1:0] _io_resp_bits_cfiType_T_82 = _io_resp_bits_cfiType_T_81 | _io_resp_bits_cfiType_T_55; // @[Mux.scala:30:73] assign _io_resp_bits_cfiType_WIRE = _io_resp_bits_cfiType_T_82; // @[Mux.scala:30:73] assign io_resp_bits_cfiType_0 = _io_resp_bits_cfiType_WIRE; // @[Mux.scala:30:73] wire leftOne = idxHit[0]; // @[Misc.scala:178:18, :181:37] wire leftOne_1 = idxHit[1]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne = idxHit[2]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_1 = leftOne_1 | rightOne; // @[Misc.scala:178:18, :183:16] wire rightTwo = leftOne_1 & rightOne; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_2 = leftOne | rightOne_1; // @[Misc.scala:178:18, :183:16] wire leftTwo = rightTwo | leftOne & rightOne_1; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_3 = idxHit[3]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_2 = idxHit[4]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_4 = leftOne_3 | rightOne_2; // @[Misc.scala:178:18, :183:16] wire leftTwo_1 = leftOne_3 & rightOne_2; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_5 = idxHit[5]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_3 = idxHit[6]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_4 = leftOne_5 | rightOne_3; // @[Misc.scala:178:18, :183:16] wire rightTwo_1 = leftOne_5 & rightOne_3; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_5 = leftOne_4 | rightOne_4; // @[Misc.scala:183:16] wire rightTwo_2 = leftTwo_1 | rightTwo_1 | leftOne_4 & rightOne_4; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_6 = leftOne_2 | rightOne_5; // @[Misc.scala:183:16] wire leftTwo_2 = leftTwo | rightTwo_2 | leftOne_2 & rightOne_5; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_7 = idxHit[7]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_8 = idxHit[8]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_6 = idxHit[9]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_7 = leftOne_8 | rightOne_6; // @[Misc.scala:178:18, :183:16] wire rightTwo_3 = leftOne_8 & rightOne_6; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_9 = leftOne_7 | rightOne_7; // @[Misc.scala:178:18, :183:16] wire leftTwo_3 = rightTwo_3 | leftOne_7 & rightOne_7; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_10 = idxHit[10]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_8 = idxHit[11]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_11 = leftOne_10 | rightOne_8; // @[Misc.scala:178:18, :183:16] wire leftTwo_4 = leftOne_10 & rightOne_8; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_12 = idxHit[12]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_9 = idxHit[13]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_10 = leftOne_12 | rightOne_9; // @[Misc.scala:178:18, :183:16] wire rightTwo_4 = leftOne_12 & rightOne_9; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_11 = leftOne_11 | rightOne_10; // @[Misc.scala:183:16] wire rightTwo_5 = leftTwo_4 | rightTwo_4 | leftOne_11 & rightOne_10; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_12 = leftOne_9 | rightOne_11; // @[Misc.scala:183:16] wire rightTwo_6 = leftTwo_3 | rightTwo_5 | leftOne_9 & rightOne_11; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_13 = leftOne_6 | rightOne_12; // @[Misc.scala:183:16] wire leftTwo_5 = leftTwo_2 | rightTwo_6 | leftOne_6 & rightOne_12; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_14 = idxHit[14]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_15 = idxHit[15]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_13 = idxHit[16]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_14 = leftOne_15 | rightOne_13; // @[Misc.scala:178:18, :183:16] wire rightTwo_7 = leftOne_15 & rightOne_13; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_16 = leftOne_14 | rightOne_14; // @[Misc.scala:178:18, :183:16] wire leftTwo_6 = rightTwo_7 | leftOne_14 & rightOne_14; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_17 = idxHit[17]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_15 = idxHit[18]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_18 = leftOne_17 | rightOne_15; // @[Misc.scala:178:18, :183:16] wire leftTwo_7 = leftOne_17 & rightOne_15; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_19 = idxHit[19]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_16 = idxHit[20]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_17 = leftOne_19 | rightOne_16; // @[Misc.scala:178:18, :183:16] wire rightTwo_8 = leftOne_19 & rightOne_16; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_18 = leftOne_18 | rightOne_17; // @[Misc.scala:183:16] wire rightTwo_9 = leftTwo_7 | rightTwo_8 | leftOne_18 & rightOne_17; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_20 = leftOne_16 | rightOne_18; // @[Misc.scala:183:16] wire leftTwo_8 = leftTwo_6 | rightTwo_9 | leftOne_16 & rightOne_18; // @[Misc.scala:183:{16,37,49,61}] wire leftOne_21 = idxHit[21]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_22 = idxHit[22]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_19 = idxHit[23]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_20 = leftOne_22 | rightOne_19; // @[Misc.scala:178:18, :183:16] wire rightTwo_10 = leftOne_22 & rightOne_19; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_23 = leftOne_21 | rightOne_20; // @[Misc.scala:178:18, :183:16] wire leftTwo_9 = rightTwo_10 | leftOne_21 & rightOne_20; // @[Misc.scala:178:18, :183:{16,49,61}] wire leftOne_24 = idxHit[24]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_21 = idxHit[25]; // @[Misc.scala:178:18, :181:37, :182:39] wire leftOne_25 = leftOne_24 | rightOne_21; // @[Misc.scala:178:18, :183:16] wire leftTwo_10 = leftOne_24 & rightOne_21; // @[Misc.scala:178:18, :183:{49,61}] wire leftOne_26 = idxHit[26]; // @[Misc.scala:178:18, :181:37, :182:39] wire rightOne_22 = idxHit[27]; // @[Misc.scala:178:18, :182:39] wire rightOne_23 = leftOne_26 | rightOne_22; // @[Misc.scala:178:18, :183:16] wire rightTwo_11 = leftOne_26 & rightOne_22; // @[Misc.scala:178:18, :183:{49,61}] wire rightOne_24 = leftOne_25 | rightOne_23; // @[Misc.scala:183:16] wire rightTwo_12 = leftTwo_10 | rightTwo_11 | leftOne_25 & rightOne_23; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_25 = leftOne_23 | rightOne_24; // @[Misc.scala:183:16] wire rightTwo_13 = leftTwo_9 | rightTwo_12 | leftOne_23 & rightOne_24; // @[Misc.scala:183:{16,37,49,61}] wire rightOne_26 = leftOne_20 | rightOne_25; // @[Misc.scala:183:16] wire rightTwo_14 = leftTwo_8 | rightTwo_13 | leftOne_20 & rightOne_25; // @[Misc.scala:183:{16,37,49,61}] wire [27:0] _isValid_T_4 = ~idxHit; // @[BTB.scala:218:32, :297:26] wire [27:0] _isValid_T_5 = isValid & _isValid_T_4; // @[BTB.scala:207:24, :297:{24,26}] reg [7:0] history; // @[BTB.scala:117:24] assign res_history = history; // @[BTB.scala:91:19, :117:24] reg [9:0] reset_waddr; // @[BTB.scala:119:36] wire _resetting_T = reset_waddr[9]; // @[BTB.scala:119:36, :120:39] wire resetting = ~_resetting_T; // @[BTB.scala:120:{27,39}] wire wen; // @[BTB.scala:121:29] wire [9:0] waddr_1; // @[BTB.scala:122:31] wire wdata; // @[BTB.scala:123:31] wire [10:0] _reset_waddr_T = {1'h0, reset_waddr} + 11'h1; // @[BTB.scala:119:36, :124:49] wire [9:0] _reset_waddr_T_1 = _reset_waddr_T[9:0]; // @[BTB.scala:124:49] wire _isBranch_T = cfiType_0 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_1 = cfiType_1 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_2 = cfiType_2 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_3 = cfiType_3 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_4 = cfiType_4 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_5 = cfiType_5 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_6 = cfiType_6 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_7 = cfiType_7 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_8 = cfiType_8 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_9 = cfiType_9 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_10 = cfiType_10 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_11 = cfiType_11 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_12 = cfiType_12 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_13 = cfiType_13 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_14 = cfiType_14 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_15 = cfiType_15 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_16 = cfiType_16 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_17 = cfiType_17 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_18 = cfiType_18 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_19 = cfiType_19 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_20 = cfiType_20 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_21 = cfiType_21 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_22 = cfiType_22 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_23 = cfiType_23 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_24 = cfiType_24 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_25 = cfiType_25 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_26 = cfiType_26 == 2'h0; // @[BTB.scala:208:20, :305:44] wire _isBranch_T_27 = cfiType_27 == 2'h0; // @[BTB.scala:208:20, :305:44] wire [1:0] isBranch_lo_lo_lo_hi = {_isBranch_T_2, _isBranch_T_1}; // @[package.scala:45:27] wire [2:0] isBranch_lo_lo_lo = {isBranch_lo_lo_lo_hi, _isBranch_T}; // @[package.scala:45:27] wire [1:0] isBranch_lo_lo_hi_lo = {_isBranch_T_4, _isBranch_T_3}; // @[package.scala:45:27] wire [1:0] isBranch_lo_lo_hi_hi = {_isBranch_T_6, _isBranch_T_5}; // @[package.scala:45:27] wire [3:0] isBranch_lo_lo_hi = {isBranch_lo_lo_hi_hi, isBranch_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_lo_lo = {isBranch_lo_lo_hi, isBranch_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_lo_hi = {_isBranch_T_9, _isBranch_T_8}; // @[package.scala:45:27] wire [2:0] isBranch_lo_hi_lo = {isBranch_lo_hi_lo_hi, _isBranch_T_7}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_hi_lo = {_isBranch_T_11, _isBranch_T_10}; // @[package.scala:45:27] wire [1:0] isBranch_lo_hi_hi_hi = {_isBranch_T_13, _isBranch_T_12}; // @[package.scala:45:27] wire [3:0] isBranch_lo_hi_hi = {isBranch_lo_hi_hi_hi, isBranch_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_lo_hi = {isBranch_lo_hi_hi, isBranch_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] isBranch_lo = {isBranch_lo_hi, isBranch_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_lo_hi = {_isBranch_T_16, _isBranch_T_15}; // @[package.scala:45:27] wire [2:0] isBranch_hi_lo_lo = {isBranch_hi_lo_lo_hi, _isBranch_T_14}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_hi_lo = {_isBranch_T_18, _isBranch_T_17}; // @[package.scala:45:27] wire [1:0] isBranch_hi_lo_hi_hi = {_isBranch_T_20, _isBranch_T_19}; // @[package.scala:45:27] wire [3:0] isBranch_hi_lo_hi = {isBranch_hi_lo_hi_hi, isBranch_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_hi_lo = {isBranch_hi_lo_hi, isBranch_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_lo_hi = {_isBranch_T_23, _isBranch_T_22}; // @[package.scala:45:27] wire [2:0] isBranch_hi_hi_lo = {isBranch_hi_hi_lo_hi, _isBranch_T_21}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_hi_lo = {_isBranch_T_25, _isBranch_T_24}; // @[package.scala:45:27] wire [1:0] isBranch_hi_hi_hi_hi = {_isBranch_T_27, _isBranch_T_26}; // @[package.scala:45:27] wire [3:0] isBranch_hi_hi_hi = {isBranch_hi_hi_hi_hi, isBranch_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] isBranch_hi_hi = {isBranch_hi_hi_hi, isBranch_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] isBranch_hi = {isBranch_hi_hi, isBranch_hi_lo}; // @[package.scala:45:27] wire [27:0] _isBranch_T_28 = {isBranch_hi, isBranch_lo}; // @[package.scala:45:27] wire [27:0] _isBranch_T_29 = idxHit & _isBranch_T_28; // @[package.scala:45:27] wire isBranch = |_isBranch_T_29; // @[BTB.scala:305:{28,72}] assign io_resp_bits_bht_history_0 = res_history; // @[BTB.scala:91:19, :187:7] wire _res_res_value_T_8; // @[BTB.scala:92:21] assign io_resp_bits_bht_value_0 = res_value; // @[BTB.scala:91:19, :187:7] wire [36:0] res_res_value_hi = io_req_bits_addr_0[38:2]; // @[BTB.scala:85:21, :187:7] wire [8:0] _res_res_value_T = res_res_value_hi[8:0]; // @[BTB.scala:85:21, :86:9] wire [27:0] _res_res_value_T_1 = res_res_value_hi[36:9]; // @[BTB.scala:85:21, :86:48] wire [1:0] _res_res_value_T_2 = _res_res_value_T_1[1:0]; // @[BTB.scala:86:{48,77}] wire [8:0] _res_res_value_T_3 = {_res_res_value_T[8:2], _res_res_value_T[1:0] ^ _res_res_value_T_2}; // @[BTB.scala:86:{9,42,77}] wire [15:0] _res_res_value_T_4 = {8'h0, history} * 16'hDD; // @[BTB.scala:82:12, :117:24] wire [2:0] _res_res_value_T_5 = _res_res_value_T_4[7:5]; // @[BTB.scala:82:{12,19}] wire [8:0] _res_res_value_T_6 = {_res_res_value_T_5, 6'h0}; // @[BTB.scala:82:19, :88:44] wire [8:0] _res_res_value_T_7 = _res_res_value_T_3 ^ _res_res_value_T_6; // @[BTB.scala:86:42, :88:{20,44}] assign _res_res_value_T_8 = ~resetting & _table_ext_R0_data; // @[BTB.scala:92:21, :116:26, :120:27] assign res_value = _res_res_value_T_8; // @[BTB.scala:91:19, :92:21] wire [6:0] _history_T = history[7:1]; // @[BTB.scala:113:35, :117:24] wire [7:0] _history_T_1 = {io_bht_advance_bits_bht_value_0, _history_T}; // @[BTB.scala:113:{19,35}, :187:7] wire _GEN = io_bht_update_valid_0 & io_bht_update_bits_branch_0; // @[BTB.scala:97:9, :121:29, :187:7, :310:32, :311:40] assign wen = _GEN | resetting; // @[BTB.scala:97:9, :120:27, :121:29, :310:32, :311:40] wire [36:0] waddr_hi = io_bht_update_bits_pc_0[38:2]; // @[BTB.scala:85:21, :187:7] wire [8:0] _waddr_T_40 = waddr_hi[8:0]; // @[BTB.scala:85:21, :86:9] wire [27:0] _waddr_T_41 = waddr_hi[36:9]; // @[BTB.scala:85:21, :86:48] wire [1:0] _waddr_T_42 = _waddr_T_41[1:0]; // @[BTB.scala:86:{48,77}] wire [8:0] _waddr_T_43 = {_waddr_T_40[8:2], _waddr_T_40[1:0] ^ _waddr_T_42}; // @[BTB.scala:86:{9,42,77}] wire [15:0] _waddr_T_44 = {8'h0, io_bht_update_bits_prediction_history_0} * 16'hDD; // @[BTB.scala:82:12, :187:7] wire [2:0] _waddr_T_45 = _waddr_T_44[7:5]; // @[BTB.scala:82:{12,19}] wire [8:0] _waddr_T_46 = {_waddr_T_45, 6'h0}; // @[BTB.scala:82:19, :88:44] wire [8:0] _waddr_T_47 = _waddr_T_43 ^ _waddr_T_46; // @[BTB.scala:86:42, :88:{20,44}] assign waddr_1 = io_bht_update_valid_0 & io_bht_update_bits_branch_0 & ~resetting ? {1'h0, _waddr_T_47} : reset_waddr; // @[BTB.scala:88:20, :98:{11,23}, :99:13, :119:36, :120:27, :122:31, :187:7, :310:32, :311:40] assign wdata = _GEN & ~resetting & io_bht_update_bits_taken_0; // @[BTB.scala:97:9, :98:{11,23}, :100:13, :120:27, :121:29, :123:31, :187:7, :310:32, :311:40] wire [6:0] _history_T_2 = io_bht_update_bits_prediction_history_0[7:1]; // @[BTB.scala:110:37, :187:7] wire [7:0] _history_T_3 = {io_bht_update_bits_taken_0, _history_T_2}; // @[BTB.scala:110:{19,37}, :187:7] assign io_resp_bits_taken_0 = ~(~res_value & isBranch); // @[BTB.scala:91:19, :187:7, :288:22, :305:72, :320:{11,22,35,56}] reg [2:0] count; // @[BTB.scala:56:30] reg [2:0] pos; // @[BTB.scala:57:28] reg [38:0] stack_0; // @[BTB.scala:58:26] reg [38:0] stack_1; // @[BTB.scala:58:26] reg [38:0] stack_2; // @[BTB.scala:58:26] reg [38:0] stack_3; // @[BTB.scala:58:26] reg [38:0] stack_4; // @[BTB.scala:58:26] reg [38:0] stack_5; // @[BTB.scala:58:26] wire _doPeek_T = &cfiType_0; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_1 = &cfiType_1; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_2 = &cfiType_2; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_3 = &cfiType_3; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_4 = &cfiType_4; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_5 = &cfiType_5; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_6 = &cfiType_6; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_7 = &cfiType_7; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_8 = &cfiType_8; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_9 = &cfiType_9; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_10 = &cfiType_10; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_11 = &cfiType_11; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_12 = &cfiType_12; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_13 = &cfiType_13; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_14 = &cfiType_14; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_15 = &cfiType_15; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_16 = &cfiType_16; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_17 = &cfiType_17; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_18 = &cfiType_18; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_19 = &cfiType_19; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_20 = &cfiType_20; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_21 = &cfiType_21; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_22 = &cfiType_22; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_23 = &cfiType_23; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_24 = &cfiType_24; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_25 = &cfiType_25; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_26 = &cfiType_26; // @[BTB.scala:208:20, :326:42] wire _doPeek_T_27 = &cfiType_27; // @[BTB.scala:208:20, :326:42] wire [1:0] doPeek_lo_lo_lo_hi = {_doPeek_T_2, _doPeek_T_1}; // @[package.scala:45:27] wire [2:0] doPeek_lo_lo_lo = {doPeek_lo_lo_lo_hi, _doPeek_T}; // @[package.scala:45:27] wire [1:0] doPeek_lo_lo_hi_lo = {_doPeek_T_4, _doPeek_T_3}; // @[package.scala:45:27] wire [1:0] doPeek_lo_lo_hi_hi = {_doPeek_T_6, _doPeek_T_5}; // @[package.scala:45:27] wire [3:0] doPeek_lo_lo_hi = {doPeek_lo_lo_hi_hi, doPeek_lo_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_lo_lo = {doPeek_lo_lo_hi, doPeek_lo_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_lo_hi = {_doPeek_T_9, _doPeek_T_8}; // @[package.scala:45:27] wire [2:0] doPeek_lo_hi_lo = {doPeek_lo_hi_lo_hi, _doPeek_T_7}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_hi_lo = {_doPeek_T_11, _doPeek_T_10}; // @[package.scala:45:27] wire [1:0] doPeek_lo_hi_hi_hi = {_doPeek_T_13, _doPeek_T_12}; // @[package.scala:45:27] wire [3:0] doPeek_lo_hi_hi = {doPeek_lo_hi_hi_hi, doPeek_lo_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_lo_hi = {doPeek_lo_hi_hi, doPeek_lo_hi_lo}; // @[package.scala:45:27] wire [13:0] doPeek_lo = {doPeek_lo_hi, doPeek_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_lo_hi = {_doPeek_T_16, _doPeek_T_15}; // @[package.scala:45:27] wire [2:0] doPeek_hi_lo_lo = {doPeek_hi_lo_lo_hi, _doPeek_T_14}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_hi_lo = {_doPeek_T_18, _doPeek_T_17}; // @[package.scala:45:27] wire [1:0] doPeek_hi_lo_hi_hi = {_doPeek_T_20, _doPeek_T_19}; // @[package.scala:45:27] wire [3:0] doPeek_hi_lo_hi = {doPeek_hi_lo_hi_hi, doPeek_hi_lo_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_hi_lo = {doPeek_hi_lo_hi, doPeek_hi_lo_lo}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_lo_hi = {_doPeek_T_23, _doPeek_T_22}; // @[package.scala:45:27] wire [2:0] doPeek_hi_hi_lo = {doPeek_hi_hi_lo_hi, _doPeek_T_21}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_hi_lo = {_doPeek_T_25, _doPeek_T_24}; // @[package.scala:45:27] wire [1:0] doPeek_hi_hi_hi_hi = {_doPeek_T_27, _doPeek_T_26}; // @[package.scala:45:27] wire [3:0] doPeek_hi_hi_hi = {doPeek_hi_hi_hi_hi, doPeek_hi_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] doPeek_hi_hi = {doPeek_hi_hi_hi, doPeek_hi_hi_lo}; // @[package.scala:45:27] wire [13:0] doPeek_hi = {doPeek_hi_hi, doPeek_hi_lo}; // @[package.scala:45:27] wire [27:0] _doPeek_T_28 = {doPeek_hi, doPeek_lo}; // @[package.scala:45:27] wire [27:0] _doPeek_T_29 = idxHit & _doPeek_T_28; // @[package.scala:45:27] wire doPeek = |_doPeek_T_29; // @[BTB.scala:326:{26,67}] wire _io_ras_head_valid_T = ~(|count); // @[BTB.scala:54:29, :56:30] assign _io_ras_head_valid_T_1 = ~_io_ras_head_valid_T; // @[BTB.scala:54:29, :327:26] assign io_ras_head_valid_0 = _io_ras_head_valid_T_1; // @[BTB.scala:187:7, :327:26] wire [7:0][38:0] _GEN_0 = {{stack_0}, {stack_0}, {stack_5}, {stack_4}, {stack_3}, {stack_2}, {stack_1}, {stack_0}}; // @[BTB.scala:58:26, :328:22] assign io_ras_head_bits_0 = _GEN_0[pos]; // @[BTB.scala:57:28, :187:7, :328:22] assign io_resp_bits_target_0 = (|count) & doPeek ? io_ras_head_bits_0 : _io_resp_bits_target_T_181; // @[BTB.scala:54:29, :56:30, :187:7, :289:{23,29}, :326:67, :329:{24,35}, :330:27] wire [3:0] _GEN_1 = {1'h0, count}; // @[BTB.scala:43:44, :56:30] wire [3:0] _count_T = _GEN_1 + 4'h1; // @[BTB.scala:43:44] wire [2:0] _count_T_1 = _count_T[2:0]; // @[BTB.scala:43:44] wire _nextPos_T = pos < 3'h5; // @[BTB.scala:44:47, :57:28] wire _nextPos_T_1 = _nextPos_T; // @[BTB.scala:44:{40,47}] wire [3:0] _GEN_2 = {1'h0, pos}; // @[BTB.scala:44:64, :57:28] wire [3:0] _nextPos_T_2 = _GEN_2 + 4'h1; // @[BTB.scala:44:64] wire [2:0] _nextPos_T_3 = _nextPos_T_2[2:0]; // @[BTB.scala:44:64] wire [2:0] nextPos = _nextPos_T_1 ? _nextPos_T_3 : 3'h0; // @[BTB.scala:44:{22,40,64}, :51:40] wire [3:0] _count_T_2 = _GEN_1 - 4'h1; // @[BTB.scala:43:44, :50:20] wire [2:0] _count_T_3 = _count_T_2[2:0]; // @[BTB.scala:50:20] wire _pos_T = |pos; // @[BTB.scala:51:40, :57:28] wire _pos_T_1 = _pos_T; // @[BTB.scala:51:{33,40}] wire [3:0] _pos_T_2 = _GEN_2 - 4'h1; // @[BTB.scala:44:64, :51:50] wire [2:0] _pos_T_3 = _pos_T_2[2:0]; // @[BTB.scala:51:50] wire [2:0] _pos_T_4 = _pos_T_1 ? _pos_T_3 : 3'h5; // @[BTB.scala:51:{15,33,50}] wire [4:0] _T_5 = idxWritesEven ? idxPageReplEn[4:0] : tgtPageReplEn[4:0]; // @[BTB.scala:241:26, :247:26, :274:25, :280:24] wire [24:0] _T_8 = idxWritesEven ? r_btb_update_bits_pc[38:14] : io_req_bits_addr_0[38:14]; // @[Valid.scala:135:21] wire [4:0] _T_12 = idxWritesEven ? tgtPageReplEn[5:1] : idxPageReplEn[5:1]; // @[BTB.scala:241:26, :247:26, :274:25, :282:24] wire [24:0] _T_15 = idxWritesEven ? io_req_bits_addr_0[38:14] : r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21] wire _T_139 = io_ras_update_bits_cfiType_0 == 2'h2; // @[BTB.scala:187:7, :333:40] always @(posedge clock) begin // @[BTB.scala:187:7] if (r_btb_update_valid & waddr == 5'h0) begin // @[Valid.scala:135:21] idxs_0 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_0 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_0 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_0 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_0 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_0 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1) begin // @[Valid.scala:135:21] idxs_1 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_1 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_1 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_1 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_1 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_1 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h2) begin // @[Valid.scala:135:21] idxs_2 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_2 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_2 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_2 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_2 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_2 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h3) begin // @[Valid.scala:135:21] idxs_3 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_3 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_3 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_3 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_3 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_3 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h4) begin // @[Valid.scala:135:21] idxs_4 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_4 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_4 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_4 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_4 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_4 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h5) begin // @[Valid.scala:135:21] idxs_5 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_5 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_5 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_5 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_5 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_5 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h6) begin // @[Valid.scala:135:21] idxs_6 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_6 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_6 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_6 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_6 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_6 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h7) begin // @[Valid.scala:135:21] idxs_7 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_7 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_7 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_7 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_7 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_7 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h8) begin // @[Valid.scala:135:21] idxs_8 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_8 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_8 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_8 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_8 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_8 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h9) begin // @[Valid.scala:135:21] idxs_9 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_9 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_9 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_9 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_9 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_9 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hA) begin // @[Valid.scala:135:21] idxs_10 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_10 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_10 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_10 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_10 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_10 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hB) begin // @[Valid.scala:135:21] idxs_11 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_11 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_11 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_11 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_11 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_11 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hC) begin // @[Valid.scala:135:21] idxs_12 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_12 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_12 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_12 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_12 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_12 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hD) begin // @[Valid.scala:135:21] idxs_13 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_13 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_13 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_13 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_13 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_13 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hE) begin // @[Valid.scala:135:21] idxs_14 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_14 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_14 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_14 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_14 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_14 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'hF) begin // @[Valid.scala:135:21] idxs_15 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_15 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_15 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_15 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_15 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_15 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h10) begin // @[Valid.scala:135:21] idxs_16 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_16 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_16 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_16 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_16 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_16 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h11) begin // @[Valid.scala:135:21] idxs_17 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_17 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_17 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_17 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_17 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_17 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h12) begin // @[Valid.scala:135:21] idxs_18 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_18 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_18 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_18 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_18 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_18 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h13) begin // @[Valid.scala:135:21] idxs_19 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_19 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_19 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_19 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_19 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_19 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h14) begin // @[Valid.scala:135:21] idxs_20 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_20 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_20 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_20 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_20 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_20 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h15) begin // @[Valid.scala:135:21] idxs_21 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_21 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_21 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_21 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_21 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_21 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h16) begin // @[Valid.scala:135:21] idxs_22 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_22 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_22 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_22 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_22 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_22 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h17) begin // @[Valid.scala:135:21] idxs_23 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_23 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_23 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_23 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_23 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_23 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h18) begin // @[Valid.scala:135:21] idxs_24 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_24 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_24 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_24 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_24 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_24 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h19) begin // @[Valid.scala:135:21] idxs_25 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_25 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_25 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_25 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_25 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_25 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1A) begin // @[Valid.scala:135:21] idxs_26 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_26 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_26 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_26 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_26 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_26 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & waddr == 5'h1B) begin // @[Valid.scala:135:21] idxs_27 <= _idxs_T; // @[BTB.scala:199:17, :264:40] idxPages_27 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}] tgts_27 <= _tgts_T; // @[BTB.scala:201:17, :265:33] tgtPages_27 <= tgtPageUpdate; // @[OneHot.scala:32:10] cfiType_27 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21] brIdx_27 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}] end if (r_btb_update_valid & _T_5[0]) // @[Valid.scala:135:21] pages_0 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[0]) // @[Valid.scala:135:21] pages_1 <= _T_15; // @[BTB.scala:203:18, :283:10] if (r_btb_update_valid & _T_5[2]) // @[Valid.scala:135:21] pages_2 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[2]) // @[Valid.scala:135:21] pages_3 <= _T_15; // @[BTB.scala:203:18, :283:10] if (r_btb_update_valid & _T_5[4]) // @[Valid.scala:135:21] pages_4 <= _T_8; // @[BTB.scala:203:18, :281:10] if (r_btb_update_valid & _T_12[4]) // @[Valid.scala:135:21] pages_5 <= _T_15; // @[BTB.scala:203:18, :283:10] if (io_btb_update_valid_0) begin // @[BTB.scala:187:7] r_btb_update_pipe_b_prediction_cfiType <= io_btb_update_bits_prediction_cfiType_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_taken <= io_btb_update_bits_prediction_taken_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_mask <= io_btb_update_bits_prediction_mask_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bridx <= io_btb_update_bits_prediction_bridx_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_target <= io_btb_update_bits_prediction_target_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_entry <= io_btb_update_bits_prediction_entry_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bht_history <= io_btb_update_bits_prediction_bht_history_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_prediction_bht_value <= io_btb_update_bits_prediction_bht_value_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_pc <= io_btb_update_bits_pc_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_target <= io_btb_update_bits_target_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_isValid <= io_btb_update_bits_isValid_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_br_pc <= io_btb_update_bits_br_pc_0; // @[Valid.scala:142:26] r_btb_update_pipe_b_cfiType <= io_btb_update_bits_cfiType_0; // @[Valid.scala:142:26] end if (io_resp_valid_0) begin // @[BTB.scala:187:7] r_resp_pipe_b_cfiType <= io_resp_bits_cfiType_0; // @[Valid.scala:142:26] r_resp_pipe_b_taken <= io_resp_bits_taken_0; // @[Valid.scala:142:26] r_resp_pipe_b_mask <= io_resp_bits_mask_0; // @[Valid.scala:142:26] r_resp_pipe_b_bridx <= io_resp_bits_bridx_0; // @[Valid.scala:142:26] r_resp_pipe_b_target <= io_resp_bits_target_0; // @[Valid.scala:142:26] r_resp_pipe_b_entry <= io_resp_bits_entry_0; // @[Valid.scala:142:26] r_resp_pipe_b_bht_history <= io_resp_bits_bht_history_0; // @[Valid.scala:142:26] r_resp_pipe_b_bht_value <= io_resp_bits_bht_value_0; // @[Valid.scala:142:26] end if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h0) // @[BTB.scala:44:22, :45:20, :51:40, :58:26, :187:7, :332:32, :333:{40,58}] stack_0 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h1) // @[package.scala:39:86] stack_1 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h2) // @[package.scala:39:86] stack_2 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h3) // @[package.scala:39:86] stack_3 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h4) // @[BTB.scala:44:22, :45:20, :58:26, :187:7, :332:32, :333:{40,58}] stack_4 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h5) // @[BTB.scala:44:22, :45:20, :58:26, :187:7, :332:32, :333:{40,58}] stack_5 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7] if (reset) begin // @[BTB.scala:187:7] pageValid <= 6'h0; // @[BTB.scala:204:26] isValid <= 28'h0; // @[BTB.scala:207:24] r_btb_update_pipe_v <= 1'h0; // @[Valid.scala:141:24] nextPageRepl <= 3'h0; // @[BTB.scala:51:40, :237:29] state_reg <= 27'h0; // @[Replacement.scala:168:70] r_resp_pipe_v <= 1'h0; // @[Valid.scala:141:24] history <= 8'h0; // @[BTB.scala:117:24] reset_waddr <= 10'h0; // @[BTB.scala:119:36] count <= 3'h0; // @[BTB.scala:51:40, :56:30] pos <= 3'h0; // @[BTB.scala:51:40, :57:28] end else begin // @[BTB.scala:187:7] if (r_btb_update_valid) // @[Valid.scala:135:21] pageValid <= _pageValid_T_1[5:0]; // @[BTB.scala:204:26, :284:{15,44}] if (io_flush_0) // @[BTB.scala:187:7] isValid <= 28'h0; // @[BTB.scala:207:24] else if (leftTwo_5 | rightTwo_14 | leftOne_13 & rightOne_26) // @[Misc.scala:183:{16,37,49,61}] isValid <= _isValid_T_5; // @[BTB.scala:207:24, :297:24] else if (r_btb_update_valid) // @[Valid.scala:135:21] isValid <= _isValid_T_3[27:0]; // @[BTB.scala:207:24, :269:{13,19}] r_btb_update_pipe_v <= io_btb_update_valid_0; // @[Valid.scala:141:24] if (r_btb_update_valid & (doIdxPageRepl | doTgtPageRepl)) // @[Valid.scala:135:21] nextPageRepl <= _nextPageRepl_T_2; // @[BTB.scala:237:29, :252:24] if (r_resp_valid & r_resp_bits_taken | r_btb_update_valid) // @[Valid.scala:135:21] state_reg <= _state_reg_T_92; // @[Replacement.scala:168:70, :202:12] r_resp_pipe_v <= io_resp_valid_0; // @[Valid.scala:141:24] if (io_bht_update_valid_0 & io_bht_update_bits_mispredict_0) // @[BTB.scala:187:7, :307:33, :310:32, :311:40] history <= io_bht_update_bits_branch_0 ? _history_T_3 : io_bht_update_bits_prediction_history_0; // @[BTB.scala:107:13, :110:{13,19}, :117:24, :187:7, :307:33, :313:46, :316:50] else if (io_bht_advance_valid_0) // @[BTB.scala:187:7] history <= _history_T_1; // @[BTB.scala:113:19, :117:24] if (resetting) // @[BTB.scala:120:27] reset_waddr <= _reset_waddr_T_1; // @[BTB.scala:119:36, :124:49] if (io_ras_update_valid_0) begin // @[BTB.scala:187:7] if (_T_139) begin // @[BTB.scala:333:40] if (count[2:1] != 2'h3) // @[BTB.scala:43:17, :56:30] count <= _count_T_1; // @[BTB.scala:43:44, :56:30] pos <= nextPos; // @[BTB.scala:44:22, :57:28] end else if ((&io_ras_update_bits_cfiType_0) & (|count)) begin // @[BTB.scala:49:37, :50:11, :54:29, :56:30, :187:7, :335:{46,63}] count <= _count_T_3; // @[BTB.scala:50:20, :56:30] pos <= _pos_T_4; // @[BTB.scala:51:15, :57:28] end end end always @(posedge) table_512x1 table_ext ( // @[BTB.scala:116:26] .R0_addr (_res_res_value_T_7), // @[BTB.scala:88:20] .R0_en (1'h1), // @[BTB.scala:187:7] .R0_clk (clock), .R0_data (_table_ext_R0_data), .W0_addr (waddr_1[8:0]), // @[BTB.scala:122:31, :125:21] .W0_en (wen), // @[BTB.scala:121:29] .W0_clk (clock), .W0_data (wdata) // @[BTB.scala:123:31] ); // @[BTB.scala:116:26] assign io_resp_valid = io_resp_valid_0; // @[BTB.scala:187:7] assign io_resp_bits_cfiType = io_resp_bits_cfiType_0; // @[BTB.scala:187:7] assign io_resp_bits_taken = io_resp_bits_taken_0; // @[BTB.scala:187:7] assign io_resp_bits_mask = io_resp_bits_mask_0; // @[BTB.scala:187:7] assign io_resp_bits_bridx = io_resp_bits_bridx_0; // @[BTB.scala:187:7] assign io_resp_bits_target = io_resp_bits_target_0; // @[BTB.scala:187:7] assign io_resp_bits_entry = io_resp_bits_entry_0; // @[BTB.scala:187:7] assign io_resp_bits_bht_history = io_resp_bits_bht_history_0; // @[BTB.scala:187:7] assign io_resp_bits_bht_value = io_resp_bits_bht_value_0; // @[BTB.scala:187:7] assign io_ras_head_valid = io_ras_head_valid_0; // @[BTB.scala:187:7] assign io_ras_head_bits = io_ras_head_bits_0; // @[BTB.scala:187:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File tage.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f3_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)*l, histLength)-1, i*l) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry))) val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f3_resp(w).valid := RegNext(s2_req_rhits(w)) io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w))) io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr) } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) table.write( Mux(doing_reset, reset_idx , update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))), Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools ) val update_hi_wdata = Wire(Vec(bankWidth, Bool())) hi_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)), Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata), Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val update_lo_wdata = Wire(Vec(bankWidth, Bool())) lo_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)), Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata), Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_||_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag update_hi_wdata(w) := io.update_u(w)(1) update_lo_wdata(w) := io.update_u(w)(0) } when (io.update_mask.reduce(_||_)) { when (wrbypass_hits.reduce(_||_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048 ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(io.f0_pc) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f3_resps = VecInit(tables.map(_.io.f3_resp)) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var altpred = io.resp_in(0).f3(w).taken val final_altpred = WireInit(io.resp_in(0).f3(w).taken) var provided = false.B var provider = 0.U io.resp.f3(w).taken := io.resp_in(0).f3(w).taken for (i <- 0 until tageNTables) { val hit = f3_resps(i)(w).valid val ctr = f3_resps(i)(w).bits.ctr when (hit) { io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2)) final_altpred := altpred } provided = provided || hit provider = Mux(hit, i.U, provider) altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred) } f3_meta.provider(w).valid := provided f3_meta.provider(w).bits := provider f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }
module TageTable_6( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f3_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14] output io_f3_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14] output io_f3_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14] output io_f3_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8] wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8] wire [10:0] table_MPORT_data_3; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_2; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_1; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_0; // @[tage.scala:123:8] wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87] wire [43:0] _table_R0_data; // @[tage.scala:91:27] wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27] wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26] wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [1:0] idx_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [1:0] tag_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [35:0] _idx_T = {io_f1_req_pc_0[39:6], io_f1_req_pc_0[5:4] ^ idx_history}; // @[frontend.scala:162:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40] wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32] wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32] wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:162:35] wire [28:0] _tag_T_1 = {_tag_T[28:2], _tag_T[1:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] s1_tag = _tag_T_1[6:0]; // @[tage.scala:62:{50,64}] wire [10:0] _s2_req_rtage_WIRE_2 = _table_R0_data[10:0]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_4 = _table_R0_data[21:11]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_6 = _table_R0_data[32:22]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_8 = _table_R0_data[43:33]; // @[tage.scala:91:27, :97:87] reg [6:0] s2_tag; // @[tage.scala:95:29] wire _s2_req_rtage_T_2; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_1; // @[tage.scala:97:87] wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87] assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87] assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87] wire _s2_req_rtage_T_5; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_4; // @[tage.scala:97:87] wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87] assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87] assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87] wire _s2_req_rtage_T_8; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_7; // @[tage.scala:97:87] wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87] assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87] assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87] wire _s2_req_rtage_T_11; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_10; // @[tage.scala:97:87] wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87] assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87] assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54] wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54] wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}] wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}] wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}] wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [1:0] idx_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [1:0] tag_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [35:0] _idx_T_1 = {io_update_pc_0[39:6], io_update_pc_0[5:4] ^ idx_history_1}; // @[frontend.scala:162:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:162:35] wire [28:0] _tag_T_3 = {_tag_T_2[28:2], _tag_T_2[1:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] update_tag = _tag_T_3[6:0]; // @[tage.scala:62:{50,64}] wire [6:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26] wire [7:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102] assign table_MPORT_data_0 = doing_reset ? 11'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_1 = doing_reset ? 11'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_2 = doing_reset ? 11'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_3 = doing_reset ? 11'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90] wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90] wire _update_hi_wdata_0_T; // @[tage.scala:166:44] wire _update_hi_wdata_1_T; // @[tage.scala:166:44] wire _update_hi_wdata_2_T; // @[tage.scala:166:44] wire _update_hi_wdata_3_T; // @[tage.scala:166:44] wire update_hi_wdata_0; // @[tage.scala:127:29] wire update_hi_wdata_1; // @[tage.scala:127:29] wire update_hi_wdata_2; // @[tage.scala:127:29] wire update_hi_wdata_3; // @[tage.scala:127:29] wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21] assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}] wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80] wire [1:0] lo_1; // @[tage.scala:131:80] assign lo_1 = _GEN; // @[tage.scala:131:80] wire [1:0] lo_2; // @[tage.scala:138:80] assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80] wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80] wire [1:0] hi_5; // @[tage.scala:131:80] assign hi_5 = _GEN_0; // @[tage.scala:131:80] wire [1:0] hi_6; // @[tage.scala:138:80] assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80] wire _update_lo_wdata_0_T; // @[tage.scala:167:44] wire _update_lo_wdata_1_T; // @[tage.scala:167:44] wire _update_lo_wdata_2_T; // @[tage.scala:167:44] wire _update_lo_wdata_3_T; // @[tage.scala:167:44] wire update_lo_wdata_0; // @[tage.scala:134:29] wire update_lo_wdata_1; // @[tage.scala:134:29] wire update_lo_wdata_2; // @[tage.scala:134:29] wire update_lo_wdata_3; // @[tage.scala:134:29] wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21] assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}] reg [6:0] wrbypass_tags_0; // @[tage.scala:141:29] reg [6:0] wrbypass_tags_1; // @[tage.scala:141:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29] reg [2:0] wrbypass_0_0; // @[tage.scala:143:29] reg [2:0] wrbypass_0_1; // @[tage.scala:143:29] reg [2:0] wrbypass_0_2; // @[tage.scala:143:29] reg [2:0] wrbypass_0_3; // @[tage.scala:143:29] reg [2:0] wrbypass_1_0; // @[tage.scala:143:29] reg [2:0] wrbypass_1_1; // @[tage.scala:143:29] reg [2:0] wrbypass_1_2; // @[tage.scala:143:29] reg [2:0] wrbypass_1_3; // @[tage.scala:143:29] reg wrbypass_enq_idx; // @[tage.scala:144:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}] wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39] end else // @[tage.scala:144:33, :170:38, :171:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29] io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38] io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38] io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38] io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38] io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38] if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29] if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29] if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] end else begin // @[tage.scala:143:29, :170:38, :171:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end always @(posedge) hi_us_5 hi_us ( // @[tage.scala:89:27] .R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_hi_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}] .W0_clk (clock), .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8] .W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}] ); // @[tage.scala:89:27] lo_us_5 lo_us ( // @[tage.scala:90:27] .R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_lo_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}] .W0_clk (clock), .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8] .W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}] ); // @[tage.scala:90:27] table_5 table_0 ( // @[tage.scala:91:27] .R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_table_R0_data), .W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8] .W0_clk (clock), .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8] .W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}] ); // @[tage.scala:91:27] assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module MSHR_11( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [7:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [7:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [7:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [4:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [4:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [7:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [7:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [4:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [4:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [4:0] io_schedule_bits_a_bits_source = 5'h0; // @[MSHR.scala:84:7] wire [4:0] io_schedule_bits_c_bits_source = 5'h0; // @[MSHR.scala:84:7] wire [4:0] io_schedule_bits_d_bits_sink = 5'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [7:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [7:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [7:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 8'h40; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 8'h40; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [7:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 8'h40; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLFragmenter_BootAddrReg( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [12:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [12:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [8:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [12:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [8:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [12:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [12:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [13:0] _find_T_2 = 14'h0; // @[Parameters.scala:137:46] wire [13:0] _find_T_3 = 14'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [8:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [12:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [8:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [12:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [12:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [12:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [8:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [12:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [12:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [8:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [12:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [12:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] | dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[12:4]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [12:0] _find_T; // @[Parameters.scala:137:31] wire [13:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[12:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [9:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } } File common.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ object consts { /*------------------------------------------------------------------------ | For rounding to integer values, rounding mode 'odd' rounds to minimum | magnitude instead, same as 'minMag'. *------------------------------------------------------------------------*/ def round_near_even = "b000".U(3.W) def round_minMag = "b001".U(3.W) def round_min = "b010".U(3.W) def round_max = "b011".U(3.W) def round_near_maxMag = "b100".U(3.W) def round_odd = "b110".U(3.W) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def tininess_beforeRounding = 0.U def tininess_afterRounding = 1.U /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def flRoundOpt_sigMSBitAlwaysZero = 1 def flRoundOpt_subnormsAlwaysExact = 2 def flRoundOpt_neverUnderflows = 4 def flRoundOpt_neverOverflows = 8 /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ def divSqrtOpt_twoBitsPerCycle = 16 } class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle { val isNaN: Bool = Bool() // overrides all other fields val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig' val isZero: Bool = Bool() // overrides 'sExp' and 'sig' val sign: Bool = Bool() val sExp: SInt = SInt((expWidth + 2).W) val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0 } //*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS: object isSigNaNRawFloat { def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2) }
module RecFNToRecFN_5( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [64:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h0; // @[RecFNToRecFN.scala:44:5] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19] wire [64:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23] RoundAnyRawFNToRecFN_ie8_is24_oe11_os53_2 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19] .io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46] .io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23] .io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23] .io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[RecFNToRecFN.scala:72:19] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File LCG.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.Cat /** A 16-bit psuedo-random generator based on a linear conguential * generator (LCG). The state is stored in an unitialised register. * When using the C++ backend, it is straigtforward to arrange a * random initial value for each uninitialised register, effectively * seeding each LCG16 instance with a different seed. */ class LCG16 extends Module { val io = IO(new Bundle { val out = Output(UInt(16.W)) val inc = Input(Bool()) }) val state = Reg(UInt(32.W)) when (io.inc) { state := state * 1103515245.U(32.W) + 12345.U(32.W) } io.out := state(30, 15) } /** An n-bit psuedo-random generator made from many instances of a * 16-bit LCG. Parameter 'width' must be larger than 0. */ class LCG(val w: Int) extends Module { val io = IO(new Bundle { val out = Output(UInt(w.W)) val inc = Input(Bool()) }) require(w > 0) val numLCG16s : Int = (w+15)/16 val outs = Seq.fill(numLCG16s) { LCG16(io.inc) } io.out := Cat(outs) } object LCG16 { def apply(inc: Bool = true.B): UInt = { val lcg = Module(new LCG16) lcg.io.inc := inc lcg.io.out } } object LCG { def apply(w: Int, inc: Bool = true.B): UInt = { val lcg = Module(new LCG(w)) lcg.io.inc := inc lcg.io.out } }
module LCG16( // @[LCG.scala:15:7] input clock, // @[LCG.scala:15:7] input reset, // @[LCG.scala:15:7] output [15:0] io_out // @[LCG.scala:16:14] ); wire io_inc = 1'h1; // @[LCG.scala:15:7, :16:14] wire [15:0] _io_out_T; // @[LCG.scala:24:18] wire [15:0] io_out_0; // @[LCG.scala:15:7] reg [31:0] state; // @[LCG.scala:20:18] wire [63:0] _state_T = {32'h0, state} * 64'h41C64E6D; // @[LCG.scala:20:18, :22:20] wire [64:0] _state_T_1 = {1'h0, _state_T} + 65'h3039; // @[LCG.scala:22:{20,41}] wire [63:0] _state_T_2 = _state_T_1[63:0]; // @[LCG.scala:22:41] assign _io_out_T = state[30:15]; // @[LCG.scala:20:18, :24:18] assign io_out_0 = _io_out_T; // @[LCG.scala:15:7, :24:18] always @(posedge clock) // @[LCG.scala:15:7] state <= _state_T_2[31:0]; // @[LCG.scala:20:18, :22:{11,41}] assign io_out = io_out_0; // @[LCG.scala:15:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_209( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_472( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_216 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ListBuffer.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean) { val queueBits = log2Up(queues) val entryBits = log2Up(entries) } class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle { val index = UInt(params.queueBits.W) val data = Output(params.gen) } class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module { override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}" val io = IO(new Bundle { // push is visible on the same cycle; flow queues val push = Flipped(Decoupled(new ListBufferPush(params))) val valid = UInt(params.queues.W) val pop = Flipped(Valid(UInt(params.queueBits.W))) val data = Output(params.gen) }) val valid = RegInit(0.U(params.queues.W)) val head = Mem(params.queues, UInt(params.entryBits.W)) val tail = Mem(params.queues, UInt(params.entryBits.W)) val used = RegInit(0.U(params.entries.W)) val next = Mem(params.entries, UInt(params.entryBits.W)) val data = Mem(params.entries, params.gen) val freeOH = ~(leftOR(~used) << 1) & ~used val freeIdx = OHToUInt(freeOH) val valid_set = WireDefault(0.U(params.queues.W)) val valid_clr = WireDefault(0.U(params.queues.W)) val used_set = WireDefault(0.U(params.entries.W)) val used_clr = WireDefault(0.U(params.entries.W)) val push_tail = tail.read(io.push.bits.index) val push_valid = valid(io.push.bits.index) io.push.ready := !used.andR when (io.push.fire) { valid_set := UIntToOH(io.push.bits.index, params.queues) used_set := freeOH data.write(freeIdx, io.push.bits.data) when (push_valid) { next.write(push_tail, freeIdx) } .otherwise { head.write(io.push.bits.index, freeIdx) } tail.write(io.push.bits.index, freeIdx) } val pop_head = head.read(io.pop.bits) val pop_valid = valid(io.pop.bits) // Bypass push data to the peek port io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head))) io.valid := (if (!params.bypass) valid else (valid | valid_set)) // It is an error to pop something that is not valid assert (!io.pop.fire || (io.valid)(io.pop.bits)) when (io.pop.fire) { used_clr := UIntToOH(pop_head, params.entries) when (pop_head === tail.read(io.pop.bits)) { valid_clr := UIntToOH(io.pop.bits, params.queues) } head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head))) } // Empty bypass changes no state when ((!params.bypass).B || !io.pop.valid || pop_valid) { used := (used & ~used_clr) | used_set valid := (valid & ~valid_clr) | valid_set } }
module ListBuffer_QueuedRequest_q66_e22( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input [6:0] io_push_bits_index, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_0, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_2, // @[ListBuffer.scala:39:14] input io_push_bits_data_control, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_opcode, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_param, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_size, // @[ListBuffer.scala:39:14] input [7:0] io_push_bits_data_source, // @[ListBuffer.scala:39:14] input [12:0] io_push_bits_data_tag, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_offset, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_put, // @[ListBuffer.scala:39:14] output [65:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input [6:0] io_pop_bits, // @[ListBuffer.scala:39:14] output io_data_prio_0, // @[ListBuffer.scala:39:14] output io_data_prio_1, // @[ListBuffer.scala:39:14] output io_data_prio_2, // @[ListBuffer.scala:39:14] output io_data_control, // @[ListBuffer.scala:39:14] output [2:0] io_data_opcode, // @[ListBuffer.scala:39:14] output [2:0] io_data_param, // @[ListBuffer.scala:39:14] output [2:0] io_data_size, // @[ListBuffer.scala:39:14] output [7:0] io_data_source, // @[ListBuffer.scala:39:14] output [12:0] io_data_tag, // @[ListBuffer.scala:39:14] output [5:0] io_data_offset, // @[ListBuffer.scala:39:14] output [5:0] io_data_put // @[ListBuffer.scala:39:14] ); wire [45:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [4:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [4:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [4:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [4:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7] wire [6:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_0_0 = io_push_bits_data_prio_0; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_2_0 = io_push_bits_data_prio_2; // @[ListBuffer.scala:36:7] wire io_push_bits_data_control_0 = io_push_bits_data_control; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_opcode_0 = io_push_bits_data_opcode; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_param_0 = io_push_bits_data_param; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_size_0 = io_push_bits_data_size; // @[ListBuffer.scala:36:7] wire [7:0] io_push_bits_data_source_0 = io_push_bits_data_source; // @[ListBuffer.scala:36:7] wire [12:0] io_push_bits_data_tag_0 = io_push_bits_data_tag; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_data_offset_0 = io_push_bits_data_offset; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_data_put_0 = io_push_bits_data_put; // @[ListBuffer.scala:36:7] wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7] wire [6:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_1 = 1'h0; // @[ListBuffer.scala:36:7] wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20] wire [6:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49] wire [6:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49] wire io_push_ready_0; // @[ListBuffer.scala:36:7] wire io_data_prio_0_0; // @[ListBuffer.scala:36:7] wire io_data_prio_1_0; // @[ListBuffer.scala:36:7] wire io_data_prio_2_0; // @[ListBuffer.scala:36:7] wire io_data_control_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_opcode_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_param_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_size_0; // @[ListBuffer.scala:36:7] wire [7:0] io_data_source_0; // @[ListBuffer.scala:36:7] wire [12:0] io_data_tag_0; // @[ListBuffer.scala:36:7] wire [5:0] io_data_offset_0; // @[ListBuffer.scala:36:7] wire [5:0] io_data_put_0; // @[ListBuffer.scala:36:7] wire [65:0] io_valid_0; // @[ListBuffer.scala:36:7] reg [65:0] valid; // @[ListBuffer.scala:47:22] assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22] reg [21:0] used; // @[ListBuffer.scala:50:22] assign io_data_prio_0_0 = _data_ext_R0_data[0]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_prio_1_0 = _data_ext_R0_data[1]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_prio_2_0 = _data_ext_R0_data[2]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_control_0 = _data_ext_R0_data[3]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_opcode_0 = _data_ext_R0_data[6:4]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_param_0 = _data_ext_R0_data[9:7]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_size_0 = _data_ext_R0_data[12:10]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_source_0 = _data_ext_R0_data[20:13]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_tag_0 = _data_ext_R0_data[33:21]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_offset_0 = _data_ext_R0_data[39:34]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_put_0 = _data_ext_R0_data[45:40]; // @[ListBuffer.scala:36:7, :52:18] wire [21:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [22:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [21:0] _freeOH_T_2 = _freeOH_T_1[21:0]; // @[package.scala:253:{48,53}] wire [21:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}] wire [23:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [21:0] _freeOH_T_5 = _freeOH_T_4[21:0]; // @[package.scala:253:{48,53}] wire [21:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}] wire [25:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [21:0] _freeOH_T_8 = _freeOH_T_7[21:0]; // @[package.scala:253:{48,53}] wire [21:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}] wire [29:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [21:0] _freeOH_T_11 = _freeOH_T_10[21:0]; // @[package.scala:253:{48,53}] wire [21:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}] wire [37:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [21:0] _freeOH_T_14 = _freeOH_T_13[21:0]; // @[package.scala:253:{48,53}] wire [21:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}] wire [21:0] _freeOH_T_16 = _freeOH_T_15; // @[package.scala:253:43, :254:17] wire [22:0] _freeOH_T_17 = {_freeOH_T_16, 1'h0}; // @[package.scala:254:17] wire [22:0] _freeOH_T_18 = ~_freeOH_T_17; // @[ListBuffer.scala:54:{16,32}] wire [21:0] _freeOH_T_19 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}] wire [22:0] freeOH = {1'h0, _freeOH_T_18[21:0] & _freeOH_T_19}; // @[ListBuffer.scala:54:{16,38,40}] wire [6:0] freeIdx_hi = freeOH[22:16]; // @[OneHot.scala:30:18] wire [15:0] freeIdx_lo = freeOH[15:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_1 = {9'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_1 = _freeIdx_T_1[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_1 = _freeIdx_T_1[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_2 = _freeIdx_T_3[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_2 = _freeIdx_T_3[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_3 = _freeIdx_T_5[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_3 = _freeIdx_T_5[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_8 = _freeIdx_T_7[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_9 = {_freeIdx_T_6, _freeIdx_T_8}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_10 = {_freeIdx_T_4, _freeIdx_T_9}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_11 = {_freeIdx_T_2, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [4:0] freeIdx = {_freeIdx_T, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [65:0] valid_set; // @[ListBuffer.scala:57:30] wire [65:0] valid_clr; // @[ListBuffer.scala:58:30] wire [21:0] used_set; // @[ListBuffer.scala:59:30] wire [21:0] used_clr; // @[ListBuffer.scala:60:30] wire [65:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25] wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25] wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26] assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}] assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20] wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35] wire [127:0] _valid_set_T = 128'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [65:0] _valid_set_T_1 = _valid_set_T[65:0]; // @[OneHot.scala:65:{12,27}] assign valid_set = data_MPORT_en ? _valid_set_T_1 : 66'h0; // @[OneHot.scala:65:27] assign used_set = data_MPORT_en ? freeOH[21:0] : 22'h0; // @[Decoupled.scala:51:35] wire [65:0] _GEN = {59'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24] wire [65:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24] wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24]
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File Counters.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ // Produces 0-width value when counting to 1 class ZCounter(val n: Int) { val value = RegInit(0.U(log2Ceil(n).W)) def inc(): Bool = { if (n == 1) true.B else { val wrap = value === (n-1).U value := Mux(!isPow2(n).B && wrap, 0.U, value + 1.U) wrap } } } object ZCounter { def apply(n: Int) = new ZCounter(n) def apply(cond: Bool, n: Int): (UInt, Bool) = { val c = new ZCounter(n) var wrap: Bool = null when (cond) { wrap = c.inc() } (c.value, cond && wrap) } } object TwoWayCounter { def apply(up: Bool, down: Bool, max: Int): UInt = { val cnt = RegInit(0.U(log2Up(max + 1).W)) when (up && !down) { cnt := cnt + 1.U } when (down && !up) { cnt := cnt - 1.U } cnt } } // a counter that clock gates most of its MSBs using the LSB carry-out case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true, inhibit: Bool = false.B) { private val isWide = width > (2 * inc.getWidth) private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width private val small = if (reset) RegInit(0.U(smallWidth.W)) else Reg(UInt(smallWidth.W)) private val nextSmall = small +& inc when (!inhibit) { small := nextSmall } private val large = if (isWide) { val r = if (reset) RegInit(0.U((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) when (nextSmall(smallWidth) && !inhibit) { r := r + 1.U } r } else null val value = if (isWide) Cat(large, small) else small lazy val carryOut = { val lo = (small ^ nextSmall) >> 1 if (!isWide) lo else { val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 Cat(hi, lo) } } def := (x: UInt) = { small := x if (isWide) large := x >> smallWidth } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr | (mask >> 1), ~(~addr | mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0) msbsLess || (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound || straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r || ignore) cur.cfg.w := aligned && (pmp.cfg.w || ignore) cur.cfg.x := aligned && (pmp.cfg.x || ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill when (!vill || ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill || useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt | supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts | (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) | io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined || usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U | (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu) val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) && (!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) && (!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) || usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal || !csr_exists || ((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) || is_counter && !allow_counter || decodeFast(debug_csrs.keys.toList) && !reg_debug || decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal || io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr | (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv || is_wfi && !allow_wfi || is_ret && !allow_sret || is_ret && addr(10) && addr(7) && !reg_debug || (is_sfence || is_hfence_gvma) && !allow_sfence_vma || is_hfence_vvma && !allow_hfence_vvma || is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U || is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) || CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) || addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma || is_hfence_gvma || is_hlsv || is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) || is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) || is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt || trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call || insn_break || insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call || insn_break || io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) || exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep || io.retire <= 1.U) assert(!reg_singleStepped || io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe | (if (usingCompressed && !coreParams.misaWritable) 0 else 1) | (if (usingUser) 0x100 else 0) | (if (usingSupervisor) 0x200 else 0) | (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi || io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags | io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */ val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U } when (mode_ok || !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain) bp.control.dmode := dMode when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) | (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) | (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U || t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }
module CSRFile_3( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_interrupts_seip, // @[CSR.scala:384:14] input [2:0] io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [63:0] io_rw_rdata, // @[CSR.scala:384:14] input [63:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_fp_illegal, // @[CSR.scala:384:14] output io_decode_0_fp_csr, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_eret, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_cease, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [31:0] io_status_isa, // @[CSR.scala:384:14] output [1:0] io_status_dprv, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output [1:0] io_status_prv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_sd, // @[CSR.scala:384:14] output io_status_mpv, // @[CSR.scala:384:14] output io_status_gva, // @[CSR.scala:384:14] output io_status_tsr, // @[CSR.scala:384:14] output io_status_tw, // @[CSR.scala:384:14] output io_status_tvm, // @[CSR.scala:384:14] output io_status_mxr, // @[CSR.scala:384:14] output io_status_sum, // @[CSR.scala:384:14] output io_status_mprv, // @[CSR.scala:384:14] output [1:0] io_status_fs, // @[CSR.scala:384:14] output [1:0] io_status_mpp, // @[CSR.scala:384:14] output io_status_spp, // @[CSR.scala:384:14] output io_status_mpie, // @[CSR.scala:384:14] output io_status_spie, // @[CSR.scala:384:14] output io_status_mie, // @[CSR.scala:384:14] output io_status_sie, // @[CSR.scala:384:14] output io_hstatus_spvp, // @[CSR.scala:384:14] output io_hstatus_spv, // @[CSR.scala:384:14] output io_hstatus_gva, // @[CSR.scala:384:14] output io_gstatus_debug, // @[CSR.scala:384:14] output io_gstatus_cease, // @[CSR.scala:384:14] output io_gstatus_wfi, // @[CSR.scala:384:14] output [31:0] io_gstatus_isa, // @[CSR.scala:384:14] output [1:0] io_gstatus_dprv, // @[CSR.scala:384:14] output io_gstatus_dv, // @[CSR.scala:384:14] output [1:0] io_gstatus_prv, // @[CSR.scala:384:14] output io_gstatus_v, // @[CSR.scala:384:14] output io_gstatus_sd, // @[CSR.scala:384:14] output [22:0] io_gstatus_zero2, // @[CSR.scala:384:14] output io_gstatus_mpv, // @[CSR.scala:384:14] output io_gstatus_gva, // @[CSR.scala:384:14] output io_gstatus_mbe, // @[CSR.scala:384:14] output io_gstatus_sbe, // @[CSR.scala:384:14] output [1:0] io_gstatus_sxl, // @[CSR.scala:384:14] output [7:0] io_gstatus_zero1, // @[CSR.scala:384:14] output io_gstatus_tsr, // @[CSR.scala:384:14] output io_gstatus_tw, // @[CSR.scala:384:14] output io_gstatus_tvm, // @[CSR.scala:384:14] output io_gstatus_mxr, // @[CSR.scala:384:14] output io_gstatus_sum, // @[CSR.scala:384:14] output io_gstatus_mprv, // @[CSR.scala:384:14] output [1:0] io_gstatus_fs, // @[CSR.scala:384:14] output [1:0] io_gstatus_mpp, // @[CSR.scala:384:14] output [1:0] io_gstatus_vs, // @[CSR.scala:384:14] output io_gstatus_spp, // @[CSR.scala:384:14] output io_gstatus_mpie, // @[CSR.scala:384:14] output io_gstatus_ube, // @[CSR.scala:384:14] output io_gstatus_spie, // @[CSR.scala:384:14] output io_gstatus_upie, // @[CSR.scala:384:14] output io_gstatus_mie, // @[CSR.scala:384:14] output io_gstatus_hie, // @[CSR.scala:384:14] output io_gstatus_sie, // @[CSR.scala:384:14] output io_gstatus_uie, // @[CSR.scala:384:14] output [3:0] io_ptbr_mode, // @[CSR.scala:384:14] output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14] output [39:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input io_retire, // @[CSR.scala:384:14] input [63:0] io_cause, // @[CSR.scala:384:14] input [39:0] io_pc, // @[CSR.scala:384:14] input [39:0] io_tval, // @[CSR.scala:384:14] input [39:0] io_htval, // @[CSR.scala:384:14] input io_mhtinst_read_pseudo, // @[CSR.scala:384:14] input io_gva, // @[CSR.scala:384:14] output [63:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] input io_fcsr_flags_valid, // @[CSR.scala:384:14] input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [63:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_bp_0_control_dmode, // @[CSR.scala:384:14] output io_bp_0_control_action, // @[CSR.scala:384:14] output [1:0] io_bp_0_control_tmatch, // @[CSR.scala:384:14] output io_bp_0_control_m, // @[CSR.scala:384:14] output io_bp_0_control_s, // @[CSR.scala:384:14] output io_bp_0_control_u, // @[CSR.scala:384:14] output io_bp_0_control_x, // @[CSR.scala:384:14] output io_bp_0_control_w, // @[CSR.scala:384:14] output io_bp_0_control_r, // @[CSR.scala:384:14] output [38:0] io_bp_0_address, // @[CSR.scala:384:14] output [47:0] io_bp_0_textra_pad2, // @[CSR.scala:384:14] output io_bp_0_textra_pad1, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output io_inhibit_cycle, // @[CSR.scala:384:14] input [31:0] io_inst_0, // @[CSR.scala:384:14] output io_trace_0_valid, // @[CSR.scala:384:14] output [39:0] io_trace_0_iaddr, // @[CSR.scala:384:14] output [31:0] io_trace_0_insn, // @[CSR.scala:384:14] output [2:0] io_trace_0_priv, // @[CSR.scala:384:14] output io_trace_0_exception, // @[CSR.scala:384:14] output io_trace_0_interrupt, // @[CSR.scala:384:14] output [63:0] io_trace_0_cause, // @[CSR.scala:384:14] output [39:0] io_trace_0_tval, // @[CSR.scala:384:14] output io_customCSRs_0_ren, // @[CSR.scala:384:14] output io_customCSRs_0_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14] output io_customCSRs_1_ren, // @[CSR.scala:384:14] output io_customCSRs_1_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_value, // @[CSR.scala:384:14] output io_customCSRs_2_ren, // @[CSR.scala:384:14] output io_customCSRs_2_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_2_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_2_value, // @[CSR.scala:384:14] output io_customCSRs_3_ren, // @[CSR.scala:384:14] output io_customCSRs_3_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_3_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_3_value // @[CSR.scala:384:14] ); wire io_status_sie_0; // @[CSR.scala:377:7] wire io_status_spie_0; // @[CSR.scala:377:7] wire io_status_spp_0; // @[CSR.scala:377:7] wire [1:0] io_status_fs_0; // @[CSR.scala:377:7] wire io_status_sum_0; // @[CSR.scala:377:7] wire io_status_mxr_0; // @[CSR.scala:377:7] wire io_status_sd_0; // @[CSR.scala:377:7] wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7] wire [2:0] io_hartid_0 = io_hartid; // @[CSR.scala:377:7] wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7] wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7] wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7] wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7] wire io_exception_0 = io_exception; // @[CSR.scala:377:7] wire io_retire_0 = io_retire; // @[CSR.scala:377:7] wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7] wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7] wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7] wire [39:0] io_htval_0 = io_htval; // @[CSR.scala:377:7] wire io_mhtinst_read_pseudo_0 = io_mhtinst_read_pseudo; // @[CSR.scala:377:7] wire io_gva_0 = io_gva; // @[CSR.scala:377:7] wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7] wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7] wire [31:0] io_inst_0_0 = io_inst_0; // @[CSR.scala:377:7] wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire sup_meip = 1'h1; // @[CSR.scala:406:19] wire sup_seip = 1'h1; // @[CSR.scala:406:19] wire sup_mtip = 1'h1; // @[CSR.scala:406:19] wire sup_stip = 1'h1; // @[CSR.scala:406:19] wire sup_msip = 1'h1; // @[CSR.scala:406:19] wire sup_ssip = 1'h1; // @[CSR.scala:406:19] wire del_seip = 1'h1; // @[CSR.scala:426:26] wire del_stip = 1'h1; // @[CSR.scala:426:26] wire del_ssip = 1'h1; // @[CSR.scala:426:26] wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31] wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30] wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109] wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50] wire allow_hlsv = 1'h1; // @[CSR.scala:909:43] wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45] wire _io_decode_0_fp_illegal_T_1 = 1'h1; // @[CSR.scala:915:83] wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43] wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87] wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51] wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95] wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71] wire delegable_1 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71] wire delegable_5 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71] wire delegable_9 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71] wire delegable_16 = 1'h1; // @[CSR.scala:1109:67] wire delegable_18 = 1'h1; // @[CSR.scala:1109:67] wire delegable_19 = 1'h1; // @[CSR.scala:1109:67] wire delegable_20 = 1'h1; // @[CSR.scala:1109:67] wire delegable_22 = 1'h1; // @[CSR.scala:1109:67] wire delegable_24 = 1'h1; // @[CSR.scala:1109:67] wire delegable_27 = 1'h1; // @[CSR.scala:1109:67] wire delegable_28 = 1'h1; // @[CSR.scala:1109:67] wire delegable_29 = 1'h1; // @[CSR.scala:1109:67] wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59] wire _dMode_T_1 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_2 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_0_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _dMode_T_4 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_5 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_1_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30] wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] io_gstatus_zero2_0 = 23'h0; // @[CSR.scala:377:7] wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47] wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34] wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48] wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35] wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7] wire io_rw_stall = 1'h0; // @[CSR.scala:377:7] wire io_status_mbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_status_ube = 1'h0; // @[CSR.scala:377:7] wire io_status_upie = 1'h0; // @[CSR.scala:377:7] wire io_status_hie = 1'h0; // @[CSR.scala:377:7] wire io_status_uie = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_debug_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_cease_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_wfi_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_dv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_v_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_gva_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tsr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tw_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tvm_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mxr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sum_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mprv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_ube_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_upie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_hie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_uie_0 = 1'h0; // @[CSR.scala:377:7] wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_chain = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_h = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_mselect = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_pad1_0 = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_sselect = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_set = 1'h0; // @[CSR.scala:377:7] wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47] wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34] wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44] wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31] wire sup_zero1 = 1'h0; // @[CSR.scala:406:19] wire sup_debug = 1'h0; // @[CSR.scala:406:19] wire sup_rocc = 1'h0; // @[CSR.scala:406:19] wire sup_sgeip = 1'h0; // @[CSR.scala:406:19] wire sup_vseip = 1'h0; // @[CSR.scala:406:19] wire sup_ueip = 1'h0; // @[CSR.scala:406:19] wire sup_vstip = 1'h0; // @[CSR.scala:406:19] wire sup_utip = 1'h0; // @[CSR.scala:406:19] wire sup_vssip = 1'h0; // @[CSR.scala:406:19] wire sup_usip = 1'h0; // @[CSR.scala:406:19] wire del_zero1 = 1'h0; // @[CSR.scala:426:26] wire del_debug = 1'h0; // @[CSR.scala:426:26] wire del_rocc = 1'h0; // @[CSR.scala:426:26] wire del_sgeip = 1'h0; // @[CSR.scala:426:26] wire del_meip = 1'h0; // @[CSR.scala:426:26] wire del_vseip = 1'h0; // @[CSR.scala:426:26] wire del_ueip = 1'h0; // @[CSR.scala:426:26] wire del_mtip = 1'h0; // @[CSR.scala:426:26] wire del_vstip = 1'h0; // @[CSR.scala:426:26] wire del_utip = 1'h0; // @[CSR.scala:426:26] wire del_msip = 1'h0; // @[CSR.scala:426:26] wire del_vssip = 1'h0; // @[CSR.scala:426:26] wire del_usip = 1'h0; // @[CSR.scala:426:26] wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10] wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50] wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42] wire always_zero1 = 1'h0; // @[CSR.scala:471:29] wire always_debug = 1'h0; // @[CSR.scala:471:29] wire always_rocc = 1'h0; // @[CSR.scala:471:29] wire always_sgeip = 1'h0; // @[CSR.scala:471:29] wire always_meip = 1'h0; // @[CSR.scala:471:29] wire always_vseip = 1'h0; // @[CSR.scala:471:29] wire always_seip = 1'h0; // @[CSR.scala:471:29] wire always_ueip = 1'h0; // @[CSR.scala:471:29] wire always_mtip = 1'h0; // @[CSR.scala:471:29] wire always_vstip = 1'h0; // @[CSR.scala:471:29] wire always_stip = 1'h0; // @[CSR.scala:471:29] wire always_utip = 1'h0; // @[CSR.scala:471:29] wire always_msip = 1'h0; // @[CSR.scala:471:29] wire always_vssip = 1'h0; // @[CSR.scala:471:29] wire always_ssip = 1'h0; // @[CSR.scala:471:29] wire always_usip = 1'h0; // @[CSR.scala:471:29] wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28] wire deleg_debug = 1'h0; // @[CSR.scala:476:28] wire deleg_rocc = 1'h0; // @[CSR.scala:476:28] wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28] wire deleg_meip = 1'h0; // @[CSR.scala:476:28] wire deleg_vseip = 1'h0; // @[CSR.scala:476:28] wire deleg_seip = 1'h0; // @[CSR.scala:476:28] wire deleg_ueip = 1'h0; // @[CSR.scala:476:28] wire deleg_mtip = 1'h0; // @[CSR.scala:476:28] wire deleg_vstip = 1'h0; // @[CSR.scala:476:28] wire deleg_stip = 1'h0; // @[CSR.scala:476:28] wire deleg_utip = 1'h0; // @[CSR.scala:476:28] wire deleg_msip = 1'h0; // @[CSR.scala:476:28] wire deleg_vssip = 1'h0; // @[CSR.scala:476:28] wire deleg_ssip = 1'h0; // @[CSR.scala:476:28] wire deleg_usip = 1'h0; // @[CSR.scala:476:28] wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12] wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27] wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48] wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48] wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35] wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35] wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41] wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41] wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41] wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41] wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27] wire mip_zero1 = 1'h0; // @[CSR.scala:600:24] wire mip_debug = 1'h0; // @[CSR.scala:600:24] wire mip_rocc = 1'h0; // @[CSR.scala:600:24] wire mip_sgeip = 1'h0; // @[CSR.scala:600:24] wire mip_vseip = 1'h0; // @[CSR.scala:600:24] wire mip_ueip = 1'h0; // @[CSR.scala:600:24] wire mip_vstip = 1'h0; // @[CSR.scala:600:24] wire mip_utip = 1'h0; // @[CSR.scala:600:24] wire mip_vssip = 1'h0; // @[CSR.scala:600:24] wire mip_usip = 1'h0; // @[CSR.scala:600:24] wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76] wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91] wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131] wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62] wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47] wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47] wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44] wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44] wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31] wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43] wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59] wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48] wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35] wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59] wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_2 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_3 = 1'h0; // @[CSR.scala:801:16] wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8] wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116] wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74] wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43] wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33] wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37] wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34] wire trapToNmi = 1'h0; // @[CSR.scala:992:32] wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21] wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58] wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53] wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74] wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39] wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56] wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40] wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24] wire en = 1'h0; // @[CSR.scala:1096:79] wire delegable = 1'h0; // @[CSR.scala:1097:65] wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24] wire en_2 = 1'h0; // @[CSR.scala:1096:79] wire delegable_2 = 1'h0; // @[CSR.scala:1097:65] wire delegable_3 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24] wire en_4 = 1'h0; // @[CSR.scala:1096:79] wire delegable_4 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24] wire en_6 = 1'h0; // @[CSR.scala:1096:79] wire delegable_6 = 1'h0; // @[CSR.scala:1097:65] wire delegable_7 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24] wire en_8 = 1'h0; // @[CSR.scala:1096:79] wire delegable_8 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24] wire en_10 = 1'h0; // @[CSR.scala:1096:79] wire delegable_10 = 1'h0; // @[CSR.scala:1097:65] wire delegable_11 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24] wire en_12 = 1'h0; // @[CSR.scala:1096:79] wire delegable_12 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24] wire en_13 = 1'h0; // @[CSR.scala:1096:79] wire delegable_13 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24] wire en_14 = 1'h0; // @[CSR.scala:1096:79] wire delegable_14 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24] wire en_15 = 1'h0; // @[CSR.scala:1096:79] wire delegable_15 = 1'h0; // @[CSR.scala:1097:65] wire delegable_17 = 1'h0; // @[CSR.scala:1109:67] wire delegable_21 = 1'h0; // @[CSR.scala:1109:67] wire delegable_23 = 1'h0; // @[CSR.scala:1109:67] wire delegable_25 = 1'h0; // @[CSR.scala:1109:67] wire delegable_26 = 1'h0; // @[CSR.scala:1109:67] wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44] wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42] wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56] wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42] wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82] wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62] wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35] wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29] wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42] wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61] wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_23 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_24 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_25 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_26 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_27 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73] wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33] wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59] wire _reg_bp_0_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_0_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_0_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_0_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_1_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_1_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_1_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] io_gstatus_zero1_0 = 8'h0; // @[CSR.scala:377:7] wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47] wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34] wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59] wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48] wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35] wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_dprv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_prv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_sxl_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_fs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_mpp_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_vs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_zero = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47] wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34] wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44] wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31] wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31] wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48] wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41] wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41] wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41] wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41] wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27] wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44] wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22] wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49] wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48] wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_xs = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_vs = 2'h0; // @[CSR.scala:755:35] wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49] wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59] wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59] wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36] wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36] wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62] wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] newBPC_lo_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_lo_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_hi_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7] wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41] wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59] wire [29:0] _io_rw_rdata_T_137 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_138 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_139 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_140 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_141 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_142 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_143 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73] wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7] wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41] wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51] wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7] wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41] wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51] wire [5:0] newBPC_hi_lo_1 = 6'h0; // @[CSR.scala:1477:67] wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7] wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41] wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36] wire [4:0] newBPC_hi_hi_hi_1 = 5'h0; // @[CSR.scala:1477:67] wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12] wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27] wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34] wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27] wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_17 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_21 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_23 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_26 = 16'h0; // @[CSR.scala:1109:45] wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10] wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] lo_hi_lo_lo = 4'h0; // @[CSR.scala:768:51] wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51] wire [3:0] newBPC_lo_hi_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] newBPC_hi_lo_lo_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [3:0] io_bp_0_control_ttype = 4'h2; // @[CSR.scala:377:7] wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[CSR.scala:377:7] wire [39:0] io_bp_0_control_reserved = 40'h0; // @[CSR.scala:377:7] wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14] wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14] wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26] wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15] wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153] wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26] wire [63:0] _io_rw_rdata_T_128 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _newBPC_T_24 = 64'h0; // @[CSR.scala:1477:67] wire [63:0] _newBPC_T_26 = 64'h0; // @[CSR.scala:1643:9] wire [63:0] _reg_custom_1_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_2_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_3_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_2_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_3_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49] wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49] wire [56:0] newBPC_hi_1 = 57'h0; // @[CSR.scala:1477:67] wire [50:0] newBPC_hi_hi_1 = 51'h0; // @[CSR.scala:1477:67] wire [45:0] newBPC_hi_hi_lo_1 = 46'h0; // @[CSR.scala:1477:67] wire [6:0] newBPC_lo_1 = 7'h0; // @[CSR.scala:1477:67] wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44] wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31] wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48] wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35] wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41] wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41] wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41] wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44] wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31] wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49] wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51] wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49] wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36] wire [2:0] newBPC_lo_lo_1 = 3'h0; // @[CSR.scala:1477:67] wire [45:0] read_mapping_hi_hi_lo = 46'h40000000000; // @[CSR.scala:655:48] wire [45:0] newBPC_hi_hi_lo = 46'h40000000000; // @[CSR.scala:1477:67] wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49] wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49] wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31] wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35] wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31] wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70] wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27] wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32] wire [47:0] io_bp_0_textra_pad2_0 = 48'h0; // @[CSR.scala:377:7] wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46] wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35] wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168] wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_2_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_3_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_2_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_3_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1531:41] wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78] wire [63:0] _reg_misa_T_6 = 64'hFFFFFFFFFFFFEFD2; // @[CSR.scala:1263:75] wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59] wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46] wire [15:0] _delegable_T_27 = 16'h1000; // @[CSR.scala:1109:45] wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_19 = 16'h8; // @[CSR.scala:1109:45] wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120] wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120] wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120] wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120] wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120] wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49] wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120] wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43] wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120] wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120] wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120] wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49] wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120] wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43] wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120] wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120] wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120] wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120] wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43] wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120] wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39] wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120] wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39] wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120] wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [31:0] io_gstatus_isa_0 = 32'h0; // @[CSR.scala:377:7] wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47] wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34] wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14] wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46] wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48] wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35] wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59] wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27] wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27] wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51] wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51] wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51] wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51] wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70] wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32] wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51] wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20] wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59] wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31] wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59] wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41] wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41] wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41] wire [15:0] delegable_interrupts = 16'h222; // @[CSR.scala:431:50] wire [7:0] hi_1 = 8'h2; // @[CSR.scala:431:50] wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50] wire [15:0] supported_interrupts = 16'hAAA; // @[CSR.scala:431:17] wire [7:0] hi = 8'hA; // @[CSR.scala:431:10] wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10] wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10] wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10] wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10] wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44] wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31] wire [15:0] _delegable_T_28 = 16'h2000; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_24 = 16'h100; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_22 = 16'h40; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_20 = 16'h10; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_18 = 16'h4; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_16 = 16'h1; // @[CSR.scala:1109:45] wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120] wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120] wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120] wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120] wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120] wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120] wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120] wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120] wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120] wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120] wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120] wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120] wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120] wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120] wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120] wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50] wire [15:0] _delegable_T_29 = 16'h8000; // @[CSR.scala:1109:45] wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28] wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47] wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24] wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24] wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24] wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire [63:0] _newBPC_T_27 = io_rw_wdata_0; // @[CSR.scala:377:7, :1643:30] wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22] wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91] wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire _io_csr_stall_T; // @[CSR.scala:1161:27] wire _io_eret_T_1; // @[CSR.scala:1000:38] wire _io_singleStep_T_1; // @[CSR.scala:1001:34] wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24] wire _io_status_dv_T_3; // @[CSR.scala:1009:33] wire _io_status_sd_T_4; // @[CSR.scala:1003:58] wire read_sstatus_sd = io_status_sd_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35] wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35] wire _io_gstatus_sd_T_4; // @[CSR.scala:1016:61] wire _io_trace_0_valid_T = io_retire_0; // @[CSR.scala:377:7, :1621:26] wire [39:0] io_trace_0_iaddr_0 = io_pc_0; // @[CSR.scala:377:7] wire [39:0] io_trace_0_tval_0 = io_tval_0; // @[CSR.scala:377:7] wire [63:0] value_1; // @[Counters.scala:55:30] wire _io_interrupt_T_5; // @[CSR.scala:626:73] wire [63:0] interruptCause; // @[CSR.scala:625:63] wire pmp_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19] wire pmp_cfg_x; // @[PMP.scala:24:19] wire pmp_cfg_w; // @[PMP.scala:24:19] wire pmp_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_addr; // @[PMP.scala:24:19] wire [31:0] pmp_mask; // @[PMP.scala:24:19] wire pmp_1_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19] wire pmp_1_cfg_x; // @[PMP.scala:24:19] wire pmp_1_cfg_w; // @[PMP.scala:24:19] wire pmp_1_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_1_addr; // @[PMP.scala:24:19] wire [31:0] pmp_1_mask; // @[PMP.scala:24:19] wire pmp_2_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19] wire pmp_2_cfg_x; // @[PMP.scala:24:19] wire pmp_2_cfg_w; // @[PMP.scala:24:19] wire pmp_2_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_2_addr; // @[PMP.scala:24:19] wire [31:0] pmp_2_mask; // @[PMP.scala:24:19] wire pmp_3_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19] wire pmp_3_cfg_x; // @[PMP.scala:24:19] wire pmp_3_cfg_w; // @[PMP.scala:24:19] wire pmp_3_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_3_addr; // @[PMP.scala:24:19] wire [31:0] pmp_3_mask; // @[PMP.scala:24:19] wire pmp_4_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19] wire pmp_4_cfg_x; // @[PMP.scala:24:19] wire pmp_4_cfg_w; // @[PMP.scala:24:19] wire pmp_4_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_4_addr; // @[PMP.scala:24:19] wire [31:0] pmp_4_mask; // @[PMP.scala:24:19] wire pmp_5_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19] wire pmp_5_cfg_x; // @[PMP.scala:24:19] wire pmp_5_cfg_w; // @[PMP.scala:24:19] wire pmp_5_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_5_addr; // @[PMP.scala:24:19] wire [31:0] pmp_5_mask; // @[PMP.scala:24:19] wire pmp_6_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19] wire pmp_6_cfg_x; // @[PMP.scala:24:19] wire pmp_6_cfg_w; // @[PMP.scala:24:19] wire pmp_6_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_6_addr; // @[PMP.scala:24:19] wire [31:0] pmp_6_mask; // @[PMP.scala:24:19] wire pmp_7_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19] wire pmp_7_cfg_x; // @[PMP.scala:24:19] wire pmp_7_cfg_w; // @[PMP.scala:24:19] wire pmp_7_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_7_addr; // @[PMP.scala:24:19] wire [31:0] pmp_7_mask; // @[PMP.scala:24:19] wire [31:0] _io_csrw_counter_T_11; // @[CSR.scala:1223:25] wire _io_inhibit_cycle_T; // @[CSR.scala:591:40] wire [31:0] io_trace_0_insn_0 = io_inst_0_0; // @[CSR.scala:377:7] wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18] wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25] wire [63:0] cause; // @[CSR.scala:959:8] wire _io_fiom_T_6; // @[CSR.scala:631:113] wire reg_custom_read; // @[CSR.scala:799:36] wire [63:0] wdata; // @[CSR.scala:1643:39] wire reg_custom_read_1; // @[CSR.scala:799:36] wire reg_custom_read_2; // @[CSR.scala:799:36] wire reg_custom_read_3; // @[CSR.scala:799:36] wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7] wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7] wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_flush_0; // @[CSR.scala:377:7] wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_status_debug_0; // @[CSR.scala:377:7] wire io_status_cease_0; // @[CSR.scala:377:7] wire io_status_wfi_0; // @[CSR.scala:377:7] wire [31:0] io_status_isa_0; // @[CSR.scala:377:7] wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7] wire io_status_dv_0; // @[CSR.scala:377:7] wire [1:0] io_status_prv_0; // @[CSR.scala:377:7] wire io_status_v_0; // @[CSR.scala:377:7] wire io_status_mpv_0; // @[CSR.scala:377:7] wire io_status_gva_0; // @[CSR.scala:377:7] wire io_status_tsr_0; // @[CSR.scala:377:7] wire io_status_tw_0; // @[CSR.scala:377:7] wire io_status_tvm_0; // @[CSR.scala:377:7] wire io_status_mprv_0; // @[CSR.scala:377:7] wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7] wire io_status_mpie_0; // @[CSR.scala:377:7] wire io_status_mie_0; // @[CSR.scala:377:7] wire io_hstatus_spvp_0; // @[CSR.scala:377:7] wire io_hstatus_spv_0; // @[CSR.scala:377:7] wire io_hstatus_gva_0; // @[CSR.scala:377:7] wire io_gstatus_sd_0; // @[CSR.scala:377:7] wire io_gstatus_spp_0; // @[CSR.scala:377:7] wire io_gstatus_spie_0; // @[CSR.scala:377:7] wire io_gstatus_sie_0; // @[CSR.scala:377:7] wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7] wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7] wire io_bp_0_control_dmode_0; // @[CSR.scala:377:7] wire io_bp_0_control_action_0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_tmatch_0; // @[CSR.scala:377:7] wire io_bp_0_control_m_0; // @[CSR.scala:377:7] wire io_bp_0_control_s_0; // @[CSR.scala:377:7] wire io_bp_0_control_u_0; // @[CSR.scala:377:7] wire io_bp_0_control_x_0; // @[CSR.scala:377:7] wire io_bp_0_control_w_0; // @[CSR.scala:377:7] wire io_bp_0_control_r_0; // @[CSR.scala:377:7] wire [38:0] io_bp_0_address_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7] wire io_trace_0_valid_0; // @[CSR.scala:377:7] wire [2:0] io_trace_0_priv_0; // @[CSR.scala:377:7] wire io_trace_0_exception_0; // @[CSR.scala:377:7] wire io_trace_0_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_trace_0_cause_0; // @[CSR.scala:377:7] wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7] wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7] wire io_customCSRs_2_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_2_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_value_0; // @[CSR.scala:377:7] wire io_customCSRs_3_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_3_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_value_0; // @[CSR.scala:377:7] wire io_csr_stall_0; // @[CSR.scala:377:7] wire io_eret_0; // @[CSR.scala:377:7] wire io_singleStep_0; // @[CSR.scala:377:7] wire [39:0] io_evec_0; // @[CSR.scala:377:7] wire [63:0] io_time_0; // @[CSR.scala:377:7] wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7] wire io_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7] wire [31:0] io_csrw_counter; // @[CSR.scala:377:7] wire io_inhibit_cycle_0; // @[CSR.scala:377:7] wire io_fiom; // @[CSR.scala:377:7] reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28] assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_v; // @[CSR.scala:395:28] assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28] wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] reg reg_mstatus_mpv; // @[CSR.scala:395:28] assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tsr; // @[CSR.scala:395:28] assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tw; // @[CSR.scala:395:28] assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tvm; // @[CSR.scala:395:28] assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mxr; // @[CSR.scala:395:28] assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sum; // @[CSR.scala:395:28] assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mprv; // @[CSR.scala:395:28] assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28] assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spp; // @[CSR.scala:395:28] assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spie; // @[CSR.scala:395:28] assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sie; // @[CSR.scala:395:28] assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28] wire [1:0] new_prv; // @[CSR.scala:397:28] wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35] wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg reg_dcsr_ebreaks; // @[CSR.scala:403:25] reg reg_dcsr_ebreaku; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26] reg [39:0] reg_dpc; // @[CSR.scala:483:20] reg [63:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_bp_0_control_dmode; // @[CSR.scala:492:19] assign io_bp_0_control_dmode_0 = reg_bp_0_control_dmode; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_action; // @[CSR.scala:492:19] assign io_bp_0_control_action_0 = reg_bp_0_control_action; // @[CSR.scala:377:7, :492:19] reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala:492:19] assign io_bp_0_control_tmatch_0 = reg_bp_0_control_tmatch; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_m; // @[CSR.scala:492:19] assign io_bp_0_control_m_0 = reg_bp_0_control_m; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_s; // @[CSR.scala:492:19] assign io_bp_0_control_s_0 = reg_bp_0_control_s; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_u; // @[CSR.scala:492:19] assign io_bp_0_control_u_0 = reg_bp_0_control_u; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_x; // @[CSR.scala:492:19] assign io_bp_0_control_x_0 = reg_bp_0_control_x; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_w; // @[CSR.scala:492:19] assign io_bp_0_control_w_0 = reg_bp_0_control_w; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_r; // @[CSR.scala:492:19] assign io_bp_0_control_r_0 = reg_bp_0_control_r; // @[CSR.scala:377:7, :492:19] reg [38:0] reg_bp_0_address; // @[CSR.scala:492:19] assign io_bp_0_address_0 = reg_bp_0_address; // @[CSR.scala:377:7, :492:19] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19] reg [63:0] reg_mie; // @[CSR.scala:495:20] reg [63:0] reg_mideleg; // @[CSR.scala:497:18] wire [63:0] read_mideleg = {54'h0, reg_mideleg[9:1] & 9'h111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}] reg [63:0] reg_medeleg; // @[CSR.scala:501:18] wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}] reg reg_mip_seip; // @[CSR.scala:504:20] reg reg_mip_stip; // @[CSR.scala:504:20] wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24] reg reg_mip_ssip; // @[CSR.scala:504:20] wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24] reg [39:0] reg_mepc; // @[CSR.scala:505:21] reg [63:0] reg_mcause; // @[CSR.scala:506:27] reg [39:0] reg_mtval; // @[CSR.scala:507:22] reg [39:0] reg_mtval2; // @[CSR.scala:508:23] reg [63:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] reg reg_menvcfg_fiom; // @[CSR.scala:525:28] reg reg_senvcfg_fiom; // @[CSR.scala:526:28] reg [31:0] reg_mcounteren; // @[CSR.scala:531:18] wire [31:0] read_mcounteren = {29'h0, reg_mcounteren[2:0]}; // @[CSR.scala:531:18, :532:{14,32}] reg [31:0] reg_scounteren; // @[CSR.scala:535:18] wire [31:0] read_scounteren = {29'h0, reg_scounteren[2:0]}; // @[CSR.scala:535:18, :536:{14,38}] reg reg_hstatus_spvp; // @[CSR.scala:552:28] assign io_hstatus_spvp_0 = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_spv; // @[CSR.scala:552:28] assign io_hstatus_spv_0 = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_gva; // @[CSR.scala:552:28] assign io_hstatus_gva_0 = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28] reg [39:0] reg_htval; // @[CSR.scala:554:22] wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27] assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59] assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27] assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59] assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27] assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27] wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59] assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27] wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27] wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27] reg reg_vsstatus_spp; // @[CSR.scala:562:25] assign io_gstatus_spp_0 = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_spie; // @[CSR.scala:562:25] assign io_gstatus_spie_0 = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_sie; // @[CSR.scala:562:25] assign io_gstatus_sie_0 = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25] reg [39:0] reg_vsepc; // @[CSR.scala:564:22] reg [63:0] reg_vscause; // @[CSR.scala:565:24] reg [39:0] reg_vstval; // @[CSR.scala:566:23] reg [39:0] reg_sepc; // @[CSR.scala:569:21] reg [63:0] reg_scause; // @[CSR.scala:570:23] reg [39:0] reg_stval; // @[CSR.scala:571:22] reg [63:0] reg_sscratch; // @[CSR.scala:572:25] reg [38:0] reg_stvec; // @[CSR.scala:573:22] reg [3:0] reg_satp_mode; // @[CSR.scala:574:21] assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21] reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21] assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21] reg reg_wfi; // @[CSR.scala:575:54] assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54] reg [4:0] reg_fflags; // @[CSR.scala:577:23] reg [2:0] reg_frm; // @[CSR.scala:578:20] assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20] reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35] reg reg_htinst_read_pseudo; // @[CSR.scala:585:35] wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103] wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103] wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103] wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103] reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34] assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40] wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98] assign io_inhibit_cycle_0 = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40] wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75] reg [5:0] small_0; // @[Counters.scala:45:41] wire [6:0] nextSmall = {1'h0, small_0} + {6'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33] wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36] reg [57:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56] reg [5:0] small_1; // @[Counters.scala:45:41] wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33] wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36] reg [57:0] large_1; // @[Counters.scala:50:31] wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55] assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] assign io_time_0 = value_1; // @[Counters.scala:55:30] wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22] wire _mip_seip_T; // @[CSR.scala:606:57] wire mip_seip; // @[CSR.scala:600:24] assign _mip_seip_T = reg_mip_seip | io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57] assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57] wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22] wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22] wire [15:0] read_mip = _read_mip_T & 16'hAAA; // @[CSR.scala:610:{22,29}] wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56] wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}] wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42] wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61] wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60] wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62] wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42] wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51] wire _m_interrupts_T_1 = _m_interrupts_T | reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}] wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}] wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85] wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 | read_mideleg; // @[CSR.scala:498:14, :620:{85,105}] wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}] wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}] wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68] wire _s_interrupts_T; // @[CSR.scala:621:68] assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68] wire _vs_interrupts_T; // @[CSR.scala:622:70] assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70] wire _io_fiom_T_2; // @[CSR.scala:631:82] assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82] wire _s_interrupts_T_1 = reg_mstatus_v | _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}] wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98] wire _s_interrupts_T_2; // @[CSR.scala:621:98] assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98] wire _vs_interrupts_T_1; // @[CSR.scala:622:99] assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99] wire _csr_addr_legal_T_4; // @[CSR.scala:921:62] assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62] wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}] wire _s_interrupts_T_4 = _s_interrupts_T_1 | _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}] wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}] wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151] wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}] wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}] wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}] wire _vs_interrupts_T_3 = _vs_interrupts_T | _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}] wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}] wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}] wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76] wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76] wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76] wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76] wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76] wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76] wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76] wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76] wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76] wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76] wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76] wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76] wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76] wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76] wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76] wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76] wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76] wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76] wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76] wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76] wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76] wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76] wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76] wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76] wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76] wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76] wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76] wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76] wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76] wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76] wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76] wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76] wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76] wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76] wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76] wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76] wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76] wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76] wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76] wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76] wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76] wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76] wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76] wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76] wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76] wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76] wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76] wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_63 = _any_T | _any_T_1; // @[CSR.scala:1637:{76,90}] wire _any_T_64 = _any_T_63 | _any_T_2; // @[CSR.scala:1637:{76,90}] wire _any_T_65 = _any_T_64 | _any_T_3; // @[CSR.scala:1637:{76,90}] wire _any_T_66 = _any_T_65 | _any_T_4; // @[CSR.scala:1637:{76,90}] wire _any_T_67 = _any_T_66 | _any_T_5; // @[CSR.scala:1637:{76,90}] wire _any_T_68 = _any_T_67 | _any_T_6; // @[CSR.scala:1637:{76,90}] wire _any_T_69 = _any_T_68 | _any_T_7; // @[CSR.scala:1637:{76,90}] wire _any_T_70 = _any_T_69 | _any_T_8; // @[CSR.scala:1637:{76,90}] wire _any_T_71 = _any_T_70 | _any_T_9; // @[CSR.scala:1637:{76,90}] wire _any_T_72 = _any_T_71 | _any_T_10; // @[CSR.scala:1637:{76,90}] wire _any_T_73 = _any_T_72 | _any_T_11; // @[CSR.scala:1637:{76,90}] wire _any_T_74 = _any_T_73 | _any_T_12; // @[CSR.scala:1637:{76,90}] wire _any_T_75 = _any_T_74 | _any_T_13; // @[CSR.scala:1637:{76,90}] wire _any_T_76 = _any_T_75 | _any_T_14; // @[CSR.scala:1637:{76,90}] wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90] wire _any_T_78 = _any_T_77 | _any_T_15; // @[CSR.scala:1637:{76,90}] wire _any_T_79 = _any_T_78 | _any_T_16; // @[CSR.scala:1637:{76,90}] wire _any_T_80 = _any_T_79 | _any_T_17; // @[CSR.scala:1637:{76,90}] wire _any_T_81 = _any_T_80 | _any_T_18; // @[CSR.scala:1637:{76,90}] wire _any_T_82 = _any_T_81 | _any_T_19; // @[CSR.scala:1637:{76,90}] wire _any_T_83 = _any_T_82 | _any_T_20; // @[CSR.scala:1637:{76,90}] wire _any_T_84 = _any_T_83 | _any_T_21; // @[CSR.scala:1637:{76,90}] wire _any_T_85 = _any_T_84 | _any_T_22; // @[CSR.scala:1637:{76,90}] wire _any_T_86 = _any_T_85 | _any_T_23; // @[CSR.scala:1637:{76,90}] wire _any_T_87 = _any_T_86 | _any_T_24; // @[CSR.scala:1637:{76,90}] wire _any_T_88 = _any_T_87 | _any_T_25; // @[CSR.scala:1637:{76,90}] wire _any_T_89 = _any_T_88 | _any_T_26; // @[CSR.scala:1637:{76,90}] wire _any_T_90 = _any_T_89 | _any_T_27; // @[CSR.scala:1637:{76,90}] wire _any_T_91 = _any_T_90 | _any_T_28; // @[CSR.scala:1637:{76,90}] wire _any_T_92 = _any_T_91 | _any_T_29; // @[CSR.scala:1637:{76,90}] wire _any_T_93 = _any_T_92 | _any_T_30; // @[CSR.scala:1637:{76,90}] wire _any_T_94 = _any_T_93 | _any_T_31; // @[CSR.scala:1637:{76,90}] wire _any_T_95 = _any_T_94 | _any_T_32; // @[CSR.scala:1637:{76,90}] wire _any_T_96 = _any_T_95 | _any_T_33; // @[CSR.scala:1637:{76,90}] wire _any_T_97 = _any_T_96 | _any_T_34; // @[CSR.scala:1637:{76,90}] wire _any_T_98 = _any_T_97 | _any_T_35; // @[CSR.scala:1637:{76,90}] wire _any_T_99 = _any_T_98 | _any_T_36; // @[CSR.scala:1637:{76,90}] wire _any_T_100 = _any_T_99 | _any_T_37; // @[CSR.scala:1637:{76,90}] wire _any_T_101 = _any_T_100 | _any_T_38; // @[CSR.scala:1637:{76,90}] wire _any_T_102 = _any_T_101 | _any_T_39; // @[CSR.scala:1637:{76,90}] wire _any_T_103 = _any_T_102 | _any_T_40; // @[CSR.scala:1637:{76,90}] wire _any_T_104 = _any_T_103 | _any_T_41; // @[CSR.scala:1637:{76,90}] wire _any_T_105 = _any_T_104 | _any_T_42; // @[CSR.scala:1637:{76,90}] wire _any_T_106 = _any_T_105 | _any_T_43; // @[CSR.scala:1637:{76,90}] wire _any_T_107 = _any_T_106 | _any_T_44; // @[CSR.scala:1637:{76,90}] wire _any_T_108 = _any_T_107 | _any_T_45; // @[CSR.scala:1637:{76,90}] wire _any_T_109 = _any_T_108 | _any_T_46; // @[CSR.scala:1637:{76,90}] wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90] wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90] wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90] wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90] wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90] wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90] wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90] wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90] wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90] wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90] wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90] wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90] wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90] wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90] wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90] wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90] wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70] wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70] wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70] wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70] wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70] wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70] wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70] wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70] wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70] wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70] wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70] wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70] wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70] wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70] wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70] wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70] wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70] wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70] wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70] wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70] wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70] wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70] wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70] wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70] wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70] wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70] wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70] wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70] wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70] wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70] wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70] wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70] wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70] wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70] wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70] wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70] wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70] wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70] wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70] wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70] wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70] wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70] wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70] wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70] wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70] wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70] wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70] wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70] assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63] assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63] wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36] wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90] wire _io_interrupt_T_2 = _io_interrupt_T_1 | reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}] wire _io_interrupt_T_3 = reg_debug | io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88] wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}] assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}] assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73] wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31] wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}] wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}] wire _io_fiom_T_4 = _io_fiom_T_1 | _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}] assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}] assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113] assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19] assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19] assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19] assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19] assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19] assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19] assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19] assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19] assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19] assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19] assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19] assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19] assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19] assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19] assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19] assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19] assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19] assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19] assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19] assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19] assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19] assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19] assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19] assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19] assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19] assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19] assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19] assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19] assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19] assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19] assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19] assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19] assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19] assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19] assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19] assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19] assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19] assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19] assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19] assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19] assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19] assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19] assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19] assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19] assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19] assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19] assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19] assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19] assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] reg [63:0] reg_misa; // @[CSR.scala:648:25] wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32] wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h0, io_status_fs_0}; // @[CSR.scala:377:7, :649:32] wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32] wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32] wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32] wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32] wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32] wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32] wire [23:0] read_mstatus_hi_hi_lo_lo = {io_status_sd_0, 23'h0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32] wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo}; // @[CSR.scala:649:32] wire [33:0] read_mstatus_hi_hi_hi_lo = {io_status_isa_0, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32] wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32] wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32] wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32] wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32] wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13] wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41] wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41] wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}] wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}] wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35] wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41] wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41] wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}] wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}] wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35] wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}] wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35] wire [1:0] _GEN_4 = {reg_bp_0_control_x, reg_bp_0_control_w}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_lo_hi; // @[CSR.scala:655:48] assign read_mapping_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_lo_hi; // @[CSR.scala:1477:67] assign newBPC_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48, :1477:67] wire [2:0] read_mapping_lo_lo = {read_mapping_lo_lo_hi, reg_bp_0_control_r}; // @[CSR.scala:492:19, :655:48] wire [1:0] _GEN_5 = {reg_bp_0_control_s, reg_bp_0_control_u}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_hi_lo; // @[CSR.scala:655:48] assign read_mapping_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_lo; // @[CSR.scala:1477:67] assign newBPC_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_6 = {reg_bp_0_control_m, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_hi_hi; // @[CSR.scala:655:48] assign read_mapping_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_hi; // @[CSR.scala:1477:67] assign newBPC_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48, :1477:67] wire [3:0] read_mapping_lo_hi = {read_mapping_lo_hi_hi, read_mapping_lo_hi_lo}; // @[CSR.scala:655:48] wire [6:0] read_mapping_lo = {read_mapping_lo_hi, read_mapping_lo_lo}; // @[CSR.scala:655:48] wire [3:0] _GEN_7 = {2'h0, reg_bp_0_control_tmatch}; // @[CSR.scala:492:19, :655:48] wire [3:0] read_mapping_hi_lo_lo; // @[CSR.scala:655:48] assign read_mapping_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48] wire [3:0] newBPC_hi_lo_lo; // @[CSR.scala:1477:67] assign newBPC_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_8 = {reg_bp_0_control_action, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_hi_lo_hi; // @[CSR.scala:655:48] assign read_mapping_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48] wire [1:0] newBPC_hi_lo_hi; // @[CSR.scala:1477:67] assign newBPC_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48, :1477:67] wire [5:0] read_mapping_hi_lo = {read_mapping_hi_lo_hi, read_mapping_hi_lo_lo}; // @[CSR.scala:655:48] wire [4:0] _GEN_9 = {4'h2, reg_bp_0_control_dmode}; // @[CSR.scala:492:19, :655:48] wire [4:0] read_mapping_hi_hi_hi; // @[CSR.scala:655:48] assign read_mapping_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48] wire [4:0] newBPC_hi_hi_hi; // @[CSR.scala:1477:67] assign newBPC_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48, :1477:67] wire [50:0] read_mapping_hi_hi = {read_mapping_hi_hi_hi, 46'h40000000000}; // @[CSR.scala:655:48] wire [56:0] read_mapping_hi = {read_mapping_hi_hi, read_mapping_hi_lo}; // @[CSR.scala:655:48] wire [63:0] read_mapping_1_2 = {read_mapping_hi, read_mapping_lo}; // @[CSR.scala:655:48] wire _read_mapping_T = reg_bp_0_address[38]; // @[package.scala:132:38] wire [24:0] _read_mapping_T_1 = {25{_read_mapping_T}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_2_2 = {_read_mapping_T_1, reg_bp_0_address}; // @[package.scala:132:{15,20}] wire [1:0] read_mapping_lo_1 = {read_mapping_lo_hi_1, 1'h0}; // @[CSR.scala:657:47] wire [50:0] read_mapping_3_2 = {read_mapping_hi_1, read_mapping_lo_1}; // @[CSR.scala:657:47] wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire _read_mapping_T_3 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _debug_csrs_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_6 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_11 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_16 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_21 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire [1:0] _read_mapping_T_4 = {~_read_mapping_T_3, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] | _read_mapping_T_4}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}] wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}] wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}] wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27] wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27] wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27] wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27] wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27] wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27] wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27] wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27] wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27] wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27] wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [1:0] _debug_csrs_T_2 = {~_debug_csrs_T_1, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] | _debug_csrs_T_2}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}] wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38] wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}] wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}] wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22] wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49] wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49] wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18] wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28] wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29] wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51] wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51] wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51] wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51] wire [3:0] lo_hi_lo_hi = {2'h0, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51] wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, 4'h0}; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51] wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51] wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51] wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51] wire [23:0] hi_hi_lo_lo = {read_sstatus_sd, 23'h0}; // @[CSR.scala:755:35, :768:51] wire [27:0] hi_hi_lo_4 = {4'h0, hi_hi_lo_lo}; // @[CSR.scala:768:51] wire [64:0] hi_hi_5 = {37'h0, hi_hi_lo_4}; // @[CSR.scala:768:51] wire [82:0] hi_7 = {hi_hi_5, 18'h800}; // @[CSR.scala:768:51] wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43] wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28] wire [39:0] _T_30 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49] wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49] wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36] wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}] wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}] wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27] wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}] wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}] wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27] reg [63:0] reg_custom_0; // @[CSR.scala:798:43] assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43] wire _reg_custom_read_T = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50] assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_1; // @[CSR.scala:798:43] assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_2 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_2; // @[CSR.scala:798:43] assign io_customCSRs_2_value_0 = reg_custom_2; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_2_T_2 = reg_custom_2; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_2_T_6 = reg_custom_2; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_4 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_5 = io_rw_addr_0 == 12'hF11; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_2 = _reg_custom_read_T_4 & _reg_custom_read_T_5; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_2_ren_0 = reg_custom_read_2; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_3; // @[CSR.scala:798:43] assign io_customCSRs_3_value_0 = reg_custom_3; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_3_T_2 = reg_custom_3; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_3_T_6 = reg_custom_3; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_6 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_7 = io_rw_addr_0 == 12'hF13; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_3 = _reg_custom_read_T_6 & _reg_custom_read_T_7; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_3_ren_0 = reg_custom_read_3; // @[CSR.scala:377:7, :799:36] wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19] wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [149:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [149:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [149:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22] wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23] wire decoded_addr_97_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77] wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23] wire decoded_addr_55_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77] wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23] wire decoded_addr_10_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77] wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23] wire decoded_addr_118_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77] wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23] wire decoded_addr_94_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77] wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23] wire decoded_addr_100_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77] wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23] wire decoded_addr_72_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77] wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23] wire decoded_addr_108_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77] wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23] wire decoded_addr_76_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77] wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23] wire decoded_addr_129_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77] wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23] wire decoded_addr_132_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77] wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23] wire decoded_addr_136_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77] wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23] wire decoded_addr_29_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77] wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23] wire decoded_addr_131_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77] wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23] wire decoded_addr_49_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77] wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23] wire decoded_addr_89_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77] wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23] wire decoded_addr_57_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77] wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23] wire decoded_addr_36_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77] wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23] wire decoded_addr_68_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77] wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23] wire decoded_addr_99_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77] wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23] wire decoded_addr_130_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77] wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23] wire decoded_addr_103_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77] wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23] wire decoded_addr_121_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77] wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23] wire decoded_addr_146_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77] wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23] wire decoded_addr_17_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77] wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23] wire decoded_addr_27_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77] wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23] wire decoded_addr_83_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77] wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23] wire decoded_addr_52_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77] wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23] wire decoded_addr_144_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77] wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23] wire decoded_addr_70_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77] wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23] wire decoded_addr_111_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77] wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23] wire decoded_addr_82_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77] wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23] wire decoded_addr_31_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77] wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23] wire decoded_addr_0_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77] wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23] wire decoded_addr_59_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77] wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23] wire decoded_addr_138_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77] wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23] wire decoded_addr_126_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77] wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23] wire decoded_addr_74_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77] wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23] wire decoded_addr_116_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77] wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23] wire decoded_addr_90_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77] wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23] wire decoded_addr_113_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77] wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23] wire decoded_addr_1_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77] wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23] wire decoded_addr_16_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77] wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23] wire decoded_addr_78_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77] wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23] wire decoded_addr_39_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77] wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23] wire decoded_addr_51_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77] wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23] wire decoded_addr_109_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77] wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23] wire decoded_addr_91_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77] wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23] wire decoded_addr_81_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77] wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23] wire decoded_addr_67_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77] wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23] wire decoded_addr_105_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77] wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23] wire decoded_addr_122_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77] wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23] wire decoded_addr_24_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77] wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23] wire decoded_addr_124_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77] wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23] wire decoded_addr_26_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77] wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23] wire decoded_addr_128_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77] wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23] wire decoded_addr_7_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77] wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23] wire decoded_addr_62_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77] wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23] wire decoded_addr_77_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77] wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23] wire decoded_addr_46_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77] wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23] wire decoded_addr_112_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77] wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23] wire decoded_addr_60_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77] wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23] wire decoded_addr_92_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77] wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23] wire decoded_addr_148_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77] wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23] wire decoded_addr_14_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77] wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23] wire decoded_addr_21_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77] wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23] wire decoded_addr_33_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77] wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23] wire decoded_addr_19_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77] wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23] wire decoded_addr_133_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77] wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23] wire decoded_addr_149_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77] wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23] wire decoded_addr_50_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77] wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23] wire decoded_addr_75_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77] wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23] wire decoded_addr_102_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77] wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23] wire decoded_addr_84_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77] wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23] wire decoded_addr_45_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77] wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23] wire decoded_addr_64_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77] wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23] wire decoded_addr_120_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77] wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23] wire decoded_addr_30_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77] wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23] wire decoded_addr_5_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77] wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23] wire decoded_addr_32_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77] wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23] wire decoded_addr_143_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77] wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23] wire decoded_addr_117_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77] wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23] wire decoded_addr_63_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77] wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23] wire decoded_addr_107_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77] wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23] wire decoded_addr_88_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77] wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23] wire decoded_addr_114_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77] wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23] wire decoded_addr_73_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77] wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23] wire decoded_addr_53_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77] wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23] wire decoded_addr_147_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77] wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23] wire decoded_addr_41_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77] wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23] wire decoded_addr_56_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77] wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23] wire decoded_addr_37_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77] wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23] wire decoded_addr_79_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77] wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23] wire decoded_addr_96_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77] wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23] wire decoded_addr_4_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77] wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23] wire decoded_addr_101_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77] wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23] wire decoded_addr_119_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77] wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23] wire decoded_addr_22_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77] wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23] wire decoded_addr_139_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77] wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23] wire decoded_addr_11_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77] wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23] wire decoded_addr_134_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77] wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23] wire decoded_addr_12_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77] wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23] wire decoded_addr_65_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77] wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23] wire decoded_addr_86_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77] wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23] wire decoded_addr_47_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77] wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23] wire decoded_addr_106_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77] wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23] wire decoded_addr_58_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77] wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23] wire decoded_addr_87_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77] wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23] wire decoded_addr_142_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77] wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23] wire decoded_addr_13_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77] wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23] wire decoded_addr_35_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77] wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23] wire decoded_addr_2_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77] wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23] wire decoded_addr_66_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77] wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23] wire decoded_addr_42_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77] wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23] wire decoded_addr_61_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77] wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23] wire decoded_addr_48_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77] wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23] wire decoded_addr_44_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77] wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23] wire decoded_addr_15_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77] wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23] wire decoded_addr_145_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77] wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23] wire decoded_addr_93_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77] wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23] wire decoded_addr_6_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77] wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23] wire decoded_addr_28_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77] wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23] wire decoded_addr_25_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77] wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23] wire decoded_addr_137_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77] wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23] wire decoded_addr_123_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77] wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23] wire decoded_addr_23_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77] wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23] wire decoded_addr_69_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77] wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23] wire decoded_addr_141_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77] wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23] wire decoded_addr_9_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77] wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23] wire decoded_addr_104_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77] wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23] wire decoded_addr_8_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77] wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23] wire decoded_addr_125_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77] wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23] wire decoded_addr_85_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77] wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23] wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77] wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23] wire decoded_addr_20_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77] wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23] wire decoded_addr_135_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77] wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23] wire decoded_addr_115_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77] wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23] wire decoded_addr_43_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77] wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23] wire decoded_addr_71_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77] wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23] wire decoded_addr_110_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77] wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23] wire decoded_addr_140_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77] wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23] wire decoded_addr_34_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77] wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23] wire decoded_addr_40_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77] wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23] wire decoded_addr_80_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77] wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23] wire decoded_addr_98_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77] wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23] wire decoded_addr_18_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77] wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23] wire decoded_addr_3_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77] wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23] wire decoded_addr_38_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77] wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23] wire decoded_addr_127_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77] wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23] wire decoded_addr_95_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77] wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_25 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}] wire [63:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_28 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}] wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}] assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}] assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_2_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_3_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39] wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _reg_bp_0_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [63:0] _reg_bp_1_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39] wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31] wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44] wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] | 7'h73}; // @[CSR.scala:892:{30,44}] wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22] wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [8:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_4 = |_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23] wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23] wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23] wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23] wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23] wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37] wire [8:0] decoded_1; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_11 = |_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37] assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37] wire is_break = decoded_1[7]; // @[pla.scala:81:23] wire is_ret = decoded_1[6]; // @[pla.scala:81:23] wire is_wfi = decoded_1[4]; // @[pla.scala:81:23] wire is_sfence = decoded_1[3]; // @[pla.scala:81:23] wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23] wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23] wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23] wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}] wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}] wire is_counter = _is_counter_T_2 | _is_counter_T_5; // @[package.scala:213:55] wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}] wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74] wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}] wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire allow_wfi = _allow_wfi_T_1 | _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}] wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}] wire _allow_sfence_vma_T_2 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77] wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}] wire allow_sfence_vma = _allow_sfence_vma_T_1 | _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}] wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88] wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}] wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81] wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}] wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}] wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}] wire _allow_sret_T_2 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79] wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}] wire allow_sret = _allow_sret_T_1 | _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}] wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_10 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70] wire [31:0] _GEN_11 = read_mcounteren >> _GEN_10; // @[CSR.scala:532:14, :912:70] wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70] assign _allow_counter_T_1 = _GEN_11; // @[CSR.scala:912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_11; // @[CSR.scala:912:70, :945:36] wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70] wire _allow_counter_T_3 = _allow_counter_T | _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}] wire _allow_counter_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46] wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}] wire [31:0] _GEN_12 = read_scounteren >> _GEN_10; // @[CSR.scala:536:14, :912:70, :913:75] wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75] assign _allow_counter_T_7 = _GEN_12; // @[CSR.scala:913:75] wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_12; // @[CSR.scala:913:75, :945:128] wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75] wire _allow_counter_T_9 = _allow_counter_T_6 | _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}] wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57] wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91] wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire [31:0] _GEN_13 = 32'h0 >> _GEN_10; // @[CSR.scala:912:70, :914:63] wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63] assign _allow_counter_T_14 = _GEN_13; // @[CSR.scala:914:63] wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_13; // @[CSR.scala:914:63, :945:71] wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63] wire _io_decode_0_fp_illegal_T = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39] wire _io_decode_0_fp_illegal_T_2 = reg_mstatus_v & _io_decode_0_fp_illegal_T_1; // @[CSR.scala:395:28, :915:{64,83}] wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T | _io_decode_0_fp_illegal_T_2; // @[CSR.scala:915:{39,47,64}] wire _io_decode_0_fp_illegal_T_4 = reg_misa[5]; // @[CSR.scala:648:25, :915:103] wire _io_decode_0_fp_illegal_T_5 = ~_io_decode_0_fp_illegal_T_4; // @[CSR.scala:915:{94,103}] assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3 | _io_decode_0_fp_illegal_T_5; // @[CSR.scala:915:{47,91,94}] assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91] wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}] wire _io_decode_0_vector_illegal_T_4 = reg_misa[21]; // @[CSR.scala:648:25, :916:107] wire _io_decode_0_vector_illegal_T_5 = ~_io_decode_0_vector_illegal_T_4; // @[CSR.scala:916:{98,107}] wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire _io_decode_0_rocc_illegal_T_4 = reg_misa[23]; // @[CSR.scala:648:25, :919:105] wire _io_decode_0_rocc_illegal_T_5 = ~_io_decode_0_rocc_illegal_T_4; // @[CSR.scala:919:{96,105}] wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42] wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_20 = addr == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_21 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_22 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_23 = addr == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_24 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_25 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_26 = addr == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_27 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_28 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_29 = addr == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_30 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_31 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_32 = addr == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_33 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_34 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_35 = addr == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_36 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_37 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_38 = addr == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_39 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_40 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_41 = addr == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_42 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_43 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_44 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_45 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_46 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_47 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_48 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_49 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_50 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_51 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_52 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_53 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_54 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_55 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_56 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_57 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_58 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_59 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_60 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_61 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_62 = addr == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_63 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_64 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_65 = addr == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_66 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_67 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_68 = addr == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_69 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_70 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_71 = addr == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_72 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_73 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_74 = addr == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_75 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_76 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_77 = addr == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_78 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_79 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_80 = addr == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_81 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_82 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_83 = addr == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_84 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_85 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_86 = addr == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_87 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_88 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_89 = addr == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_90 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_91 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_92 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_93 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_94 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_95 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_96 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_97 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_98 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_99 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_100 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_101 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_102 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_103 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_104 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_105 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_106 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_107 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_108 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_109 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_110 = addr == 12'h306; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_111 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_112 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_113 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_114 = addr == 12'h100; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_115 = addr == 12'h144; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_116 = addr == 12'h104; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_117 = addr == 12'h140; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_118 = addr == 12'h142; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_119 = addr == 12'h143; // @[CSR.scala:897:27, :899:93] wire _GEN_14 = addr == 12'h180; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_120; // @[CSR.scala:899:93] assign _csr_exists_T_120 = _GEN_14; // @[CSR.scala:899:93] wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_0_read_illegal_T_3 = _GEN_14; // @[CSR.scala:899:93, :925:14] wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_14; // @[CSR.scala:899:93, :947:12] wire _csr_exists_T_121 = addr == 12'h141; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_122 = addr == 12'h105; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_123 = addr == 12'h106; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_124 = addr == 12'h303; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_125 = addr == 12'h302; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_126 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_127 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_128 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_129 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_130 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_131 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_132 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_133 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_134 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_135 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_136 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_137 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_138 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_139 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_140 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_141 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_142 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_143 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_144 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_145 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_146 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_147 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_148 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_149 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_150 = _csr_exists_T | _csr_exists_T_1; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_151 = _csr_exists_T_150 | _csr_exists_T_2; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_152 = _csr_exists_T_151 | _csr_exists_T_3; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_153 = _csr_exists_T_152 | _csr_exists_T_4; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_154 = _csr_exists_T_153 | _csr_exists_T_5; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_155 = _csr_exists_T_154 | _csr_exists_T_6; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_156 = _csr_exists_T_155 | _csr_exists_T_7; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_157 = _csr_exists_T_156 | _csr_exists_T_8; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_158 = _csr_exists_T_157 | _csr_exists_T_9; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_159 = _csr_exists_T_158 | _csr_exists_T_10; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_160 = _csr_exists_T_159 | _csr_exists_T_11; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_161 = _csr_exists_T_160 | _csr_exists_T_12; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_162 = _csr_exists_T_161 | _csr_exists_T_13; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_163 = _csr_exists_T_162 | _csr_exists_T_14; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_164 = _csr_exists_T_163 | _csr_exists_T_15; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_165 = _csr_exists_T_164 | _csr_exists_T_16; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_166 = _csr_exists_T_165 | _csr_exists_T_17; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_167 = _csr_exists_T_166 | _csr_exists_T_18; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_168 = _csr_exists_T_167 | _csr_exists_T_19; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_169 = _csr_exists_T_168 | _csr_exists_T_20; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_170 = _csr_exists_T_169 | _csr_exists_T_21; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_171 = _csr_exists_T_170 | _csr_exists_T_22; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_172 = _csr_exists_T_171 | _csr_exists_T_23; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_173 = _csr_exists_T_172 | _csr_exists_T_24; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_174 = _csr_exists_T_173 | _csr_exists_T_25; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_175 = _csr_exists_T_174 | _csr_exists_T_26; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_176 = _csr_exists_T_175 | _csr_exists_T_27; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_177 = _csr_exists_T_176 | _csr_exists_T_28; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_178 = _csr_exists_T_177 | _csr_exists_T_29; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_179 = _csr_exists_T_178 | _csr_exists_T_30; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_180 = _csr_exists_T_179 | _csr_exists_T_31; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_181 = _csr_exists_T_180 | _csr_exists_T_32; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_182 = _csr_exists_T_181 | _csr_exists_T_33; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_183 = _csr_exists_T_182 | _csr_exists_T_34; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_184 = _csr_exists_T_183 | _csr_exists_T_35; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_185 = _csr_exists_T_184 | _csr_exists_T_36; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_186 = _csr_exists_T_185 | _csr_exists_T_37; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_187 = _csr_exists_T_186 | _csr_exists_T_38; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_188 = _csr_exists_T_187 | _csr_exists_T_39; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_189 = _csr_exists_T_188 | _csr_exists_T_40; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_190 = _csr_exists_T_189 | _csr_exists_T_41; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_191 = _csr_exists_T_190 | _csr_exists_T_42; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_192 = _csr_exists_T_191 | _csr_exists_T_43; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_193 = _csr_exists_T_192 | _csr_exists_T_44; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_194 = _csr_exists_T_193 | _csr_exists_T_45; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_195 = _csr_exists_T_194 | _csr_exists_T_46; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_196 = _csr_exists_T_195 | _csr_exists_T_47; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_197 = _csr_exists_T_196 | _csr_exists_T_48; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_198 = _csr_exists_T_197 | _csr_exists_T_49; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_199 = _csr_exists_T_198 | _csr_exists_T_50; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_200 = _csr_exists_T_199 | _csr_exists_T_51; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_201 = _csr_exists_T_200 | _csr_exists_T_52; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_202 = _csr_exists_T_201 | _csr_exists_T_53; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_203 = _csr_exists_T_202 | _csr_exists_T_54; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_204 = _csr_exists_T_203 | _csr_exists_T_55; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_205 = _csr_exists_T_204 | _csr_exists_T_56; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_206 = _csr_exists_T_205 | _csr_exists_T_57; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_207 = _csr_exists_T_206 | _csr_exists_T_58; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_208 = _csr_exists_T_207 | _csr_exists_T_59; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_209 = _csr_exists_T_208 | _csr_exists_T_60; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_210 = _csr_exists_T_209 | _csr_exists_T_61; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_211 = _csr_exists_T_210 | _csr_exists_T_62; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_212 = _csr_exists_T_211 | _csr_exists_T_63; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_213 = _csr_exists_T_212 | _csr_exists_T_64; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_214 = _csr_exists_T_213 | _csr_exists_T_65; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_215 = _csr_exists_T_214 | _csr_exists_T_66; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_216 = _csr_exists_T_215 | _csr_exists_T_67; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_217 = _csr_exists_T_216 | _csr_exists_T_68; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_218 = _csr_exists_T_217 | _csr_exists_T_69; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_219 = _csr_exists_T_218 | _csr_exists_T_70; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_220 = _csr_exists_T_219 | _csr_exists_T_71; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_221 = _csr_exists_T_220 | _csr_exists_T_72; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_222 = _csr_exists_T_221 | _csr_exists_T_73; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_223 = _csr_exists_T_222 | _csr_exists_T_74; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_224 = _csr_exists_T_223 | _csr_exists_T_75; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_225 = _csr_exists_T_224 | _csr_exists_T_76; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_226 = _csr_exists_T_225 | _csr_exists_T_77; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_227 = _csr_exists_T_226 | _csr_exists_T_78; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_228 = _csr_exists_T_227 | _csr_exists_T_79; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_229 = _csr_exists_T_228 | _csr_exists_T_80; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_230 = _csr_exists_T_229 | _csr_exists_T_81; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_231 = _csr_exists_T_230 | _csr_exists_T_82; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_232 = _csr_exists_T_231 | _csr_exists_T_83; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_233 = _csr_exists_T_232 | _csr_exists_T_84; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_234 = _csr_exists_T_233 | _csr_exists_T_85; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_235 = _csr_exists_T_234 | _csr_exists_T_86; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_236 = _csr_exists_T_235 | _csr_exists_T_87; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_237 = _csr_exists_T_236 | _csr_exists_T_88; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_238 = _csr_exists_T_237 | _csr_exists_T_89; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_239 = _csr_exists_T_238 | _csr_exists_T_90; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_240 = _csr_exists_T_239 | _csr_exists_T_91; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_241 = _csr_exists_T_240 | _csr_exists_T_92; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_242 = _csr_exists_T_241 | _csr_exists_T_93; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_243 = _csr_exists_T_242 | _csr_exists_T_94; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_244 = _csr_exists_T_243 | _csr_exists_T_95; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_245 = _csr_exists_T_244 | _csr_exists_T_96; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_246 = _csr_exists_T_245 | _csr_exists_T_97; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_247 = _csr_exists_T_246 | _csr_exists_T_98; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_248 = _csr_exists_T_247 | _csr_exists_T_99; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_249 = _csr_exists_T_248 | _csr_exists_T_100; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_250 = _csr_exists_T_249 | _csr_exists_T_101; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_251 = _csr_exists_T_250 | _csr_exists_T_102; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_252 = _csr_exists_T_251 | _csr_exists_T_103; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_253 = _csr_exists_T_252 | _csr_exists_T_104; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_254 = _csr_exists_T_253 | _csr_exists_T_105; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_255 = _csr_exists_T_254 | _csr_exists_T_106; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_256 = _csr_exists_T_255 | _csr_exists_T_107; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_257 = _csr_exists_T_256 | _csr_exists_T_108; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_258 = _csr_exists_T_257 | _csr_exists_T_109; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_259 = _csr_exists_T_258 | _csr_exists_T_110; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_260 = _csr_exists_T_259 | _csr_exists_T_111; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_261 = _csr_exists_T_260 | _csr_exists_T_112; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_262 = _csr_exists_T_261 | _csr_exists_T_113; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_263 = _csr_exists_T_262 | _csr_exists_T_114; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_264 = _csr_exists_T_263 | _csr_exists_T_115; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_265 = _csr_exists_T_264 | _csr_exists_T_116; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_266 = _csr_exists_T_265 | _csr_exists_T_117; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_267 = _csr_exists_T_266 | _csr_exists_T_118; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_268 = _csr_exists_T_267 | _csr_exists_T_119; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_269 = _csr_exists_T_268 | _csr_exists_T_120; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_270 = _csr_exists_T_269 | _csr_exists_T_121; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_271 = _csr_exists_T_270 | _csr_exists_T_122; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_272 = _csr_exists_T_271 | _csr_exists_T_123; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_273 = _csr_exists_T_272 | _csr_exists_T_124; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_274 = _csr_exists_T_273 | _csr_exists_T_125; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_275 = _csr_exists_T_274 | _csr_exists_T_126; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_276 = _csr_exists_T_275 | _csr_exists_T_127; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_277 = _csr_exists_T_276 | _csr_exists_T_128; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_278 = _csr_exists_T_277 | _csr_exists_T_129; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_279 = _csr_exists_T_278 | _csr_exists_T_130; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_280 = _csr_exists_T_279 | _csr_exists_T_131; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_281 = _csr_exists_T_280 | _csr_exists_T_132; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_282 = _csr_exists_T_281 | _csr_exists_T_133; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_283 = _csr_exists_T_282 | _csr_exists_T_134; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_284 = _csr_exists_T_283 | _csr_exists_T_135; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_285 = _csr_exists_T_284 | _csr_exists_T_136; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_286 = _csr_exists_T_285 | _csr_exists_T_137; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_287 = _csr_exists_T_286 | _csr_exists_T_138; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_288 = _csr_exists_T_287 | _csr_exists_T_139; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_289 = _csr_exists_T_288 | _csr_exists_T_140; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_290 = _csr_exists_T_289 | _csr_exists_T_141; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_291 = _csr_exists_T_290 | _csr_exists_T_142; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_292 = _csr_exists_T_291 | _csr_exists_T_143; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_293 = _csr_exists_T_292 | _csr_exists_T_144; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_294 = _csr_exists_T_293 | _csr_exists_T_145; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_295 = _csr_exists_T_294 | _csr_exists_T_146; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_296 = _csr_exists_T_295 | _csr_exists_T_147; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_297 = _csr_exists_T_296 | _csr_exists_T_148; // @[CSR.scala:899:{93,111}] wire csr_exists = _csr_exists_T_297 | _csr_exists_T_149; // @[CSR.scala:899:{93,111}] wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28] wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7] wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T | _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 | _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59] wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}] wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 | _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56] wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21] wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}] wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 | _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18] wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56] wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21] assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21] assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49] wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17] wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}] wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 | _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14] wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17] wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}] wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 | _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14] wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_0_system_illegal_T_16 = is_sfence | is_hfence_gvma; // @[CSR.scala:903:82, :939:18] wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40] wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}] wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 | _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37] wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105] wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53] wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46] wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34] wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64] wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37] wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61] wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61] wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}] wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}] wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 | _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}] wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 | _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}] wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}] wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 | _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34] wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}] assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma | is_hfence_gvma; // @[CSR.scala:903:82, :950:22] wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T | is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}] wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}] wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41] wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}] wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 | _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14] wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}] wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}] wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}] wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 | _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44] wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}] wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}] wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}] wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 | _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17] assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}] wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}] wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}] wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40] wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14] assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14] assign io_trace_0_cause_0 = cause; // @[CSR.scala:377:7, :959:8] wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25] wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31] wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32] wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30] wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35] wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33] wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78] wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58] wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36] wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29] wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29] wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31] assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25] wire _GEN_15 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53] wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53] assign _causeIsDebugInt_T_1 = _GEN_15; // @[CSR.scala:963:53] wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58] assign _causeIsDebugTrigger_T_2 = _GEN_15; // @[CSR.scala:963:53, :964:58] wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}] wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}] wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}] wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}] wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}] wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62] wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62] wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62] wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}] wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134] wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}] wire _trapToDebug_T = reg_singleStepped | causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56] wire _trapToDebug_T_1 = _trapToDebug_T | causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}] wire _trapToDebug_T_2 = _trapToDebug_T_1 | causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}] wire _trapToDebug_T_3 = _trapToDebug_T_2 | reg_debug; // @[CSR.scala:482:26, :966:{98,119}] wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}] wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37] wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}] wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55] wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}] wire [63:0] _GEN_16 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100] wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_16; // @[CSR.scala:498:14, :970:100] wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100] wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_16; // @[CSR.scala:502:14, :970:{100,132}] wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132] wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}] wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}] wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34] wire [63:0] _GEN_17 = 64'h0 >> _GEN_16; // @[CSR.scala:970:100, :971:80] wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80] assign _delegateVS_T_2 = _GEN_17; // @[CSR.scala:971:80] wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112] assign _delegateVS_T_4 = _GEN_17; // @[CSR.scala:971:{80,112}] wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80] wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112] wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}] wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}] wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15] wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15] wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}] wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33] wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}] wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24] wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}] wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70] wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}] wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}] wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38] wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}] wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}] wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45] wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46] wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46] wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}] wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70] wire _GEN_18 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107] wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107] assign _causeIsRnmiInt_T_4 = _GEN_18; // @[CSR.scala:985:107] wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69] assign _causeIsRnmiBEU_T_3 = _GEN_18; // @[CSR.scala:985:107, :986:69] wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 | _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}] wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}] wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}] wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}] wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}] wire _GEN_19 = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24] wire _io_eret_T; // @[CSR.scala:1000:24] assign _io_eret_T = _GEN_19; // @[CSR.scala:1000:24] wire _exception_T; // @[CSR.scala:1020:29] assign _exception_T = _GEN_19; // @[CSR.scala:1000:24, :1020:29] assign _io_eret_T_1 = _io_eret_T | insn_ret; // @[CSR.scala:893:83, :1000:{24,38}] assign io_eret_0 = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38] wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37] assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}] assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34] wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32] wire _io_status_sd_T_2 = _io_status_sd_T; // @[CSR.scala:1003:{32,37}] assign _io_status_sd_T_4 = _io_status_sd_T_2; // @[CSR.scala:1003:{37,58}] assign io_status_sd_0 = _io_status_sd_T_4; // @[CSR.scala:377:7, :1003:58] assign io_status_isa_0 = reg_misa[31:0]; // @[CSR.scala:377:7, :648:25, :1005:17] wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45] wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}] assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}] assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24] wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60] wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}] wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}] assign _io_status_dv_T_3 = reg_mstatus_v | _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}] assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33] wire _io_gstatus_sd_T = &io_gstatus_fs_0; // @[CSR.scala:377:7, :1016:34] wire _io_gstatus_sd_T_2 = _io_gstatus_sd_T; // @[CSR.scala:1016:{34,39}] wire _io_gstatus_sd_T_3 = &io_gstatus_vs_0; // @[CSR.scala:377:7, :1016:78] assign _io_gstatus_sd_T_4 = _io_gstatus_sd_T_2 | _io_gstatus_sd_T_3; // @[CSR.scala:1016:{39,61,78}] assign io_gstatus_sd_0 = _io_gstatus_sd_T_4; // @[CSR.scala:377:7, :1016:61] wire exception = _exception_T | io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}] wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24] assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37]
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops }
module BranchKillableQueue_4( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty, // @[util.scala:463:14] output [3:0] io_count // @[util.scala:463:14] ); wire [130:0] _ram_ext_R0_data; // @[util.scala:503:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _do_enq_T_4 = 1'h1; // @[util.scala:514:42] wire _do_enq_T_7 = 1'h1; // @[util.scala:514:102] wire _valids_0_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_0_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_1_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_1_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_2_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_2_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_3_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_3_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_4_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_4_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_5_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_5_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_6_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_6_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_7_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_7_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_8_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_8_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_9_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_9_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_10_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_10_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_11_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_11_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_12_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_12_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_13_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_13_T_6 = 1'h1; // @[util.scala:520:83] wire _valids_14_T_3 = 1'h1; // @[util.scala:520:34] wire _valids_14_T_6 = 1'h1; // @[util.scala:520:83] wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:97:23] wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_10 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_11 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_12 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_13 = 1'h0; // @[util.scala:504:34] wire _valids_WIRE_14 = 1'h0; // @[util.scala:504:34] wire _do_enq_T_2 = 1'h0; // @[util.scala:126:59] wire _do_enq_T_3 = 1'h0; // @[util.scala:61:61] wire _do_enq_T_6 = 1'h0; // @[util.scala:514:113] wire _valids_0_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_0_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_0_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_1_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_1_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_1_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_2_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_2_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_2_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_3_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_3_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_3_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_4_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_4_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_4_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_5_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_5_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_5_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_6_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_6_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_6_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_7_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_7_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_7_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_8_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_8_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_8_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_9_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_9_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_9_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_10_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_10_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_10_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_11_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_11_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_11_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_12_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_12_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_12_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_13_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_13_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_13_T_5 = 1'h0; // @[util.scala:520:94] wire _valids_14_T_1 = 1'h0; // @[util.scala:126:59] wire _valids_14_T_2 = 1'h0; // @[util.scala:61:61] wire _valids_14_T_5 = 1'h0; // @[util.scala:520:94] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:458:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:458:7] wire [3:0] _do_enq_T_1 = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_0_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_1_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_2_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_3_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_4_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_5_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_6_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_7_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_8_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_9_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_10_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_11_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_12_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_13_T = 4'h0; // @[util.scala:126:51] wire [3:0] _valids_14_T = 4'h0; // @[util.scala:126:51] wire _io_enq_ready_T; // @[util.scala:543:21] wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:93:25, :458:7] wire _io_deq_valid_T_1; // @[util.scala:548:42] wire [31:0] out_uop_inst; // @[util.scala:545:19] wire [31:0] out_uop_debug_inst; // @[util.scala:545:19] wire out_uop_is_rvc; // @[util.scala:545:19] wire [33:0] out_uop_debug_pc; // @[util.scala:545:19] wire out_uop_iq_type_0; // @[util.scala:545:19] wire out_uop_iq_type_1; // @[util.scala:545:19] wire out_uop_iq_type_2; // @[util.scala:545:19] wire out_uop_iq_type_3; // @[util.scala:545:19] wire out_uop_fu_code_0; // @[util.scala:545:19] wire out_uop_fu_code_1; // @[util.scala:545:19] wire out_uop_fu_code_2; // @[util.scala:545:19] wire out_uop_fu_code_3; // @[util.scala:545:19] wire out_uop_fu_code_4; // @[util.scala:545:19] wire out_uop_fu_code_5; // @[util.scala:545:19] wire out_uop_fu_code_6; // @[util.scala:545:19] wire out_uop_fu_code_7; // @[util.scala:545:19] wire out_uop_fu_code_8; // @[util.scala:545:19] wire out_uop_fu_code_9; // @[util.scala:545:19] wire out_uop_iw_issued; // @[util.scala:545:19] wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19] wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19] wire out_uop_iw_p1_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p2_speculative_child; // @[util.scala:545:19] wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19] wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19] wire out_uop_dis_col_sel; // @[util.scala:545:19] wire [3:0] out_uop_br_mask; // @[util.scala:545:19] wire [1:0] out_uop_br_tag; // @[util.scala:545:19] wire [3:0] out_uop_br_type; // @[util.scala:545:19] wire out_uop_is_sfb; // @[util.scala:545:19] wire out_uop_is_fence; // @[util.scala:545:19] wire out_uop_is_fencei; // @[util.scala:545:19] wire out_uop_is_sfence; // @[util.scala:545:19] wire out_uop_is_amo; // @[util.scala:545:19] wire out_uop_is_eret; // @[util.scala:545:19] wire out_uop_is_sys_pc2epc; // @[util.scala:545:19] wire out_uop_is_rocc; // @[util.scala:545:19] wire out_uop_is_mov; // @[util.scala:545:19] wire [3:0] out_uop_ftq_idx; // @[util.scala:545:19] wire out_uop_edge_inst; // @[util.scala:545:19] wire [5:0] out_uop_pc_lob; // @[util.scala:545:19] wire out_uop_taken; // @[util.scala:545:19] wire out_uop_imm_rename; // @[util.scala:545:19] wire [2:0] out_uop_imm_sel; // @[util.scala:545:19] wire [4:0] out_uop_pimm; // @[util.scala:545:19] wire [19:0] out_uop_imm_packed; // @[util.scala:545:19] wire [1:0] out_uop_op1_sel; // @[util.scala:545:19] wire [2:0] out_uop_op2_sel; // @[util.scala:545:19] wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19] wire out_uop_fp_ctrl_wen; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19] wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19] wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19] wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19] wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19] wire out_uop_fp_ctrl_toint; // @[util.scala:545:19] wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19] wire out_uop_fp_ctrl_fma; // @[util.scala:545:19] wire out_uop_fp_ctrl_div; // @[util.scala:545:19] wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19] wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19] wire out_uop_fp_ctrl_vec; // @[util.scala:545:19] wire [4:0] out_uop_rob_idx; // @[util.scala:545:19] wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19] wire [3:0] out_uop_stq_idx; // @[util.scala:545:19] wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19] wire [5:0] out_uop_pdst; // @[util.scala:545:19] wire [5:0] out_uop_prs1; // @[util.scala:545:19] wire [5:0] out_uop_prs2; // @[util.scala:545:19] wire [5:0] out_uop_prs3; // @[util.scala:545:19] wire [3:0] out_uop_ppred; // @[util.scala:545:19] wire out_uop_prs1_busy; // @[util.scala:545:19] wire out_uop_prs2_busy; // @[util.scala:545:19] wire out_uop_prs3_busy; // @[util.scala:545:19] wire out_uop_ppred_busy; // @[util.scala:545:19] wire [5:0] out_uop_stale_pdst; // @[util.scala:545:19] wire out_uop_exception; // @[util.scala:545:19] wire [63:0] out_uop_exc_cause; // @[util.scala:545:19] wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19] wire [1:0] out_uop_mem_size; // @[util.scala:545:19] wire out_uop_mem_signed; // @[util.scala:545:19] wire out_uop_uses_ldq; // @[util.scala:545:19] wire out_uop_uses_stq; // @[util.scala:545:19] wire out_uop_is_unique; // @[util.scala:545:19] wire out_uop_flush_on_commit; // @[util.scala:545:19] wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19] wire out_uop_ldst_is_rs1; // @[util.scala:545:19] wire [5:0] out_uop_ldst; // @[util.scala:545:19] wire [5:0] out_uop_lrs1; // @[util.scala:545:19] wire [5:0] out_uop_lrs2; // @[util.scala:545:19] wire [5:0] out_uop_lrs3; // @[util.scala:545:19] wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19] wire out_uop_frs3_en; // @[util.scala:545:19] wire out_uop_fcn_dw; // @[util.scala:545:19] wire [4:0] out_uop_fcn_op; // @[util.scala:545:19] wire out_uop_fp_val; // @[util.scala:545:19] wire [2:0] out_uop_fp_rm; // @[util.scala:545:19] wire [1:0] out_uop_fp_typ; // @[util.scala:545:19] wire out_uop_xcpt_pf_if; // @[util.scala:545:19] wire out_uop_xcpt_ae_if; // @[util.scala:545:19] wire out_uop_xcpt_ma_if; // @[util.scala:545:19] wire out_uop_bp_debug_if; // @[util.scala:545:19] wire out_uop_bp_xcpt_if; // @[util.scala:545:19] wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19] wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19] wire [33:0] out_addr; // @[util.scala:545:19] wire [63:0] out_data; // @[util.scala:545:19] wire out_is_hella; // @[util.scala:545:19] wire out_tag_match; // @[util.scala:545:19] wire [1:0] out_old_meta_coh_state; // @[util.scala:545:19] wire [21:0] out_old_meta_tag; // @[util.scala:545:19] wire [1:0] out_way_en; // @[util.scala:545:19] wire [4:0] out_sdq_id; // @[util.scala:545:19] wire _io_empty_T_1; // @[util.scala:512:27] wire [3:0] _io_count_T_5; // @[util.scala:556:22] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count_0; // @[util.scala:458:7] assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:503:22, :545:19] assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:503:22, :545:19] assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:503:22, :545:19] assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:503:22, :545:19] assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:503:22, :545:19] assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:503:22, :545:19] assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:503:22, :545:19] assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:503:22, :545:19] reg valids_0; // @[util.scala:504:26] wire _valids_0_T_4 = valids_0; // @[util.scala:504:26, :520:31] reg valids_1; // @[util.scala:504:26] wire _valids_1_T_4 = valids_1; // @[util.scala:504:26, :520:31] reg valids_2; // @[util.scala:504:26] wire _valids_2_T_4 = valids_2; // @[util.scala:504:26, :520:31] reg valids_3; // @[util.scala:504:26] wire _valids_3_T_4 = valids_3; // @[util.scala:504:26, :520:31] reg valids_4; // @[util.scala:504:26] wire _valids_4_T_4 = valids_4; // @[util.scala:504:26, :520:31] reg valids_5; // @[util.scala:504:26] wire _valids_5_T_4 = valids_5; // @[util.scala:504:26, :520:31] reg valids_6; // @[util.scala:504:26] wire _valids_6_T_4 = valids_6; // @[util.scala:504:26, :520:31] reg valids_7; // @[util.scala:504:26] wire _valids_7_T_4 = valids_7; // @[util.scala:504:26, :520:31] reg valids_8; // @[util.scala:504:26] wire _valids_8_T_4 = valids_8; // @[util.scala:504:26, :520:31] reg valids_9; // @[util.scala:504:26] wire _valids_9_T_4 = valids_9; // @[util.scala:504:26, :520:31] reg valids_10; // @[util.scala:504:26] wire _valids_10_T_4 = valids_10; // @[util.scala:504:26, :520:31] reg valids_11; // @[util.scala:504:26] wire _valids_11_T_4 = valids_11; // @[util.scala:504:26, :520:31] reg valids_12; // @[util.scala:504:26] wire _valids_12_T_4 = valids_12; // @[util.scala:504:26, :520:31] reg valids_13; // @[util.scala:504:26] wire _valids_13_T_4 = valids_13; // @[util.scala:504:26, :520:31] reg valids_14; // @[util.scala:504:26] wire _valids_14_T_4 = valids_14; // @[util.scala:504:26, :520:31] reg [31:0] uops_0_inst; // @[util.scala:505:22] reg [31:0] uops_0_debug_inst; // @[util.scala:505:22] reg uops_0_is_rvc; // @[util.scala:505:22] reg [33:0] uops_0_debug_pc; // @[util.scala:505:22] reg uops_0_iq_type_0; // @[util.scala:505:22] reg uops_0_iq_type_1; // @[util.scala:505:22] reg uops_0_iq_type_2; // @[util.scala:505:22] reg uops_0_iq_type_3; // @[util.scala:505:22] reg uops_0_fu_code_0; // @[util.scala:505:22] reg uops_0_fu_code_1; // @[util.scala:505:22] reg uops_0_fu_code_2; // @[util.scala:505:22] reg uops_0_fu_code_3; // @[util.scala:505:22] reg uops_0_fu_code_4; // @[util.scala:505:22] reg uops_0_fu_code_5; // @[util.scala:505:22] reg uops_0_fu_code_6; // @[util.scala:505:22] reg uops_0_fu_code_7; // @[util.scala:505:22] reg uops_0_fu_code_8; // @[util.scala:505:22] reg uops_0_fu_code_9; // @[util.scala:505:22] reg uops_0_iw_issued; // @[util.scala:505:22] reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_0_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_0_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_0_br_mask; // @[util.scala:505:22] wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_0_br_tag; // @[util.scala:505:22] reg [3:0] uops_0_br_type; // @[util.scala:505:22] reg uops_0_is_sfb; // @[util.scala:505:22] reg uops_0_is_fence; // @[util.scala:505:22] reg uops_0_is_fencei; // @[util.scala:505:22] reg uops_0_is_sfence; // @[util.scala:505:22] reg uops_0_is_amo; // @[util.scala:505:22] reg uops_0_is_eret; // @[util.scala:505:22] reg uops_0_is_sys_pc2epc; // @[util.scala:505:22] reg uops_0_is_rocc; // @[util.scala:505:22] reg uops_0_is_mov; // @[util.scala:505:22] reg [3:0] uops_0_ftq_idx; // @[util.scala:505:22] reg uops_0_edge_inst; // @[util.scala:505:22] reg [5:0] uops_0_pc_lob; // @[util.scala:505:22] reg uops_0_taken; // @[util.scala:505:22] reg uops_0_imm_rename; // @[util.scala:505:22] reg [2:0] uops_0_imm_sel; // @[util.scala:505:22] reg [4:0] uops_0_pimm; // @[util.scala:505:22] reg [19:0] uops_0_imm_packed; // @[util.scala:505:22] reg [1:0] uops_0_op1_sel; // @[util.scala:505:22] reg [2:0] uops_0_op2_sel; // @[util.scala:505:22] reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_0_fp_ctrl_wen; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_0_fp_ctrl_toint; // @[util.scala:505:22] reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_0_fp_ctrl_fma; // @[util.scala:505:22] reg uops_0_fp_ctrl_div; // @[util.scala:505:22] reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_0_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_0_rob_idx; // @[util.scala:505:22] reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_0_stq_idx; // @[util.scala:505:22] reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_0_pdst; // @[util.scala:505:22] reg [5:0] uops_0_prs1; // @[util.scala:505:22] reg [5:0] uops_0_prs2; // @[util.scala:505:22] reg [5:0] uops_0_prs3; // @[util.scala:505:22] reg [3:0] uops_0_ppred; // @[util.scala:505:22] reg uops_0_prs1_busy; // @[util.scala:505:22] reg uops_0_prs2_busy; // @[util.scala:505:22] reg uops_0_prs3_busy; // @[util.scala:505:22] reg uops_0_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_0_stale_pdst; // @[util.scala:505:22] reg uops_0_exception; // @[util.scala:505:22] reg [63:0] uops_0_exc_cause; // @[util.scala:505:22] reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_0_mem_size; // @[util.scala:505:22] reg uops_0_mem_signed; // @[util.scala:505:22] reg uops_0_uses_ldq; // @[util.scala:505:22] reg uops_0_uses_stq; // @[util.scala:505:22] reg uops_0_is_unique; // @[util.scala:505:22] reg uops_0_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22] reg uops_0_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_0_ldst; // @[util.scala:505:22] reg [5:0] uops_0_lrs1; // @[util.scala:505:22] reg [5:0] uops_0_lrs2; // @[util.scala:505:22] reg [5:0] uops_0_lrs3; // @[util.scala:505:22] reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22] reg uops_0_frs3_en; // @[util.scala:505:22] reg uops_0_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_0_fcn_op; // @[util.scala:505:22] reg uops_0_fp_val; // @[util.scala:505:22] reg [2:0] uops_0_fp_rm; // @[util.scala:505:22] reg [1:0] uops_0_fp_typ; // @[util.scala:505:22] reg uops_0_xcpt_pf_if; // @[util.scala:505:22] reg uops_0_xcpt_ae_if; // @[util.scala:505:22] reg uops_0_xcpt_ma_if; // @[util.scala:505:22] reg uops_0_bp_debug_if; // @[util.scala:505:22] reg uops_0_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_1_inst; // @[util.scala:505:22] reg [31:0] uops_1_debug_inst; // @[util.scala:505:22] reg uops_1_is_rvc; // @[util.scala:505:22] reg [33:0] uops_1_debug_pc; // @[util.scala:505:22] reg uops_1_iq_type_0; // @[util.scala:505:22] reg uops_1_iq_type_1; // @[util.scala:505:22] reg uops_1_iq_type_2; // @[util.scala:505:22] reg uops_1_iq_type_3; // @[util.scala:505:22] reg uops_1_fu_code_0; // @[util.scala:505:22] reg uops_1_fu_code_1; // @[util.scala:505:22] reg uops_1_fu_code_2; // @[util.scala:505:22] reg uops_1_fu_code_3; // @[util.scala:505:22] reg uops_1_fu_code_4; // @[util.scala:505:22] reg uops_1_fu_code_5; // @[util.scala:505:22] reg uops_1_fu_code_6; // @[util.scala:505:22] reg uops_1_fu_code_7; // @[util.scala:505:22] reg uops_1_fu_code_8; // @[util.scala:505:22] reg uops_1_fu_code_9; // @[util.scala:505:22] reg uops_1_iw_issued; // @[util.scala:505:22] reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_1_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_1_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_1_br_mask; // @[util.scala:505:22] wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_1_br_tag; // @[util.scala:505:22] reg [3:0] uops_1_br_type; // @[util.scala:505:22] reg uops_1_is_sfb; // @[util.scala:505:22] reg uops_1_is_fence; // @[util.scala:505:22] reg uops_1_is_fencei; // @[util.scala:505:22] reg uops_1_is_sfence; // @[util.scala:505:22] reg uops_1_is_amo; // @[util.scala:505:22] reg uops_1_is_eret; // @[util.scala:505:22] reg uops_1_is_sys_pc2epc; // @[util.scala:505:22] reg uops_1_is_rocc; // @[util.scala:505:22] reg uops_1_is_mov; // @[util.scala:505:22] reg [3:0] uops_1_ftq_idx; // @[util.scala:505:22] reg uops_1_edge_inst; // @[util.scala:505:22] reg [5:0] uops_1_pc_lob; // @[util.scala:505:22] reg uops_1_taken; // @[util.scala:505:22] reg uops_1_imm_rename; // @[util.scala:505:22] reg [2:0] uops_1_imm_sel; // @[util.scala:505:22] reg [4:0] uops_1_pimm; // @[util.scala:505:22] reg [19:0] uops_1_imm_packed; // @[util.scala:505:22] reg [1:0] uops_1_op1_sel; // @[util.scala:505:22] reg [2:0] uops_1_op2_sel; // @[util.scala:505:22] reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_1_fp_ctrl_wen; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_1_fp_ctrl_toint; // @[util.scala:505:22] reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_1_fp_ctrl_fma; // @[util.scala:505:22] reg uops_1_fp_ctrl_div; // @[util.scala:505:22] reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_1_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_1_rob_idx; // @[util.scala:505:22] reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_1_stq_idx; // @[util.scala:505:22] reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_1_pdst; // @[util.scala:505:22] reg [5:0] uops_1_prs1; // @[util.scala:505:22] reg [5:0] uops_1_prs2; // @[util.scala:505:22] reg [5:0] uops_1_prs3; // @[util.scala:505:22] reg [3:0] uops_1_ppred; // @[util.scala:505:22] reg uops_1_prs1_busy; // @[util.scala:505:22] reg uops_1_prs2_busy; // @[util.scala:505:22] reg uops_1_prs3_busy; // @[util.scala:505:22] reg uops_1_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_1_stale_pdst; // @[util.scala:505:22] reg uops_1_exception; // @[util.scala:505:22] reg [63:0] uops_1_exc_cause; // @[util.scala:505:22] reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_1_mem_size; // @[util.scala:505:22] reg uops_1_mem_signed; // @[util.scala:505:22] reg uops_1_uses_ldq; // @[util.scala:505:22] reg uops_1_uses_stq; // @[util.scala:505:22] reg uops_1_is_unique; // @[util.scala:505:22] reg uops_1_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22] reg uops_1_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_1_ldst; // @[util.scala:505:22] reg [5:0] uops_1_lrs1; // @[util.scala:505:22] reg [5:0] uops_1_lrs2; // @[util.scala:505:22] reg [5:0] uops_1_lrs3; // @[util.scala:505:22] reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22] reg uops_1_frs3_en; // @[util.scala:505:22] reg uops_1_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_1_fcn_op; // @[util.scala:505:22] reg uops_1_fp_val; // @[util.scala:505:22] reg [2:0] uops_1_fp_rm; // @[util.scala:505:22] reg [1:0] uops_1_fp_typ; // @[util.scala:505:22] reg uops_1_xcpt_pf_if; // @[util.scala:505:22] reg uops_1_xcpt_ae_if; // @[util.scala:505:22] reg uops_1_xcpt_ma_if; // @[util.scala:505:22] reg uops_1_bp_debug_if; // @[util.scala:505:22] reg uops_1_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_2_inst; // @[util.scala:505:22] reg [31:0] uops_2_debug_inst; // @[util.scala:505:22] reg uops_2_is_rvc; // @[util.scala:505:22] reg [33:0] uops_2_debug_pc; // @[util.scala:505:22] reg uops_2_iq_type_0; // @[util.scala:505:22] reg uops_2_iq_type_1; // @[util.scala:505:22] reg uops_2_iq_type_2; // @[util.scala:505:22] reg uops_2_iq_type_3; // @[util.scala:505:22] reg uops_2_fu_code_0; // @[util.scala:505:22] reg uops_2_fu_code_1; // @[util.scala:505:22] reg uops_2_fu_code_2; // @[util.scala:505:22] reg uops_2_fu_code_3; // @[util.scala:505:22] reg uops_2_fu_code_4; // @[util.scala:505:22] reg uops_2_fu_code_5; // @[util.scala:505:22] reg uops_2_fu_code_6; // @[util.scala:505:22] reg uops_2_fu_code_7; // @[util.scala:505:22] reg uops_2_fu_code_8; // @[util.scala:505:22] reg uops_2_fu_code_9; // @[util.scala:505:22] reg uops_2_iw_issued; // @[util.scala:505:22] reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_2_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_2_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_2_br_mask; // @[util.scala:505:22] wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_2_br_tag; // @[util.scala:505:22] reg [3:0] uops_2_br_type; // @[util.scala:505:22] reg uops_2_is_sfb; // @[util.scala:505:22] reg uops_2_is_fence; // @[util.scala:505:22] reg uops_2_is_fencei; // @[util.scala:505:22] reg uops_2_is_sfence; // @[util.scala:505:22] reg uops_2_is_amo; // @[util.scala:505:22] reg uops_2_is_eret; // @[util.scala:505:22] reg uops_2_is_sys_pc2epc; // @[util.scala:505:22] reg uops_2_is_rocc; // @[util.scala:505:22] reg uops_2_is_mov; // @[util.scala:505:22] reg [3:0] uops_2_ftq_idx; // @[util.scala:505:22] reg uops_2_edge_inst; // @[util.scala:505:22] reg [5:0] uops_2_pc_lob; // @[util.scala:505:22] reg uops_2_taken; // @[util.scala:505:22] reg uops_2_imm_rename; // @[util.scala:505:22] reg [2:0] uops_2_imm_sel; // @[util.scala:505:22] reg [4:0] uops_2_pimm; // @[util.scala:505:22] reg [19:0] uops_2_imm_packed; // @[util.scala:505:22] reg [1:0] uops_2_op1_sel; // @[util.scala:505:22] reg [2:0] uops_2_op2_sel; // @[util.scala:505:22] reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_2_fp_ctrl_wen; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_2_fp_ctrl_toint; // @[util.scala:505:22] reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_2_fp_ctrl_fma; // @[util.scala:505:22] reg uops_2_fp_ctrl_div; // @[util.scala:505:22] reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_2_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_2_rob_idx; // @[util.scala:505:22] reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_2_stq_idx; // @[util.scala:505:22] reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_2_pdst; // @[util.scala:505:22] reg [5:0] uops_2_prs1; // @[util.scala:505:22] reg [5:0] uops_2_prs2; // @[util.scala:505:22] reg [5:0] uops_2_prs3; // @[util.scala:505:22] reg [3:0] uops_2_ppred; // @[util.scala:505:22] reg uops_2_prs1_busy; // @[util.scala:505:22] reg uops_2_prs2_busy; // @[util.scala:505:22] reg uops_2_prs3_busy; // @[util.scala:505:22] reg uops_2_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_2_stale_pdst; // @[util.scala:505:22] reg uops_2_exception; // @[util.scala:505:22] reg [63:0] uops_2_exc_cause; // @[util.scala:505:22] reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_2_mem_size; // @[util.scala:505:22] reg uops_2_mem_signed; // @[util.scala:505:22] reg uops_2_uses_ldq; // @[util.scala:505:22] reg uops_2_uses_stq; // @[util.scala:505:22] reg uops_2_is_unique; // @[util.scala:505:22] reg uops_2_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22] reg uops_2_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_2_ldst; // @[util.scala:505:22] reg [5:0] uops_2_lrs1; // @[util.scala:505:22] reg [5:0] uops_2_lrs2; // @[util.scala:505:22] reg [5:0] uops_2_lrs3; // @[util.scala:505:22] reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22] reg uops_2_frs3_en; // @[util.scala:505:22] reg uops_2_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_2_fcn_op; // @[util.scala:505:22] reg uops_2_fp_val; // @[util.scala:505:22] reg [2:0] uops_2_fp_rm; // @[util.scala:505:22] reg [1:0] uops_2_fp_typ; // @[util.scala:505:22] reg uops_2_xcpt_pf_if; // @[util.scala:505:22] reg uops_2_xcpt_ae_if; // @[util.scala:505:22] reg uops_2_xcpt_ma_if; // @[util.scala:505:22] reg uops_2_bp_debug_if; // @[util.scala:505:22] reg uops_2_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_3_inst; // @[util.scala:505:22] reg [31:0] uops_3_debug_inst; // @[util.scala:505:22] reg uops_3_is_rvc; // @[util.scala:505:22] reg [33:0] uops_3_debug_pc; // @[util.scala:505:22] reg uops_3_iq_type_0; // @[util.scala:505:22] reg uops_3_iq_type_1; // @[util.scala:505:22] reg uops_3_iq_type_2; // @[util.scala:505:22] reg uops_3_iq_type_3; // @[util.scala:505:22] reg uops_3_fu_code_0; // @[util.scala:505:22] reg uops_3_fu_code_1; // @[util.scala:505:22] reg uops_3_fu_code_2; // @[util.scala:505:22] reg uops_3_fu_code_3; // @[util.scala:505:22] reg uops_3_fu_code_4; // @[util.scala:505:22] reg uops_3_fu_code_5; // @[util.scala:505:22] reg uops_3_fu_code_6; // @[util.scala:505:22] reg uops_3_fu_code_7; // @[util.scala:505:22] reg uops_3_fu_code_8; // @[util.scala:505:22] reg uops_3_fu_code_9; // @[util.scala:505:22] reg uops_3_iw_issued; // @[util.scala:505:22] reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_3_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_3_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_3_br_mask; // @[util.scala:505:22] wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_3_br_tag; // @[util.scala:505:22] reg [3:0] uops_3_br_type; // @[util.scala:505:22] reg uops_3_is_sfb; // @[util.scala:505:22] reg uops_3_is_fence; // @[util.scala:505:22] reg uops_3_is_fencei; // @[util.scala:505:22] reg uops_3_is_sfence; // @[util.scala:505:22] reg uops_3_is_amo; // @[util.scala:505:22] reg uops_3_is_eret; // @[util.scala:505:22] reg uops_3_is_sys_pc2epc; // @[util.scala:505:22] reg uops_3_is_rocc; // @[util.scala:505:22] reg uops_3_is_mov; // @[util.scala:505:22] reg [3:0] uops_3_ftq_idx; // @[util.scala:505:22] reg uops_3_edge_inst; // @[util.scala:505:22] reg [5:0] uops_3_pc_lob; // @[util.scala:505:22] reg uops_3_taken; // @[util.scala:505:22] reg uops_3_imm_rename; // @[util.scala:505:22] reg [2:0] uops_3_imm_sel; // @[util.scala:505:22] reg [4:0] uops_3_pimm; // @[util.scala:505:22] reg [19:0] uops_3_imm_packed; // @[util.scala:505:22] reg [1:0] uops_3_op1_sel; // @[util.scala:505:22] reg [2:0] uops_3_op2_sel; // @[util.scala:505:22] reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_3_fp_ctrl_wen; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_3_fp_ctrl_toint; // @[util.scala:505:22] reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_3_fp_ctrl_fma; // @[util.scala:505:22] reg uops_3_fp_ctrl_div; // @[util.scala:505:22] reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_3_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_3_rob_idx; // @[util.scala:505:22] reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_3_stq_idx; // @[util.scala:505:22] reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_3_pdst; // @[util.scala:505:22] reg [5:0] uops_3_prs1; // @[util.scala:505:22] reg [5:0] uops_3_prs2; // @[util.scala:505:22] reg [5:0] uops_3_prs3; // @[util.scala:505:22] reg [3:0] uops_3_ppred; // @[util.scala:505:22] reg uops_3_prs1_busy; // @[util.scala:505:22] reg uops_3_prs2_busy; // @[util.scala:505:22] reg uops_3_prs3_busy; // @[util.scala:505:22] reg uops_3_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_3_stale_pdst; // @[util.scala:505:22] reg uops_3_exception; // @[util.scala:505:22] reg [63:0] uops_3_exc_cause; // @[util.scala:505:22] reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_3_mem_size; // @[util.scala:505:22] reg uops_3_mem_signed; // @[util.scala:505:22] reg uops_3_uses_ldq; // @[util.scala:505:22] reg uops_3_uses_stq; // @[util.scala:505:22] reg uops_3_is_unique; // @[util.scala:505:22] reg uops_3_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22] reg uops_3_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_3_ldst; // @[util.scala:505:22] reg [5:0] uops_3_lrs1; // @[util.scala:505:22] reg [5:0] uops_3_lrs2; // @[util.scala:505:22] reg [5:0] uops_3_lrs3; // @[util.scala:505:22] reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22] reg uops_3_frs3_en; // @[util.scala:505:22] reg uops_3_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_3_fcn_op; // @[util.scala:505:22] reg uops_3_fp_val; // @[util.scala:505:22] reg [2:0] uops_3_fp_rm; // @[util.scala:505:22] reg [1:0] uops_3_fp_typ; // @[util.scala:505:22] reg uops_3_xcpt_pf_if; // @[util.scala:505:22] reg uops_3_xcpt_ae_if; // @[util.scala:505:22] reg uops_3_xcpt_ma_if; // @[util.scala:505:22] reg uops_3_bp_debug_if; // @[util.scala:505:22] reg uops_3_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_4_inst; // @[util.scala:505:22] reg [31:0] uops_4_debug_inst; // @[util.scala:505:22] reg uops_4_is_rvc; // @[util.scala:505:22] reg [33:0] uops_4_debug_pc; // @[util.scala:505:22] reg uops_4_iq_type_0; // @[util.scala:505:22] reg uops_4_iq_type_1; // @[util.scala:505:22] reg uops_4_iq_type_2; // @[util.scala:505:22] reg uops_4_iq_type_3; // @[util.scala:505:22] reg uops_4_fu_code_0; // @[util.scala:505:22] reg uops_4_fu_code_1; // @[util.scala:505:22] reg uops_4_fu_code_2; // @[util.scala:505:22] reg uops_4_fu_code_3; // @[util.scala:505:22] reg uops_4_fu_code_4; // @[util.scala:505:22] reg uops_4_fu_code_5; // @[util.scala:505:22] reg uops_4_fu_code_6; // @[util.scala:505:22] reg uops_4_fu_code_7; // @[util.scala:505:22] reg uops_4_fu_code_8; // @[util.scala:505:22] reg uops_4_fu_code_9; // @[util.scala:505:22] reg uops_4_iw_issued; // @[util.scala:505:22] reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_4_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_4_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_4_br_mask; // @[util.scala:505:22] wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_4_br_tag; // @[util.scala:505:22] reg [3:0] uops_4_br_type; // @[util.scala:505:22] reg uops_4_is_sfb; // @[util.scala:505:22] reg uops_4_is_fence; // @[util.scala:505:22] reg uops_4_is_fencei; // @[util.scala:505:22] reg uops_4_is_sfence; // @[util.scala:505:22] reg uops_4_is_amo; // @[util.scala:505:22] reg uops_4_is_eret; // @[util.scala:505:22] reg uops_4_is_sys_pc2epc; // @[util.scala:505:22] reg uops_4_is_rocc; // @[util.scala:505:22] reg uops_4_is_mov; // @[util.scala:505:22] reg [3:0] uops_4_ftq_idx; // @[util.scala:505:22] reg uops_4_edge_inst; // @[util.scala:505:22] reg [5:0] uops_4_pc_lob; // @[util.scala:505:22] reg uops_4_taken; // @[util.scala:505:22] reg uops_4_imm_rename; // @[util.scala:505:22] reg [2:0] uops_4_imm_sel; // @[util.scala:505:22] reg [4:0] uops_4_pimm; // @[util.scala:505:22] reg [19:0] uops_4_imm_packed; // @[util.scala:505:22] reg [1:0] uops_4_op1_sel; // @[util.scala:505:22] reg [2:0] uops_4_op2_sel; // @[util.scala:505:22] reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_4_fp_ctrl_wen; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_4_fp_ctrl_toint; // @[util.scala:505:22] reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_4_fp_ctrl_fma; // @[util.scala:505:22] reg uops_4_fp_ctrl_div; // @[util.scala:505:22] reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_4_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_4_rob_idx; // @[util.scala:505:22] reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_4_stq_idx; // @[util.scala:505:22] reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_4_pdst; // @[util.scala:505:22] reg [5:0] uops_4_prs1; // @[util.scala:505:22] reg [5:0] uops_4_prs2; // @[util.scala:505:22] reg [5:0] uops_4_prs3; // @[util.scala:505:22] reg [3:0] uops_4_ppred; // @[util.scala:505:22] reg uops_4_prs1_busy; // @[util.scala:505:22] reg uops_4_prs2_busy; // @[util.scala:505:22] reg uops_4_prs3_busy; // @[util.scala:505:22] reg uops_4_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_4_stale_pdst; // @[util.scala:505:22] reg uops_4_exception; // @[util.scala:505:22] reg [63:0] uops_4_exc_cause; // @[util.scala:505:22] reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_4_mem_size; // @[util.scala:505:22] reg uops_4_mem_signed; // @[util.scala:505:22] reg uops_4_uses_ldq; // @[util.scala:505:22] reg uops_4_uses_stq; // @[util.scala:505:22] reg uops_4_is_unique; // @[util.scala:505:22] reg uops_4_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22] reg uops_4_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_4_ldst; // @[util.scala:505:22] reg [5:0] uops_4_lrs1; // @[util.scala:505:22] reg [5:0] uops_4_lrs2; // @[util.scala:505:22] reg [5:0] uops_4_lrs3; // @[util.scala:505:22] reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22] reg uops_4_frs3_en; // @[util.scala:505:22] reg uops_4_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_4_fcn_op; // @[util.scala:505:22] reg uops_4_fp_val; // @[util.scala:505:22] reg [2:0] uops_4_fp_rm; // @[util.scala:505:22] reg [1:0] uops_4_fp_typ; // @[util.scala:505:22] reg uops_4_xcpt_pf_if; // @[util.scala:505:22] reg uops_4_xcpt_ae_if; // @[util.scala:505:22] reg uops_4_xcpt_ma_if; // @[util.scala:505:22] reg uops_4_bp_debug_if; // @[util.scala:505:22] reg uops_4_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_5_inst; // @[util.scala:505:22] reg [31:0] uops_5_debug_inst; // @[util.scala:505:22] reg uops_5_is_rvc; // @[util.scala:505:22] reg [33:0] uops_5_debug_pc; // @[util.scala:505:22] reg uops_5_iq_type_0; // @[util.scala:505:22] reg uops_5_iq_type_1; // @[util.scala:505:22] reg uops_5_iq_type_2; // @[util.scala:505:22] reg uops_5_iq_type_3; // @[util.scala:505:22] reg uops_5_fu_code_0; // @[util.scala:505:22] reg uops_5_fu_code_1; // @[util.scala:505:22] reg uops_5_fu_code_2; // @[util.scala:505:22] reg uops_5_fu_code_3; // @[util.scala:505:22] reg uops_5_fu_code_4; // @[util.scala:505:22] reg uops_5_fu_code_5; // @[util.scala:505:22] reg uops_5_fu_code_6; // @[util.scala:505:22] reg uops_5_fu_code_7; // @[util.scala:505:22] reg uops_5_fu_code_8; // @[util.scala:505:22] reg uops_5_fu_code_9; // @[util.scala:505:22] reg uops_5_iw_issued; // @[util.scala:505:22] reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_5_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_5_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_5_br_mask; // @[util.scala:505:22] wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_5_br_tag; // @[util.scala:505:22] reg [3:0] uops_5_br_type; // @[util.scala:505:22] reg uops_5_is_sfb; // @[util.scala:505:22] reg uops_5_is_fence; // @[util.scala:505:22] reg uops_5_is_fencei; // @[util.scala:505:22] reg uops_5_is_sfence; // @[util.scala:505:22] reg uops_5_is_amo; // @[util.scala:505:22] reg uops_5_is_eret; // @[util.scala:505:22] reg uops_5_is_sys_pc2epc; // @[util.scala:505:22] reg uops_5_is_rocc; // @[util.scala:505:22] reg uops_5_is_mov; // @[util.scala:505:22] reg [3:0] uops_5_ftq_idx; // @[util.scala:505:22] reg uops_5_edge_inst; // @[util.scala:505:22] reg [5:0] uops_5_pc_lob; // @[util.scala:505:22] reg uops_5_taken; // @[util.scala:505:22] reg uops_5_imm_rename; // @[util.scala:505:22] reg [2:0] uops_5_imm_sel; // @[util.scala:505:22] reg [4:0] uops_5_pimm; // @[util.scala:505:22] reg [19:0] uops_5_imm_packed; // @[util.scala:505:22] reg [1:0] uops_5_op1_sel; // @[util.scala:505:22] reg [2:0] uops_5_op2_sel; // @[util.scala:505:22] reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_5_fp_ctrl_wen; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_5_fp_ctrl_toint; // @[util.scala:505:22] reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_5_fp_ctrl_fma; // @[util.scala:505:22] reg uops_5_fp_ctrl_div; // @[util.scala:505:22] reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_5_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_5_rob_idx; // @[util.scala:505:22] reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_5_stq_idx; // @[util.scala:505:22] reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_5_pdst; // @[util.scala:505:22] reg [5:0] uops_5_prs1; // @[util.scala:505:22] reg [5:0] uops_5_prs2; // @[util.scala:505:22] reg [5:0] uops_5_prs3; // @[util.scala:505:22] reg [3:0] uops_5_ppred; // @[util.scala:505:22] reg uops_5_prs1_busy; // @[util.scala:505:22] reg uops_5_prs2_busy; // @[util.scala:505:22] reg uops_5_prs3_busy; // @[util.scala:505:22] reg uops_5_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_5_stale_pdst; // @[util.scala:505:22] reg uops_5_exception; // @[util.scala:505:22] reg [63:0] uops_5_exc_cause; // @[util.scala:505:22] reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_5_mem_size; // @[util.scala:505:22] reg uops_5_mem_signed; // @[util.scala:505:22] reg uops_5_uses_ldq; // @[util.scala:505:22] reg uops_5_uses_stq; // @[util.scala:505:22] reg uops_5_is_unique; // @[util.scala:505:22] reg uops_5_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22] reg uops_5_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_5_ldst; // @[util.scala:505:22] reg [5:0] uops_5_lrs1; // @[util.scala:505:22] reg [5:0] uops_5_lrs2; // @[util.scala:505:22] reg [5:0] uops_5_lrs3; // @[util.scala:505:22] reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22] reg uops_5_frs3_en; // @[util.scala:505:22] reg uops_5_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_5_fcn_op; // @[util.scala:505:22] reg uops_5_fp_val; // @[util.scala:505:22] reg [2:0] uops_5_fp_rm; // @[util.scala:505:22] reg [1:0] uops_5_fp_typ; // @[util.scala:505:22] reg uops_5_xcpt_pf_if; // @[util.scala:505:22] reg uops_5_xcpt_ae_if; // @[util.scala:505:22] reg uops_5_xcpt_ma_if; // @[util.scala:505:22] reg uops_5_bp_debug_if; // @[util.scala:505:22] reg uops_5_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_6_inst; // @[util.scala:505:22] reg [31:0] uops_6_debug_inst; // @[util.scala:505:22] reg uops_6_is_rvc; // @[util.scala:505:22] reg [33:0] uops_6_debug_pc; // @[util.scala:505:22] reg uops_6_iq_type_0; // @[util.scala:505:22] reg uops_6_iq_type_1; // @[util.scala:505:22] reg uops_6_iq_type_2; // @[util.scala:505:22] reg uops_6_iq_type_3; // @[util.scala:505:22] reg uops_6_fu_code_0; // @[util.scala:505:22] reg uops_6_fu_code_1; // @[util.scala:505:22] reg uops_6_fu_code_2; // @[util.scala:505:22] reg uops_6_fu_code_3; // @[util.scala:505:22] reg uops_6_fu_code_4; // @[util.scala:505:22] reg uops_6_fu_code_5; // @[util.scala:505:22] reg uops_6_fu_code_6; // @[util.scala:505:22] reg uops_6_fu_code_7; // @[util.scala:505:22] reg uops_6_fu_code_8; // @[util.scala:505:22] reg uops_6_fu_code_9; // @[util.scala:505:22] reg uops_6_iw_issued; // @[util.scala:505:22] reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_6_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_6_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_6_br_mask; // @[util.scala:505:22] wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_6_br_tag; // @[util.scala:505:22] reg [3:0] uops_6_br_type; // @[util.scala:505:22] reg uops_6_is_sfb; // @[util.scala:505:22] reg uops_6_is_fence; // @[util.scala:505:22] reg uops_6_is_fencei; // @[util.scala:505:22] reg uops_6_is_sfence; // @[util.scala:505:22] reg uops_6_is_amo; // @[util.scala:505:22] reg uops_6_is_eret; // @[util.scala:505:22] reg uops_6_is_sys_pc2epc; // @[util.scala:505:22] reg uops_6_is_rocc; // @[util.scala:505:22] reg uops_6_is_mov; // @[util.scala:505:22] reg [3:0] uops_6_ftq_idx; // @[util.scala:505:22] reg uops_6_edge_inst; // @[util.scala:505:22] reg [5:0] uops_6_pc_lob; // @[util.scala:505:22] reg uops_6_taken; // @[util.scala:505:22] reg uops_6_imm_rename; // @[util.scala:505:22] reg [2:0] uops_6_imm_sel; // @[util.scala:505:22] reg [4:0] uops_6_pimm; // @[util.scala:505:22] reg [19:0] uops_6_imm_packed; // @[util.scala:505:22] reg [1:0] uops_6_op1_sel; // @[util.scala:505:22] reg [2:0] uops_6_op2_sel; // @[util.scala:505:22] reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_6_fp_ctrl_wen; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_6_fp_ctrl_toint; // @[util.scala:505:22] reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_6_fp_ctrl_fma; // @[util.scala:505:22] reg uops_6_fp_ctrl_div; // @[util.scala:505:22] reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_6_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_6_rob_idx; // @[util.scala:505:22] reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_6_stq_idx; // @[util.scala:505:22] reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_6_pdst; // @[util.scala:505:22] reg [5:0] uops_6_prs1; // @[util.scala:505:22] reg [5:0] uops_6_prs2; // @[util.scala:505:22] reg [5:0] uops_6_prs3; // @[util.scala:505:22] reg [3:0] uops_6_ppred; // @[util.scala:505:22] reg uops_6_prs1_busy; // @[util.scala:505:22] reg uops_6_prs2_busy; // @[util.scala:505:22] reg uops_6_prs3_busy; // @[util.scala:505:22] reg uops_6_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_6_stale_pdst; // @[util.scala:505:22] reg uops_6_exception; // @[util.scala:505:22] reg [63:0] uops_6_exc_cause; // @[util.scala:505:22] reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_6_mem_size; // @[util.scala:505:22] reg uops_6_mem_signed; // @[util.scala:505:22] reg uops_6_uses_ldq; // @[util.scala:505:22] reg uops_6_uses_stq; // @[util.scala:505:22] reg uops_6_is_unique; // @[util.scala:505:22] reg uops_6_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22] reg uops_6_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_6_ldst; // @[util.scala:505:22] reg [5:0] uops_6_lrs1; // @[util.scala:505:22] reg [5:0] uops_6_lrs2; // @[util.scala:505:22] reg [5:0] uops_6_lrs3; // @[util.scala:505:22] reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22] reg uops_6_frs3_en; // @[util.scala:505:22] reg uops_6_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_6_fcn_op; // @[util.scala:505:22] reg uops_6_fp_val; // @[util.scala:505:22] reg [2:0] uops_6_fp_rm; // @[util.scala:505:22] reg [1:0] uops_6_fp_typ; // @[util.scala:505:22] reg uops_6_xcpt_pf_if; // @[util.scala:505:22] reg uops_6_xcpt_ae_if; // @[util.scala:505:22] reg uops_6_xcpt_ma_if; // @[util.scala:505:22] reg uops_6_bp_debug_if; // @[util.scala:505:22] reg uops_6_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_7_inst; // @[util.scala:505:22] reg [31:0] uops_7_debug_inst; // @[util.scala:505:22] reg uops_7_is_rvc; // @[util.scala:505:22] reg [33:0] uops_7_debug_pc; // @[util.scala:505:22] reg uops_7_iq_type_0; // @[util.scala:505:22] reg uops_7_iq_type_1; // @[util.scala:505:22] reg uops_7_iq_type_2; // @[util.scala:505:22] reg uops_7_iq_type_3; // @[util.scala:505:22] reg uops_7_fu_code_0; // @[util.scala:505:22] reg uops_7_fu_code_1; // @[util.scala:505:22] reg uops_7_fu_code_2; // @[util.scala:505:22] reg uops_7_fu_code_3; // @[util.scala:505:22] reg uops_7_fu_code_4; // @[util.scala:505:22] reg uops_7_fu_code_5; // @[util.scala:505:22] reg uops_7_fu_code_6; // @[util.scala:505:22] reg uops_7_fu_code_7; // @[util.scala:505:22] reg uops_7_fu_code_8; // @[util.scala:505:22] reg uops_7_fu_code_9; // @[util.scala:505:22] reg uops_7_iw_issued; // @[util.scala:505:22] reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_7_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_7_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_7_br_mask; // @[util.scala:505:22] wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_7_br_tag; // @[util.scala:505:22] reg [3:0] uops_7_br_type; // @[util.scala:505:22] reg uops_7_is_sfb; // @[util.scala:505:22] reg uops_7_is_fence; // @[util.scala:505:22] reg uops_7_is_fencei; // @[util.scala:505:22] reg uops_7_is_sfence; // @[util.scala:505:22] reg uops_7_is_amo; // @[util.scala:505:22] reg uops_7_is_eret; // @[util.scala:505:22] reg uops_7_is_sys_pc2epc; // @[util.scala:505:22] reg uops_7_is_rocc; // @[util.scala:505:22] reg uops_7_is_mov; // @[util.scala:505:22] reg [3:0] uops_7_ftq_idx; // @[util.scala:505:22] reg uops_7_edge_inst; // @[util.scala:505:22] reg [5:0] uops_7_pc_lob; // @[util.scala:505:22] reg uops_7_taken; // @[util.scala:505:22] reg uops_7_imm_rename; // @[util.scala:505:22] reg [2:0] uops_7_imm_sel; // @[util.scala:505:22] reg [4:0] uops_7_pimm; // @[util.scala:505:22] reg [19:0] uops_7_imm_packed; // @[util.scala:505:22] reg [1:0] uops_7_op1_sel; // @[util.scala:505:22] reg [2:0] uops_7_op2_sel; // @[util.scala:505:22] reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_7_fp_ctrl_wen; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_7_fp_ctrl_toint; // @[util.scala:505:22] reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_7_fp_ctrl_fma; // @[util.scala:505:22] reg uops_7_fp_ctrl_div; // @[util.scala:505:22] reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_7_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_7_rob_idx; // @[util.scala:505:22] reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_7_stq_idx; // @[util.scala:505:22] reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_7_pdst; // @[util.scala:505:22] reg [5:0] uops_7_prs1; // @[util.scala:505:22] reg [5:0] uops_7_prs2; // @[util.scala:505:22] reg [5:0] uops_7_prs3; // @[util.scala:505:22] reg [3:0] uops_7_ppred; // @[util.scala:505:22] reg uops_7_prs1_busy; // @[util.scala:505:22] reg uops_7_prs2_busy; // @[util.scala:505:22] reg uops_7_prs3_busy; // @[util.scala:505:22] reg uops_7_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_7_stale_pdst; // @[util.scala:505:22] reg uops_7_exception; // @[util.scala:505:22] reg [63:0] uops_7_exc_cause; // @[util.scala:505:22] reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_7_mem_size; // @[util.scala:505:22] reg uops_7_mem_signed; // @[util.scala:505:22] reg uops_7_uses_ldq; // @[util.scala:505:22] reg uops_7_uses_stq; // @[util.scala:505:22] reg uops_7_is_unique; // @[util.scala:505:22] reg uops_7_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22] reg uops_7_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_7_ldst; // @[util.scala:505:22] reg [5:0] uops_7_lrs1; // @[util.scala:505:22] reg [5:0] uops_7_lrs2; // @[util.scala:505:22] reg [5:0] uops_7_lrs3; // @[util.scala:505:22] reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22] reg uops_7_frs3_en; // @[util.scala:505:22] reg uops_7_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_7_fcn_op; // @[util.scala:505:22] reg uops_7_fp_val; // @[util.scala:505:22] reg [2:0] uops_7_fp_rm; // @[util.scala:505:22] reg [1:0] uops_7_fp_typ; // @[util.scala:505:22] reg uops_7_xcpt_pf_if; // @[util.scala:505:22] reg uops_7_xcpt_ae_if; // @[util.scala:505:22] reg uops_7_xcpt_ma_if; // @[util.scala:505:22] reg uops_7_bp_debug_if; // @[util.scala:505:22] reg uops_7_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_8_inst; // @[util.scala:505:22] reg [31:0] uops_8_debug_inst; // @[util.scala:505:22] reg uops_8_is_rvc; // @[util.scala:505:22] reg [33:0] uops_8_debug_pc; // @[util.scala:505:22] reg uops_8_iq_type_0; // @[util.scala:505:22] reg uops_8_iq_type_1; // @[util.scala:505:22] reg uops_8_iq_type_2; // @[util.scala:505:22] reg uops_8_iq_type_3; // @[util.scala:505:22] reg uops_8_fu_code_0; // @[util.scala:505:22] reg uops_8_fu_code_1; // @[util.scala:505:22] reg uops_8_fu_code_2; // @[util.scala:505:22] reg uops_8_fu_code_3; // @[util.scala:505:22] reg uops_8_fu_code_4; // @[util.scala:505:22] reg uops_8_fu_code_5; // @[util.scala:505:22] reg uops_8_fu_code_6; // @[util.scala:505:22] reg uops_8_fu_code_7; // @[util.scala:505:22] reg uops_8_fu_code_8; // @[util.scala:505:22] reg uops_8_fu_code_9; // @[util.scala:505:22] reg uops_8_iw_issued; // @[util.scala:505:22] reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_8_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_8_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_8_br_mask; // @[util.scala:505:22] wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_8_br_tag; // @[util.scala:505:22] reg [3:0] uops_8_br_type; // @[util.scala:505:22] reg uops_8_is_sfb; // @[util.scala:505:22] reg uops_8_is_fence; // @[util.scala:505:22] reg uops_8_is_fencei; // @[util.scala:505:22] reg uops_8_is_sfence; // @[util.scala:505:22] reg uops_8_is_amo; // @[util.scala:505:22] reg uops_8_is_eret; // @[util.scala:505:22] reg uops_8_is_sys_pc2epc; // @[util.scala:505:22] reg uops_8_is_rocc; // @[util.scala:505:22] reg uops_8_is_mov; // @[util.scala:505:22] reg [3:0] uops_8_ftq_idx; // @[util.scala:505:22] reg uops_8_edge_inst; // @[util.scala:505:22] reg [5:0] uops_8_pc_lob; // @[util.scala:505:22] reg uops_8_taken; // @[util.scala:505:22] reg uops_8_imm_rename; // @[util.scala:505:22] reg [2:0] uops_8_imm_sel; // @[util.scala:505:22] reg [4:0] uops_8_pimm; // @[util.scala:505:22] reg [19:0] uops_8_imm_packed; // @[util.scala:505:22] reg [1:0] uops_8_op1_sel; // @[util.scala:505:22] reg [2:0] uops_8_op2_sel; // @[util.scala:505:22] reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_8_fp_ctrl_wen; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_8_fp_ctrl_toint; // @[util.scala:505:22] reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_8_fp_ctrl_fma; // @[util.scala:505:22] reg uops_8_fp_ctrl_div; // @[util.scala:505:22] reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_8_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_8_rob_idx; // @[util.scala:505:22] reg [3:0] uops_8_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_8_stq_idx; // @[util.scala:505:22] reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_8_pdst; // @[util.scala:505:22] reg [5:0] uops_8_prs1; // @[util.scala:505:22] reg [5:0] uops_8_prs2; // @[util.scala:505:22] reg [5:0] uops_8_prs3; // @[util.scala:505:22] reg [3:0] uops_8_ppred; // @[util.scala:505:22] reg uops_8_prs1_busy; // @[util.scala:505:22] reg uops_8_prs2_busy; // @[util.scala:505:22] reg uops_8_prs3_busy; // @[util.scala:505:22] reg uops_8_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_8_stale_pdst; // @[util.scala:505:22] reg uops_8_exception; // @[util.scala:505:22] reg [63:0] uops_8_exc_cause; // @[util.scala:505:22] reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_8_mem_size; // @[util.scala:505:22] reg uops_8_mem_signed; // @[util.scala:505:22] reg uops_8_uses_ldq; // @[util.scala:505:22] reg uops_8_uses_stq; // @[util.scala:505:22] reg uops_8_is_unique; // @[util.scala:505:22] reg uops_8_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22] reg uops_8_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_8_ldst; // @[util.scala:505:22] reg [5:0] uops_8_lrs1; // @[util.scala:505:22] reg [5:0] uops_8_lrs2; // @[util.scala:505:22] reg [5:0] uops_8_lrs3; // @[util.scala:505:22] reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22] reg uops_8_frs3_en; // @[util.scala:505:22] reg uops_8_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_8_fcn_op; // @[util.scala:505:22] reg uops_8_fp_val; // @[util.scala:505:22] reg [2:0] uops_8_fp_rm; // @[util.scala:505:22] reg [1:0] uops_8_fp_typ; // @[util.scala:505:22] reg uops_8_xcpt_pf_if; // @[util.scala:505:22] reg uops_8_xcpt_ae_if; // @[util.scala:505:22] reg uops_8_xcpt_ma_if; // @[util.scala:505:22] reg uops_8_bp_debug_if; // @[util.scala:505:22] reg uops_8_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_9_inst; // @[util.scala:505:22] reg [31:0] uops_9_debug_inst; // @[util.scala:505:22] reg uops_9_is_rvc; // @[util.scala:505:22] reg [33:0] uops_9_debug_pc; // @[util.scala:505:22] reg uops_9_iq_type_0; // @[util.scala:505:22] reg uops_9_iq_type_1; // @[util.scala:505:22] reg uops_9_iq_type_2; // @[util.scala:505:22] reg uops_9_iq_type_3; // @[util.scala:505:22] reg uops_9_fu_code_0; // @[util.scala:505:22] reg uops_9_fu_code_1; // @[util.scala:505:22] reg uops_9_fu_code_2; // @[util.scala:505:22] reg uops_9_fu_code_3; // @[util.scala:505:22] reg uops_9_fu_code_4; // @[util.scala:505:22] reg uops_9_fu_code_5; // @[util.scala:505:22] reg uops_9_fu_code_6; // @[util.scala:505:22] reg uops_9_fu_code_7; // @[util.scala:505:22] reg uops_9_fu_code_8; // @[util.scala:505:22] reg uops_9_fu_code_9; // @[util.scala:505:22] reg uops_9_iw_issued; // @[util.scala:505:22] reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_9_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_9_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_9_br_mask; // @[util.scala:505:22] wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_9_br_tag; // @[util.scala:505:22] reg [3:0] uops_9_br_type; // @[util.scala:505:22] reg uops_9_is_sfb; // @[util.scala:505:22] reg uops_9_is_fence; // @[util.scala:505:22] reg uops_9_is_fencei; // @[util.scala:505:22] reg uops_9_is_sfence; // @[util.scala:505:22] reg uops_9_is_amo; // @[util.scala:505:22] reg uops_9_is_eret; // @[util.scala:505:22] reg uops_9_is_sys_pc2epc; // @[util.scala:505:22] reg uops_9_is_rocc; // @[util.scala:505:22] reg uops_9_is_mov; // @[util.scala:505:22] reg [3:0] uops_9_ftq_idx; // @[util.scala:505:22] reg uops_9_edge_inst; // @[util.scala:505:22] reg [5:0] uops_9_pc_lob; // @[util.scala:505:22] reg uops_9_taken; // @[util.scala:505:22] reg uops_9_imm_rename; // @[util.scala:505:22] reg [2:0] uops_9_imm_sel; // @[util.scala:505:22] reg [4:0] uops_9_pimm; // @[util.scala:505:22] reg [19:0] uops_9_imm_packed; // @[util.scala:505:22] reg [1:0] uops_9_op1_sel; // @[util.scala:505:22] reg [2:0] uops_9_op2_sel; // @[util.scala:505:22] reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_9_fp_ctrl_wen; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_9_fp_ctrl_toint; // @[util.scala:505:22] reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_9_fp_ctrl_fma; // @[util.scala:505:22] reg uops_9_fp_ctrl_div; // @[util.scala:505:22] reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_9_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_9_rob_idx; // @[util.scala:505:22] reg [3:0] uops_9_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_9_stq_idx; // @[util.scala:505:22] reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_9_pdst; // @[util.scala:505:22] reg [5:0] uops_9_prs1; // @[util.scala:505:22] reg [5:0] uops_9_prs2; // @[util.scala:505:22] reg [5:0] uops_9_prs3; // @[util.scala:505:22] reg [3:0] uops_9_ppred; // @[util.scala:505:22] reg uops_9_prs1_busy; // @[util.scala:505:22] reg uops_9_prs2_busy; // @[util.scala:505:22] reg uops_9_prs3_busy; // @[util.scala:505:22] reg uops_9_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_9_stale_pdst; // @[util.scala:505:22] reg uops_9_exception; // @[util.scala:505:22] reg [63:0] uops_9_exc_cause; // @[util.scala:505:22] reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_9_mem_size; // @[util.scala:505:22] reg uops_9_mem_signed; // @[util.scala:505:22] reg uops_9_uses_ldq; // @[util.scala:505:22] reg uops_9_uses_stq; // @[util.scala:505:22] reg uops_9_is_unique; // @[util.scala:505:22] reg uops_9_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22] reg uops_9_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_9_ldst; // @[util.scala:505:22] reg [5:0] uops_9_lrs1; // @[util.scala:505:22] reg [5:0] uops_9_lrs2; // @[util.scala:505:22] reg [5:0] uops_9_lrs3; // @[util.scala:505:22] reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22] reg uops_9_frs3_en; // @[util.scala:505:22] reg uops_9_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_9_fcn_op; // @[util.scala:505:22] reg uops_9_fp_val; // @[util.scala:505:22] reg [2:0] uops_9_fp_rm; // @[util.scala:505:22] reg [1:0] uops_9_fp_typ; // @[util.scala:505:22] reg uops_9_xcpt_pf_if; // @[util.scala:505:22] reg uops_9_xcpt_ae_if; // @[util.scala:505:22] reg uops_9_xcpt_ma_if; // @[util.scala:505:22] reg uops_9_bp_debug_if; // @[util.scala:505:22] reg uops_9_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_10_inst; // @[util.scala:505:22] reg [31:0] uops_10_debug_inst; // @[util.scala:505:22] reg uops_10_is_rvc; // @[util.scala:505:22] reg [33:0] uops_10_debug_pc; // @[util.scala:505:22] reg uops_10_iq_type_0; // @[util.scala:505:22] reg uops_10_iq_type_1; // @[util.scala:505:22] reg uops_10_iq_type_2; // @[util.scala:505:22] reg uops_10_iq_type_3; // @[util.scala:505:22] reg uops_10_fu_code_0; // @[util.scala:505:22] reg uops_10_fu_code_1; // @[util.scala:505:22] reg uops_10_fu_code_2; // @[util.scala:505:22] reg uops_10_fu_code_3; // @[util.scala:505:22] reg uops_10_fu_code_4; // @[util.scala:505:22] reg uops_10_fu_code_5; // @[util.scala:505:22] reg uops_10_fu_code_6; // @[util.scala:505:22] reg uops_10_fu_code_7; // @[util.scala:505:22] reg uops_10_fu_code_8; // @[util.scala:505:22] reg uops_10_fu_code_9; // @[util.scala:505:22] reg uops_10_iw_issued; // @[util.scala:505:22] reg uops_10_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_10_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_10_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_10_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_10_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_10_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_10_br_mask; // @[util.scala:505:22] wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_10_br_tag; // @[util.scala:505:22] reg [3:0] uops_10_br_type; // @[util.scala:505:22] reg uops_10_is_sfb; // @[util.scala:505:22] reg uops_10_is_fence; // @[util.scala:505:22] reg uops_10_is_fencei; // @[util.scala:505:22] reg uops_10_is_sfence; // @[util.scala:505:22] reg uops_10_is_amo; // @[util.scala:505:22] reg uops_10_is_eret; // @[util.scala:505:22] reg uops_10_is_sys_pc2epc; // @[util.scala:505:22] reg uops_10_is_rocc; // @[util.scala:505:22] reg uops_10_is_mov; // @[util.scala:505:22] reg [3:0] uops_10_ftq_idx; // @[util.scala:505:22] reg uops_10_edge_inst; // @[util.scala:505:22] reg [5:0] uops_10_pc_lob; // @[util.scala:505:22] reg uops_10_taken; // @[util.scala:505:22] reg uops_10_imm_rename; // @[util.scala:505:22] reg [2:0] uops_10_imm_sel; // @[util.scala:505:22] reg [4:0] uops_10_pimm; // @[util.scala:505:22] reg [19:0] uops_10_imm_packed; // @[util.scala:505:22] reg [1:0] uops_10_op1_sel; // @[util.scala:505:22] reg [2:0] uops_10_op2_sel; // @[util.scala:505:22] reg uops_10_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_10_fp_ctrl_wen; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_10_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_10_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_10_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_10_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_10_fp_ctrl_toint; // @[util.scala:505:22] reg uops_10_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_10_fp_ctrl_fma; // @[util.scala:505:22] reg uops_10_fp_ctrl_div; // @[util.scala:505:22] reg uops_10_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_10_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_10_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_10_rob_idx; // @[util.scala:505:22] reg [3:0] uops_10_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_10_stq_idx; // @[util.scala:505:22] reg [1:0] uops_10_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_10_pdst; // @[util.scala:505:22] reg [5:0] uops_10_prs1; // @[util.scala:505:22] reg [5:0] uops_10_prs2; // @[util.scala:505:22] reg [5:0] uops_10_prs3; // @[util.scala:505:22] reg [3:0] uops_10_ppred; // @[util.scala:505:22] reg uops_10_prs1_busy; // @[util.scala:505:22] reg uops_10_prs2_busy; // @[util.scala:505:22] reg uops_10_prs3_busy; // @[util.scala:505:22] reg uops_10_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_10_stale_pdst; // @[util.scala:505:22] reg uops_10_exception; // @[util.scala:505:22] reg [63:0] uops_10_exc_cause; // @[util.scala:505:22] reg [4:0] uops_10_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_10_mem_size; // @[util.scala:505:22] reg uops_10_mem_signed; // @[util.scala:505:22] reg uops_10_uses_ldq; // @[util.scala:505:22] reg uops_10_uses_stq; // @[util.scala:505:22] reg uops_10_is_unique; // @[util.scala:505:22] reg uops_10_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_10_csr_cmd; // @[util.scala:505:22] reg uops_10_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_10_ldst; // @[util.scala:505:22] reg [5:0] uops_10_lrs1; // @[util.scala:505:22] reg [5:0] uops_10_lrs2; // @[util.scala:505:22] reg [5:0] uops_10_lrs3; // @[util.scala:505:22] reg [1:0] uops_10_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:505:22] reg uops_10_frs3_en; // @[util.scala:505:22] reg uops_10_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_10_fcn_op; // @[util.scala:505:22] reg uops_10_fp_val; // @[util.scala:505:22] reg [2:0] uops_10_fp_rm; // @[util.scala:505:22] reg [1:0] uops_10_fp_typ; // @[util.scala:505:22] reg uops_10_xcpt_pf_if; // @[util.scala:505:22] reg uops_10_xcpt_ae_if; // @[util.scala:505:22] reg uops_10_xcpt_ma_if; // @[util.scala:505:22] reg uops_10_bp_debug_if; // @[util.scala:505:22] reg uops_10_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_10_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_10_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_11_inst; // @[util.scala:505:22] reg [31:0] uops_11_debug_inst; // @[util.scala:505:22] reg uops_11_is_rvc; // @[util.scala:505:22] reg [33:0] uops_11_debug_pc; // @[util.scala:505:22] reg uops_11_iq_type_0; // @[util.scala:505:22] reg uops_11_iq_type_1; // @[util.scala:505:22] reg uops_11_iq_type_2; // @[util.scala:505:22] reg uops_11_iq_type_3; // @[util.scala:505:22] reg uops_11_fu_code_0; // @[util.scala:505:22] reg uops_11_fu_code_1; // @[util.scala:505:22] reg uops_11_fu_code_2; // @[util.scala:505:22] reg uops_11_fu_code_3; // @[util.scala:505:22] reg uops_11_fu_code_4; // @[util.scala:505:22] reg uops_11_fu_code_5; // @[util.scala:505:22] reg uops_11_fu_code_6; // @[util.scala:505:22] reg uops_11_fu_code_7; // @[util.scala:505:22] reg uops_11_fu_code_8; // @[util.scala:505:22] reg uops_11_fu_code_9; // @[util.scala:505:22] reg uops_11_iw_issued; // @[util.scala:505:22] reg uops_11_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_11_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_11_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_11_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_11_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_11_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_11_br_mask; // @[util.scala:505:22] wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_11_br_tag; // @[util.scala:505:22] reg [3:0] uops_11_br_type; // @[util.scala:505:22] reg uops_11_is_sfb; // @[util.scala:505:22] reg uops_11_is_fence; // @[util.scala:505:22] reg uops_11_is_fencei; // @[util.scala:505:22] reg uops_11_is_sfence; // @[util.scala:505:22] reg uops_11_is_amo; // @[util.scala:505:22] reg uops_11_is_eret; // @[util.scala:505:22] reg uops_11_is_sys_pc2epc; // @[util.scala:505:22] reg uops_11_is_rocc; // @[util.scala:505:22] reg uops_11_is_mov; // @[util.scala:505:22] reg [3:0] uops_11_ftq_idx; // @[util.scala:505:22] reg uops_11_edge_inst; // @[util.scala:505:22] reg [5:0] uops_11_pc_lob; // @[util.scala:505:22] reg uops_11_taken; // @[util.scala:505:22] reg uops_11_imm_rename; // @[util.scala:505:22] reg [2:0] uops_11_imm_sel; // @[util.scala:505:22] reg [4:0] uops_11_pimm; // @[util.scala:505:22] reg [19:0] uops_11_imm_packed; // @[util.scala:505:22] reg [1:0] uops_11_op1_sel; // @[util.scala:505:22] reg [2:0] uops_11_op2_sel; // @[util.scala:505:22] reg uops_11_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_11_fp_ctrl_wen; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_11_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_11_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_11_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_11_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_11_fp_ctrl_toint; // @[util.scala:505:22] reg uops_11_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_11_fp_ctrl_fma; // @[util.scala:505:22] reg uops_11_fp_ctrl_div; // @[util.scala:505:22] reg uops_11_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_11_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_11_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_11_rob_idx; // @[util.scala:505:22] reg [3:0] uops_11_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_11_stq_idx; // @[util.scala:505:22] reg [1:0] uops_11_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_11_pdst; // @[util.scala:505:22] reg [5:0] uops_11_prs1; // @[util.scala:505:22] reg [5:0] uops_11_prs2; // @[util.scala:505:22] reg [5:0] uops_11_prs3; // @[util.scala:505:22] reg [3:0] uops_11_ppred; // @[util.scala:505:22] reg uops_11_prs1_busy; // @[util.scala:505:22] reg uops_11_prs2_busy; // @[util.scala:505:22] reg uops_11_prs3_busy; // @[util.scala:505:22] reg uops_11_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_11_stale_pdst; // @[util.scala:505:22] reg uops_11_exception; // @[util.scala:505:22] reg [63:0] uops_11_exc_cause; // @[util.scala:505:22] reg [4:0] uops_11_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_11_mem_size; // @[util.scala:505:22] reg uops_11_mem_signed; // @[util.scala:505:22] reg uops_11_uses_ldq; // @[util.scala:505:22] reg uops_11_uses_stq; // @[util.scala:505:22] reg uops_11_is_unique; // @[util.scala:505:22] reg uops_11_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_11_csr_cmd; // @[util.scala:505:22] reg uops_11_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_11_ldst; // @[util.scala:505:22] reg [5:0] uops_11_lrs1; // @[util.scala:505:22] reg [5:0] uops_11_lrs2; // @[util.scala:505:22] reg [5:0] uops_11_lrs3; // @[util.scala:505:22] reg [1:0] uops_11_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:505:22] reg uops_11_frs3_en; // @[util.scala:505:22] reg uops_11_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_11_fcn_op; // @[util.scala:505:22] reg uops_11_fp_val; // @[util.scala:505:22] reg [2:0] uops_11_fp_rm; // @[util.scala:505:22] reg [1:0] uops_11_fp_typ; // @[util.scala:505:22] reg uops_11_xcpt_pf_if; // @[util.scala:505:22] reg uops_11_xcpt_ae_if; // @[util.scala:505:22] reg uops_11_xcpt_ma_if; // @[util.scala:505:22] reg uops_11_bp_debug_if; // @[util.scala:505:22] reg uops_11_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_11_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_11_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_12_inst; // @[util.scala:505:22] reg [31:0] uops_12_debug_inst; // @[util.scala:505:22] reg uops_12_is_rvc; // @[util.scala:505:22] reg [33:0] uops_12_debug_pc; // @[util.scala:505:22] reg uops_12_iq_type_0; // @[util.scala:505:22] reg uops_12_iq_type_1; // @[util.scala:505:22] reg uops_12_iq_type_2; // @[util.scala:505:22] reg uops_12_iq_type_3; // @[util.scala:505:22] reg uops_12_fu_code_0; // @[util.scala:505:22] reg uops_12_fu_code_1; // @[util.scala:505:22] reg uops_12_fu_code_2; // @[util.scala:505:22] reg uops_12_fu_code_3; // @[util.scala:505:22] reg uops_12_fu_code_4; // @[util.scala:505:22] reg uops_12_fu_code_5; // @[util.scala:505:22] reg uops_12_fu_code_6; // @[util.scala:505:22] reg uops_12_fu_code_7; // @[util.scala:505:22] reg uops_12_fu_code_8; // @[util.scala:505:22] reg uops_12_fu_code_9; // @[util.scala:505:22] reg uops_12_iw_issued; // @[util.scala:505:22] reg uops_12_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_12_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_12_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_12_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_12_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_12_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_12_br_mask; // @[util.scala:505:22] wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_12_br_tag; // @[util.scala:505:22] reg [3:0] uops_12_br_type; // @[util.scala:505:22] reg uops_12_is_sfb; // @[util.scala:505:22] reg uops_12_is_fence; // @[util.scala:505:22] reg uops_12_is_fencei; // @[util.scala:505:22] reg uops_12_is_sfence; // @[util.scala:505:22] reg uops_12_is_amo; // @[util.scala:505:22] reg uops_12_is_eret; // @[util.scala:505:22] reg uops_12_is_sys_pc2epc; // @[util.scala:505:22] reg uops_12_is_rocc; // @[util.scala:505:22] reg uops_12_is_mov; // @[util.scala:505:22] reg [3:0] uops_12_ftq_idx; // @[util.scala:505:22] reg uops_12_edge_inst; // @[util.scala:505:22] reg [5:0] uops_12_pc_lob; // @[util.scala:505:22] reg uops_12_taken; // @[util.scala:505:22] reg uops_12_imm_rename; // @[util.scala:505:22] reg [2:0] uops_12_imm_sel; // @[util.scala:505:22] reg [4:0] uops_12_pimm; // @[util.scala:505:22] reg [19:0] uops_12_imm_packed; // @[util.scala:505:22] reg [1:0] uops_12_op1_sel; // @[util.scala:505:22] reg [2:0] uops_12_op2_sel; // @[util.scala:505:22] reg uops_12_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_12_fp_ctrl_wen; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_12_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_12_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_12_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_12_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_12_fp_ctrl_toint; // @[util.scala:505:22] reg uops_12_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_12_fp_ctrl_fma; // @[util.scala:505:22] reg uops_12_fp_ctrl_div; // @[util.scala:505:22] reg uops_12_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_12_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_12_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_12_rob_idx; // @[util.scala:505:22] reg [3:0] uops_12_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_12_stq_idx; // @[util.scala:505:22] reg [1:0] uops_12_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_12_pdst; // @[util.scala:505:22] reg [5:0] uops_12_prs1; // @[util.scala:505:22] reg [5:0] uops_12_prs2; // @[util.scala:505:22] reg [5:0] uops_12_prs3; // @[util.scala:505:22] reg [3:0] uops_12_ppred; // @[util.scala:505:22] reg uops_12_prs1_busy; // @[util.scala:505:22] reg uops_12_prs2_busy; // @[util.scala:505:22] reg uops_12_prs3_busy; // @[util.scala:505:22] reg uops_12_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_12_stale_pdst; // @[util.scala:505:22] reg uops_12_exception; // @[util.scala:505:22] reg [63:0] uops_12_exc_cause; // @[util.scala:505:22] reg [4:0] uops_12_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_12_mem_size; // @[util.scala:505:22] reg uops_12_mem_signed; // @[util.scala:505:22] reg uops_12_uses_ldq; // @[util.scala:505:22] reg uops_12_uses_stq; // @[util.scala:505:22] reg uops_12_is_unique; // @[util.scala:505:22] reg uops_12_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_12_csr_cmd; // @[util.scala:505:22] reg uops_12_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_12_ldst; // @[util.scala:505:22] reg [5:0] uops_12_lrs1; // @[util.scala:505:22] reg [5:0] uops_12_lrs2; // @[util.scala:505:22] reg [5:0] uops_12_lrs3; // @[util.scala:505:22] reg [1:0] uops_12_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:505:22] reg uops_12_frs3_en; // @[util.scala:505:22] reg uops_12_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_12_fcn_op; // @[util.scala:505:22] reg uops_12_fp_val; // @[util.scala:505:22] reg [2:0] uops_12_fp_rm; // @[util.scala:505:22] reg [1:0] uops_12_fp_typ; // @[util.scala:505:22] reg uops_12_xcpt_pf_if; // @[util.scala:505:22] reg uops_12_xcpt_ae_if; // @[util.scala:505:22] reg uops_12_xcpt_ma_if; // @[util.scala:505:22] reg uops_12_bp_debug_if; // @[util.scala:505:22] reg uops_12_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_12_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_12_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_13_inst; // @[util.scala:505:22] reg [31:0] uops_13_debug_inst; // @[util.scala:505:22] reg uops_13_is_rvc; // @[util.scala:505:22] reg [33:0] uops_13_debug_pc; // @[util.scala:505:22] reg uops_13_iq_type_0; // @[util.scala:505:22] reg uops_13_iq_type_1; // @[util.scala:505:22] reg uops_13_iq_type_2; // @[util.scala:505:22] reg uops_13_iq_type_3; // @[util.scala:505:22] reg uops_13_fu_code_0; // @[util.scala:505:22] reg uops_13_fu_code_1; // @[util.scala:505:22] reg uops_13_fu_code_2; // @[util.scala:505:22] reg uops_13_fu_code_3; // @[util.scala:505:22] reg uops_13_fu_code_4; // @[util.scala:505:22] reg uops_13_fu_code_5; // @[util.scala:505:22] reg uops_13_fu_code_6; // @[util.scala:505:22] reg uops_13_fu_code_7; // @[util.scala:505:22] reg uops_13_fu_code_8; // @[util.scala:505:22] reg uops_13_fu_code_9; // @[util.scala:505:22] reg uops_13_iw_issued; // @[util.scala:505:22] reg uops_13_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_13_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_13_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_13_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_13_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_13_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_13_br_mask; // @[util.scala:505:22] wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_13_br_tag; // @[util.scala:505:22] reg [3:0] uops_13_br_type; // @[util.scala:505:22] reg uops_13_is_sfb; // @[util.scala:505:22] reg uops_13_is_fence; // @[util.scala:505:22] reg uops_13_is_fencei; // @[util.scala:505:22] reg uops_13_is_sfence; // @[util.scala:505:22] reg uops_13_is_amo; // @[util.scala:505:22] reg uops_13_is_eret; // @[util.scala:505:22] reg uops_13_is_sys_pc2epc; // @[util.scala:505:22] reg uops_13_is_rocc; // @[util.scala:505:22] reg uops_13_is_mov; // @[util.scala:505:22] reg [3:0] uops_13_ftq_idx; // @[util.scala:505:22] reg uops_13_edge_inst; // @[util.scala:505:22] reg [5:0] uops_13_pc_lob; // @[util.scala:505:22] reg uops_13_taken; // @[util.scala:505:22] reg uops_13_imm_rename; // @[util.scala:505:22] reg [2:0] uops_13_imm_sel; // @[util.scala:505:22] reg [4:0] uops_13_pimm; // @[util.scala:505:22] reg [19:0] uops_13_imm_packed; // @[util.scala:505:22] reg [1:0] uops_13_op1_sel; // @[util.scala:505:22] reg [2:0] uops_13_op2_sel; // @[util.scala:505:22] reg uops_13_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_13_fp_ctrl_wen; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_13_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_13_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_13_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_13_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_13_fp_ctrl_toint; // @[util.scala:505:22] reg uops_13_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_13_fp_ctrl_fma; // @[util.scala:505:22] reg uops_13_fp_ctrl_div; // @[util.scala:505:22] reg uops_13_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_13_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_13_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_13_rob_idx; // @[util.scala:505:22] reg [3:0] uops_13_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_13_stq_idx; // @[util.scala:505:22] reg [1:0] uops_13_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_13_pdst; // @[util.scala:505:22] reg [5:0] uops_13_prs1; // @[util.scala:505:22] reg [5:0] uops_13_prs2; // @[util.scala:505:22] reg [5:0] uops_13_prs3; // @[util.scala:505:22] reg [3:0] uops_13_ppred; // @[util.scala:505:22] reg uops_13_prs1_busy; // @[util.scala:505:22] reg uops_13_prs2_busy; // @[util.scala:505:22] reg uops_13_prs3_busy; // @[util.scala:505:22] reg uops_13_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_13_stale_pdst; // @[util.scala:505:22] reg uops_13_exception; // @[util.scala:505:22] reg [63:0] uops_13_exc_cause; // @[util.scala:505:22] reg [4:0] uops_13_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_13_mem_size; // @[util.scala:505:22] reg uops_13_mem_signed; // @[util.scala:505:22] reg uops_13_uses_ldq; // @[util.scala:505:22] reg uops_13_uses_stq; // @[util.scala:505:22] reg uops_13_is_unique; // @[util.scala:505:22] reg uops_13_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_13_csr_cmd; // @[util.scala:505:22] reg uops_13_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_13_ldst; // @[util.scala:505:22] reg [5:0] uops_13_lrs1; // @[util.scala:505:22] reg [5:0] uops_13_lrs2; // @[util.scala:505:22] reg [5:0] uops_13_lrs3; // @[util.scala:505:22] reg [1:0] uops_13_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:505:22] reg uops_13_frs3_en; // @[util.scala:505:22] reg uops_13_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_13_fcn_op; // @[util.scala:505:22] reg uops_13_fp_val; // @[util.scala:505:22] reg [2:0] uops_13_fp_rm; // @[util.scala:505:22] reg [1:0] uops_13_fp_typ; // @[util.scala:505:22] reg uops_13_xcpt_pf_if; // @[util.scala:505:22] reg uops_13_xcpt_ae_if; // @[util.scala:505:22] reg uops_13_xcpt_ma_if; // @[util.scala:505:22] reg uops_13_bp_debug_if; // @[util.scala:505:22] reg uops_13_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_13_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_13_debug_tsrc; // @[util.scala:505:22] reg [31:0] uops_14_inst; // @[util.scala:505:22] reg [31:0] uops_14_debug_inst; // @[util.scala:505:22] reg uops_14_is_rvc; // @[util.scala:505:22] reg [33:0] uops_14_debug_pc; // @[util.scala:505:22] reg uops_14_iq_type_0; // @[util.scala:505:22] reg uops_14_iq_type_1; // @[util.scala:505:22] reg uops_14_iq_type_2; // @[util.scala:505:22] reg uops_14_iq_type_3; // @[util.scala:505:22] reg uops_14_fu_code_0; // @[util.scala:505:22] reg uops_14_fu_code_1; // @[util.scala:505:22] reg uops_14_fu_code_2; // @[util.scala:505:22] reg uops_14_fu_code_3; // @[util.scala:505:22] reg uops_14_fu_code_4; // @[util.scala:505:22] reg uops_14_fu_code_5; // @[util.scala:505:22] reg uops_14_fu_code_6; // @[util.scala:505:22] reg uops_14_fu_code_7; // @[util.scala:505:22] reg uops_14_fu_code_8; // @[util.scala:505:22] reg uops_14_fu_code_9; // @[util.scala:505:22] reg uops_14_iw_issued; // @[util.scala:505:22] reg uops_14_iw_issued_partial_agen; // @[util.scala:505:22] reg uops_14_iw_issued_partial_dgen; // @[util.scala:505:22] reg uops_14_iw_p1_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p2_speculative_child; // @[util.scala:505:22] reg uops_14_iw_p1_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p2_bypass_hint; // @[util.scala:505:22] reg uops_14_iw_p3_bypass_hint; // @[util.scala:505:22] reg uops_14_dis_col_sel; // @[util.scala:505:22] reg [3:0] uops_14_br_mask; // @[util.scala:505:22] wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:97:21, :505:22] reg [1:0] uops_14_br_tag; // @[util.scala:505:22] reg [3:0] uops_14_br_type; // @[util.scala:505:22] reg uops_14_is_sfb; // @[util.scala:505:22] reg uops_14_is_fence; // @[util.scala:505:22] reg uops_14_is_fencei; // @[util.scala:505:22] reg uops_14_is_sfence; // @[util.scala:505:22] reg uops_14_is_amo; // @[util.scala:505:22] reg uops_14_is_eret; // @[util.scala:505:22] reg uops_14_is_sys_pc2epc; // @[util.scala:505:22] reg uops_14_is_rocc; // @[util.scala:505:22] reg uops_14_is_mov; // @[util.scala:505:22] reg [3:0] uops_14_ftq_idx; // @[util.scala:505:22] reg uops_14_edge_inst; // @[util.scala:505:22] reg [5:0] uops_14_pc_lob; // @[util.scala:505:22] reg uops_14_taken; // @[util.scala:505:22] reg uops_14_imm_rename; // @[util.scala:505:22] reg [2:0] uops_14_imm_sel; // @[util.scala:505:22] reg [4:0] uops_14_pimm; // @[util.scala:505:22] reg [19:0] uops_14_imm_packed; // @[util.scala:505:22] reg [1:0] uops_14_op1_sel; // @[util.scala:505:22] reg [2:0] uops_14_op2_sel; // @[util.scala:505:22] reg uops_14_fp_ctrl_ldst; // @[util.scala:505:22] reg uops_14_fp_ctrl_wen; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren1; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren2; // @[util.scala:505:22] reg uops_14_fp_ctrl_ren3; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap12; // @[util.scala:505:22] reg uops_14_fp_ctrl_swap23; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagIn; // @[util.scala:505:22] reg [1:0] uops_14_fp_ctrl_typeTagOut; // @[util.scala:505:22] reg uops_14_fp_ctrl_fromint; // @[util.scala:505:22] reg uops_14_fp_ctrl_toint; // @[util.scala:505:22] reg uops_14_fp_ctrl_fastpipe; // @[util.scala:505:22] reg uops_14_fp_ctrl_fma; // @[util.scala:505:22] reg uops_14_fp_ctrl_div; // @[util.scala:505:22] reg uops_14_fp_ctrl_sqrt; // @[util.scala:505:22] reg uops_14_fp_ctrl_wflags; // @[util.scala:505:22] reg uops_14_fp_ctrl_vec; // @[util.scala:505:22] reg [4:0] uops_14_rob_idx; // @[util.scala:505:22] reg [3:0] uops_14_ldq_idx; // @[util.scala:505:22] reg [3:0] uops_14_stq_idx; // @[util.scala:505:22] reg [1:0] uops_14_rxq_idx; // @[util.scala:505:22] reg [5:0] uops_14_pdst; // @[util.scala:505:22] reg [5:0] uops_14_prs1; // @[util.scala:505:22] reg [5:0] uops_14_prs2; // @[util.scala:505:22] reg [5:0] uops_14_prs3; // @[util.scala:505:22] reg [3:0] uops_14_ppred; // @[util.scala:505:22] reg uops_14_prs1_busy; // @[util.scala:505:22] reg uops_14_prs2_busy; // @[util.scala:505:22] reg uops_14_prs3_busy; // @[util.scala:505:22] reg uops_14_ppred_busy; // @[util.scala:505:22] reg [5:0] uops_14_stale_pdst; // @[util.scala:505:22] reg uops_14_exception; // @[util.scala:505:22] reg [63:0] uops_14_exc_cause; // @[util.scala:505:22] reg [4:0] uops_14_mem_cmd; // @[util.scala:505:22] reg [1:0] uops_14_mem_size; // @[util.scala:505:22] reg uops_14_mem_signed; // @[util.scala:505:22] reg uops_14_uses_ldq; // @[util.scala:505:22] reg uops_14_uses_stq; // @[util.scala:505:22] reg uops_14_is_unique; // @[util.scala:505:22] reg uops_14_flush_on_commit; // @[util.scala:505:22] reg [2:0] uops_14_csr_cmd; // @[util.scala:505:22] reg uops_14_ldst_is_rs1; // @[util.scala:505:22] reg [5:0] uops_14_ldst; // @[util.scala:505:22] reg [5:0] uops_14_lrs1; // @[util.scala:505:22] reg [5:0] uops_14_lrs2; // @[util.scala:505:22] reg [5:0] uops_14_lrs3; // @[util.scala:505:22] reg [1:0] uops_14_dst_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:505:22] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:505:22] reg uops_14_frs3_en; // @[util.scala:505:22] reg uops_14_fcn_dw; // @[util.scala:505:22] reg [4:0] uops_14_fcn_op; // @[util.scala:505:22] reg uops_14_fp_val; // @[util.scala:505:22] reg [2:0] uops_14_fp_rm; // @[util.scala:505:22] reg [1:0] uops_14_fp_typ; // @[util.scala:505:22] reg uops_14_xcpt_pf_if; // @[util.scala:505:22] reg uops_14_xcpt_ae_if; // @[util.scala:505:22] reg uops_14_xcpt_ma_if; // @[util.scala:505:22] reg uops_14_bp_debug_if; // @[util.scala:505:22] reg uops_14_bp_xcpt_if; // @[util.scala:505:22] reg [2:0] uops_14_debug_fsrc; // @[util.scala:505:22] reg [2:0] uops_14_debug_tsrc; // @[util.scala:505:22] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:509:29] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :512:27] wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _do_enq_T_5 = _do_enq_T; // @[Decoupled.scala:51:35] wire _do_enq_T_8 = _do_enq_T_5; // @[util.scala:514:{39,99}] wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}] wire [15:0] _GEN = {{valids_0}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44] wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:458:7, :515:71] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}] wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}] wire _valids_0_T_7 = _valids_0_T_4; // @[util.scala:520:{31,80}] wire _valids_1_T_7 = _valids_1_T_4; // @[util.scala:520:{31,80}] wire _valids_2_T_7 = _valids_2_T_4; // @[util.scala:520:{31,80}] wire _valids_3_T_7 = _valids_3_T_4; // @[util.scala:520:{31,80}] wire _valids_4_T_7 = _valids_4_T_4; // @[util.scala:520:{31,80}] wire _valids_5_T_7 = _valids_5_T_4; // @[util.scala:520:{31,80}] wire _valids_6_T_7 = _valids_6_T_4; // @[util.scala:520:{31,80}] wire _valids_7_T_7 = _valids_7_T_4; // @[util.scala:520:{31,80}] wire _valids_8_T_7 = _valids_8_T_4; // @[util.scala:520:{31,80}] wire _valids_9_T_7 = _valids_9_T_4; // @[util.scala:520:{31,80}] wire _valids_10_T_7 = _valids_10_T_4; // @[util.scala:520:{31,80}] wire _valids_11_T_7 = _valids_11_T_4; // @[util.scala:520:{31,80}] wire _valids_12_T_7 = _valids_12_T_4; // @[util.scala:520:{31,80}] wire _valids_13_T_7 = _valids_13_T_4; // @[util.scala:520:{31,80}] wire _valids_14_T_7 = _valids_14_T_4; // @[util.scala:520:{31,80}] wire wrap = enq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = deq_ptr_value == 4'hE; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:458:7, :545:19] assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:458:7, :545:19] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:458:7, :545:19] assign io_deq_bits_way_en_0 = out_way_en; // @[util.scala:458:7, :545:19] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:458:7, :545:19] wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][33:0] _GEN_6 = {{uops_0_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_14_iq_type_0}, {uops_13_iq_type_0}, {uops_12_iq_type_0}, {uops_11_iq_type_0}, {uops_10_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_14_iq_type_1}, {uops_13_iq_type_1}, {uops_12_iq_type_1}, {uops_11_iq_type_1}, {uops_10_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_14_iq_type_2}, {uops_13_iq_type_2}, {uops_12_iq_type_2}, {uops_11_iq_type_2}, {uops_10_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_14_iq_type_3}, {uops_13_iq_type_3}, {uops_12_iq_type_3}, {uops_11_iq_type_3}, {uops_10_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21] assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_14_fu_code_0}, {uops_13_fu_code_0}, {uops_12_fu_code_0}, {uops_11_fu_code_0}, {uops_10_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_14_fu_code_1}, {uops_13_fu_code_1}, {uops_12_fu_code_1}, {uops_11_fu_code_1}, {uops_10_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_14_fu_code_2}, {uops_13_fu_code_2}, {uops_12_fu_code_2}, {uops_11_fu_code_2}, {uops_10_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_14_fu_code_3}, {uops_13_fu_code_3}, {uops_12_fu_code_3}, {uops_11_fu_code_3}, {uops_10_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_14_fu_code_4}, {uops_13_fu_code_4}, {uops_12_fu_code_4}, {uops_11_fu_code_4}, {uops_10_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_14_fu_code_5}, {uops_13_fu_code_5}, {uops_12_fu_code_5}, {uops_11_fu_code_5}, {uops_10_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_14_fu_code_6}, {uops_13_fu_code_6}, {uops_12_fu_code_6}, {uops_11_fu_code_6}, {uops_10_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_14_fu_code_7}, {uops_13_fu_code_7}, {uops_12_fu_code_7}, {uops_11_fu_code_7}, {uops_10_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_14_fu_code_8}, {uops_13_fu_code_8}, {uops_12_fu_code_8}, {uops_11_fu_code_8}, {uops_10_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_14_fu_code_9}, {uops_13_fu_code_9}, {uops_12_fu_code_9}, {uops_11_fu_code_9}, {uops_10_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21] assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_14_iw_issued}, {uops_13_iw_issued}, {uops_12_iw_issued}, {uops_11_iw_issued}, {uops_10_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_14_iw_issued_partial_agen}, {uops_13_iw_issued_partial_agen}, {uops_12_iw_issued_partial_agen}, {uops_11_iw_issued_partial_agen}, {uops_10_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_14_iw_issued_partial_dgen}, {uops_13_iw_issued_partial_dgen}, {uops_12_iw_issued_partial_dgen}, {uops_11_iw_issued_partial_dgen}, {uops_10_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_14_iw_p1_speculative_child}, {uops_13_iw_p1_speculative_child}, {uops_12_iw_p1_speculative_child}, {uops_11_iw_p1_speculative_child}, {uops_10_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_14_iw_p2_speculative_child}, {uops_13_iw_p2_speculative_child}, {uops_12_iw_p2_speculative_child}, {uops_11_iw_p2_speculative_child}, {uops_10_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_14_iw_p1_bypass_hint}, {uops_13_iw_p1_bypass_hint}, {uops_12_iw_p1_bypass_hint}, {uops_11_iw_p1_bypass_hint}, {uops_10_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_14_iw_p2_bypass_hint}, {uops_13_iw_p2_bypass_hint}, {uops_12_iw_p2_bypass_hint}, {uops_11_iw_p2_bypass_hint}, {uops_10_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_14_iw_p3_bypass_hint}, {uops_13_iw_p3_bypass_hint}, {uops_12_iw_p3_bypass_hint}, {uops_11_iw_p3_bypass_hint}, {uops_10_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21] assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_14_dis_col_sel}, {uops_13_dis_col_sel}, {uops_12_dis_col_sel}, {uops_11_dis_col_sel}, {uops_10_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_30 = {{uops_0_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21] assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_31 = {{uops_0_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21] assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_14_br_type}, {uops_13_br_type}, {uops_12_br_type}, {uops_11_br_type}, {uops_10_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21] assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21] assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_14_is_sfence}, {uops_13_is_sfence}, {uops_12_is_sfence}, {uops_11_is_sfence}, {uops_10_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21] assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_14_is_eret}, {uops_13_is_eret}, {uops_12_is_eret}, {uops_11_is_eret}, {uops_10_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21] assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_14_is_rocc}, {uops_13_is_rocc}, {uops_12_is_rocc}, {uops_11_is_rocc}, {uops_10_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21] assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_14_is_mov}, {uops_13_is_mov}, {uops_12_is_mov}, {uops_11_is_mov}, {uops_10_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21] assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21] assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21] assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21] assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_14_imm_rename}, {uops_13_imm_rename}, {uops_12_imm_rename}, {uops_11_imm_rename}, {uops_10_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_14_imm_sel}, {uops_13_imm_sel}, {uops_12_imm_sel}, {uops_11_imm_sel}, {uops_10_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_14_pimm}, {uops_13_pimm}, {uops_12_pimm}, {uops_11_pimm}, {uops_10_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21] assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21] assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_14_op1_sel}, {uops_13_op1_sel}, {uops_12_op1_sel}, {uops_11_op1_sel}, {uops_10_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_14_op2_sel}, {uops_13_op2_sel}, {uops_12_op2_sel}, {uops_11_op2_sel}, {uops_10_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21] assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_14_fp_ctrl_ldst}, {uops_13_fp_ctrl_ldst}, {uops_12_fp_ctrl_ldst}, {uops_11_fp_ctrl_ldst}, {uops_10_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_14_fp_ctrl_wen}, {uops_13_fp_ctrl_wen}, {uops_12_fp_ctrl_wen}, {uops_11_fp_ctrl_wen}, {uops_10_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_14_fp_ctrl_ren1}, {uops_13_fp_ctrl_ren1}, {uops_12_fp_ctrl_ren1}, {uops_11_fp_ctrl_ren1}, {uops_10_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_14_fp_ctrl_ren2}, {uops_13_fp_ctrl_ren2}, {uops_12_fp_ctrl_ren2}, {uops_11_fp_ctrl_ren2}, {uops_10_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_14_fp_ctrl_ren3}, {uops_13_fp_ctrl_ren3}, {uops_12_fp_ctrl_ren3}, {uops_11_fp_ctrl_ren3}, {uops_10_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_14_fp_ctrl_swap12}, {uops_13_fp_ctrl_swap12}, {uops_12_fp_ctrl_swap12}, {uops_11_fp_ctrl_swap12}, {uops_10_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_14_fp_ctrl_swap23}, {uops_13_fp_ctrl_swap23}, {uops_12_fp_ctrl_swap23}, {uops_11_fp_ctrl_swap23}, {uops_10_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_14_fp_ctrl_typeTagIn}, {uops_13_fp_ctrl_typeTagIn}, {uops_12_fp_ctrl_typeTagIn}, {uops_11_fp_ctrl_typeTagIn}, {uops_10_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_14_fp_ctrl_typeTagOut}, {uops_13_fp_ctrl_typeTagOut}, {uops_12_fp_ctrl_typeTagOut}, {uops_11_fp_ctrl_typeTagOut}, {uops_10_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_14_fp_ctrl_fromint}, {uops_13_fp_ctrl_fromint}, {uops_12_fp_ctrl_fromint}, {uops_11_fp_ctrl_fromint}, {uops_10_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_14_fp_ctrl_toint}, {uops_13_fp_ctrl_toint}, {uops_12_fp_ctrl_toint}, {uops_11_fp_ctrl_toint}, {uops_10_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_14_fp_ctrl_fastpipe}, {uops_13_fp_ctrl_fastpipe}, {uops_12_fp_ctrl_fastpipe}, {uops_11_fp_ctrl_fastpipe}, {uops_10_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_14_fp_ctrl_fma}, {uops_13_fp_ctrl_fma}, {uops_12_fp_ctrl_fma}, {uops_11_fp_ctrl_fma}, {uops_10_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_14_fp_ctrl_div}, {uops_13_fp_ctrl_div}, {uops_12_fp_ctrl_div}, {uops_11_fp_ctrl_div}, {uops_10_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_14_fp_ctrl_sqrt}, {uops_13_fp_ctrl_sqrt}, {uops_12_fp_ctrl_sqrt}, {uops_11_fp_ctrl_sqrt}, {uops_10_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_14_fp_ctrl_wflags}, {uops_13_fp_ctrl_wflags}, {uops_12_fp_ctrl_wflags}, {uops_11_fp_ctrl_wflags}, {uops_10_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_14_fp_ctrl_vec}, {uops_13_fp_ctrl_vec}, {uops_12_fp_ctrl_vec}, {uops_11_fp_ctrl_vec}, {uops_10_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_69 = {{uops_0_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_71 = {{uops_0_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21] assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_73 = {{uops_0_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_74 = {{uops_0_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_75 = {{uops_0_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_76 = {{uops_0_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_77 = {{uops_0_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21] assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21] assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21] assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21] assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21] assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21] assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21] assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21] assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_14_csr_cmd}, {uops_13_csr_cmd}, {uops_12_csr_cmd}, {uops_11_csr_cmd}, {uops_10_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21] assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21] assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21] assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21] assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_14_fcn_dw}, {uops_13_fcn_dw}, {uops_12_fcn_dw}, {uops_11_fcn_dw}, {uops_10_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_14_fcn_op}, {uops_13_fcn_op}, {uops_12_fcn_op}, {uops_11_fcn_op}, {uops_10_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21] assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_14_fp_rm}, {uops_13_fp_rm}, {uops_12_fp_rm}, {uops_11_fp_rm}, {uops_10_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_14_fp_typ}, {uops_13_fp_typ}, {uops_12_fp_typ}, {uops_11_fp_typ}, {uops_10_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21] assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21] assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21] assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21] assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:458:7, :515:71, :548:32] assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42] wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34] wire [3:0] _io_count_T = {4{maybe_full}}; // @[util.scala:509:29, :557:12] wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40] wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hF; // @[util.scala:551:34, :560:26] wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26] wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26] assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12] assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22] wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_132 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_133 = do_enq & _GEN_132; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_134 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_135 = do_enq & _GEN_134; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_136 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_137 = do_enq & _GEN_136; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_138 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_139 = do_enq & _GEN_138; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_140 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_141 = do_enq & _GEN_140; // @[util.scala:514:26, :520:18, :526:19, :528:35] wire _GEN_142 = do_enq & wrap; // @[Counter.scala:73:24] always @(posedge clock) begin // @[util.scala:458:7] if (reset) begin // @[util.scala:458:7] valids_0 <= 1'h0; // @[util.scala:504:26] valids_1 <= 1'h0; // @[util.scala:504:26] valids_2 <= 1'h0; // @[util.scala:504:26] valids_3 <= 1'h0; // @[util.scala:504:26] valids_4 <= 1'h0; // @[util.scala:504:26] valids_5 <= 1'h0; // @[util.scala:504:26] valids_6 <= 1'h0; // @[util.scala:504:26] valids_7 <= 1'h0; // @[util.scala:504:26] valids_8 <= 1'h0; // @[util.scala:504:26] valids_9 <= 1'h0; // @[util.scala:504:26] valids_10 <= 1'h0; // @[util.scala:504:26] valids_11 <= 1'h0; // @[util.scala:504:26] valids_12 <= 1'h0; // @[util.scala:504:26] valids_13 <= 1'h0; // @[util.scala:504:26] valids_14 <= 1'h0; // @[util.scala:504:26] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:509:29] end else begin // @[util.scala:458:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 | _valids_0_T_7); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 | _valids_1_T_7); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 | _valids_2_T_7); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 | _valids_3_T_7); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 | _valids_4_T_7); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 | _valids_5_T_7); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 | _valids_6_T_7); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 | _valids_8_T_7); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_133 | _valids_9_T_7); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_135 | _valids_10_T_7); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_137 | _valids_11_T_7); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_139 | _valids_12_T_7); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_141 | _valids_13_T_7); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & wrap_1) & (_GEN_142 | _valids_14_T_7); // @[Counter.scala:73:24] if (do_enq) // @[util.scala:514:26] enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (do_deq) // @[util.scala:515:26] deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18] maybe_full <= do_enq; // @[util.scala:509:29, :514:26] end if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_0) // @[util.scala:504:26] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_1) // @[util.scala:504:26] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_2) // @[util.scala:504:26] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_3) // @[util.scala:504:26] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_4) // @[util.scala:504:26] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_5) // @[util.scala:504:26] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_6) // @[util.scala:504:26] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_7) // @[util.scala:504:26] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_8) // @[util.scala:504:26] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_133) begin // @[util.scala:520:18, :526:19, :528:35] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_132) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_9) // @[util.scala:504:26] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_135) begin // @[util.scala:520:18, :526:19, :528:35] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_10_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_10_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_10_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_10_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_10_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_10_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_10_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_10_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_10_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_10_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_10_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_10_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_10_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_10_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_10_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_10_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_10_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_10_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_10_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_10_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_10_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_134) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_10) // @[util.scala:504:26] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_137) begin // @[util.scala:520:18, :526:19, :528:35] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_11_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_11_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_11_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_11_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_11_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_11_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_11_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_11_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_11_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_11_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_11_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_11_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_11_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_11_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_11_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_11_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_11_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_11_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_11_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_11_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_11_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_136) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_11) // @[util.scala:504:26] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_139) begin // @[util.scala:520:18, :526:19, :528:35] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_12_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_12_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_12_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_12_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_12_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_12_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_12_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_12_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_12_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_12_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_12_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_12_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_12_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_12_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_12_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_12_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_12_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_12_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_12_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_12_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_12_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_138) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_12) // @[util.scala:504:26] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_141) begin // @[util.scala:520:18, :526:19, :528:35] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_13_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_13_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_13_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_13_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_13_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_13_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_13_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_13_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_13_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_13_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_13_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_13_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_13_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_13_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_13_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_13_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_13_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_13_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_13_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_13_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_13_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & _GEN_140) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_13) // @[util.scala:504:26] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:97:21, :505:22] if (_GEN_142) begin // @[util.scala:520:18, :526:19, :528:35] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22] uops_14_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22] uops_14_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22] uops_14_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22] uops_14_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22] uops_14_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22] uops_14_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22] uops_14_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22] uops_14_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22] uops_14_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22] uops_14_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22] uops_14_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22] uops_14_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22] uops_14_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22] uops_14_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22] uops_14_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22] uops_14_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22] uops_14_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22] uops_14_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22] uops_14_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22] uops_14_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22] uops_14_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22] end if (do_enq & wrap) // @[Counter.scala:73:24] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22] else if (valids_14) // @[util.scala:504:26] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:97:21, :505:22] always @(posedge) ram_15x131 ram_ext ( // @[util.scala:503:22] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:514:26] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:458:7, :503:22] ); // @[util.scala:503:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] assign io_count = io_count_0; // @[util.scala:458:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File DCache.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.amba.AMBAProt import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing} import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => chisel3.experimental.annotate( new chisel3.experimental.ChiselAnnotation { def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } ) } class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) with CanHaveErrors { val correctable = (cacheParams.tagCode.canCorrect || cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W))) val uncorrectable = (cacheParams.tagCode.canDetect || cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W))) val bus = Valid(UInt(paddrBits.W)) } class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = UInt(untagBits.W) val write = Bool() val wdata = UInt((encBits * rowBytes / eccBytes).W) val wordMask = UInt((rowBytes / subWordBytes).W) val eccMask = UInt((wordBytes / eccBytes).W) val way_en = UInt(nWays.W) } class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Valid(new DCacheDataReq)) val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W))) }) require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits") val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits val data_arrays = Seq.tabulate(rowBits / subWordBits) { i => DescribedSRAM( name = s"${tileParams.baseName}_dcache_data_arrays_${i}", desc = "DCache Data Array", size = nSets * cacheBlockBytes / rowBytes, data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W)) ) } val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield { val valid = io.req.valid && ((data_arrays.size == 1).B || io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_)) val wData = wWords(i).grouped(encBits) array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice) } val data = array.read(addr, valid && !io.req.bits.write) data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq } (io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt } } class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val write = Bool() val addr = UInt(vaddrBitsExtended.W) val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) { override lazy val module = new DCacheModule(this) } class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) { val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2))) val s1_resp = Output(new TLBResp(coreDataBytes.log2)) val s2_kill = Input(Bool()) } class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits") require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode]) require(cacheParams.silentDrop || cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease") val usingRMW = eccBytes > 1 || usingAtomicsInCache val mmioOffset = outer.firstMMIO edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests val clock_en_reg = Reg(Bool()) io.cpu.clock_enabled := clock_en_reg val gated_clock = if (!cacheParams.clockGate) clock else ClockGate(clock, clock_en_reg, "dcache_clock_gate") class DCacheModuleImpl { // entering gated-clock domain val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages))) val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance) // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) /** Metadata Arbiter: * 0: Tag update on reset * 1: Tag update on ECC error * 2: Tag update on hit * 3: Tag update on refill * 4: Tag update on release * 5: Tag update on flush * 6: Tag update on probe * 7: Tag update on CPU request */ val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( name = s"${tileParams.baseName}_dcache_tag_array", desc = "DCache Tag Array", size = nSets, data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data)) ) // data val data = Module(new DCacheDataArray) /** Data Arbiter * 0: data from pending store buffer * 1: data from TL-D refill * 2: release to TL-A * 3: hit path to CPU */ val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits data.io.req.valid := dataArb.io.out.valid dataArb.io.out.ready := true.B metaArb.io.out.ready := clock_en_reg val tl_out_a = Wire(chiselTypeOf(tl_out.a)) tl_out.a <> { val a_queue_depth = outer.crossing match { case RationalCrossing(_) => // TODO make this depend on the actual ratio? if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2 else 2 min maxUncachedInFlight-1 case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing case _: CreditedCrossing => 0 // Adequate buffering within the crossing } Queue(tl_out_a, a_queue_depth, flow = true) } val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true)) tl_out.c <> q.io.deq (q.io.enq, q.io.count === 0.U) } else { (tl_out.c, true.B) } val s1_valid = RegNext(io.cpu.req.fire, false.B) val s1_probe = RegNext(tl_out.b.fire, false.B) val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :( val s1_nack = WireDefault(false.B) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_valid_not_nacked = s1_valid && !s1_nack val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B) val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B) val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write val s0_req = WireInit(io.cpu.req.bits) s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0)) s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0))) when (!metaArb.io.in(7).ready) { s0_req.phys := true.B } val s1_req = RegEnable(s0_req, s0_clk_en) val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0)) val s0_tlb_req = WireInit(io.tlb_port.req.bits) when (!io.tlb_port.req.fire) { s0_tlb_req.passthrough := s0_req.phys s0_tlb_req.vaddr := s0_req.addr s0_tlb_req.size := s0_req.size s0_tlb_req.cmd := s0_req.cmd s0_tlb_req.prv := s0_req.dprv s0_tlb_req.v := s0_req.dv } val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en || io.tlb_port.req.valid) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_readwrite = s1_read || s1_write val s1_sfence = s1_req.cmd === M_SFENCE || s1_req.cmd === M_HFENCEV || s1_req.cmd === M_HFENCEG val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0) val s1_flush_valid = Reg(Bool()) val s1_waw_hazard = Wire(Bool()) val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10) val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush val flushed = RegInit(true.B) val flushing = RegInit(false.B) val flushing_req = Reg(chiselTypeOf(s1_req)) val cached_grant_wait = RegInit(false.B) val resetting = RegInit(false.B) val flushCounter = RegInit((nSets * (nWays-1)).U(log2Ceil(nSets * nWays).W)) val release_ack_wait = RegInit(false.B) val release_ack_addr = Reg(UInt(paddrBits.W)) val release_state = RegInit(s_ready) val refill_way = Reg(UInt()) val any_pstore_valid = Wire(Bool()) val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty) val releaseWay = Wire(UInt()) io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack // I/O MSHRs val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B))) val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq)) val uncachedResp = WireInit(new HellaCacheReq, DontCare) // hit initiation path val s0_read = isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits) dataArb.io.in(3).bits := dataArb.io.in(1).bits dataArb.io.in(3).bits.write := false.B dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0)) dataArb.io.in(3).bits.wordMask := { val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) => val upper_mask = Mux((i >= wordBytes.log2).B || io.cpu.req.bits.size <= i.U, 0.U, ((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U) val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) | upper_mask val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in) upper ## lower } Fill(subWordBytes / eccBytes, mask) } dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(3).bits.way_en := ~0.U(nWays.W) when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B } val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en) val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en) metaArb.io.in(7).valid := io.cpu.req.valid metaArb.io.in(7).bits.write := false.B metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB) metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B } // address translation val s1_cmd_uses_tlb = s1_readwrite || s1_flush_line || s1_req.cmd === M_WOK io.ptw <> tlb.io.ptw tlb.io.kill := io.cpu.s2_kill || s2_tlb_req_valid && io.tlb_port.s2_kill tlb.io.req.valid := s1_tlb_req_valid || s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb tlb.io.req.bits := s1_tlb_req when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B } when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B } tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence tlb.io.sfence.bits.rs1 := s1_req.size(0) tlb.io.sfence.bits.rs2 := s1_req.size(1) tlb.io.sfence.bits.asid := io.cpu.s1_data.data tlb.io.sfence.bits.addr := s1_req.addr tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG io.tlb_port.req.ready := clock_en_reg io.tlb_port.s1_resp := tlb.io.resp when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B } pma_checker.io <> DontCare pma_checker.io.req.bits.passthrough := true.B pma_checker.io.req.bits.vaddr := s1_req.addr pma_checker.io.req.bits.size := s1_req.size pma_checker.io.req.bits.cmd := s1_req.cmd pma_checker.io.req.bits.prv := s1_req.dprv pma_checker.io.req.bits.v := s1_req.dv val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0)) val s1_victim_way = Wire(UInt()) val (s1_hit_way, s1_hit_state, s1_meta) = if (usingDataScratchpad) { val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) | io_mmio_address_prefix.get val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset) (inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt))) } else { val metaReq = metaArb.io.out val metaIdx = metaReq.bits.idx when (metaReq.valid && metaReq.bits.write) { val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask) } val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> tagLSB val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt val s1_meta_hit_state = ( s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U)) .reduce (_|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset)) (s1_meta_hit_way, s1_meta_hit_state, s1_meta) } val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way)) val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B))) val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded)) val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr) // for partial writes, s1_data.mask must be a subset of s1_mask_xwr assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR) val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B) val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR val s2_probe = RegNext(s1_probe, init=false.B) val releaseInFlight = s1_probe || s2_probe || release_state =/= s_ready val s2_not_nacked_in_s1 = RegNext(!s1_nack) val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1 val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1 val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill val s2_req = Reg(chiselTypeOf(io.cpu.req.bits)) val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0) val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0) val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp)) val s2_pma = Reg(chiselTypeOf(tlb.io.resp)) val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis when (s1_valid_not_nacked || s1_flush_valid) { s2_req := s1_req s2_req.addr := s1_paddr s2_tlb_xcpt := tlb.io.resp s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) } val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked || s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0)) val s2_read = isRead(s2_req.cmd) val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read || s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s1_meta_decoded = s1_meta.map(tECC.decode(_)) val s1_meta_clk_en = s1_valid_not_nacked || s1_flush_valid || s1_probe val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata)) val s2_meta_error = (s2_meta_uncorrectable_errors | s2_meta_correctable_errors).orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = { val wordsPerRow = rowBits / subWordBits val en = s1_valid || inWriteback || io.cpu.replay_next val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U)) val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits))) if (cacheParams.pipelineWayMux) { val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en) (for (i <- 0 until wordsPerRow) yield { val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en) val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i))) (0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_|_) }).asUInt } else { val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow)) (for (i <- 0 until wordsPerRow) yield { RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en) }).asUInt } } val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked || s1_flush_valid) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_store_merge = Wire(Bool()) val s2_hit_valid = s2_hit_state.isValid() val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_error = s2_data_decoded.map(_.error).orR val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit val s2_no_alloc_hazard = if (!usingVM || pgIdxBits >= untagBits) false.B else { // make sure that any in-flight non-allocating accesses are ordered before // any allocating accesses. this can only happen if aliasing is possible. val any_no_alloc_in_flight = Reg(Bool()) when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B } when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B } val s1_need_check = any_no_alloc_in_flight || s2_valid && s2_req.no_alloc val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req) val s1_uncached_hits = concerns.map { c => val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U val mask_match = (concern_wmask & s1_mask_xwr).orR || c._2.cmd === M_PWR || s1_req.cmd === M_PWR val cmd_match = isWrite(c._2.cmd) || isWrite(s1_req.cmd) c._1 && s1_need_check && cmd_match && addr_match && mask_match } val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked) s2_uncached_hits.orR } val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard || s2_store_merge) val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit val s2_uncached = !s2_pma.cacheable || s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR dontTouch(s2_valid_cached_miss) val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss || s2_valid_flush_line || s2_valid_data_error || s2_flush_valid) val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill val s2_victimize = s2_want_victimize && !s2_cannot_victimize val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked || s1_flush_valid)) val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way) val s2_victim_tag = Mux(s2_valid_data_error || s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag) val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) dontTouch(s2_victim_dirty) val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error && (supports_flush.B && s2_cmd_flush_all && flushed && !flushing || supports_flush.B && s2_cmd_flush_line && !s2_hit || s2_req.cmd === M_WOK) io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B } // tag updates on ECC errors val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected) metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked || s2_flush_valid_pre_tag_ecc || s2_probe) metaArb.io.in(1).bits.write := true.B metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors | Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors)) metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB)) metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits) metaArb.io.in(1).bits.data := tECC.encode { val new_meta = WireDefault(s2_first_meta_corrected) when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset } new_meta.asUInt } // tag updates on hit metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta metaArb.io.in(2).bits.write := !io.cpu.s2_kill metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt) // load reservations and TL error reporting val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC val lrscCount = RegInit(0.U) val lrscValid = lrscCount > lrscBackoff.U val lrscBackingOff = lrscCount > 0.U && !lrscValid val lrscAddr = Reg(UInt()) val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits) val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch) when ((s2_valid_hit && s2_lr && !cached_grant_wait || s2_valid_cached_miss) && !io.cpu.s2_kill) { lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U) lrscAddr := s2_req.addr >> blockOffBits } when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U } when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U } when (s1_probe) { lrscCount := 0.U } // don't perform data correction if it might clobber a recent store val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid || s2_valid) && usingDataScratchpad.B // pending store buffer val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write) val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write) val pstore1_storegen_data = WireDefault(pstore1_data) val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge val pstore2_valid = RegInit(false.B) val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard) val pstore_drain_on_miss = releaseInFlight || RegNext(io.cpu.s2_nack) val pstore1_held = RegInit(false.B) val pstore1_valid_likely = s2_valid && s2_write || pstore1_held def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill || pstore1_held val pstore1_valid = s2_store_valid || pstore1_held any_pstore_valid := pstore1_held || pstore2_valid val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) || pstore1_rmw) assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid) ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard") ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss") ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") def should_pstore_drain(truly: Bool) = { val s2_kill = truly && io.cpu.s2_kill !pstore1_merge_likely && (usingRMW.B && pstore_drain_structural || (((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) || pstore2_valid) && (pstore_drain_opportunistic || pstore_drain_on_miss))) } val pstore_drain = should_pstore_drain(true.B) pstore1_held := (s2_store_valid && !s2_store_merge || pstore1_held) && pstore2_valid && !pstore_drain val advance_pstore1 = (pstore1_valid || s2_valid_correct) && (pstore2_valid === pstore_drain) pstore2_valid := pstore2_valid && !pstore_drain || advance_pstore1 val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1) val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1) val pstore2_storegen_data = { for (i <- 0 until wordBytes) yield RegEnable(pstore1_storegen_data(8*(i+1)-1, 8*i), advance_pstore1 || pstore1_merge && pstore1_mask(i)) }.asUInt val pstore2_storegen_mask = { val mask = Reg(UInt(wordBytes.W)) when (advance_pstore1 || pstore1_merge) { val mergedMask = pstore1_mask | Mux(pstore1_merge, mask, 0.U) mask := ~Mux(s2_correct, 0.U, ~mergedMask) } mask } s2_store_merge := (if (eccBytes == 1) false.B else { ccover(pstore1_merge, "STORE_MERGED", "D$ store merged") // only merge stores to ECC granules that are already stored-to, to avoid // WAW hazards val wordMatch = (eccMask(pstore2_storegen_mask) | ~eccMask(pstore1_mask)).andR val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes)) val tagMatch = (s2_hit_way & pstore2_way).orR pstore2_valid && wordMatch && idxMatch && tagMatch }) dataArb.io.in(0).valid := should_pstore_drain(false.B) dataArb.io.in(0).bits.write := pstore_drain dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr) dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way) dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B) dataArb.io.in(0).bits.wordMask := { val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2)) FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask) } dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)) // store->load RAW hazard detection def s1Depends(addr: UInt, mask: UInt) = addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) && Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR) val s1_hazard = (pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) || (pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)) val s1_raw_hazard = s1_read && s1_hazard s1_waw_hazard := (if (eccBytes == 1) false.B else { ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") s1_write && (s1_hazard || needsRead(s1_req) && !s1_did_read) }) when (s1_valid && s1_raw_hazard) { s1_nack := true.B } // performance hints to processor io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) || !(!s2_waw_hazard || s2_store_merge) // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR val acquire_address = (s2_req.addr >> idxLSB) << idxLSB val access_address = s2_req.addr val a_size = s2_req.size val a_data = Fill(beatWords, pstore1_data) val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3) val get = edge.Get(a_source, access_address, a_size)._2 val put = edge.Put(a_source, access_address, a_size, a_data)._2 val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached)) WireDefault(new TLBundleA(edge.bundle), DontCare) } tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending || (s2_valid_cached_miss && !(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) && (cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty || !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, Mux(s2_req.cmd === M_PWR, putpartial, Mux(!s2_read, put, atomics)))) // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M.U || user_bit_cacheable // if the address is cacheable, enable outer caches x.bufferable := user_bit_cacheable x.modifiable := user_bit_cacheable x.readalloc := user_bit_cacheable x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B } // Set pending bits for outstanding TileLink transaction val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset when (tl_out_a.fire) { when (s2_uncached) { (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => when (s) { f := true.B r := s2_req r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD) } } }.otherwise { cached_grant_wait := true.B refill_way := s2_victim_or_hit_way } } // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_opc, grantIsUncached, grantIsUncachedData) = { val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck) val uncachedGrantOpcodesWithData = Seq(AccessAckData) val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData val whole_opc = tl_out.d.bits.opcode if (usingDataScratchpad) { assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes)) // the only valid TL-D messages are uncached, so we can do some pruning val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0) val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData) (opc, true.B, data) } else { (whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData)) } } tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached) val grantIsCached = d_opc.isOneOf(Grant, GrantData) val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit val grantIsRefill = d_opc === GrantData // Writes the data array val grantInProgress = RegInit(false.B) val blockProbeAfterGrantCount = RegInit(0.U) when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U } val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release) tl_out.d.ready := Mux(grantIsCached, (!d_first || tl_out.e.ready) && canAcceptCachedGrant, true.B) val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs) when (tl_out.d.fire) { when (grantIsCached) { grantInProgress := true.B assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") when(d_last) { cached_grant_wait := false.B grantInProgress := false.B blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U replacer.miss } } .elsewhen (grantIsUncached) { (uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) => when (s && d_last) { assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle! f := false.B } } when (grantIsUncachedData) { if (!cacheParams.separateUncachedResp) { if (!cacheParams.pipelineWayMux) s1_data_way := 1.U << nWays s2_req.cmd := M_XRD s2_req.size := uncachedResp.size s2_req.signed := uncachedResp.signed s2_req.tag := uncachedResp.tag s2_req.addr := { require(rowOffBits >= beatOffBits) val dontCareBits = s1_paddr >> rowOffBits << rowOffBits dontCareBits | uncachedResp.addr(beatOffBits-1, 0) } s2_uncached_resp_addr := uncachedResp.addr } } } .elsewhen (grantIsVoluntary) { assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! release_ack_wait := false.B } } // Finish TileLink transaction by issuing a GrantAck tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant tl_out.e.bits := edge.GrantAck(tl_out.d.bits) assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached)) // data refill // note this ready-valid signaling ignores E-channel backpressure, which // benignly means the data RAM might occasionally be redundantly written dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.e.valid := false.B tl_out.d.ready := false.B } if (!usingDataScratchpad) { dataArb.io.in(1).bits.write := true.B dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB | d_address_inc dataArb.io.in(1).bits.way_en := refill_way dataArb.io.in(1).bits.wdata := tl_d_data_encoded dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W) } else { dataArb.io.in(1).bits := dataArb.io.in(0).bits } // tag updates on refill // ignore backpressure from metaArb, which can only be caused by tag ECC // errors on hit-under-miss. failing to write the new tag will leave the // line invalid, so we'll simply request the line again later. metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied metaArb.io.in(3).bits.write := true.B metaArb.io.in(3).bits.way_en := refill_way metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt) if (!cacheParams.separateUncachedResp) { // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid when (grantIsUncachedData && (blockUncachedGrant || s1_valid)) { tl_out.d.ready := false.B // ...but insert bubble to guarantee grant's eventual forward progress when (tl_out.d.valid) { io.cpu.req.ready := false.B dataArb.io.in(1).valid := true.B dataArb.io.in(1).bits.write := false.B blockUncachedGrant := !dataArb.io.in(1).ready } } } ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked") // Handle an incoming TileLink Probe message val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U || lrscValid val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U val block_probe_for_ordering = releaseInFlight || block_probe_for_pending_release_ack || grantInProgress metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress || lrscBackingOff) tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress || block_probe_for_ordering || s1_valid || s2_valid) metaArb.io.in(6).bits.write := false.B metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address) metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data // replacement policy s1_victim_way := (if (replacer.perSet && nWays > 1) { val repl_array = Mem(nSets, UInt(replacer.nBits.W)) val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_state = Reg(UInt(replacer.nBits.W)) val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way)) val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx)) when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state } val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx) val wdata = Mux(resetting, 0.U, s2_new_repl_state) val wen = resetting || s2_repl_wen when (wen) { repl_array(waddr) := wdata } replacer.get_replace_way(s1_repl_state) } else { replacer.way }) // release val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c) val releaseRejected = Wire(Bool()) val s1_release_data_valid = RegNext(dataArb.io.in(2).fire) val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected) releaseRejected := s2_release_data_valid && !tl_out_c.fire val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid)) val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN) val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param) val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U) tl_out_c.valid := (s2_release_data_valid || (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait) tl_out_c.bits := nackResponseMessage val newCoh = WireDefault(probeNewCoh) releaseWay := s2_probe_way if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack) val discard_line = s2_valid_flush_line && s2_req.size(1) || s2_flush_valid && flushing_req.size(1) release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback, Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line || s2_flush_valid || s2_readwrite && !s2_hit_valid), s_voluntary_release, s_voluntary_write_meta)) probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB) } when (s2_probe) { val probeNack = WireDefault(true.B) when (s2_meta_error) { release_state := s_probe_retry }.elsewhen (s2_prb_ack_data) { release_state := s_probe_rep_dirty }.elsewhen (s2_probe_state.isValid()) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) }.otherwise { tl_out_c.valid := true.B probeNack := !releaseDone release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) } when (probeNack) { s1_nack := true.B } } when (release_state === s_probe_retry) { metaArb.io.in(6).valid := true.B metaArb.io.in(6).bits.idx := probeIdx(probe_bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address) when (metaArb.io.in(6).ready) { release_state := s_ready s1_probe := true.B } } when (release_state === s_probe_rep_miss) { tl_out_c.valid := true.B when (releaseDone) { release_state := s_ready } } when (release_state === s_probe_rep_clean) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state === s_probe_rep_dirty) { tl_out_c.bits := dirtyReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) { when (release_state === s_voluntary_release) { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param)._2 }.otherwise { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param, data = 0.U)._2 } newCoh := voluntaryNewCoh releaseWay := s2_victim_or_hit_way when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire && c_first) { release_ack_wait := true.B release_ack_addr := probe_bits.address } } tl_out_c.bits.source := probe_bits.source tl_out_c.bits.address := probe_bits.address tl_out_c.bits.data := s2_data_corrected tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } tl_out_c.bits.user.lift(AMBAProt).foreach { x => x.fetch := false.B x.secure := true.B x.privileged := true.B x.bufferable := true.B x.modifiable := true.B x.readalloc := true.B x.writealloc := true.B } dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false.B dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) | (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits) dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(2).bits.way_en := ~0.U(nWays.W) metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaArb.io.in(4).bits.write := true.B metaArb.io.in(4).bits.way_en := releaseWay metaArb.io.in(4).bits.idx := probeIdx(probe_bits) metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0)) metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt) when (metaArb.io.in(4).fire) { release_state := s_ready } // cached response (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false.B io.cpu.s2_uncached := s2_uncached && !s2_hit io.cpu.s2_paddr := s2_req.addr io.cpu.s2_gpa := s2_tlb_xcpt.gpa io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any // slave-port accesses, since they don't affect local memory ordering. val s1_isSlavePortAccess = s1_req.no_xcpt val s2_isSlavePortAccess = s2_req.no_xcpt io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess || s2_valid && !s2_isSlavePortAccess || cached_grant_wait || uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) || uncachedInFlight.asUInt.orR val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC))) } else { ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked") } // uncached response val s1_uncached_data_word = { val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val words = tl_out.d.bits.data.grouped(wordBits) words(word_idx) } val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next) val doUncachedResp = RegNext(io.cpu.replay_next) io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc || doUncachedResp) && !s2_data_error io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B when (doUncachedResp) { assert(!s2_valid_hit) io.cpu.resp.bits.replay := true.B io.cpu.resp.bits.addr := s2_uncached_resp_addr } io.cpu.uncached_resp.map { resp => resp.valid := tl_out.d.valid && grantIsUncachedData resp.bits.tag := uncachedResp.tag resp.bits.size := uncachedResp.size resp.bits.signed := uncachedResp.signed resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data resp.bits.data_raw := s1_uncached_data_word when (grantIsUncachedData && !resp.ready) { tl_out.d.ready := false.B } } // load data subword mux/sign extension val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_|_) val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_|_) val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) | s2_data_word val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data | s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_raw := s2_data_word io.cpu.resp.bits.store_data := pstore1_data // AMOs if (usingRMW) { val amoalus = (0 until coreDataBits / xLen).map { i => val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := pstore1_mask >> (i * xBytes) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR) amoalu.io.lhs := s2_data_word >> (i * xLen) amoalu.io.rhs := pstore1_data >> (i * xLen) amoalu } pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else { val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask)) amoalus.map(_.io.out_unmasked).asUInt & mask | s2_data_word_corrected & ~mask }) } else if (!usingAtomics) { assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") } if (coreParams.useVector) { edge.manager.managers.foreach { m => // Statically ensure that no-allocate accesses are permitted. // We could consider turning some of these into dynamic PMA checks. require(!m.supportsAcquireB || m.supportsGet, "With a vector unit, cacheable memory must support Get") require(!m.supportsAcquireT || m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial") } } // flushes if (!usingDataScratchpad) when (RegNext(reset.asBool)) { resetting := true.B } val flushCounterNext = flushCounter +& 1.U val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0) ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush") ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush") s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait metaArb.io.in(5).valid := flushing && !flushed metaArb.io.in(5).bits.write := false.B metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0) metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits) metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. if (supports_flush) { when (s2_valid_masked && s2_cmd_flush_all) { when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) { flushing := true.B flushing_req := s2_req } } when (tl_out_a.fire && !s2_uncached) { flushed := false.B } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) when (s2_flush_valid) { flushCounter := flushCounterNext when (flushDone) { flushed := true.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } when (flushed && release_state === s_ready && !release_ack_wait) { flushing := false.B } } } metaArb.io.in(0).valid := resetting metaArb.io.in(0).bits := metaArb.io.in(5).bits metaArb.io.in(0).bits.write := true.B metaArb.io.in(0).bits.way_en := ~0.U(nWays.W) metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt) when (resetting) { flushCounter := flushCounterNext when (flushDone) { resetting := false.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } // gate the clock clock_en_reg := !cacheParams.clockGate.B || io.ptw.customCSRs.disableDCacheClockGate || io.cpu.keep_clock_enabled || metaArb.io.out.valid || // subsumes resetting || flushing s1_probe || s2_probe || s1_valid || s2_valid || io.tlb_port.req.valid || s1_tlb_req_valid || s2_tlb_req_valid || pstore1_held || pstore2_valid || release_state =/= s_ready || release_ack_wait || !release_queue_empty || !tlb.io.req.ready || cached_grant_wait || uncachedInFlight.asUInt.orR || lrscCount > 0.U || blockProbeAfterGrantCount > 0.U // performance events io.cpu.perf.acquire := edge.done(tl_out_a) io.cpu.perf.release := edge.done(tl_out_c) io.cpu.perf.grant := tl_out.d.valid && d_last io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.storeBufferEmptyAfterLoad := !( (s1_valid && s1_write) || ((s2_valid && s2_write && !s2_waw_hazard) || pstore1_held) || pstore2_valid) io.cpu.perf.storeBufferEmptyAfterStore := !( (s1_valid && s1_write) || (s2_valid && s2_write && pstore1_rmw) || ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) && pstore2_valid)) io.cpu.perf.canAcceptStoreThenLoad := !( ((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) || (pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write))) io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) || pstore2_valid)) io.cpu.perf.blocked := { // stop reporting blocked just before unblocking to avoid overly conservative stalling val beatsBeforeEnd = outer.crossing match { case SynchronousCrossing(_) => 2 case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2 case _: AsynchronousCrossing => 1 // likewise case _: CreditedCrossing => 1 // likewise } val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else { val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W)) when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U } refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U } cached_grant_wait && !near_end_of_refill } // report errors val (data_error, data_error_uncorrectable, data_error_addr) = if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else { (RegNext(tl_out_c.fire && inWriteback && s2_data_error), RegNext(s2_data_error_uncorrectable), probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register } { val error_addr = Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)), data_error_addr >> idxLSB) << idxLSB io.errors.uncorrectable.foreach { u => u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable || data_error && data_error_uncorrectable u.bits := error_addr } io.errors.correctable.foreach { c => c.valid := metaArb.io.in(1).valid || data_error c.bits := error_addr io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } } } io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied || tl_out.d.bits.corrupt) io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } if (usingDataScratchpad) { val data_error_cover = Seq( property.CoverBoolean(!data_error, Seq("no_data_error")), property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), Seq(), "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { val data_error_type = Seq( property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")), property.CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) val request_source = if (supports_flush) { Seq( property.CoverBoolean(!flushing, Seq("access")), property.CoverBoolean(flushing, Seq("during_flush"))) } else { Seq(property.CoverBoolean(true.B, Seq("never_flush"))) } val tag_error_cover = Seq( property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")), property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) property.cover(new property.CrossProperty( Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } } // leaving gated-clock domain val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl } def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_)) def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask)) def likelyNeedsRead(req: HellaCacheReq) = { val res = !req.cmd.isOneOf(M_XWR, M_PFW) || req.size < log2Ceil(eccBytes).U assert(!needsRead(req) || res) res } def needsRead(req: HellaCacheReq) = isRead(req.cmd) || (isWrite(req.cmd) && (req.cmd === M_PWR || req.size < log2Ceil(eccBytes).U)) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (!usingDataScratchpad) ccover(cond, label, desc) require(!usingVM || tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB") def tagLSB: Int = untagBits def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB) def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = { val res = Wire(new TLBundleB(edge.bundle)) res :#= DontCare res.address := paddr res.source := (mmioOffset - 1).U res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))) else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2 } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module DCacheDataArray_2( // @[DCache.scala:49:7] input clock, // @[DCache.scala:49:7] input reset, // @[DCache.scala:49:7] input io_req_valid, // @[DCache.scala:50:14] input [7:0] io_req_bits_addr, // @[DCache.scala:50:14] input io_req_bits_write, // @[DCache.scala:50:14] input [63:0] io_req_bits_wdata, // @[DCache.scala:50:14] input io_req_bits_wordMask, // @[DCache.scala:50:14] input [7:0] io_req_bits_eccMask, // @[DCache.scala:50:14] input [3:0] io_req_bits_way_en, // @[DCache.scala:50:14] output [63:0] io_resp_0, // @[DCache.scala:50:14] output [63:0] io_resp_1, // @[DCache.scala:50:14] output [63:0] io_resp_2, // @[DCache.scala:50:14] output [63:0] io_resp_3 // @[DCache.scala:50:14] ); wire [255:0] _rerocc_tile_dcache_data_arrays_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_req_valid_0 = io_req_valid; // @[DCache.scala:49:7] wire [7:0] io_req_bits_addr_0 = io_req_bits_addr; // @[DCache.scala:49:7] wire io_req_bits_write_0 = io_req_bits_write; // @[DCache.scala:49:7] wire [63:0] io_req_bits_wdata_0 = io_req_bits_wdata; // @[DCache.scala:49:7] wire io_req_bits_wordMask_0 = io_req_bits_wordMask; // @[DCache.scala:49:7] wire [7:0] io_req_bits_eccMask_0 = io_req_bits_eccMask; // @[DCache.scala:49:7] wire [3:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[DCache.scala:49:7] wire _rdata_valid_T_1 = 1'h1; // @[DCache.scala:71:60] wire rdata_valid = io_req_valid_0; // @[DCache.scala:49:7, :71:30] wire [63:0] wWords_0 = io_req_bits_wdata_0; // @[package.scala:211:50] wire _rdata_valid_T = io_req_bits_wordMask_0; // @[DCache.scala:49:7, :71:83] wire [63:0] rdata_0_0; // @[package.scala:45:27] wire [63:0] rdata_0_1; // @[package.scala:45:27] wire [63:0] rdata_0_2; // @[package.scala:45:27] wire [63:0] rdata_0_3; // @[package.scala:45:27] wire [63:0] io_resp_0_0; // @[DCache.scala:49:7] wire [63:0] io_resp_1_0; // @[DCache.scala:49:7] wire [63:0] io_resp_2_0; // @[DCache.scala:49:7] wire [63:0] io_resp_3_0; // @[DCache.scala:49:7] wire eccMask_0 = io_req_bits_eccMask_0[0]; // @[DCache.scala:49:7, :56:82] wire eccMask_1 = io_req_bits_eccMask_0[1]; // @[DCache.scala:49:7, :56:82] wire eccMask_2 = io_req_bits_eccMask_0[2]; // @[DCache.scala:49:7, :56:82] wire eccMask_3 = io_req_bits_eccMask_0[3]; // @[DCache.scala:49:7, :56:82] wire eccMask_4 = io_req_bits_eccMask_0[4]; // @[DCache.scala:49:7, :56:82] wire eccMask_5 = io_req_bits_eccMask_0[5]; // @[DCache.scala:49:7, :56:82] wire eccMask_6 = io_req_bits_eccMask_0[6]; // @[DCache.scala:49:7, :56:82] wire eccMask_7 = io_req_bits_eccMask_0[7]; // @[DCache.scala:49:7, :56:82] wire _wMask_T = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_1 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_2 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_3 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_4 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_5 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_6 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_7 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108] wire wMask_0 = eccMask_0 & _wMask_T; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_1 = eccMask_1 & _wMask_T_1; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_2 = eccMask_2 & _wMask_T_2; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_3 = eccMask_3 & _wMask_T_3; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_4 = eccMask_4 & _wMask_T_4; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_5 = eccMask_5 & _wMask_T_5; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_6 = eccMask_6 & _wMask_T_6; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_7 = eccMask_7 & _wMask_T_7; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_8 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_9 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_10 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_11 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_12 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_13 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_14 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_15 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108] wire wMask_8 = eccMask_0 & _wMask_T_8; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_9 = eccMask_1 & _wMask_T_9; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_10 = eccMask_2 & _wMask_T_10; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_11 = eccMask_3 & _wMask_T_11; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_12 = eccMask_4 & _wMask_T_12; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_13 = eccMask_5 & _wMask_T_13; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_14 = eccMask_6 & _wMask_T_14; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_15 = eccMask_7 & _wMask_T_15; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_16 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_17 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_18 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_19 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_20 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_21 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_22 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_23 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108] wire wMask_16 = eccMask_0 & _wMask_T_16; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_17 = eccMask_1 & _wMask_T_17; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_18 = eccMask_2 & _wMask_T_18; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_19 = eccMask_3 & _wMask_T_19; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_20 = eccMask_4 & _wMask_T_20; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_21 = eccMask_5 & _wMask_T_21; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_22 = eccMask_6 & _wMask_T_22; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_23 = eccMask_7 & _wMask_T_23; // @[DCache.scala:56:82, :57:{87,108}] wire _wMask_T_24 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_25 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_26 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_27 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_28 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_29 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_30 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire _wMask_T_31 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108] wire wMask_24 = eccMask_0 & _wMask_T_24; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_25 = eccMask_1 & _wMask_T_25; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_26 = eccMask_2 & _wMask_T_26; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_27 = eccMask_3 & _wMask_T_27; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_28 = eccMask_4 & _wMask_T_28; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_29 = eccMask_5 & _wMask_T_29; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_30 = eccMask_6 & _wMask_T_30; // @[DCache.scala:56:82, :57:{87,108}] wire wMask_31 = eccMask_7 & _wMask_T_31; // @[DCache.scala:56:82, :57:{87,108}] wire [4:0] addr = io_req_bits_addr_0[7:3]; // @[DCache.scala:49:7, :59:31] wire [4:0] _rdata_data_WIRE = addr; // @[DCache.scala:59:31, :77:26] wire _rdata_T; // @[DCache.scala:72:17] wire _rdata_data_T_1; // @[DCache.scala:77:39] wire [7:0] _rdata_WIRE_0; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_1; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_2; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_3; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_4; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_5; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_6; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_7; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_8; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_9; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_10; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_11; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_12; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_13; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_14; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_15; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_16; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_17; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_18; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_19; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_20; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_21; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_22; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_23; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_24; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_25; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_26; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_27; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_28; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_29; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_30; // @[DCache.scala:75:32] wire [7:0] _rdata_WIRE_31; // @[DCache.scala:75:32] assign _rdata_T = rdata_valid & io_req_bits_write_0; // @[DCache.scala:49:7, :71:30, :72:17] wire [7:0] rdata_wData_0 = wWords_0[7:0]; // @[package.scala:211:50] assign _rdata_WIRE_0 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_8 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_16 = rdata_wData_0; // @[package.scala:211:50] assign _rdata_WIRE_24 = rdata_wData_0; // @[package.scala:211:50] wire [7:0] rdata_wData_1 = wWords_0[15:8]; // @[package.scala:211:50] assign _rdata_WIRE_1 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_9 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_17 = rdata_wData_1; // @[package.scala:211:50] assign _rdata_WIRE_25 = rdata_wData_1; // @[package.scala:211:50] wire [7:0] rdata_wData_2 = wWords_0[23:16]; // @[package.scala:211:50] assign _rdata_WIRE_2 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_10 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_18 = rdata_wData_2; // @[package.scala:211:50] assign _rdata_WIRE_26 = rdata_wData_2; // @[package.scala:211:50] wire [7:0] rdata_wData_3 = wWords_0[31:24]; // @[package.scala:211:50] assign _rdata_WIRE_3 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_11 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_19 = rdata_wData_3; // @[package.scala:211:50] assign _rdata_WIRE_27 = rdata_wData_3; // @[package.scala:211:50] wire [7:0] rdata_wData_4 = wWords_0[39:32]; // @[package.scala:211:50] assign _rdata_WIRE_4 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_12 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_20 = rdata_wData_4; // @[package.scala:211:50] assign _rdata_WIRE_28 = rdata_wData_4; // @[package.scala:211:50] wire [7:0] rdata_wData_5 = wWords_0[47:40]; // @[package.scala:211:50] assign _rdata_WIRE_5 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_13 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_21 = rdata_wData_5; // @[package.scala:211:50] assign _rdata_WIRE_29 = rdata_wData_5; // @[package.scala:211:50] wire [7:0] rdata_wData_6 = wWords_0[55:48]; // @[package.scala:211:50] assign _rdata_WIRE_6 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_14 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_22 = rdata_wData_6; // @[package.scala:211:50] assign _rdata_WIRE_30 = rdata_wData_6; // @[package.scala:211:50] wire [7:0] rdata_wData_7 = wWords_0[63:56]; // @[package.scala:211:50] assign _rdata_WIRE_7 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_15 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_23 = rdata_wData_7; // @[package.scala:211:50] assign _rdata_WIRE_31 = rdata_wData_7; // @[package.scala:211:50] wire _rdata_data_T = ~io_req_bits_write_0; // @[DCache.scala:49:7, :77:42] assign _rdata_data_T_1 = rdata_valid & _rdata_data_T; // @[DCache.scala:71:30, :77:{39,42}] wire [15:0] rdata_lo_lo = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[15:0]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[31:16]; // @[package.scala:45:27] wire [31:0] rdata_lo = {rdata_lo_hi, rdata_lo_lo}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[47:32]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[63:48]; // @[package.scala:45:27] wire [31:0] rdata_hi = {rdata_hi_hi, rdata_hi_lo}; // @[package.scala:45:27] assign rdata_0_0 = {rdata_hi, rdata_lo}; // @[package.scala:45:27] assign io_resp_0_0 = rdata_0_0; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_1 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[79:64]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_1 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[95:80]; // @[package.scala:45:27] wire [31:0] rdata_lo_1 = {rdata_lo_hi_1, rdata_lo_lo_1}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_1 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[111:96]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_1 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[127:112]; // @[package.scala:45:27] wire [31:0] rdata_hi_1 = {rdata_hi_hi_1, rdata_hi_lo_1}; // @[package.scala:45:27] assign rdata_0_1 = {rdata_hi_1, rdata_lo_1}; // @[package.scala:45:27] assign io_resp_1_0 = rdata_0_1; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_2 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[143:128]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_2 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[159:144]; // @[package.scala:45:27] wire [31:0] rdata_lo_2 = {rdata_lo_hi_2, rdata_lo_lo_2}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_2 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[175:160]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_2 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[191:176]; // @[package.scala:45:27] wire [31:0] rdata_hi_2 = {rdata_hi_hi_2, rdata_hi_lo_2}; // @[package.scala:45:27] assign rdata_0_2 = {rdata_hi_2, rdata_lo_2}; // @[package.scala:45:27] assign io_resp_2_0 = rdata_0_2; // @[package.scala:45:27] wire [15:0] rdata_lo_lo_3 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[207:192]; // @[package.scala:45:27] wire [15:0] rdata_lo_hi_3 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[223:208]; // @[package.scala:45:27] wire [31:0] rdata_lo_3 = {rdata_lo_hi_3, rdata_lo_lo_3}; // @[package.scala:45:27] wire [15:0] rdata_hi_lo_3 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[239:224]; // @[package.scala:45:27] wire [15:0] rdata_hi_hi_3 = _rerocc_tile_dcache_data_arrays_0_RW0_rdata[255:240]; // @[package.scala:45:27] wire [31:0] rdata_hi_3 = {rdata_hi_hi_3, rdata_hi_lo_3}; // @[package.scala:45:27] assign rdata_0_3 = {rdata_hi_3, rdata_lo_3}; // @[package.scala:45:27] assign io_resp_3_0 = rdata_0_3; // @[package.scala:45:27] rerocc_tile_dcache_data_arrays_0_0 rerocc_tile_dcache_data_arrays_0 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_rdata_T ? addr : _rdata_data_WIRE), // @[DescribedSRAM.scala:17:26] .RW0_en (_rdata_data_T_1 | _rdata_T), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (io_req_bits_write_0), // @[DCache.scala:49:7] .RW0_wdata ({_rdata_WIRE_31, _rdata_WIRE_30, _rdata_WIRE_29, _rdata_WIRE_28, _rdata_WIRE_27, _rdata_WIRE_26, _rdata_WIRE_25, _rdata_WIRE_24, _rdata_WIRE_23, _rdata_WIRE_22, _rdata_WIRE_21, _rdata_WIRE_20, _rdata_WIRE_19, _rdata_WIRE_18, _rdata_WIRE_17, _rdata_WIRE_16, _rdata_WIRE_15, _rdata_WIRE_14, _rdata_WIRE_13, _rdata_WIRE_12, _rdata_WIRE_11, _rdata_WIRE_10, _rdata_WIRE_9, _rdata_WIRE_8, _rdata_WIRE_7, _rdata_WIRE_6, _rdata_WIRE_5, _rdata_WIRE_4, _rdata_WIRE_3, _rdata_WIRE_2, _rdata_WIRE_1, _rdata_WIRE_0}), // @[DescribedSRAM.scala:17:26] .RW0_rdata (_rerocc_tile_dcache_data_arrays_0_RW0_rdata), .RW0_wmask ({wMask_31, wMask_30, wMask_29, wMask_28, wMask_27, wMask_26, wMask_25, wMask_24, wMask_23, wMask_22, wMask_21, wMask_20, wMask_19, wMask_18, wMask_17, wMask_16, wMask_15, wMask_14, wMask_13, wMask_12, wMask_11, wMask_10, wMask_9, wMask_8, wMask_7, wMask_6, wMask_5, wMask_4, wMask_3, wMask_2, wMask_1, wMask_0}) // @[DescribedSRAM.scala:17:26] ); // @[DescribedSRAM.scala:17:26] assign io_resp_0 = io_resp_0_0; // @[DCache.scala:49:7] assign io_resp_1 = io_resp_1_0; // @[DCache.scala:49:7] assign io_resp_2 = io_resp_2_0; // @[DCache.scala:49:7] assign io_resp_3 = io_resp_3_0; // @[DCache.scala:49:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } }
module Repeater_TLBundleA_a29d128s7k1z4u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [28:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [15:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [127:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [28:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [15:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output [127:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [6:0] saved_source; // @[Repeater.scala:21:18] reg [28:0] saved_address; // @[Repeater.scala:21:18] reg [15:0] saved_mask; // @[Repeater.scala:21:18] reg [127:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18] saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18] saved_data <= io_enq_bits_data; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File Plic.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.experimental._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.{Annotated, MuxT, property} import scala.math.min import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.SeqToAugmentedSeq class GatewayPLICIO extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val complete = Input(Bool()) } class LevelGateway extends Module { val io = IO(new Bundle { val interrupt = Input(Bool()) val plic = new GatewayPLICIO }) val inFlight = RegInit(false.B) when (io.interrupt && io.plic.ready) { inFlight := true.B } when (io.plic.complete) { inFlight := false.B } io.plic.valid := io.interrupt && !inFlight } object PLICConsts { def maxDevices = 1023 def maxMaxHarts = 15872 def priorityBase = 0x0 def pendingBase = 0x1000 def enableBase = 0x2000 def hartBase = 0x200000 def claimOffset = 4 def priorityBytes = 4 def enableOffset(i: Int) = i * ((maxDevices+7)/8) def hartOffset(i: Int) = i * 0x1000 def enableBase(i: Int):Int = enableOffset(i) + enableBase def hartBase(i: Int):Int = hartOffset(i) + hartBase def size(maxHarts: Int): Int = { require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}") 1 << log2Ceil(hartBase(maxHarts)) } require(hartBase >= enableBase(maxMaxHarts)) } case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts) { require (maxPriorities >= 0) def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1) } case object PLICKey extends Field[Option[PLICParams]](None) case class PLICAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object PLICAttachKey extends Field(PLICAttachParams()) /** Platform-Level Interrupt Controller */ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // plic0 => max devices 1023 val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) { override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val extra = Map( "interrupt-controller" -> Nil, "riscv,ndev" -> Seq(ResourceInt(nDevices)), "riscv,max-priority" -> Seq(ResourceInt(nPriorities)), "#interrupt-cells" -> Seq(ResourceInt(1))) Description(name, mapping ++ extra) } } val node : TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes, undefZero = true, concurrency = 1) // limiting concurrency handles RAW hazards on claim registers val intnode: IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false, inputRequiresOutput = false) /* Negotiated sizes */ def nDevices: Int = intnode.edges.in.map(_.source.num).sum def minPriorities = min(params.maxPriorities, nDevices) def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1 def nHarts = intnode.edges.out.map(_.source.num).sum // Assign all the devices unique ranges lazy val sources = intnode.edges.in.map(_.source) lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten ResourceBinding { flatSources.foreach { s => s.resources.foreach { r => // +1 because interrupt 0 is reserved (s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) } } } } lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) val (io_devices, edgesIn) = intnode.in.unzip val (io_harts, _) = intnode.out.unzip // Compact the interrupt vector the same way val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence val harts = io_harts.flatten def getNInterrupts = interrupts.size println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):") flatSources.foreach { s => // +1 because 0 is reserved, +1-1 because the range is half-open println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}") } println("") require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}") require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}") require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}") require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}") // For now, use LevelGateways for all TL2 interrupts val gateways = interrupts.map { case i => val gateway = Module(new LevelGateway) gateway.io.interrupt := i gateway.io.plic } val prioBits = log2Ceil(nPriorities+1) val priority = if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W))) else WireDefault(VecInit.fill(nDevices max 1)(1.U)) val threshold = if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W))) else WireDefault(VecInit.fill(nHarts)(0.U)) val pending = RegInit(VecInit.fill(nDevices max 1){false.B}) /* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */ val firstEnable = nDevices min 7 val fullEnables = (nDevices - firstEnable) / 8 val tailEnable = nDevices - firstEnable - 8*fullEnables def enableRegs = (Reg(UInt(firstEnable.W)) +: Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++ (if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None) val enables = Seq.fill(nHarts) { enableRegs } val enableVec = VecInit(enables.map(x => Cat(x.reverse))) val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W)))) val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W))) val pendingUInt = Cat(pending.reverse) if(nDevices > 0) { for (hart <- 0 until nHarts) { val fanin = Module(new PLICFanIn(nDevices, prioBits)) fanin.io.prio := priority fanin.io.ip := enableVec(hart) & pendingUInt maxDevs(hart) := fanin.io.dev harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages) } } // Priority registers are 32-bit aligned so treat each as its own group. // Otherwise, the off-by-one nature of the priority registers gets confusing. require(PLICConsts.priorityBytes == 4, s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}") def priorityRegDesc(i: Int) = RegFieldDesc( name = s"priority_$i", desc = s"Acting priority of interrupt source $i", group = Some(s"priority_${i}"), groupDesc = Some(s"Acting priority of interrupt source ${i}"), reset = if (nPriorities > 0) None else Some(1)) def pendingRegDesc(i: Int) = RegFieldDesc( name = s"pending_$i", desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.", group = Some("pending"), groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."), volatile = true) def enableRegDesc(i: Int, j: Int, wide: Int) = { val low = if (j == 0) 1 else j*8 val high = low + wide - 1 RegFieldDesc( name = s"enables_${j}", desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.", group = Some(s"enables_${i}"), groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source.")) } def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, priorityRegDesc(i)) } else { RegField.r(prioBits, x, priorityRegDesc(i)) } val priorityRegFields = priority.zipWithIndex.map { case (p, i) => PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) -> Seq(priorityRegField(p, i+1)) } val pendingRegFields = Seq(PLICConsts.pendingBase -> (RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))})) val enableRegFields = enables.zipWithIndex.map { case (e, i) => PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) => RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) } // When a hart reads a claim/complete register, then the // device which is currently its highest priority is no longer pending. // This code exploits the fact that, practically, only one claim/complete // register can be read at a time. We check for this because if the address map // were to change, it may no longer be true. // Note: PLIC doesn't care which hart reads the register. val claimer = Wire(Vec(nHarts, Bool())) assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_) val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools) ((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) => g.ready := !p when (c || g.valid) { p := !c } } // When a hart writes a claim/complete register, then // the written device (as long as it is actually enabled for that // hart) is marked complete. // This code exploits the fact that, practically, only one claim/complete register // can be written at a time. We check for this because if the address map // were to change, it may no longer be true. // Note -- PLIC doesn't care which hart writes the register. val completer = Wire(Vec(nHarts, Bool())) assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot val completerDev = Wire(UInt(log2Up(nDevices + 1).W)) val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U) (gateways zip completedDevs.asBools.tail) foreach { case (g, c) => g.complete := c } def thresholdRegDesc(i: Int) = RegFieldDesc( name = s"threshold_$i", desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.", reset = if (nPriorities > 0) None else Some(1)) def thresholdRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, thresholdRegDesc(i)) } else { RegField.r(prioBits, x, thresholdRegDesc(i)) } val hartRegFields = Seq.tabulate(nHarts) { i => PLICConsts.hartBase(i) -> Seq( thresholdRegField(threshold(i), i), RegField(32-prioBits), RegField(32, RegReadFn { valid => claimer(i) := valid (true.B, maxDevs(i)) }, RegWriteFn { (valid, data) => assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), "completerDev should be consistent for all harts") completerDev := data.extract(log2Ceil(nDevices+1)-1, 0) completer(i) := valid && enableVec0(i)(completerDev) true.B }, Some(RegFieldDesc(s"claim_complete_$i", s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." + s"Writing the interrupt number back completes the interrupt.", reset = None, wrType = Some(RegFieldWrType.MODIFY), rdAction = Some(RegFieldRdAction.MODIFY), volatile = true)) ) ) } node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*) if (nDevices >= 2) { val claimed = claimer(0) && maxDevs(0) > 0.U val completed = completer(0) property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete") property.cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim") val ep = enables(0).asUInt & pending.asUInt val ep2 = RegNext(ep) val diff = ep & ~ep2 property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle") if (nPriorities > 0) ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)), "THRESHOLD", "interrupt pending but less than threshold") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc) } } class PLICFanIn(nDevices: Int, prioBits: Int) extends Module { val io = IO(new Bundle { val prio = Flipped(Vec(nDevices, UInt(prioBits.W))) val ip = Flipped(UInt(nDevices.W)) val dev = UInt(log2Ceil(nDevices+1).W) val max = UInt(prioBits.W) }) def findMax(x: Seq[UInt]): (UInt, UInt) = { if (x.length > 1) { val half = 1 << (log2Ceil(x.length) - 1) val left = findMax(x take half) val right = findMax(x drop half) MuxT(left._1 >= right._1, left, (right._1, half.U | right._2)) } else (x.head, 0.U) } val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) } val (maxPri, maxDev) = findMax(effectivePriority) io.max := maxPri // strips the always-constant high '1' bit io.dev := maxDev } /** Trait that will connect a PLIC to a subsystem */ trait CanHavePeripheryPLIC { this: BaseSubsystem => val (plicOpt, plicDomainOpt) = p(PLICKey).map { params => val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere) val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain") val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) } plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } } plicDomainWrapper { plic.intnode :=* ibus.toPLIC } (plic, plicDomainWrapper) }.unzip }
module PLICFanIn_10( // @[Plic.scala:338:7] input clock, // @[Plic.scala:338:7] input reset, // @[Plic.scala:338:7] input io_prio_0, // @[Plic.scala:339:14] input io_ip, // @[Plic.scala:339:14] output io_dev, // @[Plic.scala:339:14] output io_max // @[Plic.scala:339:14] ); wire io_prio_0_0 = io_prio_0; // @[Plic.scala:338:7] wire io_ip_0 = io_ip; // @[Plic.scala:338:7] wire [1:0] effectivePriority_0 = 2'h2; // @[Plic.scala:355:32] wire _effectivePriority_T = io_ip_0; // @[Plic.scala:338:7, :355:55] wire maxDev; // @[Misc.scala:35:36] wire io_dev_0; // @[Plic.scala:338:7] wire io_max_0; // @[Plic.scala:338:7] wire [1:0] effectivePriority_1 = {_effectivePriority_T, io_prio_0_0}; // @[Plic.scala:338:7, :355:{55,100}] wire [1:0] maxPri = effectivePriority_1 != 2'h3 ? 2'h2 : effectivePriority_1; // @[Misc.scala:35:9] assign maxDev = &effectivePriority_1; // @[Misc.scala:35:36] assign io_dev_0 = maxDev; // @[Misc.scala:35:36] assign io_max_0 = maxPri[0]; // @[Misc.scala:35:9] assign io_dev = io_dev_0; // @[Plic.scala:338:7] assign io_max = io_max_0; // @[Plic.scala:338:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_315( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_18( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [255:0] _GEN_0 = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [255:0] _GEN_3 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }
module dataMems_328( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ class IntXbar()(implicit p: Parameters) extends LazyModule { val intnode = new IntNexusNode( sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sourceFn = { seq => IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten) }) { override def circuitIdentity = outputs == 1 && inputs == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}" val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten intnode.out.foreach { case (o, _) => o := cat } } } class IntSyncXbar()(implicit p: Parameters) extends LazyModule { val intnode = new IntSyncNexusNode( sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sourceFn = { seq => IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten) }) { override def circuitIdentity = outputs == 1 && inputs == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}" val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten intnode.out.foreach { case (o, _) => o.sync := cat } } } object IntXbar { def apply()(implicit p: Parameters): IntNode = { val xbar = LazyModule(new IntXbar) xbar.intnode } } object IntSyncXbar { def apply()(implicit p: Parameters): IntSyncNode = { val xbar = LazyModule(new IntSyncXbar) xbar.intnode } }
module IntXbar_i1_o1_2( // @[Xbar.scala:22:9] input auto_anon_in_0, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_anon_in_0_0 = auto_anon_in_0; // @[Xbar.scala:22:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire anonIn_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9] wire anonOut_0; // @[MixedNode.scala:542:17] wire auto_anon_out_0_0; // @[Xbar.scala:22:9] assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_out_0_0 = anonOut_0; // @[Xbar.scala:22:9] assign auto_anon_out_0 = auto_anon_out_0_0; // @[Xbar.scala:22:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_101( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module InputUnit_131( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_8, // @[InputUnit.scala:170:14] input io_out_credit_available_1_9, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_9; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, 9'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_9; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToIN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.log2Up import scala.math._ import consts._ class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module { override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}" val io = IO(new Bundle { val in = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val signedOut = Input(Bool()) val out = Output(Bits(intWidth.W)) val intExceptionFlags = Output(Bits(3.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in) val magGeOne = rawIn.sExp(expWidth) val posExp = rawIn.sExp(expWidth - 1, 0) val magJustBelowOne = !magGeOne && posExp.andR //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) /*------------------------------------------------------------------------ | Assuming the input floating-point value is not a NaN, its magnitude is | at least 1, and it is not obviously so large as to lead to overflow, | convert its significand to fixed-point (i.e., with the binary point in a | fixed location). For a non-NaN input with a magnitude less than 1, this | expression contrives to ensure that the integer bits of 'alignedSig' | will all be zeros. *------------------------------------------------------------------------*/ val shiftedSig = (magGeOne ## rawIn.sig(sigWidth - 2, 0))<< Mux(magGeOne, rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0), 0.U ) val alignedSig = (shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR val unroundedInt = 0.U(intWidth.W) | alignedSig>>2 val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero) val roundIncr_near_even = (magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) || (magJustBelowOne && alignedSig(1, 0).orR) val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne val roundIncr = (roundingMode_near_even && roundIncr_near_even ) || (roundingMode_near_maxMag && roundIncr_near_maxMag) || ((roundingMode_min || roundingMode_odd) && (rawIn.sign && common_inexact)) || (roundingMode_max && (!rawIn.sign && common_inexact)) val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt) val roundedInt = Mux(roundIncr ^ rawIn.sign, complUnroundedInt + 1.U, complUnroundedInt ) | (roundingMode_odd && common_inexact) val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U) //*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM //*** 'unroundedInt'?: val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr val common_overflow = Mux(magGeOne, (posExp >= intWidth.U) || Mux(io.signedOut, Mux(rawIn.sign, magGeOne_atOverflowEdge && (unroundedInt(intWidth - 2, 0).orR || roundIncr), magGeOne_atOverflowEdge || ((posExp === (intWidth - 2).U) && roundCarryBut2) ), rawIn.sign || (magGeOne_atOverflowEdge && unroundedInt(intWidth - 2) && roundCarryBut2) ), !io.signedOut && rawIn.sign && roundIncr ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val invalidExc = rawIn.isNaN || rawIn.isInf val overflow = !invalidExc && common_overflow val inexact = !invalidExc && !common_overflow && common_inexact val excSign = !rawIn.isNaN && rawIn.sign val excOut = Mux((io.signedOut === excSign), (BigInt(1)<<(intWidth - 1)).U, 0.U ) | Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U) io.out := Mux(invalidExc || common_overflow, excOut, roundedInt) io.intExceptionFlags := invalidExc ## overflow ## inexact } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToIN_e11_s53_i64_4( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [64:0] io_in, // @[RecFNToIN.scala:49:16] input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16] input io_signedOut, // @[RecFNToIN.scala:49:16] output [63:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToIN.scala:46:7] wire io_signedOut_0 = io_signedOut; // @[RecFNToIN.scala:46:7] wire [63:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [63:0] io_out_0; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[11]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] posExp = rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[rawFloatFromRecFN.scala:52:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RecFNToIN.scala:46:7, :68:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RecFNToIN.scala:46:7, :69:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RecFNToIN.scala:46:7, :70:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RecFNToIN.scala:46:7, :71:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RecFNToIN.scala:46:7, :72:53] wire [51:0] _shiftedSig_T = rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [5:0] _shiftedSig_T_2 = rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 6'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [115:0] shiftedSig = {63'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [64:0] _alignedSig_T = shiftedSig[115:51]; // @[RecFNToIN.scala:83:49, :89:20] wire [50:0] _alignedSig_T_1 = shiftedSig[50:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [65:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [63:0] _unroundedInt_T = alignedSig[65:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [63:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T = roundingMode_near_even & roundIncr_near_even; // @[RecFNToIN.scala:67:53, :94:78, :98:35] wire _roundIncr_T_1 = roundingMode_near_maxMag & roundIncr_near_maxMag; // @[RecFNToIN.scala:71:53, :96:61, :99:35] wire _roundIncr_T_2 = _roundIncr_T | _roundIncr_T_1; // @[RecFNToIN.scala:98:{35,61}, :99:35] wire _roundIncr_T_3 = roundingMode_min | roundingMode_odd; // @[RecFNToIN.scala:69:53, :72:53, :100:28] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_5 = _roundIncr_T_3 & _roundIncr_T_4; // @[RecFNToIN.scala:100:{28,49}, :101:26] wire _roundIncr_T_6 = _roundIncr_T_2 | _roundIncr_T_5; // @[RecFNToIN.scala:98:61, :99:61, :100:49] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire _roundIncr_T_9 = roundingMode_max & _roundIncr_T_8; // @[RecFNToIN.scala:70:53, :102:{27,43}] wire roundIncr = _roundIncr_T_6 | _roundIncr_T_9; // @[RecFNToIN.scala:99:61, :101:46, :102:27] wire [63:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [63:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [64:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 65'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [63:0] _roundedInt_T_2 = _roundedInt_T_1[63:0]; // @[RecFNToIN.scala:106:31] wire [63:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire _roundedInt_T_4 = roundingMode_odd & common_inexact; // @[RecFNToIN.scala:72:53, :92:29, :108:31] wire [63:0] roundedInt = {_roundedInt_T_3[63:1], _roundedInt_T_3[0] | _roundedInt_T_4}; // @[RecFNToIN.scala:105:12, :108:{11,31}] wire magGeOne_atOverflowEdge = posExp == 11'h3F; // @[RecFNToIN.scala:62:28, :110:43] wire [61:0] _roundCarryBut2_T = unroundedInt[61:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = |(posExp[10:6]); // @[RecFNToIN.scala:62:28, :116:21] wire [62:0] _common_overflow_T_1 = unroundedInt[62:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 11'h3E; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_9 = unroundedInt[62]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = io_signedOut_0 ? _common_overflow_T_8 : _common_overflow_T_12; // @[RecFNToIN.scala:46:7, :117:20, :118:24, :124:32] wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire _common_overflow_T_15 = ~io_signedOut_0; // @[RecFNToIN.scala:46:7, :128:13] wire _common_overflow_T_16 = _common_overflow_T_15 & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_17 = _common_overflow_T_16 & roundIncr; // @[RecFNToIN.scala:101:46, :128:{27,41}] wire common_overflow = magGeOne ? _common_overflow_T_14 : _common_overflow_T_17; // @[RecFNToIN.scala:61:30, :115:12, :116:36, :128:41] wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = io_signedOut_0 == excSign; // @[RecFNToIN.scala:46:7, :137:32, :139:27] wire [63:0] _excOut_T_1 = {_excOut_T, 63'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [62:0] _excOut_T_3 = {63{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [63:0] excOut = {_excOut_T_1[63], _excOut_T_1[62:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out_0 = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_out = io_out_0; // @[RecFNToIN.scala:46:7] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module mem_28x75_0( // @[InputUnit.scala:85:18] input [4:0] R0_addr, input R0_en, input R0_clk, output [74:0] R0_data, input [4:0] R1_addr, input R1_en, input R1_clk, output [74:0] R1_data, input [4:0] R2_addr, input R2_en, input R2_clk, output [74:0] R2_data, input [4:0] R3_addr, input R3_en, input R3_clk, output [74:0] R3_data, input [4:0] R4_addr, input R4_en, input R4_clk, output [74:0] R4_data, input [4:0] R5_addr, input R5_en, input R5_clk, output [74:0] R5_data, input [4:0] R6_addr, input R6_en, input R6_clk, output [74:0] R6_data, input [4:0] R7_addr, input R7_en, input R7_clk, output [74:0] R7_data, input [4:0] R8_addr, input R8_en, input R8_clk, output [74:0] R8_data, input [4:0] R9_addr, input R9_en, input R9_clk, output [74:0] R9_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [74:0] W0_data ); reg [74:0] Memory[0:27]; // @[InputUnit.scala:85:18] always @(posedge W0_clk) begin // @[InputUnit.scala:85:18] if (W0_en & 1'h1) // @[InputUnit.scala:85:18] Memory[W0_addr] <= W0_data; // @[InputUnit.scala:85:18] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_123( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_379 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_402( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_37( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_26 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_28 = 1'h1; // @[Parameters.scala:54:67] wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_30 = 1'h1; // @[Parameters.scala:56:48] wire _legal_source_WIRE_5 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_91 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:56:32] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [5:0] io_in_b_bits_source = 6'h20; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_56 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_57 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_58 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_59 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_1 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_2 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_3 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_4 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _legal_source_T_37 = 6'h20; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_43 = 6'h20; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_44 = 6'h20; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1 = 6'h20; // @[Mux.scala:30:73] wire [5:0] _uncommonBits_T_60 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_61 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_62 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_63 = 6'h20; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_64 = 6'h20; // @[Parameters.scala:52:29] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_31 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_6 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_33 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _legal_source_T_25 = 3'h4; // @[Parameters.scala:54:10] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] uncommonBits_59 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _legal_source_T_34 = 3'h0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_64 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [1:0] uncommonBits_55 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_56 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_57 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_58 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_60 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_61 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_62 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_63 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14] wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _legal_source_T_38 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [4:0] _legal_source_T_32 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_39 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_40 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_41 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_42 = 5'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_35 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_36 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_1 = 4'h8; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_7 = 4'h8; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_13 = 4'h8; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_19 = 4'h8; // @[Parameters.scala:54:10] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_72 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_73 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_74 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_75 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_76 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_77 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_36 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_37 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_38 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_44 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_50 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_56 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_39 = _source_ok_T_38 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = _source_ok_T_44 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_51 = _source_ok_T_50 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_57 = _source_ok_T_56 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_62 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_63 = _source_ok_T_62 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_67 = _source_ok_T_65 & _source_ok_T_66; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire _source_ok_T_68 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire _source_ok_T_69 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_73 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_74 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_75 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_81 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_87 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_93 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_76 = _source_ok_T_75 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_80; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_82 = _source_ok_T_81 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_88 = _source_ok_T_87 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_92 = _source_ok_T_90; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_94 = _source_ok_T_93 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_99 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_100 = _source_ok_T_99 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_103 = source_ok_uncommonBits_14 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_104 = _source_ok_T_102 & _source_ok_T_103; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_5 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire _source_ok_T_105 = io_in_c_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_6 = _source_ok_T_105; // @[Parameters.scala:1138:31] wire _source_ok_T_106 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_110 = _source_ok_T_109 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_110 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_75 = _uncommonBits_T_75[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_76 = _uncommonBits_T_76[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_77 = _uncommonBits_T_77[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_79 = _uncommonBits_T_79[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_82 = _uncommonBits_T_82[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_83 = _uncommonBits_T_83[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_84 = _uncommonBits_T_84[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_89 = _uncommonBits_T_89[2:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31] wire _T_2103 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2103; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2103; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2177 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2177; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2177; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2177; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2177; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [1:0] b_first_counter; // @[Edges.scala:229:27] wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2174 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2174; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2174; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [40:0] inflight; // @[Monitor.scala:614:27] reg [163:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [163:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [40:0] a_set; // @[Monitor.scala:626:34] wire [40:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [163:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [163:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [163:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [163:0] _a_opcode_lookup_T_6 = {160'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [163:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[163:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [163:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [163:0] _a_size_lookup_T_6 = {160'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [163:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[163:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire _T_2029 = _T_2103 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2029 ? _a_set_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2029 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2029 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2029 ? _a_opcodes_set_T_1[163:0] : 164'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2029 ? _a_sizes_set_T_1[163:0] : 164'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [40:0] d_clr; // @[Monitor.scala:664:34] wire [40:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [163:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [163:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2075 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2075 & ~d_release_ack ? _d_clr_wo_ready_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire _T_2044 = _T_2177 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2044 ? _d_clr_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2044 ? _d_opcodes_clr_T_5[163:0] : 164'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2044 ? _d_sizes_clr_T_5[163:0] : 164'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [40:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [40:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [40:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [163:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [163:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [163:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [163:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [163:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [163:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [40:0] inflight_1; // @[Monitor.scala:726:35] reg [163:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [163:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_2; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [40:0] c_set; // @[Monitor.scala:738:34] wire [40:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [163:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [163:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [163:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [163:0] _c_opcode_lookup_T_6 = {160'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [163:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[163:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [163:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [163:0] _c_size_lookup_T_6 = {160'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [163:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[163:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire _T_2116 = _T_2174 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2116 ? _c_set_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2116 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2116 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2116 ? _c_opcodes_set_T_1[163:0] : 164'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2116 ? _c_sizes_set_T_1[163:0] : 164'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [40:0] d_clr_1; // @[Monitor.scala:774:34] wire [40:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [163:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [163:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2147 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2147 & d_release_ack_1 ? _d_clr_wo_ready_T_1[40:0] : 41'h0; // @[OneHot.scala:58:35] wire _T_2129 = _T_2177 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2129 ? _d_clr_T_1[40:0] : 41'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2129 ? _d_opcodes_clr_T_11[163:0] : 164'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2129 ? _d_sizes_clr_T_11[163:0] : 164'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [40:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [40:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [40:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [163:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [163:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [163:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [163:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [163:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [163:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [11:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_3; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_set; // @[Monitor.scala:833:25] wire _T_2183 = _T_2177 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2183 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35] wire [11:0] e_clr; // @[Monitor.scala:839:25] wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr | (mask >> 1), ~(~addr | mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0) msbsLess || (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound || straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r || ignore) cur.cfg.w := aligned && (pmp.cfg.w || ignore) cur.cfg.x := aligned && (pmp.cfg.x || ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File CustomCSRs.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config.Parameters case class CustomCSR(id: Int, mask: BigInt, init: Option[BigInt]) object CustomCSR { def constant(id: Int, value: BigInt): CustomCSR = CustomCSR(id, BigInt(0), Some(value)) } class CustomCSRIO(implicit p: Parameters) extends CoreBundle { val ren = Output(Bool()) // set by CSRFile, indicates an instruction is reading the CSR val wen = Output(Bool()) // set by CSRFile, indicates an instruction is writing the CSR val wdata = Output(UInt(xLen.W)) // wdata provided by instruction writing CSR val value = Output(UInt(xLen.W)) // current value of CSR in CSRFile val stall = Input(Bool()) // reads and writes to this CSR should stall (must be bounded) val set = Input(Bool()) // set/sdata enables external agents to set the value of this CSR val sdata = Input(UInt(xLen.W)) } class CustomCSRs(implicit p: Parameters) extends CoreBundle { // Not all cores have these CSRs, but those that do should follow the same // numbering conventions. So we list them here but default them to None. protected def bpmCSRId = 0x7c0 protected def bpmCSR: Option[CustomCSR] = None protected def chickenCSRId = 0x7c1 protected def chickenCSR: Option[CustomCSR] = None // If you override this, you'll want to concatenate super.decls def decls: Seq[CustomCSR] = bpmCSR.toSeq ++ chickenCSR val csrs = Vec(decls.size, new CustomCSRIO) def flushBTB = getOrElse(bpmCSR, _.wen, false.B) def bpmStatic = getOrElse(bpmCSR, _.value(0), false.B) def disableDCacheClockGate = getOrElse(chickenCSR, _.value(0), false.B) def disableICacheClockGate = getOrElse(chickenCSR, _.value(1), false.B) def disableCoreClockGate = getOrElse(chickenCSR, _.value(2), false.B) def disableSpeculativeICacheRefill = getOrElse(chickenCSR, _.value(3), false.B) def suppressCorruptOnGrantData = getOrElse(chickenCSR, _.value(9), false.B) protected def getByIdOrElse[T](id: Int, f: CustomCSRIO => T, alt: T): T = { val idx = decls.indexWhere(_.id == id) if (idx < 0) alt else f(csrs(idx)) } protected def getOrElse[T](csr: Option[CustomCSR], f: CustomCSRIO => T, alt: T): T = csr.map(c => getByIdOrElse(c.id, f, alt)).getOrElse(alt) } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r || w || x || c || a || l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /** PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss */ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /** PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info */ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /** ptw access exception */ val ae_ptw = Bool() /** final access exception */ val ae_final = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** hypervisor read */ val hr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor execute */ val hx = Bool() /** PTE to refill L1TLB * * source: L2TLB */ val pte = new PTE /** pte pglevel */ val level = UInt(log2Ceil(pgLevels).W) /** fragmented_superpage support */ val fragmented_superpage = Bool() /** homogeneous for both pma and pmp */ val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /** IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) */ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /** PTW performance statistics */ class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /** Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core */ class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /** enable clock generated by ptw */ val clock_enabled = Output(Bool()) } /** PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format */ class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** global mapping */ val g = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() /** valid bit */ val v = Bool() /** return true if find a pointer to next level page table */ def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /** return true if find a leaf PTE */ def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a /** user read */ def ur(dummy: Int = 0) = sr() && u /** user write*/ def uw(dummy: Int = 0) = sw() && u /** user execute */ def ux(dummy: Int = 0) = sx() && u /** supervisor read */ def sr(dummy: Int = 0) = leaf() && r /** supervisor write */ def sw(dummy: Int = 0) = leaf() && w && d /** supervisor execute */ def sx(dummy: Int = 0) = leaf() && x /** full permission: writable and executable in user mode */ def isFullPerm(dummy: Int = 0) = uw() && ux() } /** L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format */ class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() } /** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation */ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /** to n TLB */ val requestor = Flipped(Vec(n, new TLBPTWIO)) /** to HellaCache */ val mem = new HellaCacheIO /** to Core * * contains CSRs info and performance statistics */ val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /** Arbiter to arbite request from n TLB */ val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM || !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /** current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} */ val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /** tlb request */ val r_req = Reg(new PTWReq) /** current selected way in arbitor */ val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /** pte for 2-stage translation */ val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /** 2-stage translation both enable */ val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r || tmp.w || tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /** address send to mem for enquerry */ val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr */ val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i))) } /** PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation */ def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid | UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /** the valid vec for the selected set(including n ways) */ val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) | mask g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req || state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req || state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 || do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf || (pf && stage2) resp_hr := !stage2 || (!pf && !gf && pte.ur()) resp_hw := !stage2 || (!pf && !gf && pte.uw()) resp_hx := !stage2 || (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn */ private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /** use hgatp and vpn to construct a new ppn */ private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range */ private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module PTW_2( // @[PTW.scala:219:7] input clock, // @[PTW.scala:219:7] input reset, // @[PTW.scala:219:7] output io_requestor_0_req_ready, // @[PTW.scala:220:14] input io_requestor_0_req_valid, // @[PTW.scala:220:14] input io_requestor_0_req_bits_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14] output io_requestor_0_resp_valid, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_0_status_debug, // @[PTW.scala:220:14] output io_requestor_0_status_cease, // @[PTW.scala:220:14] output io_requestor_0_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14] output io_requestor_0_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14] output io_requestor_0_status_v, // @[PTW.scala:220:14] output io_requestor_0_status_sd, // @[PTW.scala:220:14] output io_requestor_0_status_mpv, // @[PTW.scala:220:14] output io_requestor_0_status_gva, // @[PTW.scala:220:14] output io_requestor_0_status_tsr, // @[PTW.scala:220:14] output io_requestor_0_status_tw, // @[PTW.scala:220:14] output io_requestor_0_status_tvm, // @[PTW.scala:220:14] output io_requestor_0_status_mxr, // @[PTW.scala:220:14] output io_requestor_0_status_sum, // @[PTW.scala:220:14] output io_requestor_0_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14] output io_requestor_0_status_spp, // @[PTW.scala:220:14] output io_requestor_0_status_mpie, // @[PTW.scala:220:14] output io_requestor_0_status_spie, // @[PTW.scala:220:14] output io_requestor_0_status_mie, // @[PTW.scala:220:14] output io_requestor_0_status_sie, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_1_req_ready, // @[PTW.scala:220:14] input io_requestor_1_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_1_resp_valid, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_1_status_debug, // @[PTW.scala:220:14] output io_requestor_1_status_cease, // @[PTW.scala:220:14] output io_requestor_1_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14] output io_requestor_1_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14] output io_requestor_1_status_v, // @[PTW.scala:220:14] output io_requestor_1_status_sd, // @[PTW.scala:220:14] output io_requestor_1_status_mpv, // @[PTW.scala:220:14] output io_requestor_1_status_gva, // @[PTW.scala:220:14] output io_requestor_1_status_tsr, // @[PTW.scala:220:14] output io_requestor_1_status_tw, // @[PTW.scala:220:14] output io_requestor_1_status_tvm, // @[PTW.scala:220:14] output io_requestor_1_status_mxr, // @[PTW.scala:220:14] output io_requestor_1_status_sum, // @[PTW.scala:220:14] output io_requestor_1_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14] output io_requestor_1_status_spp, // @[PTW.scala:220:14] output io_requestor_1_status_mpie, // @[PTW.scala:220:14] output io_requestor_1_status_spie, // @[PTW.scala:220:14] output io_requestor_1_status_mie, // @[PTW.scala:220:14] output io_requestor_1_status_sie, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_2_req_ready, // @[PTW.scala:220:14] output io_requestor_2_resp_valid, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_2_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_2_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_2_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_2_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_2_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_2_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_2_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_2_status_debug, // @[PTW.scala:220:14] output io_requestor_2_status_cease, // @[PTW.scala:220:14] output io_requestor_2_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_dprv, // @[PTW.scala:220:14] output io_requestor_2_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_prv, // @[PTW.scala:220:14] output io_requestor_2_status_v, // @[PTW.scala:220:14] output io_requestor_2_status_sd, // @[PTW.scala:220:14] output io_requestor_2_status_mpv, // @[PTW.scala:220:14] output io_requestor_2_status_gva, // @[PTW.scala:220:14] output io_requestor_2_status_tsr, // @[PTW.scala:220:14] output io_requestor_2_status_tw, // @[PTW.scala:220:14] output io_requestor_2_status_tvm, // @[PTW.scala:220:14] output io_requestor_2_status_mxr, // @[PTW.scala:220:14] output io_requestor_2_status_sum, // @[PTW.scala:220:14] output io_requestor_2_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_mpp, // @[PTW.scala:220:14] output io_requestor_2_status_spp, // @[PTW.scala:220:14] output io_requestor_2_status_mpie, // @[PTW.scala:220:14] output io_requestor_2_status_spie, // @[PTW.scala:220:14] output io_requestor_2_status_mie, // @[PTW.scala:220:14] output io_requestor_2_status_sie, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_7_mask, // @[PTW.scala:220:14] input io_mem_req_ready, // @[PTW.scala:220:14] output io_mem_req_valid, // @[PTW.scala:220:14] output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14] output io_mem_req_bits_dv, // @[PTW.scala:220:14] output io_mem_s1_kill, // @[PTW.scala:220:14] input io_mem_s2_nack, // @[PTW.scala:220:14] input io_mem_resp_valid, // @[PTW.scala:220:14] input [39:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_gf_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_gf_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14] input io_mem_store_pending, // @[PTW.scala:220:14] input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14] input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14] input io_dpath_sfence_valid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14] input [38:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14] input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14] input io_dpath_status_debug, // @[PTW.scala:220:14] input io_dpath_status_cease, // @[PTW.scala:220:14] input io_dpath_status_wfi, // @[PTW.scala:220:14] input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14] input io_dpath_status_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14] input io_dpath_status_v, // @[PTW.scala:220:14] input io_dpath_status_sd, // @[PTW.scala:220:14] input io_dpath_status_mpv, // @[PTW.scala:220:14] input io_dpath_status_gva, // @[PTW.scala:220:14] input io_dpath_status_tsr, // @[PTW.scala:220:14] input io_dpath_status_tw, // @[PTW.scala:220:14] input io_dpath_status_tvm, // @[PTW.scala:220:14] input io_dpath_status_mxr, // @[PTW.scala:220:14] input io_dpath_status_sum, // @[PTW.scala:220:14] input io_dpath_status_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14] input io_dpath_status_spp, // @[PTW.scala:220:14] input io_dpath_status_mpie, // @[PTW.scala:220:14] input io_dpath_status_spie, // @[PTW.scala:220:14] input io_dpath_status_mie, // @[PTW.scala:220:14] input io_dpath_status_sie, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14] output io_dpath_perf_l2miss, // @[PTW.scala:220:14] output io_dpath_perf_l2hit, // @[PTW.scala:220:14] output io_dpath_perf_pte_miss, // @[PTW.scala:220:14] output io_dpath_perf_pte_hit, // @[PTW.scala:220:14] output io_dpath_clock_enabled // @[PTW.scala:220:14] ); wire s2_entry_vec_0_w; // @[PTW.scala:479:59] wire s2_entry_vec_0_x; // @[PTW.scala:479:59] wire s2_entry_vec_0_u; // @[PTW.scala:479:59] wire s2_entry_vec_0_a; // @[PTW.scala:479:59] wire s2_entry_vec_0_d; // @[PTW.scala:479:59] wire writeEnable; // @[PTW.scala:433:21] wire tmp_r; // @[PTW.scala:304:37] wire tmp_w; // @[PTW.scala:304:37] wire tmp_x; // @[PTW.scala:304:37] wire tmp_u; // @[PTW.scala:304:37] wire tmp_g; // @[PTW.scala:304:37] wire tmp_a; // @[PTW.scala:304:37] wire tmp_d; // @[PTW.scala:304:37] wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37] wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37] wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25] wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25] wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25] wire _r_pte_barrier_io_y_d; // @[package.scala:267:25] wire _r_pte_barrier_io_y_a; // @[package.scala:267:25] wire _r_pte_barrier_io_y_g; // @[package.scala:267:25] wire _r_pte_barrier_io_y_u; // @[package.scala:267:25] wire _r_pte_barrier_io_y_x; // @[package.scala:267:25] wire _r_pte_barrier_io_y_w; // @[package.scala:267:25] wire _r_pte_barrier_io_y_r; // @[package.scala:267:25] wire _r_pte_barrier_io_y_v; // @[package.scala:267:25] wire [2:0] _state_barrier_io_y; // @[package.scala:267:25] wire [44:0] _l2_tlb_ram_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _arb_io_out_valid; // @[PTW.scala:236:19] wire _arb_io_out_bits_valid; // @[PTW.scala:236:19] wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19] wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19] wire [1:0] _arb_io_chosen; // @[PTW.scala:236:19] wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_valid_0 = io_requestor_0_req_bits_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_ld_0 = io_mem_s2_xcpt_gf_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_st_0 = io_mem_s2_xcpt_gf_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7] wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7] wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7] wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7] wire [38:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7] wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7] wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7] wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7] wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7] wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7] wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7] wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7] wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7] wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7] wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7] wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7] wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7] wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7] wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7] wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7] wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7] wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7] wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7] wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17] wire [31:0] io_requestor_0_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_dpath_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_2_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_2_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_need_gpa = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_valid = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_valid = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_need_gpa = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_nack_cause_raw = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_uncached = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_dv = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_replay = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_has_data = 1'h0; // @[PTW.scala:219:7] wire io_mem_replay_next = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7] wire io_mem_ordered = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_acquire = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_release = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_grant = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_tlbMiss = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_blocked = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[PTW.scala:219:7] wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7] wire io_mem_clock_enabled = 1'h0; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hg = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_spvp = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_spv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_debug = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_cease = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_wfi = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_dv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_v = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_gva = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_tsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_tw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_tvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mxr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sum = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mprv = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_spp = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_spie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_mie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_ren = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_wen = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_ren = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_wen = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_2 = 1'h0; // @[PTW.scala:242:35] wire _clock_en_T_4 = 1'h0; // @[CustomCSRs.scala:43:61] wire _hits_T_9 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_10 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_11 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_12 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_13 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_14 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_15 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_16 = 1'h0; // @[PTW.scala:366:27] wire _hit_T_1 = 1'h0; // @[PTW.scala:367:20] wire stage2_pte_cache_hit = 1'h0; // @[PTW.scala:367:24] wire _state_reg_set_left_older_T_9 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_set_left_older_T_10 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_T_70 = 1'h0; // @[package.scala:163:13] wire _state_reg_T_71 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_T_74 = 1'h0; // @[Replacement.scala:207:62] wire _state_reg_T_75 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_set_left_older_T_11 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_T_81 = 1'h0; // @[package.scala:163:13] wire _state_reg_T_82 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_T_85 = 1'h0; // @[Replacement.scala:207:62] wire _state_reg_T_86 = 1'h0; // @[Replacement.scala:218:17] wire hg = 1'h0; // @[PTW.scala:458:34] wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32] wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40] wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_2_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53] wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71] wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25] wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58] wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_2_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_2_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_resp_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] _hits_T_17 = 8'h0; // @[package.scala:45:27] wire [7:0] hits_1 = 8'h0; // @[PTW.scala:366:43] wire [1:0] io_requestor_0_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_prv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_sxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_uxl = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_fs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_mpp = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42] wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58] wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44] wire [1:0] hits_lo_lo_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_lo_hi_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_hi_lo_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_hi_hi_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hi_3 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] lo_3 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] _state_reg_T_69 = 2'h0; // @[package.scala:163:13] wire [1:0] _state_reg_T_80 = 2'h0; // @[Replacement.scala:207:62] wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:489:22] wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40] wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40] wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45] wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61] wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46] wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62] wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46] wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62] wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27] wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27] wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44] wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40] wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27] wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26] wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26] wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44] wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27] wire [6:0] io_mem_req_bits_tag = 7'h0; // @[PTW.scala:219:7] wire [6:0] io_mem_resp_bits_tag = 7'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_2_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_resp_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_size = 2'h3; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] r_pte_pte_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_1 = 44'h0; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19] wire [41:0] _r_pte_pte_ppn_T = 42'h0; // @[PTW.scala:781:30] wire [41:0] _r_pte_pte_ppn_T_2 = 42'h0; // @[PTW.scala:781:30] wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30] wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42] wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58] wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] state_reg_touch_way_sized_3 = 3'h0; // @[package.scala:163:13] wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45] wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61] wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46] wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62] wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46] wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62] wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44] wire io_requestor_1_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7] wire state_reg_set_left_older_9 = 1'h1; // @[Replacement.scala:196:33] wire state_reg_set_left_older_10 = 1'h1; // @[Replacement.scala:196:33] wire _state_reg_T_72 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_76 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_77 = 1'h1; // @[Replacement.scala:206:16] wire state_reg_set_left_older_11 = 1'h1; // @[Replacement.scala:196:33] wire _state_reg_T_83 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_87 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_88 = 1'h1; // @[Replacement.scala:206:16] wire _valid_0_T_1 = 1'h1; // @[PTW.scala:461:15] wire _valid_0_T_7 = 1'h1; // @[PTW.scala:462:15] wire _s0_suitable_T = 1'h1; // @[PTW.scala:468:52] wire l2_pte_v = 1'h1; // @[PTW.scala:489:22] wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_97 = 1'h1; // @[TLBPermissions.scala:87:22] wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28] wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56] wire r_pte_pte_v = 1'h1; // @[PTW.scala:780:26] wire r_pte_pte_1_v = 1'h1; // @[PTW.scala:771:26] wire [19:0] stage2_pte_cache_data = 20'h0; // @[Mux.scala:30:73] wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] hits_lo_1 = 4'h0; // @[package.scala:45:27] wire [3:0] hits_hi_1 = 4'h0; // @[package.scala:45:27] wire [3:0] hi_2 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] lo_2 = 4'h0; // @[OneHot.scala:31:18] wire [31:0] io_requestor_0_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_mem_s2_paddr = 32'h0; // @[PTW.scala:219:7] wire [31:0] io_dpath_gstatus_isa = 32'h0; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40] wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58] wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40] wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_2_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_2_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_word_bypass = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_raw = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_store_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_wdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_value = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [26:0] io_requestor_2_req_bits_bits_addr = 27'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7] wire [39:0] io_mem_s2_gpa = 40'h0; // @[PTW.scala:219:7] wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58] wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:489:22] wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26] wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [511:0] _valid_WIRE_0 = 512'h0; // @[PTW.scala:422:32] wire [39:0] tag_1 = 40'h8000000000; // @[PTW.scala:363:18] wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23] wire [38:0] _tag_T = 39'h0; // @[package.scala:138:15] wire [1:0] max_count; // @[PTW.scala:289:25] wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_2_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_2_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39] wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40] wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51] wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17] wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17] wire _valid_0_T_2 = io_dpath_sfence_bits_rs1_0; // @[PTW.scala:219:7, :461:19] wire _valid_0_T_8 = io_dpath_sfence_bits_rs2_0; // @[PTW.scala:219:7, :462:19] wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_2_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_2_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_2_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_2_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_2_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_2_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire _io_dpath_perf_l2miss_T_1; // @[PTW.scala:482:38] wire l2_hit; // @[PTW.scala:481:27] wire _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:394:57] wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39] wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_2_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_2_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_2_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_valid_0; // @[PTW.scala:219:7] wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7] wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7] wire io_mem_req_valid_0; // @[PTW.scala:219:7] wire io_mem_s1_kill_0; // @[PTW.scala:219:7] wire io_dpath_perf_l2miss_0; // @[PTW.scala:219:7] wire io_dpath_perf_l2hit_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_hit_0; // @[PTW.scala:219:7] wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7] reg [2:0] state; // @[PTW.scala:233:22] wire l2_refill_wire; // @[PTW.scala:234:28] wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30] wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46] wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}] reg resp_valid_0; // @[PTW.scala:242:27] assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27] reg resp_valid_1; // @[PTW.scala:242:27] assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27] reg resp_valid_2; // @[PTW.scala:242:27] assign io_requestor_2_resp_valid_0 = resp_valid_2; // @[PTW.scala:219:7, :242:27] wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24] wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}] wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}] wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}] wire clock_en = _clock_en_T_3; // @[PTW.scala:244:{74,99}] assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39] assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39] reg invalidated; // @[PTW.scala:251:24] reg [1:0] count; // @[PTW.scala:259:18] wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21] reg resp_ae_ptw; // @[PTW.scala:260:24] assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_2_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] reg resp_ae_final; // @[PTW.scala:261:26] assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_2_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] reg resp_pf; // @[PTW.scala:262:20] assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_2_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] reg resp_gf; // @[PTW.scala:263:20] assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_2_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] reg resp_hr; // @[PTW.scala:264:20] assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_2_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] reg resp_hw; // @[PTW.scala:265:20] assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_2_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] reg resp_hx; // @[PTW.scala:266:20] assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_2_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] reg resp_fragmented_superpage; // @[PTW.scala:267:38] reg [26:0] r_req_addr; // @[PTW.scala:270:18] reg r_req_need_gpa; // @[PTW.scala:270:18] assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_2_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] reg r_req_vstage1; // @[PTW.scala:270:18] reg r_req_stage2; // @[PTW.scala:270:18] reg [1:0] r_req_dest; // @[PTW.scala:272:23] reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] reg [43:0] r_pte_ppn; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] reg r_pte_d; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] wire entry_d = r_pte_d; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26] reg r_pte_a; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] wire entry_a = r_pte_a; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26] reg r_pte_g; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26] reg r_pte_u; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] wire entry_u = r_pte_u; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26] reg r_pte_x; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] wire entry_x = r_pte_x; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26] reg r_pte_w; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] wire entry_w = r_pte_w; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26] reg r_pte_r; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] wire entry_r = r_pte_r; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26] reg r_pte_v; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26] reg [1:0] aux_count; // @[PTW.scala:278:22] wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_2_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20] wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26] reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20] reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20] wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26] reg aux_pte_d; // @[PTW.scala:280:20] wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26] reg aux_pte_a; // @[PTW.scala:280:20] wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26] reg aux_pte_g; // @[PTW.scala:280:20] wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26] reg aux_pte_u; // @[PTW.scala:280:20] wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26] reg aux_pte_x; // @[PTW.scala:280:20] wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26] reg aux_pte_w; // @[PTW.scala:280:20] wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26] reg aux_pte_r; // @[PTW.scala:280:20] wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26] reg aux_pte_v; // @[PTW.scala:280:20] wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26] reg [11:0] gpa_pgoff; // @[PTW.scala:281:22] reg stage2; // @[PTW.scala:282:19] reg stage2_final; // @[PTW.scala:283:25] wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26] wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38] wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25] assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25] assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_2_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31] wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}] wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12] reg mem_resp_valid; // @[PTW.scala:292:31] reg [63:0] mem_resp_data; // @[PTW.scala:293:30] wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37] wire [9:0] _tmp_T_10; // @[PTW.scala:304:37] wire [43:0] _tmp_T_9; // @[PTW.scala:304:37] wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26] wire [1:0] _tmp_T_8; // @[PTW.scala:304:37] wire _tmp_T_7; // @[PTW.scala:304:37] wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26] wire _tmp_T_6; // @[PTW.scala:304:37] wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26] wire _tmp_T_5; // @[PTW.scala:304:37] wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26] wire _tmp_T_4; // @[PTW.scala:304:37] wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26] wire _tmp_T_3; // @[PTW.scala:304:37] wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26] wire _tmp_T_2; // @[PTW.scala:304:37] wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26] wire _tmp_T_1; // @[PTW.scala:304:37] wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26] wire _tmp_T; // @[PTW.scala:304:37] wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26] wire [43:0] tmp_ppn; // @[PTW.scala:304:37] wire tmp_v; // @[PTW.scala:304:37] assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37] assign tmp_v = _tmp_T; // @[PTW.scala:304:37] assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37] assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37] assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37] assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37] assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37] assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37] assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37] assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37] assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37] assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37] assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37] assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37] assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37] assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37] assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37] assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37] assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37] assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37] assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37] assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37] wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26] wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26] wire [43:0] pte_ppn; // @[PTW.scala:305:26] wire pte_v; // @[PTW.scala:305:26] wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26] wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38] wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}] wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54] wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99] wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}] assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}] assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (~(count[1]) & (|(tmp_ppn[8:0])) | count == 2'h0 & (|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}] wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:27])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}] wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58] wire invalid_gpa = do_both_stages & ~stage2 & (|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25] wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26] wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}] wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}] wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}] wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}] wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}] wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}] wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33] wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}] wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51] wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}] wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73] wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}] wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}] wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}] wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}] wire _pte_addr_mask_T = ~(|count); // @[PTW.scala:259:18, :324:40] wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}] wire _T_46 = count == 2'h1; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T = _T_46; // @[package.scala:39:86] wire _pmaHomogeneous_T; // @[package.scala:39:86] assign _pmaHomogeneous_T = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_3 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_23; // @[package.scala:39:86] assign _pmpHomogeneous_T_23 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_11; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_11 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_60; // @[package.scala:39:86] assign _pmpHomogeneous_T_60 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_5 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_19; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_19 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_97; // @[package.scala:39:86] assign _pmpHomogeneous_T_97 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_10; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_10 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_27 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_134; // @[package.scala:39:86] assign _pmpHomogeneous_T_134 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_15; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_15 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_35 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_171; // @[package.scala:39:86] assign _pmpHomogeneous_T_171 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_20; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_20 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_43; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_43 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_208; // @[package.scala:39:86] assign _pmpHomogeneous_T_208 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_25 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_51; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_51 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_245; // @[package.scala:39:86] assign _pmpHomogeneous_T_245 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_30; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_30 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_59; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_59 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_282; // @[package.scala:39:86] assign _pmpHomogeneous_T_282 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_35 = _T_46; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T = _T_46; // @[package.scala:39:86] wire _aux_pte_T; // @[package.scala:39:86] assign _aux_pte_T = _T_46; // @[package.scala:39:86] wire _leaf_T_5; // @[PTW.scala:751:53] assign _leaf_T_5 = _T_46; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}] wire _T_256 = count == 2'h2; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T_2 = _T_256; // @[package.scala:39:86] wire _pmaHomogeneous_T_2; // @[package.scala:39:86] assign _pmaHomogeneous_T_2 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_5 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_T_25 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_2; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_2 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_13; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_13 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_T_62; // @[package.scala:39:86] assign _pmpHomogeneous_T_62 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_7; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_7 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_21 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_T_99; // @[package.scala:39:86] assign _pmpHomogeneous_T_99 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_12; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_12 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_29; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_29 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_T_136; // @[package.scala:39:86] assign _pmpHomogeneous_T_136 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_17; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_17 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_37 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_T_173; // @[package.scala:39:86] assign _pmpHomogeneous_T_173 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_22; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_22 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_45; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_45 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_T_210; // @[package.scala:39:86] assign _pmpHomogeneous_T_210 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_27 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_53; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_53 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_T_247; // @[package.scala:39:86] assign _pmpHomogeneous_T_247 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_32; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_32 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_61; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_61 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_T_284; // @[package.scala:39:86] assign _pmpHomogeneous_T_284 = _T_256; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_37 = _T_256; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T_2 = _T_256; // @[package.scala:39:86] wire _l2_refill_T; // @[PTW.scala:713:39] assign _l2_refill_T = _T_256; // @[package.scala:39:86] wire _aux_pte_T_2; // @[package.scala:39:86] assign _aux_pte_T_2 = _T_256; // @[package.scala:39:86] wire _leaf_T_8; // @[PTW.scala:751:53] assign _leaf_T_8 = _T_256; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}] wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}] wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76] wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36] wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}] wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}] wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23] reg [6:0] state_reg; // @[Replacement.scala:168:70] reg [7:0] valid; // @[PTW.scala:352:24] reg [31:0] tags_0; // @[PTW.scala:353:19] reg [31:0] tags_1; // @[PTW.scala:353:19] reg [31:0] tags_2; // @[PTW.scala:353:19] reg [31:0] tags_3; // @[PTW.scala:353:19] reg [31:0] tags_4; // @[PTW.scala:353:19] reg [31:0] tags_5; // @[PTW.scala:353:19] reg [31:0] tags_6; // @[PTW.scala:353:19] reg [31:0] tags_7; // @[PTW.scala:353:19] reg [19:0] data_0; // @[PTW.scala:355:19] reg [19:0] data_1; // @[PTW.scala:355:19] reg [19:0] data_2; // @[PTW.scala:355:19] reg [19:0] data_3; // @[PTW.scala:355:19] reg [19:0] data_4; // @[PTW.scala:355:19] reg [19:0] data_5; // @[PTW.scala:355:19] reg [19:0] data_6; // @[PTW.scala:355:19] reg [19:0] data_7; // @[PTW.scala:355:19] wire _can_hit_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :358:18] wire _can_hit_T_1 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65] wire _can_hit_T_2 = r_req_vstage1 ? stage2 : _can_hit_T_1; // @[PTW.scala:270:18, :282:19, :358:{41,65}] wire can_hit = _can_hit_T & _can_hit_T_2; // @[PTW.scala:358:{18,35,41}] wire [32:0] tag = {r_req_vstage1, pte_addr}; // @[PTW.scala:270:18, :330:23, :364:15] wire _hits_T = {1'h0, tags_0} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_1 = {1'h0, tags_1} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_2 = {1'h0, tags_2} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_3 = {1'h0, tags_3} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_4 = {1'h0, tags_4} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_5 = {1'h0, tags_5} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_6 = {1'h0, tags_6} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_7 = {1'h0, tags_7} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire [1:0] hits_lo_lo = {_hits_T_1, _hits_T}; // @[package.scala:45:27] wire [1:0] hits_lo_hi = {_hits_T_3, _hits_T_2}; // @[package.scala:45:27] wire [3:0] hits_lo = {hits_lo_hi, hits_lo_lo}; // @[package.scala:45:27] wire [1:0] hits_hi_lo = {_hits_T_5, _hits_T_4}; // @[package.scala:45:27] wire [1:0] hits_hi_hi = {_hits_T_7, _hits_T_6}; // @[package.scala:45:27] wire [3:0] hits_hi = {hits_hi_hi, hits_hi_lo}; // @[package.scala:45:27] wire [7:0] _hits_T_8 = {hits_hi, hits_lo}; // @[package.scala:45:27] wire [7:0] hits = _hits_T_8 & valid; // @[package.scala:45:27] wire _hit_T = |hits; // @[PTW.scala:366:43, :367:20] wire pte_cache_hit = _hit_T & can_hit; // @[PTW.scala:358:35, :367:{20,24}] wire _r_T = &valid; // @[PTW.scala:352:24, :370:25] wire r_left_subtree_older = state_reg[6]; // @[Replacement.scala:168:70, :243:38] wire [2:0] r_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_3 = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] r_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :245:38] wire [2:0] state_reg_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire [2:0] state_reg_right_subtree_state_3 = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire r_left_subtree_older_1 = r_left_subtree_state[2]; // @[package.scala:163:13] wire r_left_subtree_state_1 = r_left_subtree_state[1]; // @[package.scala:163:13] wire _r_T_1 = r_left_subtree_state_1; // @[package.scala:163:13] wire r_right_subtree_state_1 = r_left_subtree_state[0]; // @[package.scala:163:13] wire _r_T_2 = r_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_T_3 = r_left_subtree_older_1 ? _r_T_1 : _r_T_2; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_4 = {r_left_subtree_older_1, _r_T_3}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_left_subtree_older_2 = r_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_left_subtree_state_2 = r_right_subtree_state[1]; // @[package.scala:163:13] wire _r_T_5 = r_left_subtree_state_2; // @[package.scala:163:13] wire r_right_subtree_state_2 = r_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_T_6 = r_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_T_7 = r_left_subtree_older_2 ? _r_T_5 : _r_T_6; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_8 = {r_left_subtree_older_2, _r_T_7}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_T_9 = r_left_subtree_older ? _r_T_4 : _r_T_8; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_T_10 = {r_left_subtree_older, _r_T_9}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [7:0] _r_T_11 = ~valid; // @[PTW.scala:352:24, :370:57] wire _r_T_12 = _r_T_11[0]; // @[OneHot.scala:48:45] wire _r_T_13 = _r_T_11[1]; // @[OneHot.scala:48:45] wire _r_T_14 = _r_T_11[2]; // @[OneHot.scala:48:45] wire _r_T_15 = _r_T_11[3]; // @[OneHot.scala:48:45] wire _r_T_16 = _r_T_11[4]; // @[OneHot.scala:48:45] wire _r_T_17 = _r_T_11[5]; // @[OneHot.scala:48:45] wire _r_T_18 = _r_T_11[6]; // @[OneHot.scala:48:45] wire _r_T_19 = _r_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_T_20 = {2'h3, ~_r_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_T_21 = _r_T_17 ? 3'h5 : _r_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_T_22 = _r_T_16 ? 3'h4 : _r_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_T_23 = _r_T_15 ? 3'h3 : _r_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_T_24 = _r_T_14 ? 3'h2 : _r_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_T_25 = _r_T_13 ? 3'h1 : _r_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_T_26 = _r_T_12 ? 3'h0 : _r_T_25; // @[OneHot.scala:48:45] wire [2:0] r = _r_T ? _r_T_10 : _r_T_26; // @[Mux.scala:50:70] wire [2:0] state_reg_touch_way_sized = r; // @[package.scala:163:13] wire [7:0] _valid_T = 8'h1 << r; // @[OneHot.scala:58:35] wire [7:0] _valid_T_1 = valid | _valid_T; // @[OneHot.scala:58:35] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_1 = state_reg_left_subtree_state[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_1 = state_reg_left_subtree_state[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13] wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_4 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_3; // @[package.scala:163:13] wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_8 = state_reg_set_left_older_1 ? _state_reg_T_7 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_9; // @[package.scala:163:13] wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_2 = state_reg_right_subtree_state[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = state_reg_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13] wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_15 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_14; // @[package.scala:163:13] wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_19 = state_reg_set_left_older_2 ? _state_reg_T_18 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire _T_167 = state == 3'h1; // @[PTW.scala:233:22, :377:24] wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46] assign _io_dpath_perf_pte_hit_T = _T_167; // @[PTW.scala:377:24, :394:46] wire _io_mem_req_valid_T; // @[PTW.scala:515:29] assign _io_mem_req_valid_T = _T_167; // @[PTW.scala:377:24, :515:29] wire _r_pte_T_4; // @[PTW.scala:672:15] assign _r_pte_T_4 = _T_167; // @[PTW.scala:377:24, :672:15] wire _r_pte_T_6; // @[PTW.scala:674:15] assign _r_pte_T_6 = _T_167; // @[PTW.scala:377:24, :674:15] wire [3:0] hi = hits[7:4]; // @[OneHot.scala:30:18] wire [3:0] lo = hits[3:0]; // @[OneHot.scala:31:18] wire [3:0] _T_30 = hi | lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_1 = _T_30[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_1 = _T_30[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_reg_touch_way_sized_1 = {|hi, |hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[2]; // @[package.scala:163:13] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T_23 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_34 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_4 = _state_reg_T_23[1]; // @[package.scala:163:13] wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13] wire _state_reg_T_24 = _state_reg_T_23[0]; // @[package.scala:163:13] wire _state_reg_T_28 = _state_reg_T_23[0]; // @[package.scala:163:13] wire _state_reg_T_25 = _state_reg_T_24; // @[package.scala:163:13] wire _state_reg_T_26 = ~_state_reg_T_25; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_27 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_26; // @[package.scala:163:13] wire _state_reg_T_29 = _state_reg_T_28; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_30 = ~_state_reg_T_29; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_31 = state_reg_set_left_older_4 ? _state_reg_T_30 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_4, _state_reg_T_27}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_32 = {state_reg_hi_3, _state_reg_T_31}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_33 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_32; // @[package.scala:163:13] wire _state_reg_set_left_older_T_5 = _state_reg_T_34[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38] wire _state_reg_T_35 = _state_reg_T_34[0]; // @[package.scala:163:13] wire _state_reg_T_39 = _state_reg_T_34[0]; // @[package.scala:163:13] wire _state_reg_T_36 = _state_reg_T_35; // @[package.scala:163:13] wire _state_reg_T_37 = ~_state_reg_T_36; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_38 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_37; // @[package.scala:163:13] wire _state_reg_T_40 = _state_reg_T_39; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_41 = ~_state_reg_T_40; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_42 = state_reg_set_left_older_5 ? _state_reg_T_41 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_4 = {state_reg_set_left_older_5, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_43 = {state_reg_hi_4, _state_reg_T_42}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_44 = state_reg_set_left_older_3 ? _state_reg_T_43 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_5 = {state_reg_set_left_older_3, _state_reg_T_33}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_45 = {state_reg_hi_5, _state_reg_T_44}; // @[Replacement.scala:202:12, :206:16] wire _leaf_T_2 = ~(|count); // @[PTW.scala:259:18, :324:40, :382:47, :751:53] wire [19:0] pte_cache_data = (hits[0] ? data_0 : 20'h0) | (hits[1] ? data_1 : 20'h0) | (hits[2] ? data_2 : 20'h0) | (hits[3] ? data_3 : 20'h0) | (hits[4] ? data_4 : 20'h0) | (hits[5] ? data_5 : 20'h0) | (hits[6] ? data_6 : 20'h0) | (hits[7] ? data_7 : 20'h0); // @[Mux.scala:30:73, :32:36] reg [6:0] state_reg_1; // @[Replacement.scala:168:70] reg [7:0] valid_1; // @[PTW.scala:352:24] reg [19:0] data_1_0; // @[PTW.scala:355:19] reg [19:0] data_1_1; // @[PTW.scala:355:19] reg [19:0] data_1_2; // @[PTW.scala:355:19] reg [19:0] data_1_3; // @[PTW.scala:355:19] reg [19:0] data_1_4; // @[PTW.scala:355:19] reg [19:0] data_1_5; // @[PTW.scala:355:19] reg [19:0] data_1_6; // @[PTW.scala:355:19] reg [19:0] data_1_7; // @[PTW.scala:355:19] wire _can_hit_T_3 = ~(|count); // @[PTW.scala:259:18, :324:40, :357:21] wire _can_hit_T_4 = ~(aux_count[1]); // @[PTW.scala:278:22, :357:60] wire _can_hit_T_5 = _can_hit_T_3 & _can_hit_T_4; // @[PTW.scala:357:{21,47,60}] wire _can_hit_T_6 = _can_hit_T_5 & r_req_vstage1; // @[PTW.scala:270:18, :357:{47,77}] wire _can_hit_T_7 = _can_hit_T_6 & stage2; // @[PTW.scala:282:19, :357:{77,94}] wire _can_hit_T_8 = ~stage2_final; // @[PTW.scala:283:25, :357:107] wire can_hit_1 = _can_hit_T_7 & _can_hit_T_8; // @[PTW.scala:357:{94,104,107}] wire _can_refill_T = ~stage2; // @[PTW.scala:282:19, :306:38, :360:33] wire _can_refill_T_1 = do_both_stages & _can_refill_T; // @[PTW.scala:288:38, :360:{30,33}] wire _can_refill_T_2 = ~stage2_final; // @[PTW.scala:283:25, :357:107, :360:44] wire can_refill = _can_refill_T_1 & _can_refill_T_2; // @[PTW.scala:360:{30,41,44}] wire _r_T_27 = &valid_1; // @[PTW.scala:352:24, :370:25] wire r_left_subtree_older_3 = state_reg_1[6]; // @[Replacement.scala:168:70, :243:38] wire [2:0] r_left_subtree_state_3 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_6 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_9 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] r_right_subtree_state_3 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :245:38] wire [2:0] state_reg_right_subtree_state_6 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire [2:0] state_reg_right_subtree_state_9 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire r_left_subtree_older_4 = r_left_subtree_state_3[2]; // @[package.scala:163:13] wire r_left_subtree_state_4 = r_left_subtree_state_3[1]; // @[package.scala:163:13] wire _r_T_28 = r_left_subtree_state_4; // @[package.scala:163:13] wire r_right_subtree_state_4 = r_left_subtree_state_3[0]; // @[package.scala:163:13] wire _r_T_29 = r_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12] wire _r_T_30 = r_left_subtree_older_4 ? _r_T_28 : _r_T_29; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_31 = {r_left_subtree_older_4, _r_T_30}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_left_subtree_older_5 = r_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38] wire r_left_subtree_state_5 = r_right_subtree_state_3[1]; // @[package.scala:163:13] wire _r_T_32 = r_left_subtree_state_5; // @[package.scala:163:13] wire r_right_subtree_state_5 = r_right_subtree_state_3[0]; // @[Replacement.scala:245:38] wire _r_T_33 = r_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12] wire _r_T_34 = r_left_subtree_older_5 ? _r_T_32 : _r_T_33; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_35 = {r_left_subtree_older_5, _r_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_T_36 = r_left_subtree_older_3 ? _r_T_31 : _r_T_35; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_T_37 = {r_left_subtree_older_3, _r_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [7:0] _r_T_38 = ~valid_1; // @[PTW.scala:352:24, :370:57] wire _r_T_39 = _r_T_38[0]; // @[OneHot.scala:48:45] wire _r_T_40 = _r_T_38[1]; // @[OneHot.scala:48:45] wire _r_T_41 = _r_T_38[2]; // @[OneHot.scala:48:45] wire _r_T_42 = _r_T_38[3]; // @[OneHot.scala:48:45] wire _r_T_43 = _r_T_38[4]; // @[OneHot.scala:48:45] wire _r_T_44 = _r_T_38[5]; // @[OneHot.scala:48:45] wire _r_T_45 = _r_T_38[6]; // @[OneHot.scala:48:45] wire _r_T_46 = _r_T_38[7]; // @[OneHot.scala:48:45] wire [2:0] _r_T_47 = {2'h3, ~_r_T_45}; // @[OneHot.scala:48:45] wire [2:0] _r_T_48 = _r_T_44 ? 3'h5 : _r_T_47; // @[OneHot.scala:48:45] wire [2:0] _r_T_49 = _r_T_43 ? 3'h4 : _r_T_48; // @[OneHot.scala:48:45] wire [2:0] _r_T_50 = _r_T_42 ? 3'h3 : _r_T_49; // @[OneHot.scala:48:45] wire [2:0] _r_T_51 = _r_T_41 ? 3'h2 : _r_T_50; // @[OneHot.scala:48:45] wire [2:0] _r_T_52 = _r_T_40 ? 3'h1 : _r_T_51; // @[OneHot.scala:48:45] wire [2:0] _r_T_53 = _r_T_39 ? 3'h0 : _r_T_52; // @[OneHot.scala:48:45] wire [2:0] r_1 = _r_T_27 ? _r_T_37 : _r_T_53; // @[Mux.scala:50:70] wire [2:0] state_reg_touch_way_sized_2 = r_1; // @[package.scala:163:13] wire [7:0] _valid_T_2 = 8'h1 << r_1; // @[OneHot.scala:58:35] wire [7:0] _valid_T_3 = valid_1 | _valid_T_2; // @[OneHot.scala:58:35] wire _state_reg_set_left_older_T_6 = state_reg_touch_way_sized_2[2]; // @[package.scala:163:13] wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T_46 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_57 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_7 = _state_reg_T_46[1]; // @[package.scala:163:13] wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[0]; // @[package.scala:163:13] wire _state_reg_T_47 = _state_reg_T_46[0]; // @[package.scala:163:13] wire _state_reg_T_51 = _state_reg_T_46[0]; // @[package.scala:163:13] wire _state_reg_T_48 = _state_reg_T_47; // @[package.scala:163:13] wire _state_reg_T_49 = ~_state_reg_T_48; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_50 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_49; // @[package.scala:163:13] wire _state_reg_T_52 = _state_reg_T_51; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_53 = ~_state_reg_T_52; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_54 = state_reg_set_left_older_7 ? _state_reg_T_53 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_7, _state_reg_T_50}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_55 = {state_reg_hi_6, _state_reg_T_54}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_56 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_55; // @[package.scala:163:13] wire _state_reg_set_left_older_T_8 = _state_reg_T_57[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_8 = state_reg_right_subtree_state_6[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_8 = state_reg_right_subtree_state_6[0]; // @[Replacement.scala:198:38] wire _state_reg_T_58 = _state_reg_T_57[0]; // @[package.scala:163:13] wire _state_reg_T_62 = _state_reg_T_57[0]; // @[package.scala:163:13] wire _state_reg_T_59 = _state_reg_T_58; // @[package.scala:163:13] wire _state_reg_T_60 = ~_state_reg_T_59; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_61 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_60; // @[package.scala:163:13] wire _state_reg_T_63 = _state_reg_T_62; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_64 = ~_state_reg_T_63; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_65 = state_reg_set_left_older_8 ? _state_reg_T_64 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_7 = {state_reg_set_left_older_8, _state_reg_T_61}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_66 = {state_reg_hi_7, _state_reg_T_65}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_67 = state_reg_set_left_older_6 ? _state_reg_T_66 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_8 = {state_reg_set_left_older_6, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_68 = {state_reg_hi_8, _state_reg_T_67}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_79 = state_reg_left_subtree_state_9; // @[package.scala:163:13] wire state_reg_left_subtree_state_10 = state_reg_left_subtree_state_9[1]; // @[package.scala:163:13] wire _state_reg_T_73 = state_reg_left_subtree_state_10; // @[package.scala:163:13] wire state_reg_right_subtree_state_10 = state_reg_left_subtree_state_9[0]; // @[package.scala:163:13] wire [1:0] state_reg_hi_9 = {1'h1, _state_reg_T_73}; // @[Replacement.scala:202:12, :203:16] wire [2:0] _state_reg_T_78 = {state_reg_hi_9, 1'h1}; // @[Replacement.scala:202:12] wire state_reg_left_subtree_state_11 = state_reg_right_subtree_state_9[1]; // @[package.scala:163:13] wire _state_reg_T_84 = state_reg_left_subtree_state_11; // @[package.scala:163:13] wire state_reg_right_subtree_state_11 = state_reg_right_subtree_state_9[0]; // @[Replacement.scala:198:38] wire [1:0] state_reg_hi_10 = {1'h1, _state_reg_T_84}; // @[Replacement.scala:202:12, :203:16] wire [2:0] _state_reg_T_89 = {state_reg_hi_10, 1'h1}; // @[Replacement.scala:202:12] wire [2:0] _state_reg_T_90 = _state_reg_T_89; // @[Replacement.scala:202:12, :206:16] wire [3:0] state_reg_hi_11 = {1'h1, _state_reg_T_79}; // @[Replacement.scala:202:12, :203:16] wire [6:0] _state_reg_T_91 = {state_reg_hi_11, _state_reg_T_90}; // @[Replacement.scala:202:12, :206:16] reg pte_hit; // @[PTW.scala:392:24] wire _io_dpath_perf_pte_hit_T_1 = pte_hit & _io_dpath_perf_pte_hit_T; // @[PTW.scala:392:24, :394:{36,46}] wire _io_dpath_perf_pte_hit_T_2 = ~io_dpath_perf_l2hit_0; // @[PTW.scala:219:7, :394:60] assign _io_dpath_perf_pte_hit_T_3 = _io_dpath_perf_pte_hit_T_1 & _io_dpath_perf_pte_hit_T_2; // @[PTW.scala:394:{36,57,60}] assign io_dpath_perf_pte_hit_0 = _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:219:7, :394:57] reg l2_refill; // @[PTW.scala:398:26] assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26] wire [8:0] r_idx; // @[package.scala:163:13] wire [8:0] _s1_rdata_WIRE; // @[PTW.scala:472:28] wire s0_valid; // @[PTW.scala:467:31] reg [511:0] g_0; // @[PTW.scala:421:16] reg [511:0] valid_2_0; // @[PTW.scala:422:24] wire [18:0] r_tag = {r_req_vstage1, r_req_addr[26:9]}; // @[package.scala:163:13] assign r_idx = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_2_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[package.scala:163:13] wire [511:0] _GEN = {503'h0, r_idx}; // @[package.scala:163:13] wire [511:0] _r_valid_vec_T = valid_2_0 >> _GEN; // @[PTW.scala:422:24, :426:34] wire r_valid_vec = _r_valid_vec_T[0]; // @[PTW.scala:426:34] reg r_valid_vec_q; // @[PTW.scala:427:28] assign writeEnable = l2_refill & ~invalidated; // @[PTW.scala:251:24, :369:68, :398:26, :433:21] wire [17:0] entry_tag; // @[PTW.scala:434:23] wire [19:0] entry_ppn; // @[PTW.scala:434:23] assign entry_ppn = r_pte_ppn[19:0]; // @[PTW.scala:275:18, :434:23, :435:17] assign entry_tag = r_tag[17:0]; // @[package.scala:163:13] wire [1:0] lo_lo = {entry_w, entry_r}; // @[PTW.scala:434:23, :446:82] wire [1:0] lo_hi = {entry_u, entry_x}; // @[PTW.scala:434:23, :446:82] wire [3:0] lo_4 = {lo_hi, lo_lo}; // @[PTW.scala:446:82] wire [1:0] hi_lo = {entry_d, entry_a}; // @[PTW.scala:434:23, :446:82] wire [37:0] hi_hi = {entry_tag, entry_ppn}; // @[PTW.scala:434:23, :446:82] wire [39:0] hi_4 = {hi_hi, hi_lo}; // @[PTW.scala:446:82] wire [511:0] mask = 512'h1 << _GEN; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T = valid_2_0 | mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T = g_0 | mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T_1 = ~mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T_2 = g_0 & _g_0_T_1; // @[PTW.scala:421:16, :452:{56,58}] wire [511:0] _g_0_T_3 = r_pte_g ? _g_0_T : _g_0_T_2; // @[PTW.scala:275:18, :452:{24,41,56}] wire [8:0] _valid_0_T_3 = io_dpath_sfence_bits_addr_0[20:12]; // @[PTW.scala:219:7, :461:96] wire [511:0] _valid_0_T_4 = 512'h1 << _valid_0_T_3; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T_5 = ~_valid_0_T_4; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T_6 = valid_2_0 & _valid_0_T_5; // @[PTW.scala:422:24, :461:{59,61}] wire [511:0] _valid_0_T_9 = valid_2_0 & g_0; // @[PTW.scala:421:16, :422:24, :462:59] wire [511:0] _valid_0_T_10 = _valid_0_T_8 ? _valid_0_T_9 : 512'h0; // @[PTW.scala:462:{14,19,59}] wire [511:0] _valid_0_T_11 = _valid_0_T_2 ? _valid_0_T_6 : _valid_0_T_10; // @[PTW.scala:461:{14,19,59}, :462:14] wire _s0_valid_T = ~l2_refill; // @[PTW.scala:398:26, :467:20] wire _T_144 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire _s0_valid_T_1; // @[Decoupled.scala:51:35] assign _s0_valid_T_1 = _T_144; // @[Decoupled.scala:51:35] wire _r_pte_T_25; // @[Decoupled.scala:51:35] assign _r_pte_T_25 = _T_144; // @[Decoupled.scala:51:35] assign s0_valid = _s0_valid_T & _s0_valid_T_1; // @[Decoupled.scala:51:35] wire _s0_suitable_T_1 = ~_arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19, :468:87] wire s0_suitable = _s0_suitable_T_1; // @[PTW.scala:468:{84,87}] wire _s1_valid_T = s0_valid & s0_suitable; // @[PTW.scala:467:31, :468:84, :469:37] wire _s1_valid_T_1 = _s1_valid_T & _arb_io_out_bits_valid; // @[PTW.scala:236:19, :469:{37,52}] reg s1_valid; // @[PTW.scala:469:27] reg s2_valid; // @[PTW.scala:470:27] wire [8:0] _s1_rdata_T = _arb_io_out_bits_bits_addr[8:0]; // @[PTW.scala:236:19, :472:54] assign _s1_rdata_WIRE = _s1_rdata_T; // @[PTW.scala:472:{28,54}] reg [44:0] r_2; // @[PTW.scala:473:66] wire [43:0] uncorrected = r_2[43:0]; // @[ECC.scala:75:24] wire [43:0] _s2_entry_vec_WIRE = uncorrected; // @[ECC.scala:75:24] wire uncorrectable = ^r_2; // @[ECC.scala:78:27] wire _s2_error_T_1 = uncorrectable; // @[ECC.scala:15:27, :78:27] reg s2_valid_vec; // @[PTW.scala:474:33] wire _s2_error_T = s2_valid_vec; // @[PTW.scala:474:33, :476:75] wire _s2_hit_vec_T = s2_valid_vec; // @[PTW.scala:474:33, :480:77] wire [511:0] _s2_g_vec_T = g_0 >> _GEN; // @[PTW.scala:421:16, :426:34, :475:45] wire _s2_g_vec_T_1 = _s2_g_vec_T[0]; // @[PTW.scala:475:45] wire _s2_g_vec_WIRE_0 = _s2_g_vec_T_1; // @[PTW.scala:475:{37,45}] reg s2_g_vec_0; // @[PTW.scala:475:29] wire l2_pte_g = s2_g_vec_0; // @[PTW.scala:475:29, :489:22] wire l2_error = _s2_error_T & _s2_error_T_1; // @[ECC.scala:15:27] wire [17:0] _s2_entry_vec_T_7; // @[PTW.scala:479:59] wire [19:0] _s2_entry_vec_T_6; // @[PTW.scala:479:59] wire _s2_entry_vec_T_5; // @[PTW.scala:479:59] wire _s2_entry_vec_T_4; // @[PTW.scala:479:59] wire l2_pte_d = s2_entry_vec_0_d; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_3; // @[PTW.scala:479:59] wire l2_pte_a = s2_entry_vec_0_a; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_2; // @[PTW.scala:479:59] wire l2_pte_u = s2_entry_vec_0_u; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_1; // @[PTW.scala:479:59] wire l2_pte_x = s2_entry_vec_0_x; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T; // @[PTW.scala:479:59] wire l2_pte_w = s2_entry_vec_0_w; // @[PTW.scala:479:59, :489:22] wire [17:0] s2_entry_vec_0_tag; // @[PTW.scala:479:59] wire [19:0] s2_entry_vec_0_ppn; // @[PTW.scala:479:59] wire s2_entry_vec_0_r; // @[PTW.scala:479:59] wire l2_pte_r = s2_entry_vec_0_r; // @[PTW.scala:479:59, :489:22] assign _s2_entry_vec_T = _s2_entry_vec_WIRE[0]; // @[PTW.scala:479:59] assign s2_entry_vec_0_r = _s2_entry_vec_T; // @[PTW.scala:479:59] assign _s2_entry_vec_T_1 = _s2_entry_vec_WIRE[1]; // @[PTW.scala:479:59] assign s2_entry_vec_0_w = _s2_entry_vec_T_1; // @[PTW.scala:479:59] assign _s2_entry_vec_T_2 = _s2_entry_vec_WIRE[2]; // @[PTW.scala:479:59] assign s2_entry_vec_0_x = _s2_entry_vec_T_2; // @[PTW.scala:479:59] assign _s2_entry_vec_T_3 = _s2_entry_vec_WIRE[3]; // @[PTW.scala:479:59] assign s2_entry_vec_0_u = _s2_entry_vec_T_3; // @[PTW.scala:479:59] assign _s2_entry_vec_T_4 = _s2_entry_vec_WIRE[4]; // @[PTW.scala:479:59] assign s2_entry_vec_0_a = _s2_entry_vec_T_4; // @[PTW.scala:479:59] assign _s2_entry_vec_T_5 = _s2_entry_vec_WIRE[5]; // @[PTW.scala:479:59] assign s2_entry_vec_0_d = _s2_entry_vec_T_5; // @[PTW.scala:479:59] assign _s2_entry_vec_T_6 = _s2_entry_vec_WIRE[25:6]; // @[PTW.scala:479:59] assign s2_entry_vec_0_ppn = _s2_entry_vec_T_6; // @[PTW.scala:479:59] assign _s2_entry_vec_T_7 = _s2_entry_vec_WIRE[43:26]; // @[PTW.scala:479:59] assign s2_entry_vec_0_tag = _s2_entry_vec_T_7; // @[PTW.scala:479:59] wire _s2_hit_vec_T_1 = r_tag == {1'h0, s2_entry_vec_0_tag}; // @[package.scala:163:13] wire s2_hit_vec_0 = _s2_hit_vec_T & _s2_hit_vec_T_1; // @[PTW.scala:480:{77,83,93}] assign l2_hit = s2_valid & s2_hit_vec_0; // @[PTW.scala:470:27, :480:83, :481:27] assign io_dpath_perf_l2hit_0 = l2_hit; // @[PTW.scala:219:7, :481:27] wire _io_dpath_perf_l2miss_T = ~s2_hit_vec_0; // @[PTW.scala:480:83, :482:41] assign _io_dpath_perf_l2miss_T_1 = s2_valid & _io_dpath_perf_l2miss_T; // @[PTW.scala:470:27, :482:{38,41}] assign io_dpath_perf_l2miss_0 = _io_dpath_perf_l2miss_T_1; // @[PTW.scala:219:7, :482:38] wire r_pte_pte_d = l2_pte_d; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_d = l2_pte_d; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_a = l2_pte_a; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_a = l2_pte_a; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_g = l2_pte_g; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_g = l2_pte_g; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_u = l2_pte_u; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_u = l2_pte_u; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_x = l2_pte_x; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_x = l2_pte_x; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_w = l2_pte_w; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_w = l2_pte_w; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_r = l2_pte_r; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_r = l2_pte_r; // @[PTW.scala:489:22, :771:26] wire [43:0] l2_pte_ppn; // @[PTW.scala:489:22] assign l2_pte_ppn = {24'h0, s2_entry_vec_0_ppn}; // @[PTW.scala:479:59, :489:22, :491:16] wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65] wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}] wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}] wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48] assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}] assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39] assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24] wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43] assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}] assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40] wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38] wire _io_mem_s1_kill_T_1 = l2_hit | _io_mem_s1_kill_T; // @[PTW.scala:481:27, :531:{28,38}] assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}] assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51] wire [55:0] _GEN_0 = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96] wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T = _GEN_0; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_7 = _GEN_0; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_37 = _GEN_0; // @[PTW.scala:544:96] wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80] assign _pmpHomogeneous_T = _GEN_0; // @[PTW.scala:544:96, :548:80] wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65] wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}] wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 | _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}] wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65] wire [55:0] _GEN_1 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_43 = _GEN_1; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_110 = _GEN_1; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_48 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_98; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_98 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_115; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_115 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_147 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_154 = _GEN_2; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_68; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_68 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_120; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_120 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_135; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_135 = _GEN_3; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_78 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_4 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_83; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_83 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_125; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_125 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_140; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_140 = _GEN_4; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 | _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 | _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90 | _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 | _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92 | _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 | _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 | _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95 | _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65] wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_96 | _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_99 = {1'h0, _pmaPgLevelHomogeneous_T_98}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_104 = ~_pmaPgLevelHomogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_106 = {1'h0, _pmaPgLevelHomogeneous_T_105}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_109 = _pmaPgLevelHomogeneous_T_108 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_109; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_116 = {1'h0, _pmaPgLevelHomogeneous_T_115}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_116 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_118 = _pmaPgLevelHomogeneous_T_117; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_121 = {1'h0, _pmaPgLevelHomogeneous_T_120}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_122 = _pmaPgLevelHomogeneous_T_121 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_123 = _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_126 = {1'h0, _pmaPgLevelHomogeneous_T_125}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_127 = _pmaPgLevelHomogeneous_T_126 & 57'h90000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_128 = _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 | _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_132 = _pmaPgLevelHomogeneous_T_131 | _pmaPgLevelHomogeneous_T_119; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_133 = _pmaPgLevelHomogeneous_T_132 | _pmaPgLevelHomogeneous_T_124; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 | _pmaPgLevelHomogeneous_T_129; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_136 = {1'h0, _pmaPgLevelHomogeneous_T_135}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_137 = _pmaPgLevelHomogeneous_T_136 & 57'h8E000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_138 = _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_139; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_141 = {1'h0, _pmaPgLevelHomogeneous_T_140}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_141 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 | _pmaPgLevelHomogeneous_T_144; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_152 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_153 = ~_pmaPgLevelHomogeneous_T_152; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_155 = {1'h0, _pmaPgLevelHomogeneous_T_154}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_156; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_159 = _pmaPgLevelHomogeneous_T_158; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_160 = ~_pmaPgLevelHomogeneous_T_159; // @[TLBPermissions.scala:87:{22,66}] wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86] wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_2 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_4 = _pmpHomogeneous_maskHomogeneous_T_3 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_6 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_4; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_7 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_7 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}] wire [31:0] _GEN_5 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_2 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_9 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_16; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_16 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_8 = |_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_15 = |_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_17 = ~_pmpHomogeneous_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_18 = {_pmpHomogeneous_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_19 = ~_pmpHomogeneous_T_18; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_20 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_19}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_21 = _pmpHomogeneous_T_20[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_22 = |_pmpHomogeneous_T_21; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_24 = _pmpHomogeneous_T_23 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_26 = _pmpHomogeneous_T_25 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_27 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_28 = _pmpHomogeneous_T_27 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_29 = pmpHomogeneous_maskHomogeneous | _pmpHomogeneous_T_28; // @[package.scala:39:76] wire _pmpHomogeneous_T_30 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_31 = ~_pmpHomogeneous_T_30; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}] wire _pmpHomogeneous_T_32 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21] wire [31:0] _pmpHomogeneous_pgMask_T_1 = _pmpHomogeneous_pgMask_T ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_3 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_1; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_4 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_3; // @[package.scala:39:{76,86}] wire [55:0] _GEN_6 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T = _GEN_6; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_6; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_33 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62] wire _pmpHomogeneous_T_34 = _pmpHomogeneous_T_32 | _pmpHomogeneous_T_33; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_35 = _pmpHomogeneous_T_31 | _pmpHomogeneous_T_34; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_36 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_29 : _pmpHomogeneous_T_35; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_37 = _pmpHomogeneous_T_36; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_38 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_8 = io_dpath_pmp_1_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_1_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_12 = _pmpHomogeneous_maskHomogeneous_T_11 ? _pmpHomogeneous_maskHomogeneous_T_9 : _pmpHomogeneous_maskHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_14 = _pmpHomogeneous_maskHomogeneous_T_13 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_15 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_15 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_14; // @[package.scala:39:{76,86}] wire [31:0] _GEN_7 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_39; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_39 = _GEN_7; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_46; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_46 = _GEN_7; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_53; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_53 = _GEN_7; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_7; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_7; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_7; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_7; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_40 = ~_pmpHomogeneous_T_39; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_41 = {_pmpHomogeneous_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_42 = ~_pmpHomogeneous_T_41; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_43 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_42}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_44 = _pmpHomogeneous_T_43[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_45 = |_pmpHomogeneous_T_44; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_47 = ~_pmpHomogeneous_T_46; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_48 = {_pmpHomogeneous_T_47[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_49 = ~_pmpHomogeneous_T_48; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_50 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_49}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_51 = _pmpHomogeneous_T_50[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_52 = |_pmpHomogeneous_T_51; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_54 = ~_pmpHomogeneous_T_53; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_55 = {_pmpHomogeneous_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_56 = ~_pmpHomogeneous_T_55; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_57 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_56}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_58 = _pmpHomogeneous_T_57[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_59 = |_pmpHomogeneous_T_58; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_61 = _pmpHomogeneous_T_60 ? _pmpHomogeneous_T_52 : _pmpHomogeneous_T_45; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_63 = _pmpHomogeneous_T_62 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_61; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_64 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_65 = _pmpHomogeneous_T_64 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_63; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_66 = pmpHomogeneous_maskHomogeneous_1 | _pmpHomogeneous_T_65; // @[package.scala:39:76] wire _pmpHomogeneous_T_67 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_68 = ~_pmpHomogeneous_T_67; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_6 = _pmpHomogeneous_pgMask_T_5 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_8 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_6; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_9 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_9 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_8; // @[package.scala:39:{76,86}] wire [55:0] _GEN_8 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_8; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_8; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_69 = pmpHomogeneous_endsBeforeLower_1 | pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_70 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_71 = _pmpHomogeneous_T_69 | _pmpHomogeneous_T_70; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_72 = _pmpHomogeneous_T_68 | _pmpHomogeneous_T_71; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_73 = _pmpHomogeneous_T_38 ? _pmpHomogeneous_T_66 : _pmpHomogeneous_T_72; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_74 = _pmpHomogeneous_T_37 & _pmpHomogeneous_T_73; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_75 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_2_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_17 = io_dpath_pmp_2_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_20 = _pmpHomogeneous_maskHomogeneous_T_19 ? _pmpHomogeneous_maskHomogeneous_T_17 : _pmpHomogeneous_maskHomogeneous_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_22 = _pmpHomogeneous_maskHomogeneous_T_21 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_20; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_23 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_22; // @[package.scala:39:{76,86}] wire [31:0] _GEN_9 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_76; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_76 = _GEN_9; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_83; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_83 = _GEN_9; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_90; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_90 = _GEN_9; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_9; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_9; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_9; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_9; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_77 = ~_pmpHomogeneous_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_78 = {_pmpHomogeneous_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_79 = ~_pmpHomogeneous_T_78; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_80 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_79}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_81 = _pmpHomogeneous_T_80[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_82 = |_pmpHomogeneous_T_81; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_84 = ~_pmpHomogeneous_T_83; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_85 = {_pmpHomogeneous_T_84[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_86 = ~_pmpHomogeneous_T_85; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_87 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_86}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_88 = _pmpHomogeneous_T_87[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_89 = |_pmpHomogeneous_T_88; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_91 = ~_pmpHomogeneous_T_90; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_92 = {_pmpHomogeneous_T_91[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_93 = ~_pmpHomogeneous_T_92; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_94 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_93}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_96 = |_pmpHomogeneous_T_95; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_98 = _pmpHomogeneous_T_97 ? _pmpHomogeneous_T_89 : _pmpHomogeneous_T_82; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_100 = _pmpHomogeneous_T_99 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_98; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_101 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_102 = _pmpHomogeneous_T_101 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_100; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_103 = pmpHomogeneous_maskHomogeneous_2 | _pmpHomogeneous_T_102; // @[package.scala:39:76] wire _pmpHomogeneous_T_104 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_105 = ~_pmpHomogeneous_T_104; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_11 = _pmpHomogeneous_pgMask_T_10 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_13 = _pmpHomogeneous_pgMask_T_12 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_11; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_14 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_14 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_13; // @[package.scala:39:{76,86}] wire [55:0] _GEN_10 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_10; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_10; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_106 = pmpHomogeneous_endsBeforeLower_2 | pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_107 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_108 = _pmpHomogeneous_T_106 | _pmpHomogeneous_T_107; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_109 = _pmpHomogeneous_T_105 | _pmpHomogeneous_T_108; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_110 = _pmpHomogeneous_T_75 ? _pmpHomogeneous_T_103 : _pmpHomogeneous_T_109; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_111 = _pmpHomogeneous_T_74 & _pmpHomogeneous_T_110; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_112 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_24 = io_dpath_pmp_3_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_25 = io_dpath_pmp_3_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_26 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_28 = _pmpHomogeneous_maskHomogeneous_T_27 ? _pmpHomogeneous_maskHomogeneous_T_25 : _pmpHomogeneous_maskHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_30 = _pmpHomogeneous_maskHomogeneous_T_29 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_28; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_31 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_31 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_30; // @[package.scala:39:{76,86}] wire [31:0] _GEN_11 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_113; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_113 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_120; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_120 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_127; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_127 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T_114[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_116 = ~_pmpHomogeneous_T_115; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_117 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_116}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_118 = _pmpHomogeneous_T_117[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_119 = |_pmpHomogeneous_T_118; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_121 = ~_pmpHomogeneous_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_122 = {_pmpHomogeneous_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_123 = ~_pmpHomogeneous_T_122; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_124 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_123}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_125 = _pmpHomogeneous_T_124[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_126 = |_pmpHomogeneous_T_125; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_128 = ~_pmpHomogeneous_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_129 = {_pmpHomogeneous_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_130 = ~_pmpHomogeneous_T_129; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_131 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_130}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_132 = _pmpHomogeneous_T_131[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_133 = |_pmpHomogeneous_T_132; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_135 = _pmpHomogeneous_T_134 ? _pmpHomogeneous_T_126 : _pmpHomogeneous_T_119; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_137 = _pmpHomogeneous_T_136 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_135; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_138 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_139 = _pmpHomogeneous_T_138 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_137; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_140 = pmpHomogeneous_maskHomogeneous_3 | _pmpHomogeneous_T_139; // @[package.scala:39:76] wire _pmpHomogeneous_T_141 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_16 = _pmpHomogeneous_pgMask_T_15 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_18 = _pmpHomogeneous_pgMask_T_17 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_19 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_19 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_18; // @[package.scala:39:{76,86}] wire [55:0] _GEN_12 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_12; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_12; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_143 = pmpHomogeneous_endsBeforeLower_3 | pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_144 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_145 = _pmpHomogeneous_T_143 | _pmpHomogeneous_T_144; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_146 = _pmpHomogeneous_T_142 | _pmpHomogeneous_T_145; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_147 = _pmpHomogeneous_T_112 ? _pmpHomogeneous_T_140 : _pmpHomogeneous_T_146; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_148 = _pmpHomogeneous_T_111 & _pmpHomogeneous_T_147; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_149 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_32 = io_dpath_pmp_4_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_33 = io_dpath_pmp_4_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_34 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_36 = _pmpHomogeneous_maskHomogeneous_T_35 ? _pmpHomogeneous_maskHomogeneous_T_33 : _pmpHomogeneous_maskHomogeneous_T_32; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_38 = _pmpHomogeneous_maskHomogeneous_T_37 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_39 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_39 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_38; // @[package.scala:39:{76,86}] wire [31:0] _GEN_13 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_150; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_150 = _GEN_13; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_157; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_157 = _GEN_13; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_164; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_164 = _GEN_13; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_13; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_13; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_13; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_13; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_151 = ~_pmpHomogeneous_T_150; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_152 = {_pmpHomogeneous_T_151[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_153 = ~_pmpHomogeneous_T_152; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_154 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_153}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_155 = _pmpHomogeneous_T_154[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_156 = |_pmpHomogeneous_T_155; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_158 = ~_pmpHomogeneous_T_157; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_159 = {_pmpHomogeneous_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_160 = ~_pmpHomogeneous_T_159; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_161 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_160}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_162 = _pmpHomogeneous_T_161[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_163 = |_pmpHomogeneous_T_162; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_165 = ~_pmpHomogeneous_T_164; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_166 = {_pmpHomogeneous_T_165[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_167 = ~_pmpHomogeneous_T_166; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_168 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_167}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_169 = _pmpHomogeneous_T_168[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_170 = |_pmpHomogeneous_T_169; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_172 = _pmpHomogeneous_T_171 ? _pmpHomogeneous_T_163 : _pmpHomogeneous_T_156; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_174 = _pmpHomogeneous_T_173 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_172; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_175 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_176 = _pmpHomogeneous_T_175 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_174; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_177 = pmpHomogeneous_maskHomogeneous_4 | _pmpHomogeneous_T_176; // @[package.scala:39:76] wire _pmpHomogeneous_T_178 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_179 = ~_pmpHomogeneous_T_178; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_21 = _pmpHomogeneous_pgMask_T_20 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_23 = _pmpHomogeneous_pgMask_T_22 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_21; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_24 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_24 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_23; // @[package.scala:39:{76,86}] wire [55:0] _GEN_14 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_14; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_14; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_180 = pmpHomogeneous_endsBeforeLower_4 | pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_181 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_182 = _pmpHomogeneous_T_180 | _pmpHomogeneous_T_181; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_183 = _pmpHomogeneous_T_179 | _pmpHomogeneous_T_182; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_184 = _pmpHomogeneous_T_149 ? _pmpHomogeneous_T_177 : _pmpHomogeneous_T_183; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_185 = _pmpHomogeneous_T_148 & _pmpHomogeneous_T_184; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_186 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_40 = io_dpath_pmp_5_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_41 = io_dpath_pmp_5_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_42 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_44 = _pmpHomogeneous_maskHomogeneous_T_43 ? _pmpHomogeneous_maskHomogeneous_T_41 : _pmpHomogeneous_maskHomogeneous_T_40; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_46 = _pmpHomogeneous_maskHomogeneous_T_45 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_44; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_47 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_47 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_46; // @[package.scala:39:{76,86}] wire [31:0] _GEN_15 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_187; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_187 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_194; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_194 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_201; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_201 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_188 = ~_pmpHomogeneous_T_187; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_189 = {_pmpHomogeneous_T_188[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_190 = ~_pmpHomogeneous_T_189; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_191 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_190}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_192 = _pmpHomogeneous_T_191[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_193 = |_pmpHomogeneous_T_192; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_195 = ~_pmpHomogeneous_T_194; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_196 = {_pmpHomogeneous_T_195[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_197 = ~_pmpHomogeneous_T_196; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_198 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_197}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_199 = _pmpHomogeneous_T_198[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_200 = |_pmpHomogeneous_T_199; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_203 = {_pmpHomogeneous_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_204 = ~_pmpHomogeneous_T_203; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_205 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_204}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_206 = _pmpHomogeneous_T_205[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_207 = |_pmpHomogeneous_T_206; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_209 = _pmpHomogeneous_T_208 ? _pmpHomogeneous_T_200 : _pmpHomogeneous_T_193; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_211 = _pmpHomogeneous_T_210 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_209; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_212 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_213 = _pmpHomogeneous_T_212 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_211; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_214 = pmpHomogeneous_maskHomogeneous_5 | _pmpHomogeneous_T_213; // @[package.scala:39:76] wire _pmpHomogeneous_T_215 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_216 = ~_pmpHomogeneous_T_215; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_26 = _pmpHomogeneous_pgMask_T_25 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_28 = _pmpHomogeneous_pgMask_T_27 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_29 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_29 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_28; // @[package.scala:39:{76,86}] wire [55:0] _GEN_16 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_16; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_16; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_217 = pmpHomogeneous_endsBeforeLower_5 | pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_218 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_219 = _pmpHomogeneous_T_217 | _pmpHomogeneous_T_218; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_220 = _pmpHomogeneous_T_216 | _pmpHomogeneous_T_219; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_221 = _pmpHomogeneous_T_186 ? _pmpHomogeneous_T_214 : _pmpHomogeneous_T_220; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_222 = _pmpHomogeneous_T_185 & _pmpHomogeneous_T_221; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_223 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_48 = io_dpath_pmp_6_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_49 = io_dpath_pmp_6_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_50 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_52 = _pmpHomogeneous_maskHomogeneous_T_51 ? _pmpHomogeneous_maskHomogeneous_T_49 : _pmpHomogeneous_maskHomogeneous_T_48; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_54 = _pmpHomogeneous_maskHomogeneous_T_53 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_52; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_55 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_55 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_54; // @[package.scala:39:{76,86}] wire [31:0] _GEN_17 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_224; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_224 = _GEN_17; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_231; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_231 = _GEN_17; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_238; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_238 = _GEN_17; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_17; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_17; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_17; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_17; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_225 = ~_pmpHomogeneous_T_224; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_226 = {_pmpHomogeneous_T_225[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_227 = ~_pmpHomogeneous_T_226; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_228 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_227}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_229 = _pmpHomogeneous_T_228[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_230 = |_pmpHomogeneous_T_229; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_232 = ~_pmpHomogeneous_T_231; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_233 = {_pmpHomogeneous_T_232[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_234 = ~_pmpHomogeneous_T_233; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_235 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_234}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_236 = _pmpHomogeneous_T_235[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_237 = |_pmpHomogeneous_T_236; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_239 = ~_pmpHomogeneous_T_238; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_240 = {_pmpHomogeneous_T_239[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_241 = ~_pmpHomogeneous_T_240; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_242 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_241}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_243 = _pmpHomogeneous_T_242[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_244 = |_pmpHomogeneous_T_243; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_246 = _pmpHomogeneous_T_245 ? _pmpHomogeneous_T_237 : _pmpHomogeneous_T_230; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_248 = _pmpHomogeneous_T_247 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_246; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_249 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_250 = _pmpHomogeneous_T_249 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_248; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_251 = pmpHomogeneous_maskHomogeneous_6 | _pmpHomogeneous_T_250; // @[package.scala:39:76] wire _pmpHomogeneous_T_252 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_253 = ~_pmpHomogeneous_T_252; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_31 = _pmpHomogeneous_pgMask_T_30 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_33 = _pmpHomogeneous_pgMask_T_32 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_31; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_34 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_34 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_33; // @[package.scala:39:{76,86}] wire [55:0] _GEN_18 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_18; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_18; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_254 = pmpHomogeneous_endsBeforeLower_6 | pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_255 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_256 = _pmpHomogeneous_T_254 | _pmpHomogeneous_T_255; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_257 = _pmpHomogeneous_T_253 | _pmpHomogeneous_T_256; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_258 = _pmpHomogeneous_T_223 ? _pmpHomogeneous_T_251 : _pmpHomogeneous_T_257; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_259 = _pmpHomogeneous_T_222 & _pmpHomogeneous_T_258; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_260 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_56 = io_dpath_pmp_7_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_57 = io_dpath_pmp_7_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_58 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_60 = _pmpHomogeneous_maskHomogeneous_T_59 ? _pmpHomogeneous_maskHomogeneous_T_57 : _pmpHomogeneous_maskHomogeneous_T_56; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_62 = _pmpHomogeneous_maskHomogeneous_T_61 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_60; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_63 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_63 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_62; // @[package.scala:39:{76,86}] wire [31:0] _GEN_19 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_261; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_261 = _GEN_19; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_268; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_268 = _GEN_19; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_275; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_275 = _GEN_19; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_19; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_19; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_262 = ~_pmpHomogeneous_T_261; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_263 = {_pmpHomogeneous_T_262[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_264 = ~_pmpHomogeneous_T_263; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_265 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_264}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_266 = _pmpHomogeneous_T_265[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_267 = |_pmpHomogeneous_T_266; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_269 = ~_pmpHomogeneous_T_268; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_270 = {_pmpHomogeneous_T_269[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_271 = ~_pmpHomogeneous_T_270; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_272 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_271}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_273 = _pmpHomogeneous_T_272[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_274 = |_pmpHomogeneous_T_273; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_276 = ~_pmpHomogeneous_T_275; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_277 = {_pmpHomogeneous_T_276[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_278 = ~_pmpHomogeneous_T_277; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_279 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_278}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_280 = _pmpHomogeneous_T_279[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_281 = |_pmpHomogeneous_T_280; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_283 = _pmpHomogeneous_T_282 ? _pmpHomogeneous_T_274 : _pmpHomogeneous_T_267; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_285 = _pmpHomogeneous_T_284 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_283; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_286 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_287 = _pmpHomogeneous_T_286 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_285; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_288 = pmpHomogeneous_maskHomogeneous_7 | _pmpHomogeneous_T_287; // @[package.scala:39:76] wire _pmpHomogeneous_T_289 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_290 = ~_pmpHomogeneous_T_289; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_36 = _pmpHomogeneous_pgMask_T_35 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_38 = _pmpHomogeneous_pgMask_T_37 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_39 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_39 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_38; // @[package.scala:39:{76,86}] wire [55:0] _GEN_20 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_20; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_20; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_291 = pmpHomogeneous_endsBeforeLower_7 | pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_292 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_293 = _pmpHomogeneous_T_291 | _pmpHomogeneous_T_292; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_294 = _pmpHomogeneous_T_290 | _pmpHomogeneous_T_293; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_295 = _pmpHomogeneous_T_260 ? _pmpHomogeneous_T_288 : _pmpHomogeneous_T_294; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire pmpHomogeneous = _pmpHomogeneous_T_259 & _pmpHomogeneous_T_295; // @[PMP.scala:118:8, :138:10] wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76] assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_2_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _T_186 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60] wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_186; // @[PTW.scala:566:60] wire _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_1_resp_bits_gpa_bits_T_3 = _T_186; // @[PTW.scala:566:60] wire _io_requestor_2_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_2_resp_bits_gpa_bits_T_3 = _T_186; // @[PTW.scala:566:60] wire _gpa_pgoff_T; // @[PTW.scala:615:36] assign _gpa_pgoff_T = _T_186; // @[PTW.scala:566:60, :615:36] wire _l2_refill_T_7; // @[PTW.scala:715:40] assign _l2_refill_T_7 = _T_186; // @[PTW.scala:566:60, :715:40] wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_2_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_2_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_2_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T | _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 | _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_1_resp_bits_gpa_bits_truncIdx = _io_requestor_1_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_1_resp_bits_gpa_bits_T_11 = io_requestor_1_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = _io_requestor_1_resp_bits_gpa_bits_T_11 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_14 = {_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_2_resp_bits_homogeneous_0 = _io_requestor_2_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_2_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_2_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_2_resp_bits_gpa_bits_T_2 = _io_requestor_2_resp_bits_gpa_bits_T | _io_requestor_2_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_2_resp_bits_gpa_bits_T_4 = _io_requestor_2_resp_bits_gpa_bits_T_2 | _io_requestor_2_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_7 = {_io_requestor_2_resp_bits_gpa_bits_T_5, _io_requestor_2_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_10 = {_io_requestor_2_resp_bits_gpa_bits_T_8, _io_requestor_2_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_2_resp_bits_gpa_bits_truncIdx = _io_requestor_2_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_2_resp_bits_gpa_bits_T_11 = io_requestor_2_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_12 = _io_requestor_2_resp_bits_gpa_bits_T_11 ? _io_requestor_2_resp_bits_gpa_bits_T_10 : _io_requestor_2_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_13 = _io_requestor_2_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_2_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_2_resp_bits_gpa_bits_T_14 = {_io_requestor_2_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_2_resp_bits_gpa_bits_0 = _io_requestor_2_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_2_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_2_resp_bits_gpa_is_pte_0 = _io_requestor_2_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] wire [2:0] next_state; // @[PTW.scala:579:31] wire do_switch; // @[PTW.scala:581:30] wire _GEN_21 = ~(|state) & _T_144; // @[Decoupled.scala:51:35] wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38] wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26] wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58] wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40] wire _resp_gf_T_1 = |_resp_gf_WIRE_0; // @[package.scala:43:40] wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67] wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}] wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32] wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32] wire [2:0] _GEN_22 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24] wire [2:0] _count_T_4; // @[PTW.scala:624:24] assign _count_T_4 = _GEN_22; // @[PTW.scala:624:24] wire [2:0] _count_T_6; // @[PTW.scala:696:22] assign _count_T_6 = _GEN_22; // @[PTW.scala:624:24, :696:22] wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38] assign _aux_count_T_3 = _GEN_22; // @[PTW.scala:624:24, :741:38] wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24] wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26] wire _T_155 = state == 3'h2; // @[PTW.scala:233:22, :583:18] wire [2:0] _next_state_T_2 = l2_hit ? 3'h1 : 3'h4; // @[PTW.scala:481:27, :636:24] wire _T_156 = state == 3'h4; // @[PTW.scala:233:22, :583:18] wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39] assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _T_167 | _T_155) & _T_156 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :377:24, :393:26, :583:18, :640:{30,39}] wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45] wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86] wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}] wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64] wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62] wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}] wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64] wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62] wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}] wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}] wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86] wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76] wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26] wire _r_pte_T = ~l2_error; // @[PTW.scala:476:81, :670:19] wire _r_pte_T_1 = l2_hit & _r_pte_T; // @[PTW.scala:481:27, :670:{16,19}] wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32] wire _r_pte_T_3 = _r_pte_T_1 & _r_pte_T_2; // @[PTW.scala:670:{16,29,32}] wire _r_pte_T_7 = _r_pte_T_6 & pte_cache_hit; // @[PTW.scala:367:24, :674:{15,25}] wire [43:0] r_pte_pte_1_ppn; // @[PTW.scala:771:26] assign r_pte_pte_1_ppn = {24'h0, pte_cache_data}; // @[Mux.scala:30:73] wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58] wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27] assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27] wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26] assign _r_pte_pte_ppn_T_3 = {42'h0, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:19] assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29] wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}] wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}] wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15] wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43] wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}] wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65] wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}] wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}] wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}] wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76] wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26] wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26] wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26] wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35] wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35] wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35] wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35] wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35] wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35] wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35] wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35] wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35] wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35] wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_7 ? 10'h0 : _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:{8,25}, :676:8] wire [43:0] _r_pte_T_31_ppn = _r_pte_T_7 ? r_pte_pte_1_ppn : _r_pte_T_30_ppn; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_7 ? 2'h0 : _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_d = _r_pte_T_7 ? r_pte_pte_1_d : _r_pte_T_30_d; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire _r_pte_T_31_a = _r_pte_T_7 ? r_pte_pte_1_a : _r_pte_T_30_a; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire _r_pte_T_31_g = _r_pte_T_7 ? r_pte_pte_1_g : _r_pte_T_30_g; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire _r_pte_T_31_u = _r_pte_T_7 ? r_pte_pte_1_u : _r_pte_T_30_u; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire _r_pte_T_31_x = _r_pte_T_7 ? r_pte_pte_1_x : _r_pte_T_30_x; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire _r_pte_T_31_w = _r_pte_T_7 ? r_pte_pte_1_w : _r_pte_T_30_w; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire _r_pte_T_31_r = _r_pte_T_7 ? r_pte_pte_1_r : _r_pte_T_30_r; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire _r_pte_T_31_v = _r_pte_T_7 | _r_pte_T_30_v; // @[PTW.scala:674:{8,25}, :676:8] wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8] wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8] wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8] wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_3 ? 10'h0 : _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:{8,29}, :672:8] wire [43:0] _r_pte_T_33_ppn = _r_pte_T_3 ? l2_pte_ppn : _r_pte_T_32_ppn; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_3 ? 2'h0 : _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:{8,29}, :672:8] wire _r_pte_T_33_d = _r_pte_T_3 ? l2_pte_d : _r_pte_T_32_d; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_a = _r_pte_T_3 ? l2_pte_a : _r_pte_T_32_a; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_g = _r_pte_T_3 ? l2_pte_g : _r_pte_T_32_g; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_u = _r_pte_T_3 ? l2_pte_u : _r_pte_T_32_u; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_x = _r_pte_T_3 ? l2_pte_x : _r_pte_T_32_x; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_w = _r_pte_T_3 ? l2_pte_w : _r_pte_T_32_w; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_r = _r_pte_T_3 ? l2_pte_r : _r_pte_T_32_r; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_v = _r_pte_T_3 | _r_pte_T_32_v; // @[PTW.scala:670:{8,29}, :672:8] wire _T_166 = l2_hit & ~l2_error & ~resp_gf; // @[PTW.scala:263:20, :476:81, :481:27, :670:{19,32}, :685:{16,29}] wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22] wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :698:27] wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}] wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44] wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}] wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97] wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}] wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}] wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}] wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22] wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49] wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}] wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30] wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}] wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37] wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}] wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44] wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}] wire _T_183 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :357:107, :701:41, :703:{28,45}] assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_183 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21] wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}] wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61] wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}] wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12] wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65, :714:30] wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}] wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}] wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41] wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}] wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59] wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44] wire _GEN_23 = traverse | _T_183; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19] wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36] wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}] wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26] wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}] wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}] wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}] wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}] wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}] wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}] wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}] wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29] wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26] wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}] wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30] wire _resp_gf_T_4 = gf | _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}] wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20] wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32] wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39] wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}] wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}] wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}] wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20] wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32] wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39] wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}] wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}] wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}] wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20] wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32] wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39] wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}] wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}] wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_88( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_598 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_598; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_598; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_666 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_666; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_666; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_666; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_528 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_528; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_528; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_598 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_577 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_577 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_666 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_642 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_642 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_666 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_241( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File Counters.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ // Produces 0-width value when counting to 1 class ZCounter(val n: Int) { val value = RegInit(0.U(log2Ceil(n).W)) def inc(): Bool = { if (n == 1) true.B else { val wrap = value === (n-1).U value := Mux(!isPow2(n).B && wrap, 0.U, value + 1.U) wrap } } } object ZCounter { def apply(n: Int) = new ZCounter(n) def apply(cond: Bool, n: Int): (UInt, Bool) = { val c = new ZCounter(n) var wrap: Bool = null when (cond) { wrap = c.inc() } (c.value, cond && wrap) } } object TwoWayCounter { def apply(up: Bool, down: Bool, max: Int): UInt = { val cnt = RegInit(0.U(log2Up(max + 1).W)) when (up && !down) { cnt := cnt + 1.U } when (down && !up) { cnt := cnt - 1.U } cnt } } // a counter that clock gates most of its MSBs using the LSB carry-out case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true, inhibit: Bool = false.B) { private val isWide = width > (2 * inc.getWidth) private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width private val small = if (reset) RegInit(0.U(smallWidth.W)) else Reg(UInt(smallWidth.W)) private val nextSmall = small +& inc when (!inhibit) { small := nextSmall } private val large = if (isWide) { val r = if (reset) RegInit(0.U((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) when (nextSmall(smallWidth) && !inhibit) { r := r + 1.U } r } else null val value = if (isWide) Cat(large, small) else small lazy val carryOut = { val lo = (small ^ nextSmall) >> 1 if (!isWide) lo else { val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 Cat(hi, lo) } } def := (x: UInt) = { small := x if (isWide) large := x >> smallWidth } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr | (mask >> 1), ~(~addr | mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0) msbsLess || (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound || straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r || ignore) cur.cfg.w := aligned && (pmp.cfg.w || ignore) cur.cfg.x := aligned && (pmp.cfg.x || ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill when (!vill || ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill || useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt | supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts | (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) | io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined || usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U | (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu) val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) && (!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) && (!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) || usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal || !csr_exists || ((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) || is_counter && !allow_counter || decodeFast(debug_csrs.keys.toList) && !reg_debug || decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal || io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr | (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv || is_wfi && !allow_wfi || is_ret && !allow_sret || is_ret && addr(10) && addr(7) && !reg_debug || (is_sfence || is_hfence_gvma) && !allow_sfence_vma || is_hfence_vvma && !allow_hfence_vvma || is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U || is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) || CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) || addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma || is_hfence_gvma || is_hlsv || is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) || is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) || is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt || trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call || insn_break || insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call || insn_break || io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) || exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep || io.retire <= 1.U) assert(!reg_singleStepped || io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe | (if (usingCompressed && !coreParams.misaWritable) 0 else 1) | (if (usingUser) 0x100 else 0) | (if (usingSupervisor) 0x200 else 0) | (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi || io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags | io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */ val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U } when (mode_ok || !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain) bp.control.dmode := dMode when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) | (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) | (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U || t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }
module CSRFile_3( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_interrupts_seip, // @[CSR.scala:384:14] input [1:0] io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [63:0] io_rw_rdata, // @[CSR.scala:384:14] input [63:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_fp_illegal, // @[CSR.scala:384:14] output io_decode_0_fp_csr, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] input [31:0] io_decode_1_inst, // @[CSR.scala:384:14] output io_decode_1_fp_illegal, // @[CSR.scala:384:14] output io_decode_1_fp_csr, // @[CSR.scala:384:14] output io_decode_1_read_illegal, // @[CSR.scala:384:14] output io_decode_1_write_illegal, // @[CSR.scala:384:14] output io_decode_1_write_flush, // @[CSR.scala:384:14] output io_decode_1_system_illegal, // @[CSR.scala:384:14] output io_decode_1_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_1_virtual_system_illegal, // @[CSR.scala:384:14] input [31:0] io_decode_2_inst, // @[CSR.scala:384:14] output io_decode_2_fp_illegal, // @[CSR.scala:384:14] output io_decode_2_fp_csr, // @[CSR.scala:384:14] output io_decode_2_read_illegal, // @[CSR.scala:384:14] output io_decode_2_write_illegal, // @[CSR.scala:384:14] output io_decode_2_write_flush, // @[CSR.scala:384:14] output io_decode_2_system_illegal, // @[CSR.scala:384:14] output io_decode_2_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_2_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_cease, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [1:0] io_status_dprv, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output [1:0] io_status_prv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_sd, // @[CSR.scala:384:14] output io_status_mpv, // @[CSR.scala:384:14] output io_status_gva, // @[CSR.scala:384:14] output io_status_tsr, // @[CSR.scala:384:14] output io_status_tw, // @[CSR.scala:384:14] output io_status_tvm, // @[CSR.scala:384:14] output io_status_mxr, // @[CSR.scala:384:14] output io_status_sum, // @[CSR.scala:384:14] output io_status_mprv, // @[CSR.scala:384:14] output [1:0] io_status_fs, // @[CSR.scala:384:14] output [1:0] io_status_mpp, // @[CSR.scala:384:14] output io_status_spp, // @[CSR.scala:384:14] output io_status_mpie, // @[CSR.scala:384:14] output io_status_spie, // @[CSR.scala:384:14] output io_status_mie, // @[CSR.scala:384:14] output io_status_sie, // @[CSR.scala:384:14] output [3:0] io_ptbr_mode, // @[CSR.scala:384:14] output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14] output [39:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input [1:0] io_retire, // @[CSR.scala:384:14] input [63:0] io_cause, // @[CSR.scala:384:14] input [39:0] io_pc, // @[CSR.scala:384:14] input [39:0] io_tval, // @[CSR.scala:384:14] output [63:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] input io_fcsr_flags_valid, // @[CSR.scala:384:14] input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14] input io_set_fs_dirty, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [63:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output io_customCSRs_0_ren, // @[CSR.scala:384:14] output io_customCSRs_0_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14] output io_customCSRs_1_ren, // @[CSR.scala:384:14] output io_customCSRs_1_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_value // @[CSR.scala:384:14] ); wire io_status_sie_0; // @[CSR.scala:377:7] wire io_status_spie_0; // @[CSR.scala:377:7] wire io_status_spp_0; // @[CSR.scala:377:7] wire [1:0] io_status_fs_0; // @[CSR.scala:377:7] wire io_status_sum_0; // @[CSR.scala:377:7] wire io_status_mxr_0; // @[CSR.scala:377:7] wire io_status_sd_0; // @[CSR.scala:377:7] wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7] wire [1:0] io_hartid_0 = io_hartid; // @[CSR.scala:377:7] wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7] wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7] wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7] wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7] wire [31:0] io_decode_1_inst_0 = io_decode_1_inst; // @[CSR.scala:377:7] wire [31:0] io_decode_2_inst_0 = io_decode_2_inst; // @[CSR.scala:377:7] wire io_exception_0 = io_exception; // @[CSR.scala:377:7] wire [1:0] io_retire_0 = io_retire; // @[CSR.scala:377:7] wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7] wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7] wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7] wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7] wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7] wire io_set_fs_dirty_0 = io_set_fs_dirty; // @[CSR.scala:377:7] wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_1_vector_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_1_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_2_vector_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_2_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire io_gstatus_sd = 1'h1; // @[CSR.scala:377:7] wire sup_meip = 1'h1; // @[CSR.scala:406:19] wire sup_seip = 1'h1; // @[CSR.scala:406:19] wire sup_mtip = 1'h1; // @[CSR.scala:406:19] wire sup_stip = 1'h1; // @[CSR.scala:406:19] wire sup_msip = 1'h1; // @[CSR.scala:406:19] wire sup_ssip = 1'h1; // @[CSR.scala:406:19] wire del_seip = 1'h1; // @[CSR.scala:426:26] wire del_stip = 1'h1; // @[CSR.scala:426:26] wire del_ssip = 1'h1; // @[CSR.scala:426:26] wire _read_mapping_T_3 = 1'h1; // @[CSR.scala:1665:45] wire _debug_csrs_T_1 = 1'h1; // @[CSR.scala:1665:45] wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31] wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30] wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109] wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50] wire allow_hlsv = 1'h1; // @[CSR.scala:909:43] wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45] wire _io_decode_0_fp_illegal_T_4 = 1'h1; // @[CSR.scala:915:103] wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43] wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87] wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51] wire _io_decode_0_vector_illegal_T_5 = 1'h1; // @[CSR.scala:916:98] wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95] wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_0_rocc_illegal_T_5 = 1'h1; // @[CSR.scala:919:96] wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _allow_wfi_T_11 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_12 = 1'h1; // @[CSR.scala:906:109] wire allow_hfence_vvma_1 = 1'h1; // @[CSR.scala:908:50] wire allow_hlsv_1 = 1'h1; // @[CSR.scala:909:43] wire _allow_counter_T_28 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_30 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_33 = 1'h1; // @[CSR.scala:914:45] wire _io_decode_1_fp_illegal_T_4 = 1'h1; // @[CSR.scala:915:103] wire _io_decode_1_vector_illegal_T = 1'h1; // @[CSR.scala:916:43] wire _io_decode_1_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87] wire _io_decode_1_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51] wire _io_decode_1_vector_illegal_T_5 = 1'h1; // @[CSR.scala:916:98] wire _io_decode_1_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95] wire _io_decode_1_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_1_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_1_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_1_rocc_illegal_T_5 = 1'h1; // @[CSR.scala:919:96] wire _io_decode_1_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _allow_wfi_T_18 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_19 = 1'h1; // @[CSR.scala:906:109] wire allow_hfence_vvma_2 = 1'h1; // @[CSR.scala:908:50] wire allow_hlsv_2 = 1'h1; // @[CSR.scala:909:43] wire _allow_counter_T_45 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_47 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_50 = 1'h1; // @[CSR.scala:914:45] wire _io_decode_2_fp_illegal_T_4 = 1'h1; // @[CSR.scala:915:103] wire _io_decode_2_vector_illegal_T = 1'h1; // @[CSR.scala:916:43] wire _io_decode_2_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87] wire _io_decode_2_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51] wire _io_decode_2_vector_illegal_T_5 = 1'h1; // @[CSR.scala:916:98] wire _io_decode_2_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95] wire _io_decode_2_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_2_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_2_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_2_rocc_illegal_T_5 = 1'h1; // @[CSR.scala:919:96] wire _io_decode_2_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _io_gstatus_sd_T = 1'h1; // @[CSR.scala:1016:34] wire _io_gstatus_sd_T_2 = 1'h1; // @[CSR.scala:1016:39] wire _io_gstatus_sd_T_4 = 1'h1; // @[CSR.scala:1016:61] wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71] wire delegable_1 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71] wire delegable_5 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71] wire delegable_9 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71] wire delegable_17 = 1'h1; // @[CSR.scala:1109:67] wire delegable_18 = 1'h1; // @[CSR.scala:1109:67] wire delegable_19 = 1'h1; // @[CSR.scala:1109:67] wire delegable_21 = 1'h1; // @[CSR.scala:1109:67] wire delegable_23 = 1'h1; // @[CSR.scala:1109:67] wire delegable_26 = 1'h1; // @[CSR.scala:1109:67] wire delegable_27 = 1'h1; // @[CSR.scala:1109:67] wire delegable_28 = 1'h1; // @[CSR.scala:1109:67] wire _io_evec_T_1 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_6 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_11 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_16 = 1'h1; // @[CSR.scala:1665:45] wire _io_evec_T_21 = 1'h1; // @[CSR.scala:1665:45] wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59] wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30] wire [31:0] io_status_isa = 32'h14112D; // @[CSR.scala:377:7] wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] io_gstatus_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47] wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34] wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48] wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35] wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7] wire io_decode_1_vector_csr = 1'h0; // @[CSR.scala:377:7] wire io_decode_2_vector_csr = 1'h0; // @[CSR.scala:377:7] wire io_rw_stall = 1'h0; // @[CSR.scala:377:7] wire io_status_mbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_status_ube = 1'h0; // @[CSR.scala:377:7] wire io_status_upie = 1'h0; // @[CSR.scala:377:7] wire io_status_hie = 1'h0; // @[CSR.scala:377:7] wire io_status_uie = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_debug = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_cease = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_wfi = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_dv = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_v = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpv = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_gva = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tsr = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tw = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tvm = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mxr = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sum = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mprv = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_ube = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_upie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_hie = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_uie = 1'h0; // @[CSR.scala:377:7] wire io_mhtinst_read_pseudo = 1'h0; // @[CSR.scala:377:7] wire io_gva = 1'h0; // @[CSR.scala:377:7] wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7] wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47] wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34] wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44] wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31] wire sup_zero1 = 1'h0; // @[CSR.scala:406:19] wire sup_debug = 1'h0; // @[CSR.scala:406:19] wire sup_rocc = 1'h0; // @[CSR.scala:406:19] wire sup_sgeip = 1'h0; // @[CSR.scala:406:19] wire sup_vseip = 1'h0; // @[CSR.scala:406:19] wire sup_ueip = 1'h0; // @[CSR.scala:406:19] wire sup_vstip = 1'h0; // @[CSR.scala:406:19] wire sup_utip = 1'h0; // @[CSR.scala:406:19] wire sup_vssip = 1'h0; // @[CSR.scala:406:19] wire sup_usip = 1'h0; // @[CSR.scala:406:19] wire del_zero1 = 1'h0; // @[CSR.scala:426:26] wire del_debug = 1'h0; // @[CSR.scala:426:26] wire del_rocc = 1'h0; // @[CSR.scala:426:26] wire del_sgeip = 1'h0; // @[CSR.scala:426:26] wire del_meip = 1'h0; // @[CSR.scala:426:26] wire del_vseip = 1'h0; // @[CSR.scala:426:26] wire del_ueip = 1'h0; // @[CSR.scala:426:26] wire del_mtip = 1'h0; // @[CSR.scala:426:26] wire del_vstip = 1'h0; // @[CSR.scala:426:26] wire del_utip = 1'h0; // @[CSR.scala:426:26] wire del_msip = 1'h0; // @[CSR.scala:426:26] wire del_vssip = 1'h0; // @[CSR.scala:426:26] wire del_usip = 1'h0; // @[CSR.scala:426:26] wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10] wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50] wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42] wire always_zero1 = 1'h0; // @[CSR.scala:471:29] wire always_debug = 1'h0; // @[CSR.scala:471:29] wire always_rocc = 1'h0; // @[CSR.scala:471:29] wire always_sgeip = 1'h0; // @[CSR.scala:471:29] wire always_meip = 1'h0; // @[CSR.scala:471:29] wire always_vseip = 1'h0; // @[CSR.scala:471:29] wire always_seip = 1'h0; // @[CSR.scala:471:29] wire always_ueip = 1'h0; // @[CSR.scala:471:29] wire always_mtip = 1'h0; // @[CSR.scala:471:29] wire always_vstip = 1'h0; // @[CSR.scala:471:29] wire always_stip = 1'h0; // @[CSR.scala:471:29] wire always_utip = 1'h0; // @[CSR.scala:471:29] wire always_msip = 1'h0; // @[CSR.scala:471:29] wire always_vssip = 1'h0; // @[CSR.scala:471:29] wire always_ssip = 1'h0; // @[CSR.scala:471:29] wire always_usip = 1'h0; // @[CSR.scala:471:29] wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28] wire deleg_debug = 1'h0; // @[CSR.scala:476:28] wire deleg_rocc = 1'h0; // @[CSR.scala:476:28] wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28] wire deleg_meip = 1'h0; // @[CSR.scala:476:28] wire deleg_vseip = 1'h0; // @[CSR.scala:476:28] wire deleg_seip = 1'h0; // @[CSR.scala:476:28] wire deleg_ueip = 1'h0; // @[CSR.scala:476:28] wire deleg_mtip = 1'h0; // @[CSR.scala:476:28] wire deleg_vstip = 1'h0; // @[CSR.scala:476:28] wire deleg_stip = 1'h0; // @[CSR.scala:476:28] wire deleg_utip = 1'h0; // @[CSR.scala:476:28] wire deleg_msip = 1'h0; // @[CSR.scala:476:28] wire deleg_vssip = 1'h0; // @[CSR.scala:476:28] wire deleg_ssip = 1'h0; // @[CSR.scala:476:28] wire deleg_usip = 1'h0; // @[CSR.scala:476:28] wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12] wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27] wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48] wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48] wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35] wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35] wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41] wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41] wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41] wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41] wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27] wire mip_zero1 = 1'h0; // @[CSR.scala:600:24] wire mip_debug = 1'h0; // @[CSR.scala:600:24] wire mip_rocc = 1'h0; // @[CSR.scala:600:24] wire mip_sgeip = 1'h0; // @[CSR.scala:600:24] wire mip_vseip = 1'h0; // @[CSR.scala:600:24] wire mip_ueip = 1'h0; // @[CSR.scala:600:24] wire mip_vstip = 1'h0; // @[CSR.scala:600:24] wire mip_utip = 1'h0; // @[CSR.scala:600:24] wire mip_vssip = 1'h0; // @[CSR.scala:600:24] wire mip_usip = 1'h0; // @[CSR.scala:600:24] wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76] wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91] wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131] wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62] wire _read_mapping_T = 1'h0; // @[package.scala:132:38] wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47] wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47] wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44] wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44] wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31] wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43] wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59] wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48] wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35] wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59] wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16] wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8] wire _io_decode_0_fp_illegal_T_1 = 1'h0; // @[CSR.scala:915:83] wire _io_decode_0_fp_illegal_T_2 = 1'h0; // @[CSR.scala:915:64] wire _io_decode_0_fp_illegal_T_5 = 1'h0; // @[CSR.scala:915:94] wire _io_decode_0_vector_illegal_T_4 = 1'h0; // @[CSR.scala:916:107] wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_rocc_illegal_T_4 = 1'h0; // @[CSR.scala:919:105] wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74] wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43] wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire _allow_counter_T_21 = 1'h0; // @[CSR.scala:913:8] wire _io_decode_1_fp_illegal_T_1 = 1'h0; // @[CSR.scala:915:83] wire _io_decode_1_fp_illegal_T_2 = 1'h0; // @[CSR.scala:915:64] wire _io_decode_1_fp_illegal_T_5 = 1'h0; // @[CSR.scala:915:94] wire _io_decode_1_vector_illegal_T_4 = 1'h0; // @[CSR.scala:916:107] wire io_decode_1_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_1_vector_csr_T = 1'h0; // @[Decode.scala:55:116] wire _io_decode_1_rocc_illegal_T_4 = 1'h0; // @[CSR.scala:919:105] wire _csr_addr_legal_T_12 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_14 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_17 = 1'h0; // @[CSR.scala:921:74] wire io_decode_1_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23] wire _io_decode_1_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116] wire _io_decode_1_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43] wire _io_decode_1_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_1_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_1_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_1_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_1_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_1_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire _allow_counter_T_38 = 1'h0; // @[CSR.scala:913:8] wire _io_decode_2_fp_illegal_T_1 = 1'h0; // @[CSR.scala:915:83] wire _io_decode_2_fp_illegal_T_2 = 1'h0; // @[CSR.scala:915:64] wire _io_decode_2_fp_illegal_T_5 = 1'h0; // @[CSR.scala:915:94] wire _io_decode_2_vector_illegal_T_4 = 1'h0; // @[CSR.scala:916:107] wire io_decode_2_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_2_vector_csr_T = 1'h0; // @[Decode.scala:55:116] wire _io_decode_2_rocc_illegal_T_4 = 1'h0; // @[CSR.scala:919:105] wire _csr_addr_legal_T_21 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_23 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_26 = 1'h0; // @[CSR.scala:921:74] wire io_decode_2_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23] wire _io_decode_2_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116] wire _io_decode_2_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43] wire _io_decode_2_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_2_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_2_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_2_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_2_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_2_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33] wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37] wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34] wire trapToNmi = 1'h0; // @[CSR.scala:992:32] wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21] wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58] wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53] wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74] wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39] wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56] wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40] wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24] wire en = 1'h0; // @[CSR.scala:1096:79] wire delegable = 1'h0; // @[CSR.scala:1097:65] wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24] wire en_2 = 1'h0; // @[CSR.scala:1096:79] wire delegable_2 = 1'h0; // @[CSR.scala:1097:65] wire delegable_3 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24] wire en_4 = 1'h0; // @[CSR.scala:1096:79] wire delegable_4 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24] wire en_6 = 1'h0; // @[CSR.scala:1096:79] wire delegable_6 = 1'h0; // @[CSR.scala:1097:65] wire delegable_7 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24] wire en_8 = 1'h0; // @[CSR.scala:1096:79] wire delegable_8 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24] wire en_10 = 1'h0; // @[CSR.scala:1096:79] wire delegable_10 = 1'h0; // @[CSR.scala:1097:65] wire delegable_11 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24] wire en_12 = 1'h0; // @[CSR.scala:1096:79] wire delegable_12 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24] wire en_13 = 1'h0; // @[CSR.scala:1096:79] wire delegable_13 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24] wire en_14 = 1'h0; // @[CSR.scala:1096:79] wire delegable_14 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24] wire en_15 = 1'h0; // @[CSR.scala:1096:79] wire delegable_15 = 1'h0; // @[CSR.scala:1097:65] wire delegable_16 = 1'h0; // @[CSR.scala:1109:67] wire delegable_20 = 1'h0; // @[CSR.scala:1109:67] wire delegable_22 = 1'h0; // @[CSR.scala:1109:67] wire delegable_24 = 1'h0; // @[CSR.scala:1109:67] wire delegable_25 = 1'h0; // @[CSR.scala:1109:67] wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44] wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42] wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56] wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42] wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82] wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62] wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35] wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29] wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42] wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61] wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_23 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_24 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_25 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_26 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_27 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_147 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_148 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73] wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33] wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59] wire _reg_bp_0_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_0_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] io_gstatus_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47] wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34] wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59] wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48] wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35] wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_dprv = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_prv = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_sxl = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_mpp = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47] wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34] wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44] wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31] wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31] wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48] wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41] wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41] wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41] wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41] wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] read_mapping_lo_lo_hi = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_lo_hi_lo = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_lo_hi_hi = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_hi_lo_hi = 2'h0; // @[CSR.scala:655:48] wire [1:0] read_mapping_lo_1 = 2'h0; // @[CSR.scala:657:47] wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27] wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44] wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22] wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49] wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48] wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_xs = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_vs = 2'h0; // @[CSR.scala:755:35] wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49] wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59] wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59] wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36] wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_2 = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_3 = 2'h0; // @[pla.scala:102:36] wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62] wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] _reg_bp_0_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_0_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12] wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27] wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34] wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27] wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_16 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_20 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_22 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_24 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45] wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7] wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41] wire [5:0] read_mapping_hi_lo = 6'h0; // @[CSR.scala:655:48] wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51] wire [5:0] _reg_bp_0_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10] wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] read_mapping_lo_hi = 4'h0; // @[CSR.scala:655:48] wire [3:0] read_mapping_hi_lo_lo = 4'h0; // @[CSR.scala:655:48] wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] lo_hi_lo_lo = 4'h0; // @[CSR.scala:768:51] wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51] wire [3:0] _reg_bp_0_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14] wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14] wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26] wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15] wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153] wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26] wire [63:0] read_mapping_1_2 = 64'h0; // @[CSR.scala:655:48] wire [63:0] read_mapping_2_2 = 64'h0; // @[package.scala:132:15] wire [63:0] _io_rw_rdata_T_1 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_2 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_128 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_150 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_151 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_152 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _reg_custom_1_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7] wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41] wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59] wire [29:0] _io_rw_rdata_T_137 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_138 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_139 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_140 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_141 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_142 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_143 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73] wire [50:0] read_mapping_hi_hi = 51'h0; // @[CSR.scala:655:48] wire [50:0] read_mapping_3_2 = 51'h0; // @[CSR.scala:657:47] wire [50:0] _io_rw_rdata_T_3 = 51'h0; // @[Mux.scala:30:73] wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31] wire [1:0] _read_mapping_T_4 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _debug_csrs_T_2 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59] wire [1:0] _io_evec_T_2 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_7 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_12 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_17 = 2'h1; // @[CSR.scala:1665:36] wire [1:0] _io_evec_T_22 = 2'h1; // @[CSR.scala:1665:36] wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7] wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41] wire [4:0] read_mapping_hi_hi_hi = 5'h0; // @[CSR.scala:655:48] wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36] wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44] wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31] wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48] wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35] wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41] wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41] wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41] wire [2:0] read_mapping_lo_lo = 3'h0; // @[CSR.scala:655:48] wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44] wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31] wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49] wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51] wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49] wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36] wire [56:0] read_mapping_hi = 57'h0; // @[CSR.scala:655:48] wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49] wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49] wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49] wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49] wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7] wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41] wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51] wire [1:0] io_gstatus_fs = 2'h3; // @[CSR.scala:377:7] wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31] wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35] wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31] wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70] wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27] wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47] wire [24:0] _read_mapping_T_1 = 25'h0; // @[package.scala:132:20] wire [45:0] read_mapping_hi_hi_lo = 46'h0; // @[CSR.scala:655:48] wire [6:0] read_mapping_lo = 7'h0; // @[CSR.scala:655:48] wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32] wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [47:0] _reg_bp_0_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46] wire [38:0] _reg_bp_0_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [39:0] io_htval = 40'h0; // @[CSR.scala:377:7] wire [39:0] _reg_bp_0_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35] wire [31:0] io_gstatus_isa = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_inst_0 = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_inst_1 = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_inst_2 = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_trace_0_insn = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_trace_1_insn = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_trace_2_insn = 32'h0; // @[CSR.scala:377:7] wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47] wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34] wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14] wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46] wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48] wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35] wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59] wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27] wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27] wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168] wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFFF7; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFFF7; // @[CSR.scala:1531:41] wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78] wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59] wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46] wire [15:0] _delegable_T_26 = 16'h1000; // @[CSR.scala:1109:45] wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_18 = 16'h8; // @[CSR.scala:1109:45] wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120] wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120] wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120] wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120] wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120] wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49] wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120] wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43] wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120] wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120] wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120] wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49] wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120] wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43] wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120] wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120] wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120] wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120] wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43] wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120] wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39] wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120] wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39] wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120] wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [9:0] _io_decode_1_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [9:0] _io_decode_2_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51] wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51] wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51] wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51] wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70] wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32] wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51] wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20] wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59] wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41] wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41] wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41] wire [15:0] delegable_interrupts = 16'h222; // @[CSR.scala:431:50] wire [7:0] hi_1 = 8'h2; // @[CSR.scala:431:50] wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50] wire [15:0] supported_interrupts = 16'hAAA; // @[CSR.scala:431:17] wire [7:0] hi = 8'hA; // @[CSR.scala:431:10] wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10] wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10] wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10] wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10] wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44] wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31] wire [15:0] _delegable_T_27 = 16'h2000; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_23 = 16'h100; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_21 = 16'h40; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_19 = 16'h10; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_17 = 16'h4; // @[CSR.scala:1109:45] wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120] wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120] wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120] wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120] wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120] wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120] wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120] wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120] wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120] wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120] wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120] wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120] wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120] wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120] wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120] wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50] wire [15:0] _delegable_T_28 = 16'h8000; // @[CSR.scala:1109:45] wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28] wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24] wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24] wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24] wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22] wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91] wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire [31:0] decoded_plaInput_2 = io_decode_1_inst_0; // @[pla.scala:77:22] wire _io_decode_1_fp_illegal_T_6; // @[CSR.scala:915:91] wire _io_decode_1_fp_csr_T; // @[Decode.scala:55:116] wire _io_decode_1_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_1_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_1_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_1_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_1_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_1_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire [31:0] decoded_plaInput_3 = io_decode_2_inst_0; // @[pla.scala:77:22] wire _io_decode_2_fp_illegal_T_6; // @[CSR.scala:915:91] wire _io_decode_2_fp_csr_T; // @[Decode.scala:55:116] wire _io_decode_2_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_2_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_2_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_2_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_2_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_2_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire _io_csr_stall_T; // @[CSR.scala:1161:27] wire _io_eret_T_1; // @[CSR.scala:1000:38] wire _io_singleStep_T_1; // @[CSR.scala:1001:34] wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24] wire _io_status_dv_T_3; // @[CSR.scala:1009:33] wire _io_status_sd_T_4; // @[CSR.scala:1003:58] wire read_sstatus_sd = io_status_sd_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35] wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35] wire [39:0] io_trace_0_iaddr = io_pc_0; // @[CSR.scala:377:7] wire [39:0] io_trace_1_iaddr = io_pc_0; // @[CSR.scala:377:7] wire [39:0] io_trace_2_iaddr = io_pc_0; // @[CSR.scala:377:7] wire [39:0] io_trace_0_tval = io_tval_0; // @[CSR.scala:377:7] wire [39:0] io_trace_1_tval = io_tval_0; // @[CSR.scala:377:7] wire [39:0] io_trace_2_tval = io_tval_0; // @[CSR.scala:377:7] wire [63:0] value_1; // @[Counters.scala:55:30] wire _io_interrupt_T_5; // @[CSR.scala:626:73] wire [63:0] interruptCause; // @[CSR.scala:625:63] wire pmp_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19] wire pmp_cfg_x; // @[PMP.scala:24:19] wire pmp_cfg_w; // @[PMP.scala:24:19] wire pmp_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_addr; // @[PMP.scala:24:19] wire [31:0] pmp_mask; // @[PMP.scala:24:19] wire pmp_1_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19] wire pmp_1_cfg_x; // @[PMP.scala:24:19] wire pmp_1_cfg_w; // @[PMP.scala:24:19] wire pmp_1_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_1_addr; // @[PMP.scala:24:19] wire [31:0] pmp_1_mask; // @[PMP.scala:24:19] wire pmp_2_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19] wire pmp_2_cfg_x; // @[PMP.scala:24:19] wire pmp_2_cfg_w; // @[PMP.scala:24:19] wire pmp_2_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_2_addr; // @[PMP.scala:24:19] wire [31:0] pmp_2_mask; // @[PMP.scala:24:19] wire pmp_3_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19] wire pmp_3_cfg_x; // @[PMP.scala:24:19] wire pmp_3_cfg_w; // @[PMP.scala:24:19] wire pmp_3_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_3_addr; // @[PMP.scala:24:19] wire [31:0] pmp_3_mask; // @[PMP.scala:24:19] wire pmp_4_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19] wire pmp_4_cfg_x; // @[PMP.scala:24:19] wire pmp_4_cfg_w; // @[PMP.scala:24:19] wire pmp_4_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_4_addr; // @[PMP.scala:24:19] wire [31:0] pmp_4_mask; // @[PMP.scala:24:19] wire pmp_5_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19] wire pmp_5_cfg_x; // @[PMP.scala:24:19] wire pmp_5_cfg_w; // @[PMP.scala:24:19] wire pmp_5_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_5_addr; // @[PMP.scala:24:19] wire [31:0] pmp_5_mask; // @[PMP.scala:24:19] wire pmp_6_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19] wire pmp_6_cfg_x; // @[PMP.scala:24:19] wire pmp_6_cfg_w; // @[PMP.scala:24:19] wire pmp_6_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_6_addr; // @[PMP.scala:24:19] wire [31:0] pmp_6_mask; // @[PMP.scala:24:19] wire pmp_7_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19] wire pmp_7_cfg_x; // @[PMP.scala:24:19] wire pmp_7_cfg_w; // @[PMP.scala:24:19] wire pmp_7_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_7_addr; // @[PMP.scala:24:19] wire [31:0] pmp_7_mask; // @[PMP.scala:24:19] wire [31:0] _io_csrw_counter_T_11; // @[CSR.scala:1223:25] wire _io_inhibit_cycle_T; // @[CSR.scala:591:40] wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18] wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25] wire [63:0] cause; // @[CSR.scala:959:8] wire _io_trace_1_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_1_priv_T; // @[CSR.scala:1624:18] wire _io_trace_1_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_1_interrupt_T; // @[CSR.scala:1626:25] wire _io_trace_2_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_2_priv_T; // @[CSR.scala:1624:18] wire _io_trace_2_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_2_interrupt_T; // @[CSR.scala:1626:25] wire _io_fiom_T_6; // @[CSR.scala:631:113] wire reg_custom_read; // @[CSR.scala:799:36] wire [63:0] wdata; // @[CSR.scala:1643:39] wire reg_custom_read_1; // @[CSR.scala:799:36] wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7] wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7] wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_flush_0; // @[CSR.scala:377:7] wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_1_fp_illegal_0; // @[CSR.scala:377:7] wire io_decode_1_fp_csr_0; // @[CSR.scala:377:7] wire io_decode_1_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_1_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_1_write_flush_0; // @[CSR.scala:377:7] wire io_decode_1_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_1_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_1_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_2_fp_illegal_0; // @[CSR.scala:377:7] wire io_decode_2_fp_csr_0; // @[CSR.scala:377:7] wire io_decode_2_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_2_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_2_write_flush_0; // @[CSR.scala:377:7] wire io_decode_2_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_2_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_2_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_status_debug_0; // @[CSR.scala:377:7] wire io_status_cease_0; // @[CSR.scala:377:7] wire io_status_wfi_0; // @[CSR.scala:377:7] wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7] wire io_status_dv_0; // @[CSR.scala:377:7] wire [1:0] io_status_prv_0; // @[CSR.scala:377:7] wire io_status_v_0; // @[CSR.scala:377:7] wire io_status_mpv_0; // @[CSR.scala:377:7] wire io_status_gva_0; // @[CSR.scala:377:7] wire io_status_tsr_0; // @[CSR.scala:377:7] wire io_status_tw_0; // @[CSR.scala:377:7] wire io_status_tvm_0; // @[CSR.scala:377:7] wire io_status_mprv_0; // @[CSR.scala:377:7] wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7] wire io_status_mpie_0; // @[CSR.scala:377:7] wire io_status_mie_0; // @[CSR.scala:377:7] wire io_hstatus_spvp; // @[CSR.scala:377:7] wire io_hstatus_spv; // @[CSR.scala:377:7] wire io_hstatus_gva; // @[CSR.scala:377:7] wire io_gstatus_spp; // @[CSR.scala:377:7] wire io_gstatus_spie; // @[CSR.scala:377:7] wire io_gstatus_sie; // @[CSR.scala:377:7] wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7] wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7] wire io_trace_0_valid; // @[CSR.scala:377:7] wire [2:0] io_trace_0_priv; // @[CSR.scala:377:7] wire io_trace_0_exception; // @[CSR.scala:377:7] wire io_trace_0_interrupt; // @[CSR.scala:377:7] wire [63:0] io_trace_0_cause; // @[CSR.scala:377:7] wire io_trace_1_valid; // @[CSR.scala:377:7] wire [2:0] io_trace_1_priv; // @[CSR.scala:377:7] wire io_trace_1_exception; // @[CSR.scala:377:7] wire io_trace_1_interrupt; // @[CSR.scala:377:7] wire [63:0] io_trace_1_cause; // @[CSR.scala:377:7] wire io_trace_2_valid; // @[CSR.scala:377:7] wire [2:0] io_trace_2_priv; // @[CSR.scala:377:7] wire io_trace_2_exception; // @[CSR.scala:377:7] wire io_trace_2_interrupt; // @[CSR.scala:377:7] wire [63:0] io_trace_2_cause; // @[CSR.scala:377:7] wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7] wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7] wire io_csr_stall_0; // @[CSR.scala:377:7] wire io_eret; // @[CSR.scala:377:7] wire io_singleStep_0; // @[CSR.scala:377:7] wire [39:0] io_evec_0; // @[CSR.scala:377:7] wire [63:0] io_time_0; // @[CSR.scala:377:7] wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7] wire io_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7] wire [31:0] io_csrw_counter; // @[CSR.scala:377:7] wire io_inhibit_cycle; // @[CSR.scala:377:7] wire io_fiom; // @[CSR.scala:377:7] reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28] assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_v; // @[CSR.scala:395:28] assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28] wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] wire _io_decode_1_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] wire _io_decode_2_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] reg reg_mstatus_mpv; // @[CSR.scala:395:28] assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tsr; // @[CSR.scala:395:28] assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tw; // @[CSR.scala:395:28] assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tvm; // @[CSR.scala:395:28] assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mxr; // @[CSR.scala:395:28] assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sum; // @[CSR.scala:395:28] assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mprv; // @[CSR.scala:395:28] assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28] assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spp; // @[CSR.scala:395:28] assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spie; // @[CSR.scala:395:28] assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sie; // @[CSR.scala:395:28] assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28] wire [1:0] new_prv; // @[CSR.scala:397:28] wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35] wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg reg_dcsr_ebreaks; // @[CSR.scala:403:25] reg reg_dcsr_ebreaku; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26] reg [39:0] reg_dpc; // @[CSR.scala:483:20] reg [63:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19] reg [63:0] reg_mie; // @[CSR.scala:495:20] reg [63:0] reg_mideleg; // @[CSR.scala:497:18] wire [63:0] read_mideleg = {54'h0, reg_mideleg[9:1] & 9'h111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}] reg [63:0] reg_medeleg; // @[CSR.scala:501:18] wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}] reg reg_mip_seip; // @[CSR.scala:504:20] reg reg_mip_stip; // @[CSR.scala:504:20] wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24] reg reg_mip_ssip; // @[CSR.scala:504:20] wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24] reg [39:0] reg_mepc; // @[CSR.scala:505:21] reg [63:0] reg_mcause; // @[CSR.scala:506:27] reg [39:0] reg_mtval; // @[CSR.scala:507:22] reg [39:0] reg_mtval2; // @[CSR.scala:508:23] reg [63:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] reg reg_menvcfg_fiom; // @[CSR.scala:525:28] reg reg_senvcfg_fiom; // @[CSR.scala:526:28] reg [31:0] reg_mcounteren; // @[CSR.scala:531:18] wire [31:0] read_mcounteren = {29'h0, reg_mcounteren[2:0]}; // @[CSR.scala:531:18, :532:{14,32}] reg [31:0] reg_scounteren; // @[CSR.scala:535:18] wire [31:0] read_scounteren = {29'h0, reg_scounteren[2:0]}; // @[CSR.scala:535:18, :536:{14,38}] reg reg_hstatus_spvp; // @[CSR.scala:552:28] assign io_hstatus_spvp = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_spv; // @[CSR.scala:552:28] assign io_hstatus_spv = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_gva; // @[CSR.scala:552:28] assign io_hstatus_gva = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28] reg [39:0] reg_htval; // @[CSR.scala:554:22] wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27] assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59] assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27] assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59] assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27] assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27] wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59] assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27] wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27] wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27] reg reg_vsstatus_spp; // @[CSR.scala:562:25] assign io_gstatus_spp = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_spie; // @[CSR.scala:562:25] assign io_gstatus_spie = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_sie; // @[CSR.scala:562:25] assign io_gstatus_sie = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25] reg [39:0] reg_vsepc; // @[CSR.scala:564:22] reg [63:0] reg_vscause; // @[CSR.scala:565:24] reg [39:0] reg_vstval; // @[CSR.scala:566:23] reg [39:0] reg_sepc; // @[CSR.scala:569:21] reg [63:0] reg_scause; // @[CSR.scala:570:23] reg [39:0] reg_stval; // @[CSR.scala:571:22] reg [63:0] reg_sscratch; // @[CSR.scala:572:25] reg [38:0] reg_stvec; // @[CSR.scala:573:22] reg [3:0] reg_satp_mode; // @[CSR.scala:574:21] assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21] reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21] assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21] reg reg_wfi; // @[CSR.scala:575:54] assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54] reg [4:0] reg_fflags; // @[CSR.scala:577:23] reg [2:0] reg_frm; // @[CSR.scala:578:20] assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20] reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35] reg reg_htinst_read_pseudo; // @[CSR.scala:585:35] wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103] wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103] wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103] wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103] reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34] assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40] wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98] assign io_inhibit_cycle = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40] wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75] reg [5:0] small_0; // @[Counters.scala:45:41] wire [6:0] nextSmall = {1'h0, small_0} + {5'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33] wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36] reg [57:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56] reg [5:0] small_1; // @[Counters.scala:45:41] wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33] wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36] reg [57:0] large_1; // @[Counters.scala:50:31] wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55] assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] assign io_time_0 = value_1; // @[Counters.scala:55:30] wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22] wire _mip_seip_T; // @[CSR.scala:606:57] wire mip_seip; // @[CSR.scala:600:24] assign _mip_seip_T = reg_mip_seip | io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57] assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57] wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22] wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22] wire [15:0] read_mip = _read_mip_T & 16'hAAA; // @[CSR.scala:610:{22,29}] wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56] wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}] wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42] wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61] wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60] wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62] wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42] wire _allow_wfi_T_7 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61] wire _allow_sfence_vma_T_4 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60] wire _allow_sret_T_4 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62] wire _allow_counter_T_17 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42] wire _allow_wfi_T_14 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61] wire _allow_sfence_vma_T_8 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60] wire _allow_sret_T_8 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62] wire _allow_counter_T_34 = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42] wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51] wire _m_interrupts_T_1 = _m_interrupts_T | reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}] wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}] wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85] wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 | read_mideleg; // @[CSR.scala:498:14, :620:{85,105}] wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}] wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}] wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68] wire _s_interrupts_T; // @[CSR.scala:621:68] assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68] wire _vs_interrupts_T; // @[CSR.scala:622:70] assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70] wire _io_fiom_T_2; // @[CSR.scala:631:82] assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82] wire _s_interrupts_T_1 = reg_mstatus_v | _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}] wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98] wire _s_interrupts_T_2; // @[CSR.scala:621:98] assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98] wire _vs_interrupts_T_1; // @[CSR.scala:622:99] assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99] wire _csr_addr_legal_T_4; // @[CSR.scala:921:62] assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62] wire _csr_addr_legal_T_13; // @[CSR.scala:921:62] assign _csr_addr_legal_T_13 = _GEN_3; // @[CSR.scala:621:98, :921:62] wire _csr_addr_legal_T_22; // @[CSR.scala:921:62] assign _csr_addr_legal_T_22 = _GEN_3; // @[CSR.scala:621:98, :921:62] wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}] wire _s_interrupts_T_4 = _s_interrupts_T_1 | _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}] wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}] wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151] wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}] wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}] wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}] wire _vs_interrupts_T_3 = _vs_interrupts_T | _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}] wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}] wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}] wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76] wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76] wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76] wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76] wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76] wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76] wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76] wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76] wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76] wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76] wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76] wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76] wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76] wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76] wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76] wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76] wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76] wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76] wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76] wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76] wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76] wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76] wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76] wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76] wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76] wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76] wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76] wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76] wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76] wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76] wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76] wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76] wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76] wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76] wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76] wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76] wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76] wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76] wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76] wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76] wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76] wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76] wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76] wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76] wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76] wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76] wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76] wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_63 = _any_T | _any_T_1; // @[CSR.scala:1637:{76,90}] wire _any_T_64 = _any_T_63 | _any_T_2; // @[CSR.scala:1637:{76,90}] wire _any_T_65 = _any_T_64 | _any_T_3; // @[CSR.scala:1637:{76,90}] wire _any_T_66 = _any_T_65 | _any_T_4; // @[CSR.scala:1637:{76,90}] wire _any_T_67 = _any_T_66 | _any_T_5; // @[CSR.scala:1637:{76,90}] wire _any_T_68 = _any_T_67 | _any_T_6; // @[CSR.scala:1637:{76,90}] wire _any_T_69 = _any_T_68 | _any_T_7; // @[CSR.scala:1637:{76,90}] wire _any_T_70 = _any_T_69 | _any_T_8; // @[CSR.scala:1637:{76,90}] wire _any_T_71 = _any_T_70 | _any_T_9; // @[CSR.scala:1637:{76,90}] wire _any_T_72 = _any_T_71 | _any_T_10; // @[CSR.scala:1637:{76,90}] wire _any_T_73 = _any_T_72 | _any_T_11; // @[CSR.scala:1637:{76,90}] wire _any_T_74 = _any_T_73 | _any_T_12; // @[CSR.scala:1637:{76,90}] wire _any_T_75 = _any_T_74 | _any_T_13; // @[CSR.scala:1637:{76,90}] wire _any_T_76 = _any_T_75 | _any_T_14; // @[CSR.scala:1637:{76,90}] wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90] wire _any_T_78 = _any_T_77 | _any_T_15; // @[CSR.scala:1637:{76,90}] wire _any_T_79 = _any_T_78 | _any_T_16; // @[CSR.scala:1637:{76,90}] wire _any_T_80 = _any_T_79 | _any_T_17; // @[CSR.scala:1637:{76,90}] wire _any_T_81 = _any_T_80 | _any_T_18; // @[CSR.scala:1637:{76,90}] wire _any_T_82 = _any_T_81 | _any_T_19; // @[CSR.scala:1637:{76,90}] wire _any_T_83 = _any_T_82 | _any_T_20; // @[CSR.scala:1637:{76,90}] wire _any_T_84 = _any_T_83 | _any_T_21; // @[CSR.scala:1637:{76,90}] wire _any_T_85 = _any_T_84 | _any_T_22; // @[CSR.scala:1637:{76,90}] wire _any_T_86 = _any_T_85 | _any_T_23; // @[CSR.scala:1637:{76,90}] wire _any_T_87 = _any_T_86 | _any_T_24; // @[CSR.scala:1637:{76,90}] wire _any_T_88 = _any_T_87 | _any_T_25; // @[CSR.scala:1637:{76,90}] wire _any_T_89 = _any_T_88 | _any_T_26; // @[CSR.scala:1637:{76,90}] wire _any_T_90 = _any_T_89 | _any_T_27; // @[CSR.scala:1637:{76,90}] wire _any_T_91 = _any_T_90 | _any_T_28; // @[CSR.scala:1637:{76,90}] wire _any_T_92 = _any_T_91 | _any_T_29; // @[CSR.scala:1637:{76,90}] wire _any_T_93 = _any_T_92 | _any_T_30; // @[CSR.scala:1637:{76,90}] wire _any_T_94 = _any_T_93 | _any_T_31; // @[CSR.scala:1637:{76,90}] wire _any_T_95 = _any_T_94 | _any_T_32; // @[CSR.scala:1637:{76,90}] wire _any_T_96 = _any_T_95 | _any_T_33; // @[CSR.scala:1637:{76,90}] wire _any_T_97 = _any_T_96 | _any_T_34; // @[CSR.scala:1637:{76,90}] wire _any_T_98 = _any_T_97 | _any_T_35; // @[CSR.scala:1637:{76,90}] wire _any_T_99 = _any_T_98 | _any_T_36; // @[CSR.scala:1637:{76,90}] wire _any_T_100 = _any_T_99 | _any_T_37; // @[CSR.scala:1637:{76,90}] wire _any_T_101 = _any_T_100 | _any_T_38; // @[CSR.scala:1637:{76,90}] wire _any_T_102 = _any_T_101 | _any_T_39; // @[CSR.scala:1637:{76,90}] wire _any_T_103 = _any_T_102 | _any_T_40; // @[CSR.scala:1637:{76,90}] wire _any_T_104 = _any_T_103 | _any_T_41; // @[CSR.scala:1637:{76,90}] wire _any_T_105 = _any_T_104 | _any_T_42; // @[CSR.scala:1637:{76,90}] wire _any_T_106 = _any_T_105 | _any_T_43; // @[CSR.scala:1637:{76,90}] wire _any_T_107 = _any_T_106 | _any_T_44; // @[CSR.scala:1637:{76,90}] wire _any_T_108 = _any_T_107 | _any_T_45; // @[CSR.scala:1637:{76,90}] wire _any_T_109 = _any_T_108 | _any_T_46; // @[CSR.scala:1637:{76,90}] wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90] wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90] wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90] wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90] wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90] wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90] wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90] wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90] wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90] wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90] wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90] wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90] wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90] wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90] wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90] wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90] wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70] wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70] wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70] wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70] wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70] wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70] wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70] wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70] wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70] wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70] wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70] wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70] wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70] wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70] wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70] wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70] wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70] wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70] wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70] wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70] wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70] wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70] wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70] wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70] wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70] wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70] wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70] wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70] wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70] wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70] wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70] wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70] wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70] wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70] wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70] wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70] wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70] wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70] wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70] wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70] wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70] wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70] wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70] wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70] wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70] wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70] wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70] wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70] assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63] assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63] wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36] wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90] wire _io_interrupt_T_2 = _io_interrupt_T_1 | reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}] wire _io_interrupt_T_3 = reg_debug | io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88] wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}] assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}] assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73] wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31] wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}] wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}] wire _io_fiom_T_4 = _io_fiom_T_1 | _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}] assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}] assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113] assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19] assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19] assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19] assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19] assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19] assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19] assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19] assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19] assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19] assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19] assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19] assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19] assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19] assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19] assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19] assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19] assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19] assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19] assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19] assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19] assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19] assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19] assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19] assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19] assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19] assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19] assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19] assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19] assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19] assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19] assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19] assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19] assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19] assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19] assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19] assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19] assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19] assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19] assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19] assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19] assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19] assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19] assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19] assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19] assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19] assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19] assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19] assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19] assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32] wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h0, io_status_fs_0}; // @[CSR.scala:377:7, :649:32] wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32] wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32] wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32] wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32] wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32] wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32] wire [23:0] read_mstatus_hi_hi_lo_lo = {io_status_sd_0, 23'h0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32] wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo}; // @[CSR.scala:649:32] wire [33:0] read_mstatus_hi_hi_hi_lo = {32'h14112D, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32] wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32] wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32] wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32] wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32] wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13] wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41] wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41] wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}] wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}] wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35] wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41] wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41] wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}] wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}] wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35] wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}] wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35] wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}] wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}] wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}] wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27] wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27] wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27] wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27] wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27] wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27] wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27] wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27] wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27] wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27] wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}] wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38] wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}] wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}] wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22] wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49] wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49] wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18] wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28] wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29] wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51] wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51] wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51] wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51] wire [3:0] lo_hi_lo_hi = {2'h0, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51] wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, 4'h0}; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51] wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51] wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51] wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51] wire [23:0] hi_hi_lo_lo = {read_sstatus_sd, 23'h0}; // @[CSR.scala:755:35, :768:51] wire [27:0] hi_hi_lo_4 = {4'h0, hi_hi_lo_lo}; // @[CSR.scala:768:51] wire [64:0] hi_hi_5 = {37'h0, hi_hi_lo_4}; // @[CSR.scala:768:51] wire [82:0] hi_7 = {hi_hi_5, 18'h800}; // @[CSR.scala:768:51] wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43] wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28] wire [39:0] _T_30 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | 2'h1}; // @[CSR.scala:1665:{26,28,31}] wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49] wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49] wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36] wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}] wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}] wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27] wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}] wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}] wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27] reg [63:0] reg_custom_0; // @[CSR.scala:798:43] assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43] wire _reg_custom_read_T = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50] assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_1; // @[CSR.scala:798:43] assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_2 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36] wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19] wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [149:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [149:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [149:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22] wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23] wire decoded_addr_97_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77] wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23] wire decoded_addr_55_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77] wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23] wire decoded_addr_10_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77] wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23] wire decoded_addr_118_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77] wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23] wire decoded_addr_94_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77] wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23] wire decoded_addr_100_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77] wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23] wire decoded_addr_72_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77] wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23] wire decoded_addr_108_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77] wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23] wire decoded_addr_76_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77] wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23] wire decoded_addr_129_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77] wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23] wire decoded_addr_132_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77] wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23] wire decoded_addr_136_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77] wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23] wire decoded_addr_29_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77] wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23] wire decoded_addr_131_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77] wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23] wire decoded_addr_49_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77] wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23] wire decoded_addr_89_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77] wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23] wire decoded_addr_57_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77] wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23] wire decoded_addr_36_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77] wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23] wire decoded_addr_68_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77] wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23] wire decoded_addr_99_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77] wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23] wire decoded_addr_130_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77] wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23] wire decoded_addr_103_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77] wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23] wire decoded_addr_121_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77] wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23] wire decoded_addr_146_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77] wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23] wire decoded_addr_17_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77] wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23] wire decoded_addr_27_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77] wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23] wire decoded_addr_83_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77] wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23] wire decoded_addr_52_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77] wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23] wire decoded_addr_144_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77] wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23] wire decoded_addr_70_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77] wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23] wire decoded_addr_111_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77] wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23] wire decoded_addr_82_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77] wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23] wire decoded_addr_31_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77] wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23] wire decoded_addr_0_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77] wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23] wire decoded_addr_59_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77] wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23] wire decoded_addr_138_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77] wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23] wire decoded_addr_126_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77] wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23] wire decoded_addr_74_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77] wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23] wire decoded_addr_116_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77] wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23] wire decoded_addr_90_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77] wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23] wire decoded_addr_113_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77] wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23] wire decoded_addr_1_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77] wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23] wire decoded_addr_16_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77] wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23] wire decoded_addr_78_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77] wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23] wire decoded_addr_39_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77] wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23] wire decoded_addr_51_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77] wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23] wire decoded_addr_109_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77] wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23] wire decoded_addr_91_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77] wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23] wire decoded_addr_81_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77] wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23] wire decoded_addr_67_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77] wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23] wire decoded_addr_105_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77] wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23] wire decoded_addr_122_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77] wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23] wire decoded_addr_24_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77] wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23] wire decoded_addr_124_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77] wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23] wire decoded_addr_26_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77] wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23] wire decoded_addr_128_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77] wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23] wire decoded_addr_7_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77] wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23] wire decoded_addr_62_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77] wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23] wire decoded_addr_77_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77] wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23] wire decoded_addr_46_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77] wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23] wire decoded_addr_112_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77] wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23] wire decoded_addr_60_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77] wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23] wire decoded_addr_92_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77] wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23] wire decoded_addr_148_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77] wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23] wire decoded_addr_14_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77] wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23] wire decoded_addr_21_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77] wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23] wire decoded_addr_33_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77] wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23] wire decoded_addr_19_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77] wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23] wire decoded_addr_133_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77] wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23] wire decoded_addr_149_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77] wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23] wire decoded_addr_50_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77] wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23] wire decoded_addr_75_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77] wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23] wire decoded_addr_102_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77] wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23] wire decoded_addr_84_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77] wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23] wire decoded_addr_45_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77] wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23] wire decoded_addr_64_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77] wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23] wire decoded_addr_120_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77] wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23] wire decoded_addr_30_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77] wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23] wire decoded_addr_5_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77] wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23] wire decoded_addr_32_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77] wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23] wire decoded_addr_143_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77] wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23] wire decoded_addr_117_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77] wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23] wire decoded_addr_63_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77] wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23] wire decoded_addr_107_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77] wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23] wire decoded_addr_88_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77] wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23] wire decoded_addr_114_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77] wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23] wire decoded_addr_73_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77] wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23] wire decoded_addr_53_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77] wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23] wire decoded_addr_147_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77] wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23] wire decoded_addr_41_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77] wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23] wire decoded_addr_56_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77] wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23] wire decoded_addr_37_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77] wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23] wire decoded_addr_79_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77] wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23] wire decoded_addr_96_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77] wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23] wire decoded_addr_4_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77] wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23] wire decoded_addr_101_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77] wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23] wire decoded_addr_119_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77] wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23] wire decoded_addr_22_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77] wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23] wire decoded_addr_139_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77] wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23] wire decoded_addr_11_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77] wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23] wire decoded_addr_134_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77] wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23] wire decoded_addr_12_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77] wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23] wire decoded_addr_65_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77] wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23] wire decoded_addr_86_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77] wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23] wire decoded_addr_47_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77] wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23] wire decoded_addr_106_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77] wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23] wire decoded_addr_58_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77] wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23] wire decoded_addr_87_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77] wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23] wire decoded_addr_142_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77] wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23] wire decoded_addr_13_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77] wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23] wire decoded_addr_35_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77] wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23] wire decoded_addr_2_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77] wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23] wire decoded_addr_66_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77] wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23] wire decoded_addr_42_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77] wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23] wire decoded_addr_61_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77] wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23] wire decoded_addr_48_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77] wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23] wire decoded_addr_44_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77] wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23] wire decoded_addr_15_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77] wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23] wire decoded_addr_145_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77] wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23] wire decoded_addr_93_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77] wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23] wire decoded_addr_6_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77] wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23] wire decoded_addr_28_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77] wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23] wire decoded_addr_25_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77] wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23] wire decoded_addr_137_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77] wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23] wire decoded_addr_123_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77] wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23] wire decoded_addr_23_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77] wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23] wire decoded_addr_69_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77] wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23] wire decoded_addr_141_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77] wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23] wire decoded_addr_9_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77] wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23] wire decoded_addr_104_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77] wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23] wire decoded_addr_8_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77] wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23] wire decoded_addr_125_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77] wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23] wire decoded_addr_85_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77] wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23] wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77] wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23] wire decoded_addr_20_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77] wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23] wire decoded_addr_135_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77] wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23] wire decoded_addr_115_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77] wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23] wire decoded_addr_43_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77] wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23] wire decoded_addr_71_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77] wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23] wire decoded_addr_110_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77] wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23] wire decoded_addr_140_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77] wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23] wire decoded_addr_34_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77] wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23] wire decoded_addr_40_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77] wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23] wire decoded_addr_80_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77] wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23] wire decoded_addr_98_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77] wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23] wire decoded_addr_18_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77] wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23] wire decoded_addr_3_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77] wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23] wire decoded_addr_127_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77] wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23] wire decoded_addr_38_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77] wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23] wire decoded_addr_95_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77] wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}] wire [63:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}] wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}] assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}] assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39] wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39] wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31] wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44] wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] | 7'h73}; // @[CSR.scala:892:{30,44}] wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22] wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [8:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_4 = |_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23] wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23] wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23] wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23] wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23] wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37] wire [8:0] decoded_1; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_11 = |_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37] assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37] wire is_break = decoded_1[7]; // @[pla.scala:81:23] wire is_ret = decoded_1[6]; // @[pla.scala:81:23] wire is_wfi = decoded_1[4]; // @[pla.scala:81:23] wire is_sfence = decoded_1[3]; // @[pla.scala:81:23] wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23] wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23] wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23] wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}] wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}] wire is_counter = _is_counter_T_2 | _is_counter_T_5; // @[package.scala:213:55] wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}] wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74] wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}] wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire allow_wfi = _allow_wfi_T_1 | _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}] wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}] wire _GEN_4 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77] wire _allow_sfence_vma_T_2; // @[CSR.scala:907:77] assign _allow_sfence_vma_T_2 = _GEN_4; // @[CSR.scala:907:77] wire _allow_sfence_vma_T_6; // @[CSR.scala:907:77] assign _allow_sfence_vma_T_6 = _GEN_4; // @[CSR.scala:907:77] wire _allow_sfence_vma_T_10; // @[CSR.scala:907:77] assign _allow_sfence_vma_T_10 = _GEN_4; // @[CSR.scala:907:77] wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}] wire allow_sfence_vma = _allow_sfence_vma_T_1 | _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}] wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88] wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}] wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81] wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}] wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}] wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}] wire _GEN_5 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79] wire _allow_sret_T_2; // @[CSR.scala:910:79] assign _allow_sret_T_2 = _GEN_5; // @[CSR.scala:910:79] wire _allow_sret_T_6; // @[CSR.scala:910:79] assign _allow_sret_T_6 = _GEN_5; // @[CSR.scala:910:79] wire _allow_sret_T_10; // @[CSR.scala:910:79] assign _allow_sret_T_10 = _GEN_5; // @[CSR.scala:910:79] wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}] wire allow_sret = _allow_sret_T_1 | _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}] wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_6 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70] wire [31:0] _GEN_7 = read_mcounteren >> _GEN_6; // @[CSR.scala:532:14, :912:70] wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70] assign _allow_counter_T_1 = _GEN_7; // @[CSR.scala:912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_7; // @[CSR.scala:912:70, :945:36] wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70] wire _allow_counter_T_3 = _allow_counter_T | _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}] wire _allow_counter_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46] wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}] wire [31:0] _GEN_8 = read_scounteren >> _GEN_6; // @[CSR.scala:536:14, :912:70, :913:75] wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75] assign _allow_counter_T_7 = _GEN_8; // @[CSR.scala:913:75] wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_8; // @[CSR.scala:913:75, :945:128] wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75] wire _allow_counter_T_9 = _allow_counter_T_6 | _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}] wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57] wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91] wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire [31:0] _GEN_9 = 32'h0 >> _GEN_6; // @[CSR.scala:912:70, :914:63] wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63] assign _allow_counter_T_14 = _GEN_9; // @[CSR.scala:914:63] wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_9; // @[CSR.scala:914:63, :945:71] wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63] wire _GEN_10 = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39] wire _io_decode_0_fp_illegal_T; // @[CSR.scala:915:39] assign _io_decode_0_fp_illegal_T = _GEN_10; // @[CSR.scala:915:39] wire _io_decode_1_fp_illegal_T; // @[CSR.scala:915:39] assign _io_decode_1_fp_illegal_T = _GEN_10; // @[CSR.scala:915:39] wire _io_decode_2_fp_illegal_T; // @[CSR.scala:915:39] assign _io_decode_2_fp_illegal_T = _GEN_10; // @[CSR.scala:915:39] wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T; // @[CSR.scala:915:{39,47}] assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3; // @[CSR.scala:915:{47,91}] assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91] wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}] wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42] wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_20 = addr == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_21 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_22 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_23 = addr == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_24 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_25 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_26 = addr == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_27 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_28 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_29 = addr == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_30 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_31 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_32 = addr == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_33 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_34 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_35 = addr == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_36 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_37 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_38 = addr == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_39 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_40 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_41 = addr == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_42 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_43 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_44 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_45 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_46 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_47 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_48 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_49 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_50 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_51 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_52 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_53 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_54 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_55 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_56 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_57 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_58 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_59 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_60 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_61 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_62 = addr == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_63 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_64 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_65 = addr == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_66 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_67 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_68 = addr == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_69 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_70 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_71 = addr == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_72 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_73 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_74 = addr == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_75 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_76 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_77 = addr == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_78 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_79 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_80 = addr == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_81 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_82 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_83 = addr == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_84 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_85 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_86 = addr == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_87 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_88 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_89 = addr == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_90 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_91 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_92 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_93 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_94 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_95 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_96 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_97 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_98 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_99 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_100 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_101 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_102 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_103 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_104 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_105 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_106 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_107 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_108 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_109 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_110 = addr == 12'h306; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_111 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_112 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_113 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_114 = addr == 12'h100; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_115 = addr == 12'h144; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_116 = addr == 12'h104; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_117 = addr == 12'h140; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_118 = addr == 12'h142; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_119 = addr == 12'h143; // @[CSR.scala:897:27, :899:93] wire _GEN_11 = addr == 12'h180; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_120; // @[CSR.scala:899:93] assign _csr_exists_T_120 = _GEN_11; // @[CSR.scala:899:93] wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_0_read_illegal_T_3 = _GEN_11; // @[CSR.scala:899:93, :925:14] wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_11; // @[CSR.scala:899:93, :947:12] wire _csr_exists_T_121 = addr == 12'h141; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_122 = addr == 12'h105; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_123 = addr == 12'h106; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_124 = addr == 12'h303; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_125 = addr == 12'h302; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_126 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_127 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_128 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_129 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_130 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_131 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_132 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_133 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_134 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_135 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_136 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_137 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_138 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_139 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_140 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_141 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_142 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_143 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_144 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_145 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_146 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_147 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_148 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_149 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_150 = _csr_exists_T | _csr_exists_T_1; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_151 = _csr_exists_T_150 | _csr_exists_T_2; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_152 = _csr_exists_T_151 | _csr_exists_T_3; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_153 = _csr_exists_T_152 | _csr_exists_T_4; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_154 = _csr_exists_T_153 | _csr_exists_T_5; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_155 = _csr_exists_T_154 | _csr_exists_T_6; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_156 = _csr_exists_T_155 | _csr_exists_T_7; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_157 = _csr_exists_T_156 | _csr_exists_T_8; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_158 = _csr_exists_T_157 | _csr_exists_T_9; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_159 = _csr_exists_T_158 | _csr_exists_T_10; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_160 = _csr_exists_T_159 | _csr_exists_T_11; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_161 = _csr_exists_T_160 | _csr_exists_T_12; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_162 = _csr_exists_T_161 | _csr_exists_T_13; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_163 = _csr_exists_T_162 | _csr_exists_T_14; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_164 = _csr_exists_T_163 | _csr_exists_T_15; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_165 = _csr_exists_T_164 | _csr_exists_T_16; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_166 = _csr_exists_T_165 | _csr_exists_T_17; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_167 = _csr_exists_T_166 | _csr_exists_T_18; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_168 = _csr_exists_T_167 | _csr_exists_T_19; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_169 = _csr_exists_T_168 | _csr_exists_T_20; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_170 = _csr_exists_T_169 | _csr_exists_T_21; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_171 = _csr_exists_T_170 | _csr_exists_T_22; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_172 = _csr_exists_T_171 | _csr_exists_T_23; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_173 = _csr_exists_T_172 | _csr_exists_T_24; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_174 = _csr_exists_T_173 | _csr_exists_T_25; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_175 = _csr_exists_T_174 | _csr_exists_T_26; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_176 = _csr_exists_T_175 | _csr_exists_T_27; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_177 = _csr_exists_T_176 | _csr_exists_T_28; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_178 = _csr_exists_T_177 | _csr_exists_T_29; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_179 = _csr_exists_T_178 | _csr_exists_T_30; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_180 = _csr_exists_T_179 | _csr_exists_T_31; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_181 = _csr_exists_T_180 | _csr_exists_T_32; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_182 = _csr_exists_T_181 | _csr_exists_T_33; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_183 = _csr_exists_T_182 | _csr_exists_T_34; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_184 = _csr_exists_T_183 | _csr_exists_T_35; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_185 = _csr_exists_T_184 | _csr_exists_T_36; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_186 = _csr_exists_T_185 | _csr_exists_T_37; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_187 = _csr_exists_T_186 | _csr_exists_T_38; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_188 = _csr_exists_T_187 | _csr_exists_T_39; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_189 = _csr_exists_T_188 | _csr_exists_T_40; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_190 = _csr_exists_T_189 | _csr_exists_T_41; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_191 = _csr_exists_T_190 | _csr_exists_T_42; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_192 = _csr_exists_T_191 | _csr_exists_T_43; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_193 = _csr_exists_T_192 | _csr_exists_T_44; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_194 = _csr_exists_T_193 | _csr_exists_T_45; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_195 = _csr_exists_T_194 | _csr_exists_T_46; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_196 = _csr_exists_T_195 | _csr_exists_T_47; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_197 = _csr_exists_T_196 | _csr_exists_T_48; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_198 = _csr_exists_T_197 | _csr_exists_T_49; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_199 = _csr_exists_T_198 | _csr_exists_T_50; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_200 = _csr_exists_T_199 | _csr_exists_T_51; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_201 = _csr_exists_T_200 | _csr_exists_T_52; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_202 = _csr_exists_T_201 | _csr_exists_T_53; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_203 = _csr_exists_T_202 | _csr_exists_T_54; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_204 = _csr_exists_T_203 | _csr_exists_T_55; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_205 = _csr_exists_T_204 | _csr_exists_T_56; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_206 = _csr_exists_T_205 | _csr_exists_T_57; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_207 = _csr_exists_T_206 | _csr_exists_T_58; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_208 = _csr_exists_T_207 | _csr_exists_T_59; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_209 = _csr_exists_T_208 | _csr_exists_T_60; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_210 = _csr_exists_T_209 | _csr_exists_T_61; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_211 = _csr_exists_T_210 | _csr_exists_T_62; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_212 = _csr_exists_T_211 | _csr_exists_T_63; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_213 = _csr_exists_T_212 | _csr_exists_T_64; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_214 = _csr_exists_T_213 | _csr_exists_T_65; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_215 = _csr_exists_T_214 | _csr_exists_T_66; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_216 = _csr_exists_T_215 | _csr_exists_T_67; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_217 = _csr_exists_T_216 | _csr_exists_T_68; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_218 = _csr_exists_T_217 | _csr_exists_T_69; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_219 = _csr_exists_T_218 | _csr_exists_T_70; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_220 = _csr_exists_T_219 | _csr_exists_T_71; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_221 = _csr_exists_T_220 | _csr_exists_T_72; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_222 = _csr_exists_T_221 | _csr_exists_T_73; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_223 = _csr_exists_T_222 | _csr_exists_T_74; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_224 = _csr_exists_T_223 | _csr_exists_T_75; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_225 = _csr_exists_T_224 | _csr_exists_T_76; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_226 = _csr_exists_T_225 | _csr_exists_T_77; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_227 = _csr_exists_T_226 | _csr_exists_T_78; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_228 = _csr_exists_T_227 | _csr_exists_T_79; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_229 = _csr_exists_T_228 | _csr_exists_T_80; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_230 = _csr_exists_T_229 | _csr_exists_T_81; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_231 = _csr_exists_T_230 | _csr_exists_T_82; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_232 = _csr_exists_T_231 | _csr_exists_T_83; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_233 = _csr_exists_T_232 | _csr_exists_T_84; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_234 = _csr_exists_T_233 | _csr_exists_T_85; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_235 = _csr_exists_T_234 | _csr_exists_T_86; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_236 = _csr_exists_T_235 | _csr_exists_T_87; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_237 = _csr_exists_T_236 | _csr_exists_T_88; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_238 = _csr_exists_T_237 | _csr_exists_T_89; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_239 = _csr_exists_T_238 | _csr_exists_T_90; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_240 = _csr_exists_T_239 | _csr_exists_T_91; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_241 = _csr_exists_T_240 | _csr_exists_T_92; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_242 = _csr_exists_T_241 | _csr_exists_T_93; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_243 = _csr_exists_T_242 | _csr_exists_T_94; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_244 = _csr_exists_T_243 | _csr_exists_T_95; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_245 = _csr_exists_T_244 | _csr_exists_T_96; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_246 = _csr_exists_T_245 | _csr_exists_T_97; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_247 = _csr_exists_T_246 | _csr_exists_T_98; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_248 = _csr_exists_T_247 | _csr_exists_T_99; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_249 = _csr_exists_T_248 | _csr_exists_T_100; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_250 = _csr_exists_T_249 | _csr_exists_T_101; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_251 = _csr_exists_T_250 | _csr_exists_T_102; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_252 = _csr_exists_T_251 | _csr_exists_T_103; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_253 = _csr_exists_T_252 | _csr_exists_T_104; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_254 = _csr_exists_T_253 | _csr_exists_T_105; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_255 = _csr_exists_T_254 | _csr_exists_T_106; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_256 = _csr_exists_T_255 | _csr_exists_T_107; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_257 = _csr_exists_T_256 | _csr_exists_T_108; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_258 = _csr_exists_T_257 | _csr_exists_T_109; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_259 = _csr_exists_T_258 | _csr_exists_T_110; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_260 = _csr_exists_T_259 | _csr_exists_T_111; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_261 = _csr_exists_T_260 | _csr_exists_T_112; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_262 = _csr_exists_T_261 | _csr_exists_T_113; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_263 = _csr_exists_T_262 | _csr_exists_T_114; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_264 = _csr_exists_T_263 | _csr_exists_T_115; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_265 = _csr_exists_T_264 | _csr_exists_T_116; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_266 = _csr_exists_T_265 | _csr_exists_T_117; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_267 = _csr_exists_T_266 | _csr_exists_T_118; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_268 = _csr_exists_T_267 | _csr_exists_T_119; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_269 = _csr_exists_T_268 | _csr_exists_T_120; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_270 = _csr_exists_T_269 | _csr_exists_T_121; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_271 = _csr_exists_T_270 | _csr_exists_T_122; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_272 = _csr_exists_T_271 | _csr_exists_T_123; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_273 = _csr_exists_T_272 | _csr_exists_T_124; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_274 = _csr_exists_T_273 | _csr_exists_T_125; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_275 = _csr_exists_T_274 | _csr_exists_T_126; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_276 = _csr_exists_T_275 | _csr_exists_T_127; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_277 = _csr_exists_T_276 | _csr_exists_T_128; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_278 = _csr_exists_T_277 | _csr_exists_T_129; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_279 = _csr_exists_T_278 | _csr_exists_T_130; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_280 = _csr_exists_T_279 | _csr_exists_T_131; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_281 = _csr_exists_T_280 | _csr_exists_T_132; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_282 = _csr_exists_T_281 | _csr_exists_T_133; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_283 = _csr_exists_T_282 | _csr_exists_T_134; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_284 = _csr_exists_T_283 | _csr_exists_T_135; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_285 = _csr_exists_T_284 | _csr_exists_T_136; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_286 = _csr_exists_T_285 | _csr_exists_T_137; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_287 = _csr_exists_T_286 | _csr_exists_T_138; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_288 = _csr_exists_T_287 | _csr_exists_T_139; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_289 = _csr_exists_T_288 | _csr_exists_T_140; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_290 = _csr_exists_T_289 | _csr_exists_T_141; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_291 = _csr_exists_T_290 | _csr_exists_T_142; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_292 = _csr_exists_T_291 | _csr_exists_T_143; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_293 = _csr_exists_T_292 | _csr_exists_T_144; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_294 = _csr_exists_T_293 | _csr_exists_T_145; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_295 = _csr_exists_T_294 | _csr_exists_T_146; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_296 = _csr_exists_T_295 | _csr_exists_T_147; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_297 = _csr_exists_T_296 | _csr_exists_T_148; // @[CSR.scala:899:{93,111}] wire csr_exists = _csr_exists_T_297 | _csr_exists_T_149; // @[CSR.scala:899:{93,111}] wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28] wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7] wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T | _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 | _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59] wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}] wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 | _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56] wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21] wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}] wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 | _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18] wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56] wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21] assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21] assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49] wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17] wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}] wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 | _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14] wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17] wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}] wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 | _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14] wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_0_system_illegal_T_16 = is_sfence | is_hfence_gvma; // @[CSR.scala:903:82, :939:18] wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40] wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}] wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 | _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37] wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105] wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53] wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46] wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34] wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64] wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37] wire _io_decode_1_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105] wire _io_decode_1_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53] wire _io_decode_1_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46] wire _io_decode_1_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34] wire _io_decode_1_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64] wire _io_decode_1_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37] wire _io_decode_2_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105] wire _io_decode_2_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53] wire _io_decode_2_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46] wire _io_decode_2_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34] wire _io_decode_2_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64] wire _io_decode_2_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37] wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61] wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61] wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}] wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}] wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 | _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}] wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 | _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}] wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}] wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 | _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34] wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}] assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma | is_hfence_gvma; // @[CSR.scala:903:82, :950:22] wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T | is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}] wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}] wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41] wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}] wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 | _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14] wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}] wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}] wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}] wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 | _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44] wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}] wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}] wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}] wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 | _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17] assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire [11:0] addr_1 = io_decode_1_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_1_fp_csr_plaInput = addr_1; // @[pla.scala:77:22] wire [11:0] io_decode_1_vector_csr_plaInput = addr_1; // @[pla.scala:77:22] wire [11:0] io_decode_1_read_illegal_plaInput = addr_1; // @[pla.scala:77:22] wire [11:0] io_decode_1_read_illegal_plaInput_1 = addr_1; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_2 = ~decoded_plaInput_2; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_2; // @[pla.scala:120:37] wire [8:0] decoded_2; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_invInputs_2[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_invInputs_2[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_invInputs_2[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_invInputs_2[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_invInputs_2[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_invInputs_2[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_invInputs_2[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_invInputs_2[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_invInputs_2[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_invInputs_2[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_invInputs_2[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_invInputs_2[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_invInputs_2[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_invInputs_2[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_invInputs_2[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_invInputs_2[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_invInputs_2[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_invInputs_2[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_invInputs_2[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_invInputs_2[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_invInputs_2[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_invInputs_2[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12_2 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_invInputs_2[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_invInputs_2[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_invInputs_2[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_invInputs_2[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_invInputs_2[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_invInputs_2[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14_2 = decoded_invInputs_2[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15_2 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_invInputs_2[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16_2 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_invInputs_2[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_12 = {decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_12 = {decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_8_12}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_12 = {decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_12 = {decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_12 = {decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_12 = {decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_14 = {decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2_2 = &_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_20 = decoded_andMatrixOutputs_6_2_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_plaInput_2[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_13 = {decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_13 = {decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_13 = {decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_13 = {decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_13 = {decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_13 = {decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_15 = {decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_2 = &_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_19 = decoded_andMatrixOutputs_4_2_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_plaInput_2[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_plaInput_2[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_plaInput_2[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_plaInput_2[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13_2 = decoded_plaInput_2[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_plaInput_2[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_14 = {decoded_andMatrixOutputs_andMatrixInput_8_14, decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_andMatrixOutputs_andMatrixInput_5_14, decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_14 = {decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_14 = {decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_14 = {decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_14 = {decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_14 = {decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_16 = {decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_2 = &_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_plaInput_2[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_plaInput_2[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_15 = {decoded_andMatrixOutputs_andMatrixInput_8_15, decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_andMatrixOutputs_andMatrixInput_5_15, decoded_andMatrixOutputs_andMatrixInput_6_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_15 = {decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_15 = {decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_15 = {decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_15 = {decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_15 = {decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_17 = {decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_2 = &_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_15 = decoded_andMatrixOutputs_1_2_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_plaInput_2[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_invInputs_2[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_invInputs_2[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_plaInput_2[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_plaInput_2[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_plaInput_2[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_invInputs_2[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_invInputs_2[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_invInputs_2[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_plaInput_2[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_15_2, decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_13_2, decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_16 = {decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_11_8, decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_16 = {decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_16 = {decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_7_16, decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_16, decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_16 = {decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_16 = {decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_16 = {decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_18 = {decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_2 = &_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_14 = decoded_andMatrixOutputs_0_2_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_plaInput_2[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_17 = {decoded_andMatrixOutputs_andMatrixInput_8_17, decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_andMatrixOutputs_andMatrixInput_5_17, decoded_andMatrixOutputs_andMatrixInput_6_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_17 = {decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_17 = {decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_17 = {decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_17 = {decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_17 = {decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_19 = {decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_2 = &_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_16 = decoded_andMatrixOutputs_5_2_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_plaInput_2[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_20 = {decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_2 = &_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_17 = {decoded_andMatrixOutputs_3_2_2, decoded_andMatrixOutputs_2_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_18 = |_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi_2 = {_decoded_orMatrixOutputs_T_14, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo_2 = {decoded_orMatrixOutputs_lo_hi_2, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo_2 = {_decoded_orMatrixOutputs_T_16, _decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_2 = {_decoded_orMatrixOutputs_T_20, _decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_2 = {decoded_orMatrixOutputs_hi_hi_hi_2, _decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_2 = {decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_2 = {decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_18 = decoded_orMatrixOutputs_2[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_19 = decoded_orMatrixOutputs_2[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_20 = decoded_orMatrixOutputs_2[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_21 = decoded_orMatrixOutputs_2[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_22 = decoded_orMatrixOutputs_2[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_23 = decoded_orMatrixOutputs_2[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_24 = decoded_orMatrixOutputs_2[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_25 = decoded_orMatrixOutputs_2[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_26 = decoded_orMatrixOutputs_2[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_2 = {_decoded_invMatrixOutputs_T_19, _decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_2 = {_decoded_invMatrixOutputs_T_21, _decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_2 = {decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_2 = {_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_2 = {_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_2 = {decoded_invMatrixOutputs_hi_hi_hi_2, _decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_2 = {decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_2 = {decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2}; // @[pla.scala:120:37] assign decoded_2 = decoded_invMatrixOutputs_2; // @[pla.scala:81:23, :120:37] wire is_break_1 = decoded_2[7]; // @[pla.scala:81:23] wire is_ret_1 = decoded_2[6]; // @[pla.scala:81:23] wire is_wfi_1 = decoded_2[4]; // @[pla.scala:81:23] wire is_sfence_1 = decoded_2[3]; // @[pla.scala:81:23] wire is_hfence_vvma_1 = decoded_2[2]; // @[pla.scala:81:23] wire is_hfence_gvma_1 = decoded_2[1]; // @[pla.scala:81:23] wire is_hlsv_1 = decoded_2[0]; // @[pla.scala:81:23] wire _is_counter_T_6 = addr_1 > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_7 = addr_1 < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_8 = _is_counter_T_6 & _is_counter_T_7; // @[package.scala:213:{47,55,60}] wire _is_counter_T_9 = addr_1 > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_10 = addr_1 < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_11 = _is_counter_T_9 & _is_counter_T_10; // @[package.scala:213:{47,55,60}] wire is_counter_1 = _is_counter_T_8 | _is_counter_T_11; // @[package.scala:213:55] wire _allow_wfi_T_8 = _allow_wfi_T_7; // @[CSR.scala:906:{42,61}] wire _allow_wfi_T_9 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74] wire _allow_wfi_T_13 = _allow_wfi_T_9; // @[CSR.scala:906:{74,90}] wire _allow_wfi_T_10 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire allow_wfi_1 = _allow_wfi_T_8 | _allow_wfi_T_13; // @[CSR.scala:906:{42,71,90}] wire _allow_sfence_vma_T_5 = _allow_sfence_vma_T_4; // @[CSR.scala:907:{41,60}] wire _allow_sfence_vma_T_7 = ~_allow_sfence_vma_T_6; // @[CSR.scala:907:{73,77}] wire allow_sfence_vma_1 = _allow_sfence_vma_T_5 | _allow_sfence_vma_T_7; // @[CSR.scala:907:{41,70,73}] wire _allow_hfence_vvma_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_4 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88] wire _allow_hfence_vvma_T_5 = _allow_hfence_vvma_T_3 & _allow_hfence_vvma_T_4; // @[CSR.scala:908:{53,68,88}] wire _allow_hlsv_T_4 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81] wire _allow_hlsv_T_6 = _allow_hlsv_T_5; // @[CSR.scala:909:{81,92}] wire _allow_hlsv_T_7 = _allow_hlsv_T_4 & _allow_hlsv_T_6; // @[CSR.scala:909:{46,61,92}] wire _allow_sret_T_5 = _allow_sret_T_4; // @[CSR.scala:910:{43,62}] wire _allow_sret_T_7 = ~_allow_sret_T_6; // @[CSR.scala:910:{75,79}] wire allow_sret_1 = _allow_sret_T_5 | _allow_sret_T_7; // @[CSR.scala:910:{43,72,75}] wire [4:0] counter_addr_1 = addr_1[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_12 = {27'h0, counter_addr_1}; // @[CSR.scala:911:28, :912:70] wire [31:0] _GEN_13 = read_mcounteren >> _GEN_12; // @[CSR.scala:532:14, :912:70] wire [31:0] _allow_counter_T_18; // @[CSR.scala:912:70] assign _allow_counter_T_18 = _GEN_13; // @[CSR.scala:912:70] wire [31:0] _io_decode_1_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_1_virtual_access_illegal_T_3 = _GEN_13; // @[CSR.scala:912:70, :945:36] wire _allow_counter_T_19 = _allow_counter_T_18[0]; // @[CSR.scala:912:70] wire _allow_counter_T_20 = _allow_counter_T_17 | _allow_counter_T_19; // @[CSR.scala:912:{42,52,70}] wire _allow_counter_T_22 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46] wire _allow_counter_T_23 = _allow_counter_T_22; // @[CSR.scala:913:{27,46}] wire [31:0] _GEN_14 = read_scounteren >> _GEN_12; // @[CSR.scala:536:14, :912:70, :913:75] wire [31:0] _allow_counter_T_24; // @[CSR.scala:913:75] assign _allow_counter_T_24 = _GEN_14; // @[CSR.scala:913:75] wire [31:0] _io_decode_1_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_1_virtual_access_illegal_T_11 = _GEN_14; // @[CSR.scala:913:75, :945:128] wire _allow_counter_T_25 = _allow_counter_T_24[0]; // @[CSR.scala:913:75] wire _allow_counter_T_26 = _allow_counter_T_23 | _allow_counter_T_25; // @[CSR.scala:913:{27,57,75}] wire _allow_counter_T_27 = _allow_counter_T_20 & _allow_counter_T_26; // @[CSR.scala:912:{52,86}, :913:57] wire allow_counter_1 = _allow_counter_T_27; // @[CSR.scala:912:86, :913:91] wire _allow_counter_T_29 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire [31:0] _GEN_15 = 32'h0 >> _GEN_12; // @[CSR.scala:912:70, :914:63] wire [31:0] _allow_counter_T_31; // @[CSR.scala:914:63] assign _allow_counter_T_31 = _GEN_15; // @[CSR.scala:914:63] wire [31:0] _io_decode_1_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_1_virtual_access_illegal_T_6 = _GEN_15; // @[CSR.scala:914:63, :945:71] wire _allow_counter_T_32 = _allow_counter_T_31[0]; // @[CSR.scala:914:63] wire _io_decode_1_fp_illegal_T_3 = _io_decode_1_fp_illegal_T; // @[CSR.scala:915:{39,47}] assign _io_decode_1_fp_illegal_T_6 = _io_decode_1_fp_illegal_T_3; // @[CSR.scala:915:{47,91}] assign io_decode_1_fp_illegal_0 = _io_decode_1_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91] wire _io_decode_1_vector_illegal_T_2 = reg_mstatus_v & _io_decode_1_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}] wire [11:0] io_decode_1_fp_csr_invInputs = ~io_decode_1_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_1_fp_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_1_fp_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_1_fp_csr_T = io_decode_1_fp_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_1_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_1_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_1_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_1_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_1_fp_csr_andMatrixOutputs_lo = {io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_1_fp_csr_andMatrixOutputs_hi = {io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_1_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _io_decode_1_fp_csr_andMatrixOutputs_T = {io_decode_1_fp_csr_andMatrixOutputs_hi, io_decode_1_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_1_fp_csr_andMatrixOutputs_0_2 = &_io_decode_1_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_1_fp_csr_orMatrixOutputs = io_decode_1_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_1_fp_csr_invMatrixOutputs = io_decode_1_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_1_fp_csr_plaOutput = io_decode_1_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_1_fp_csr_0 = _io_decode_1_fp_csr_T; // @[Decode.scala:55:116] wire [11:0] io_decode_1_vector_csr_invInputs = ~io_decode_1_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire [1:0] _csr_addr_legal_T_9 = addr_1[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_15 = addr_1[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_1_virtual_access_illegal_T_1 = addr_1[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_1_virtual_access_illegal_T_18 = addr_1[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_1_virtual_system_illegal_T_9 = addr_1[9:8]; // @[CSR.scala:190:36, :897:27] wire _csr_addr_legal_T_10 = reg_mstatus_prv >= _csr_addr_legal_T_9; // @[CSR.scala:190:36, :395:28, :920:42] wire csr_addr_legal_1 = _csr_addr_legal_T_10; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_11 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_16 = _csr_addr_legal_T_15 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T_298 = addr_1 == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_299 = addr_1 == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_300 = addr_1 == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_301 = addr_1 == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_302 = addr_1 == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_303 = addr_1 == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_304 = addr_1 == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_305 = addr_1 == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_306 = addr_1 == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_307 = addr_1 == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_308 = addr_1 == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_309 = addr_1 == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_310 = addr_1 == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_311 = addr_1 == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_312 = addr_1 == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_313 = addr_1 == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_314 = addr_1 == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_315 = addr_1 == 12'h1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_316 = addr_1 == 12'h2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_317 = addr_1 == 12'h3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_318 = addr_1 == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_319 = addr_1 == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_320 = addr_1 == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_321 = addr_1 == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_322 = addr_1 == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_323 = addr_1 == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_324 = addr_1 == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_325 = addr_1 == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_326 = addr_1 == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_327 = addr_1 == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_328 = addr_1 == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_329 = addr_1 == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_330 = addr_1 == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_331 = addr_1 == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_332 = addr_1 == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_333 = addr_1 == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_334 = addr_1 == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_335 = addr_1 == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_336 = addr_1 == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_337 = addr_1 == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_338 = addr_1 == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_339 = addr_1 == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_340 = addr_1 == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_341 = addr_1 == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_342 = addr_1 == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_343 = addr_1 == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_344 = addr_1 == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_345 = addr_1 == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_346 = addr_1 == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_347 = addr_1 == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_348 = addr_1 == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_349 = addr_1 == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_350 = addr_1 == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_351 = addr_1 == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_352 = addr_1 == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_353 = addr_1 == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_354 = addr_1 == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_355 = addr_1 == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_356 = addr_1 == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_357 = addr_1 == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_358 = addr_1 == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_359 = addr_1 == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_360 = addr_1 == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_361 = addr_1 == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_362 = addr_1 == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_363 = addr_1 == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_364 = addr_1 == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_365 = addr_1 == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_366 = addr_1 == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_367 = addr_1 == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_368 = addr_1 == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_369 = addr_1 == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_370 = addr_1 == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_371 = addr_1 == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_372 = addr_1 == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_373 = addr_1 == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_374 = addr_1 == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_375 = addr_1 == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_376 = addr_1 == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_377 = addr_1 == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_378 = addr_1 == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_379 = addr_1 == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_380 = addr_1 == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_381 = addr_1 == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_382 = addr_1 == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_383 = addr_1 == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_384 = addr_1 == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_385 = addr_1 == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_386 = addr_1 == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_387 = addr_1 == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_388 = addr_1 == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_389 = addr_1 == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_390 = addr_1 == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_391 = addr_1 == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_392 = addr_1 == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_393 = addr_1 == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_394 = addr_1 == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_395 = addr_1 == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_396 = addr_1 == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_397 = addr_1 == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_398 = addr_1 == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_399 = addr_1 == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_400 = addr_1 == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_401 = addr_1 == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_402 = addr_1 == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_403 = addr_1 == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_404 = addr_1 == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_405 = addr_1 == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_406 = addr_1 == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_407 = addr_1 == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_408 = addr_1 == 12'h306; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_409 = addr_1 == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_410 = addr_1 == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_411 = addr_1 == 12'h30A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_412 = addr_1 == 12'h100; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_413 = addr_1 == 12'h144; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_414 = addr_1 == 12'h104; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_415 = addr_1 == 12'h140; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_416 = addr_1 == 12'h142; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_417 = addr_1 == 12'h143; // @[CSR.scala:897:27, :899:93] wire _GEN_16 = addr_1 == 12'h180; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_418; // @[CSR.scala:899:93] assign _csr_exists_T_418 = _GEN_16; // @[CSR.scala:899:93] wire _io_decode_1_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_1_read_illegal_T_3 = _GEN_16; // @[CSR.scala:899:93, :925:14] wire _io_decode_1_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_1_virtual_access_illegal_T_24 = _GEN_16; // @[CSR.scala:899:93, :947:12] wire _csr_exists_T_419 = addr_1 == 12'h141; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_420 = addr_1 == 12'h105; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_421 = addr_1 == 12'h106; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_422 = addr_1 == 12'h303; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_423 = addr_1 == 12'h302; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_424 = addr_1 == 12'h10A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_425 = addr_1 == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_426 = addr_1 == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_427 = addr_1 == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_428 = addr_1 == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_429 = addr_1 == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_430 = addr_1 == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_431 = addr_1 == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_432 = addr_1 == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_433 = addr_1 == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_434 = addr_1 == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_435 = addr_1 == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_436 = addr_1 == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_437 = addr_1 == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_438 = addr_1 == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_439 = addr_1 == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_440 = addr_1 == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_441 = addr_1 == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_442 = addr_1 == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_443 = addr_1 == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_444 = addr_1 == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_445 = addr_1 == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_446 = addr_1 == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_447 = addr_1 == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_448 = _csr_exists_T_298 | _csr_exists_T_299; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_449 = _csr_exists_T_448 | _csr_exists_T_300; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_450 = _csr_exists_T_449 | _csr_exists_T_301; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_451 = _csr_exists_T_450 | _csr_exists_T_302; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_452 = _csr_exists_T_451 | _csr_exists_T_303; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_453 = _csr_exists_T_452 | _csr_exists_T_304; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_454 = _csr_exists_T_453 | _csr_exists_T_305; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_455 = _csr_exists_T_454 | _csr_exists_T_306; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_456 = _csr_exists_T_455 | _csr_exists_T_307; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_457 = _csr_exists_T_456 | _csr_exists_T_308; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_458 = _csr_exists_T_457 | _csr_exists_T_309; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_459 = _csr_exists_T_458 | _csr_exists_T_310; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_460 = _csr_exists_T_459 | _csr_exists_T_311; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_461 = _csr_exists_T_460 | _csr_exists_T_312; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_462 = _csr_exists_T_461 | _csr_exists_T_313; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_463 = _csr_exists_T_462 | _csr_exists_T_314; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_464 = _csr_exists_T_463 | _csr_exists_T_315; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_465 = _csr_exists_T_464 | _csr_exists_T_316; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_466 = _csr_exists_T_465 | _csr_exists_T_317; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_467 = _csr_exists_T_466 | _csr_exists_T_318; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_468 = _csr_exists_T_467 | _csr_exists_T_319; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_469 = _csr_exists_T_468 | _csr_exists_T_320; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_470 = _csr_exists_T_469 | _csr_exists_T_321; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_471 = _csr_exists_T_470 | _csr_exists_T_322; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_472 = _csr_exists_T_471 | _csr_exists_T_323; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_473 = _csr_exists_T_472 | _csr_exists_T_324; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_474 = _csr_exists_T_473 | _csr_exists_T_325; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_475 = _csr_exists_T_474 | _csr_exists_T_326; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_476 = _csr_exists_T_475 | _csr_exists_T_327; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_477 = _csr_exists_T_476 | _csr_exists_T_328; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_478 = _csr_exists_T_477 | _csr_exists_T_329; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_479 = _csr_exists_T_478 | _csr_exists_T_330; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_480 = _csr_exists_T_479 | _csr_exists_T_331; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_481 = _csr_exists_T_480 | _csr_exists_T_332; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_482 = _csr_exists_T_481 | _csr_exists_T_333; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_483 = _csr_exists_T_482 | _csr_exists_T_334; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_484 = _csr_exists_T_483 | _csr_exists_T_335; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_485 = _csr_exists_T_484 | _csr_exists_T_336; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_486 = _csr_exists_T_485 | _csr_exists_T_337; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_487 = _csr_exists_T_486 | _csr_exists_T_338; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_488 = _csr_exists_T_487 | _csr_exists_T_339; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_489 = _csr_exists_T_488 | _csr_exists_T_340; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_490 = _csr_exists_T_489 | _csr_exists_T_341; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_491 = _csr_exists_T_490 | _csr_exists_T_342; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_492 = _csr_exists_T_491 | _csr_exists_T_343; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_493 = _csr_exists_T_492 | _csr_exists_T_344; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_494 = _csr_exists_T_493 | _csr_exists_T_345; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_495 = _csr_exists_T_494 | _csr_exists_T_346; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_496 = _csr_exists_T_495 | _csr_exists_T_347; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_497 = _csr_exists_T_496 | _csr_exists_T_348; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_498 = _csr_exists_T_497 | _csr_exists_T_349; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_499 = _csr_exists_T_498 | _csr_exists_T_350; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_500 = _csr_exists_T_499 | _csr_exists_T_351; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_501 = _csr_exists_T_500 | _csr_exists_T_352; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_502 = _csr_exists_T_501 | _csr_exists_T_353; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_503 = _csr_exists_T_502 | _csr_exists_T_354; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_504 = _csr_exists_T_503 | _csr_exists_T_355; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_505 = _csr_exists_T_504 | _csr_exists_T_356; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_506 = _csr_exists_T_505 | _csr_exists_T_357; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_507 = _csr_exists_T_506 | _csr_exists_T_358; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_508 = _csr_exists_T_507 | _csr_exists_T_359; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_509 = _csr_exists_T_508 | _csr_exists_T_360; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_510 = _csr_exists_T_509 | _csr_exists_T_361; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_511 = _csr_exists_T_510 | _csr_exists_T_362; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_512 = _csr_exists_T_511 | _csr_exists_T_363; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_513 = _csr_exists_T_512 | _csr_exists_T_364; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_514 = _csr_exists_T_513 | _csr_exists_T_365; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_515 = _csr_exists_T_514 | _csr_exists_T_366; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_516 = _csr_exists_T_515 | _csr_exists_T_367; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_517 = _csr_exists_T_516 | _csr_exists_T_368; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_518 = _csr_exists_T_517 | _csr_exists_T_369; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_519 = _csr_exists_T_518 | _csr_exists_T_370; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_520 = _csr_exists_T_519 | _csr_exists_T_371; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_521 = _csr_exists_T_520 | _csr_exists_T_372; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_522 = _csr_exists_T_521 | _csr_exists_T_373; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_523 = _csr_exists_T_522 | _csr_exists_T_374; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_524 = _csr_exists_T_523 | _csr_exists_T_375; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_525 = _csr_exists_T_524 | _csr_exists_T_376; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_526 = _csr_exists_T_525 | _csr_exists_T_377; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_527 = _csr_exists_T_526 | _csr_exists_T_378; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_528 = _csr_exists_T_527 | _csr_exists_T_379; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_529 = _csr_exists_T_528 | _csr_exists_T_380; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_530 = _csr_exists_T_529 | _csr_exists_T_381; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_531 = _csr_exists_T_530 | _csr_exists_T_382; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_532 = _csr_exists_T_531 | _csr_exists_T_383; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_533 = _csr_exists_T_532 | _csr_exists_T_384; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_534 = _csr_exists_T_533 | _csr_exists_T_385; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_535 = _csr_exists_T_534 | _csr_exists_T_386; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_536 = _csr_exists_T_535 | _csr_exists_T_387; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_537 = _csr_exists_T_536 | _csr_exists_T_388; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_538 = _csr_exists_T_537 | _csr_exists_T_389; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_539 = _csr_exists_T_538 | _csr_exists_T_390; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_540 = _csr_exists_T_539 | _csr_exists_T_391; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_541 = _csr_exists_T_540 | _csr_exists_T_392; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_542 = _csr_exists_T_541 | _csr_exists_T_393; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_543 = _csr_exists_T_542 | _csr_exists_T_394; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_544 = _csr_exists_T_543 | _csr_exists_T_395; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_545 = _csr_exists_T_544 | _csr_exists_T_396; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_546 = _csr_exists_T_545 | _csr_exists_T_397; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_547 = _csr_exists_T_546 | _csr_exists_T_398; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_548 = _csr_exists_T_547 | _csr_exists_T_399; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_549 = _csr_exists_T_548 | _csr_exists_T_400; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_550 = _csr_exists_T_549 | _csr_exists_T_401; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_551 = _csr_exists_T_550 | _csr_exists_T_402; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_552 = _csr_exists_T_551 | _csr_exists_T_403; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_553 = _csr_exists_T_552 | _csr_exists_T_404; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_554 = _csr_exists_T_553 | _csr_exists_T_405; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_555 = _csr_exists_T_554 | _csr_exists_T_406; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_556 = _csr_exists_T_555 | _csr_exists_T_407; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_557 = _csr_exists_T_556 | _csr_exists_T_408; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_558 = _csr_exists_T_557 | _csr_exists_T_409; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_559 = _csr_exists_T_558 | _csr_exists_T_410; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_560 = _csr_exists_T_559 | _csr_exists_T_411; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_561 = _csr_exists_T_560 | _csr_exists_T_412; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_562 = _csr_exists_T_561 | _csr_exists_T_413; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_563 = _csr_exists_T_562 | _csr_exists_T_414; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_564 = _csr_exists_T_563 | _csr_exists_T_415; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_565 = _csr_exists_T_564 | _csr_exists_T_416; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_566 = _csr_exists_T_565 | _csr_exists_T_417; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_567 = _csr_exists_T_566 | _csr_exists_T_418; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_568 = _csr_exists_T_567 | _csr_exists_T_419; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_569 = _csr_exists_T_568 | _csr_exists_T_420; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_570 = _csr_exists_T_569 | _csr_exists_T_421; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_571 = _csr_exists_T_570 | _csr_exists_T_422; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_572 = _csr_exists_T_571 | _csr_exists_T_423; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_573 = _csr_exists_T_572 | _csr_exists_T_424; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_574 = _csr_exists_T_573 | _csr_exists_T_425; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_575 = _csr_exists_T_574 | _csr_exists_T_426; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_576 = _csr_exists_T_575 | _csr_exists_T_427; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_577 = _csr_exists_T_576 | _csr_exists_T_428; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_578 = _csr_exists_T_577 | _csr_exists_T_429; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_579 = _csr_exists_T_578 | _csr_exists_T_430; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_580 = _csr_exists_T_579 | _csr_exists_T_431; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_581 = _csr_exists_T_580 | _csr_exists_T_432; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_582 = _csr_exists_T_581 | _csr_exists_T_433; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_583 = _csr_exists_T_582 | _csr_exists_T_434; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_584 = _csr_exists_T_583 | _csr_exists_T_435; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_585 = _csr_exists_T_584 | _csr_exists_T_436; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_586 = _csr_exists_T_585 | _csr_exists_T_437; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_587 = _csr_exists_T_586 | _csr_exists_T_438; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_588 = _csr_exists_T_587 | _csr_exists_T_439; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_589 = _csr_exists_T_588 | _csr_exists_T_440; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_590 = _csr_exists_T_589 | _csr_exists_T_441; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_591 = _csr_exists_T_590 | _csr_exists_T_442; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_592 = _csr_exists_T_591 | _csr_exists_T_443; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_593 = _csr_exists_T_592 | _csr_exists_T_444; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_594 = _csr_exists_T_593 | _csr_exists_T_445; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_595 = _csr_exists_T_594 | _csr_exists_T_446; // @[CSR.scala:899:{93,111}] wire csr_exists_1 = _csr_exists_T_595 | _csr_exists_T_447; // @[CSR.scala:899:{93,111}] wire _io_decode_1_read_illegal_T = ~csr_addr_legal_1; // @[CSR.scala:920:60, :923:28] wire _io_decode_1_read_illegal_T_1 = ~csr_exists_1; // @[CSR.scala:899:111, :924:7] wire _io_decode_1_read_illegal_T_2 = _io_decode_1_read_illegal_T | _io_decode_1_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_1_read_illegal_T_4 = addr_1 == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_1_read_illegal_T_5 = _io_decode_1_read_illegal_T_3 | _io_decode_1_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_1_read_illegal_T_6 = ~allow_sfence_vma_1; // @[CSR.scala:907:70, :925:59] wire _io_decode_1_read_illegal_T_7 = _io_decode_1_read_illegal_T_5 & _io_decode_1_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}] wire _io_decode_1_read_illegal_T_8 = _io_decode_1_read_illegal_T_2 | _io_decode_1_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56] wire _io_decode_1_read_illegal_T_9 = ~allow_counter_1; // @[CSR.scala:913:91, :926:21] wire _io_decode_1_read_illegal_T_10 = is_counter_1 & _io_decode_1_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}] wire _io_decode_1_read_illegal_T_11 = _io_decode_1_read_illegal_T_8 | _io_decode_1_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18] wire [11:0] io_decode_1_read_illegal_invInputs = ~io_decode_1_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_1_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_1_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_1_read_illegal_T_12 = io_decode_1_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_1_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_1_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_1_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_1_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_1_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_1_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_1_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_1_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_1_read_illegal_andMatrixOutputs_lo_lo = {io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_1_read_illegal_andMatrixOutputs_lo_hi = {io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_1_read_illegal_andMatrixOutputs_lo = {io_decode_1_read_illegal_andMatrixOutputs_lo_hi, io_decode_1_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_1_read_illegal_andMatrixOutputs_hi_lo = {io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_1_read_illegal_andMatrixOutputs_hi_hi = {io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_1_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_1_read_illegal_andMatrixOutputs_hi = {io_decode_1_read_illegal_andMatrixOutputs_hi_hi, io_decode_1_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_1_read_illegal_andMatrixOutputs_T = {io_decode_1_read_illegal_andMatrixOutputs_hi, io_decode_1_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_1_read_illegal_andMatrixOutputs_0_2 = &_io_decode_1_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_1_read_illegal_orMatrixOutputs = io_decode_1_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_1_read_illegal_invMatrixOutputs = io_decode_1_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_1_read_illegal_plaOutput = io_decode_1_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_1_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_1_read_illegal_T_14 = _io_decode_1_read_illegal_T_12 & _io_decode_1_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_1_read_illegal_T_15 = _io_decode_1_read_illegal_T_11 | _io_decode_1_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire _io_decode_1_read_illegal_T_18 = _io_decode_1_read_illegal_T_15; // @[CSR.scala:926:36, :927:56] wire [11:0] io_decode_1_read_illegal_invInputs_1 = ~io_decode_1_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] wire _io_decode_1_read_illegal_T_19 = io_decode_1_fp_csr_0 & io_decode_1_fp_illegal_0; // @[CSR.scala:377:7, :929:21] assign _io_decode_1_read_illegal_T_20 = _io_decode_1_read_illegal_T_18 | _io_decode_1_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21] assign io_decode_1_read_illegal_0 = _io_decode_1_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_1_write_illegal_T = addr_1[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_1_write_illegal_T_1 = &_io_decode_1_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_1_write_illegal_0 = _io_decode_1_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_1_write_flush_addr_m = {_io_decode_1_write_illegal_T, addr_1[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_1_write_flush_T = io_decode_1_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_1_write_flush_T_1 = io_decode_1_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_1_write_flush_T_2 = _io_decode_1_write_flush_T & _io_decode_1_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_1_write_flush_T_3 = ~_io_decode_1_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_1_write_flush_0 = _io_decode_1_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_1_system_illegal_T = ~csr_addr_legal_1; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_1_system_illegal_T_1 = ~is_hlsv_1; // @[CSR.scala:903:82, :935:49] wire _io_decode_1_system_illegal_T_2 = _io_decode_1_system_illegal_T & _io_decode_1_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_1_system_illegal_T_3 = ~allow_wfi_1; // @[CSR.scala:906:71, :936:17] wire _io_decode_1_system_illegal_T_4 = is_wfi_1 & _io_decode_1_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}] wire _io_decode_1_system_illegal_T_5 = _io_decode_1_system_illegal_T_2 | _io_decode_1_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14] wire _io_decode_1_system_illegal_T_6 = ~allow_sret_1; // @[CSR.scala:910:72, :937:17] wire _io_decode_1_system_illegal_T_7 = is_ret_1 & _io_decode_1_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}] wire _io_decode_1_system_illegal_T_8 = _io_decode_1_system_illegal_T_5 | _io_decode_1_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14] wire _io_decode_1_system_illegal_T_9 = addr_1[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_1_system_illegal_T_10 = is_ret_1 & _io_decode_1_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_1_system_illegal_T_11 = addr_1[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_1_system_illegal_T_12 = _io_decode_1_system_illegal_T_10 & _io_decode_1_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_1_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_1_system_illegal_T_14 = _io_decode_1_system_illegal_T_12 & _io_decode_1_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_1_system_illegal_T_15 = _io_decode_1_system_illegal_T_8 | _io_decode_1_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_1_system_illegal_T_16 = is_sfence_1 | is_hfence_gvma_1; // @[CSR.scala:903:82, :939:18] wire _io_decode_1_system_illegal_T_17 = ~allow_sfence_vma_1; // @[CSR.scala:907:70, :925:59, :939:40] wire _io_decode_1_system_illegal_T_18 = _io_decode_1_system_illegal_T_16 & _io_decode_1_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}] wire _io_decode_1_system_illegal_T_19 = _io_decode_1_system_illegal_T_15 | _io_decode_1_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37] wire _io_decode_1_system_illegal_T_22 = _io_decode_1_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_1_system_illegal_T_25 = _io_decode_1_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_1_system_illegal_0 = _io_decode_1_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_1_virtual_access_illegal_T = reg_mstatus_v & csr_exists_1; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_1_virtual_access_illegal_T_2 = _io_decode_1_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_1_virtual_access_illegal_T_4 = _io_decode_1_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_1_virtual_access_illegal_T_5 = is_counter_1 & _io_decode_1_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_1_virtual_access_illegal_T_7 = _io_decode_1_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_1_virtual_access_illegal_T_8 = ~_io_decode_1_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_1_virtual_access_illegal_T_10 = ~_io_decode_1_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}] wire _io_decode_1_virtual_access_illegal_T_12 = _io_decode_1_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_1_virtual_access_illegal_T_13 = ~_io_decode_1_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_1_virtual_access_illegal_T_14 = _io_decode_1_virtual_access_illegal_T_10 & _io_decode_1_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}] wire _io_decode_1_virtual_access_illegal_T_15 = _io_decode_1_virtual_access_illegal_T_8 | _io_decode_1_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}] wire _io_decode_1_virtual_access_illegal_T_16 = _io_decode_1_virtual_access_illegal_T_5 & _io_decode_1_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_1_virtual_access_illegal_T_17 = _io_decode_1_virtual_access_illegal_T_2 | _io_decode_1_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_1_virtual_access_illegal_T_19 = _io_decode_1_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_1_virtual_access_illegal_T_21 = ~_io_decode_1_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}] wire _io_decode_1_virtual_access_illegal_T_22 = _io_decode_1_virtual_access_illegal_T_19 & _io_decode_1_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}] wire _io_decode_1_virtual_access_illegal_T_23 = _io_decode_1_virtual_access_illegal_T_17 | _io_decode_1_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34] wire _io_decode_1_virtual_access_illegal_T_28 = _io_decode_1_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_1_virtual_access_illegal_T_26 = _io_decode_1_virtual_access_illegal_T_24 & _io_decode_1_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}] assign _io_decode_1_virtual_access_illegal_T_29 = _io_decode_1_virtual_access_illegal_T & _io_decode_1_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_1_virtual_access_illegal_0 = _io_decode_1_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_1_virtual_system_illegal_T = is_hfence_vvma_1 | is_hfence_gvma_1; // @[CSR.scala:903:82, :950:22] wire _io_decode_1_virtual_system_illegal_T_1 = _io_decode_1_virtual_system_illegal_T | is_hlsv_1; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_1_virtual_system_illegal_T_3 = ~_io_decode_1_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}] wire _io_decode_1_virtual_system_illegal_T_6 = _io_decode_1_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}] wire _io_decode_1_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41] wire _io_decode_1_virtual_system_illegal_T_7 = is_wfi_1 & _io_decode_1_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}] wire _io_decode_1_virtual_system_illegal_T_8 = _io_decode_1_virtual_system_illegal_T_1 | _io_decode_1_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14] wire _io_decode_1_virtual_system_illegal_T_10 = _io_decode_1_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_1_virtual_system_illegal_T_11 = is_ret_1 & _io_decode_1_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_1_virtual_system_illegal_T_13 = ~_io_decode_1_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}] wire _io_decode_1_virtual_system_illegal_T_14 = _io_decode_1_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}] wire _io_decode_1_virtual_system_illegal_T_15 = _io_decode_1_virtual_system_illegal_T_11 & _io_decode_1_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}] wire _io_decode_1_virtual_system_illegal_T_16 = _io_decode_1_virtual_system_illegal_T_8 | _io_decode_1_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44] wire _io_decode_1_virtual_system_illegal_T_18 = ~_io_decode_1_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}] wire _io_decode_1_virtual_system_illegal_T_19 = _io_decode_1_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}] wire _io_decode_1_virtual_system_illegal_T_20 = is_sfence_1 & _io_decode_1_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}] wire _io_decode_1_virtual_system_illegal_T_21 = _io_decode_1_virtual_system_illegal_T_16 | _io_decode_1_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17] assign _io_decode_1_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_1_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_1_virtual_system_illegal_0 = _io_decode_1_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire [11:0] addr_2 = io_decode_2_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_2_fp_csr_plaInput = addr_2; // @[pla.scala:77:22] wire [11:0] io_decode_2_vector_csr_plaInput = addr_2; // @[pla.scala:77:22] wire [11:0] io_decode_2_read_illegal_plaInput = addr_2; // @[pla.scala:77:22] wire [11:0] io_decode_2_read_illegal_plaInput_1 = addr_2; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_3 = ~decoded_plaInput_3; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_3; // @[pla.scala:120:37] wire [8:0] decoded_3; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_invInputs_3[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_invInputs_3[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_invInputs_3[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_invInputs_3[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_invInputs_3[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_invInputs_3[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_invInputs_3[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_invInputs_3[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_invInputs_3[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_invInputs_3[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_invInputs_3[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_invInputs_3[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_invInputs_3[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_invInputs_3[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_invInputs_3[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_invInputs_3[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_invInputs_3[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_invInputs_3[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_invInputs_3[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_invInputs_3[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_invInputs_3[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_invInputs_3[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12_3 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_invInputs_3[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_invInputs_3[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_invInputs_3[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_invInputs_3[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_invInputs_3[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_invInputs_3[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14_3 = decoded_invInputs_3[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15_3 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_invInputs_3[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16_3 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_invInputs_3[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_18 = {decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_18 = {decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_18 = {decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_18 = {decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_18 = {decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_18 = {decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_21 = {decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2_3 = &_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_27 = decoded_andMatrixOutputs_6_2_3; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_plaInput_3[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_19 = {decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_19 = {decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_19 = {decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_19 = {decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_19 = {decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_19 = {decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_22 = {decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_3 = &_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_26 = decoded_andMatrixOutputs_4_2_3; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_plaInput_3[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_plaInput_3[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_plaInput_3[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_plaInput_3[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13_3 = decoded_plaInput_3[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_plaInput_3[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_20 = {decoded_andMatrixOutputs_andMatrixInput_8_20, decoded_andMatrixOutputs_andMatrixInput_9_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_20 = {decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_20 = {decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_20 = {decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_20 = {decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_20 = {decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_23 = {decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_3 = &_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_plaInput_3[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_plaInput_3[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_21 = {decoded_andMatrixOutputs_andMatrixInput_8_21, decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_andMatrixOutputs_andMatrixInput_5_21, decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_21 = {decoded_andMatrixOutputs_lo_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_21 = {decoded_andMatrixOutputs_lo_hi_21, decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_21 = {decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_21 = {decoded_andMatrixOutputs_hi_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_21 = {decoded_andMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_24 = {decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_3 = &_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_22 = decoded_andMatrixOutputs_1_2_3; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_plaInput_3[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_invInputs_3[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_invInputs_3[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_plaInput_3[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_plaInput_3[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_plaInput_3[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_invInputs_3[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_invInputs_3[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_invInputs_3[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_plaInput_3[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_15_3, decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_13_3, decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_22 = {decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_11_11, decoded_andMatrixOutputs_andMatrixInput_12_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_22 = {decoded_andMatrixOutputs_lo_hi_hi_22, decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_22 = {decoded_andMatrixOutputs_lo_hi_22, decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_7_22, decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_22, decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_22 = {decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_22 = {decoded_andMatrixOutputs_hi_hi_hi_22, decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_22 = {decoded_andMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_25 = {decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_3 = &_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_21 = decoded_andMatrixOutputs_0_2_3; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_plaInput_3[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_23 = {decoded_andMatrixOutputs_andMatrixInput_8_23, decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_andMatrixOutputs_andMatrixInput_5_23, decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_23 = {decoded_andMatrixOutputs_lo_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_23 = {decoded_andMatrixOutputs_lo_hi_23, decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_23 = {decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_23 = {decoded_andMatrixOutputs_hi_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_23 = {decoded_andMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_26 = {decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_3 = &_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_23 = decoded_andMatrixOutputs_5_2_3; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_plaInput_3[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_27 = {decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_3 = &_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_24 = {decoded_andMatrixOutputs_3_2_3, decoded_andMatrixOutputs_2_2_3}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_25 = |_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi_3 = {_decoded_orMatrixOutputs_T_21, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo_3 = {decoded_orMatrixOutputs_lo_hi_3, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo_3 = {_decoded_orMatrixOutputs_T_23, _decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_3 = {_decoded_orMatrixOutputs_T_27, _decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_3 = {decoded_orMatrixOutputs_hi_hi_hi_3, _decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_3 = {decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_3 = {decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_27 = decoded_orMatrixOutputs_3[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_28 = decoded_orMatrixOutputs_3[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_29 = decoded_orMatrixOutputs_3[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_30 = decoded_orMatrixOutputs_3[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_31 = decoded_orMatrixOutputs_3[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_32 = decoded_orMatrixOutputs_3[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_33 = decoded_orMatrixOutputs_3[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_34 = decoded_orMatrixOutputs_3[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_35 = decoded_orMatrixOutputs_3[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_3 = {_decoded_invMatrixOutputs_T_28, _decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_3 = {_decoded_invMatrixOutputs_T_30, _decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_3 = {decoded_invMatrixOutputs_lo_hi_3, decoded_invMatrixOutputs_lo_lo_3}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_3 = {_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_3 = {_decoded_invMatrixOutputs_T_35, _decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_3 = {decoded_invMatrixOutputs_hi_hi_hi_3, _decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_3 = {decoded_invMatrixOutputs_hi_hi_3, decoded_invMatrixOutputs_hi_lo_3}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_3 = {decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3}; // @[pla.scala:120:37] assign decoded_3 = decoded_invMatrixOutputs_3; // @[pla.scala:81:23, :120:37] wire is_break_2 = decoded_3[7]; // @[pla.scala:81:23] wire is_ret_2 = decoded_3[6]; // @[pla.scala:81:23] wire is_wfi_2 = decoded_3[4]; // @[pla.scala:81:23] wire is_sfence_2 = decoded_3[3]; // @[pla.scala:81:23] wire is_hfence_vvma_2 = decoded_3[2]; // @[pla.scala:81:23] wire is_hfence_gvma_2 = decoded_3[1]; // @[pla.scala:81:23] wire is_hlsv_2 = decoded_3[0]; // @[pla.scala:81:23] wire _is_counter_T_12 = addr_2 > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_13 = addr_2 < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_14 = _is_counter_T_12 & _is_counter_T_13; // @[package.scala:213:{47,55,60}] wire _is_counter_T_15 = addr_2 > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_16 = addr_2 < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_17 = _is_counter_T_15 & _is_counter_T_16; // @[package.scala:213:{47,55,60}] wire is_counter_2 = _is_counter_T_14 | _is_counter_T_17; // @[package.scala:213:55] wire _allow_wfi_T_15 = _allow_wfi_T_14; // @[CSR.scala:906:{42,61}] wire _allow_wfi_T_16 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74] wire _allow_wfi_T_20 = _allow_wfi_T_16; // @[CSR.scala:906:{74,90}] wire _allow_wfi_T_17 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire allow_wfi_2 = _allow_wfi_T_15 | _allow_wfi_T_20; // @[CSR.scala:906:{42,71,90}] wire _allow_sfence_vma_T_9 = _allow_sfence_vma_T_8; // @[CSR.scala:907:{41,60}] wire _allow_sfence_vma_T_11 = ~_allow_sfence_vma_T_10; // @[CSR.scala:907:{73,77}] wire allow_sfence_vma_2 = _allow_sfence_vma_T_9 | _allow_sfence_vma_T_11; // @[CSR.scala:907:{41,70,73}] wire _allow_hfence_vvma_T_6 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_7 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88] wire _allow_hfence_vvma_T_8 = _allow_hfence_vvma_T_6 & _allow_hfence_vvma_T_7; // @[CSR.scala:908:{53,68,88}] wire _allow_hlsv_T_8 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_9 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81] wire _allow_hlsv_T_10 = _allow_hlsv_T_9; // @[CSR.scala:909:{81,92}] wire _allow_hlsv_T_11 = _allow_hlsv_T_8 & _allow_hlsv_T_10; // @[CSR.scala:909:{46,61,92}] wire _allow_sret_T_9 = _allow_sret_T_8; // @[CSR.scala:910:{43,62}] wire _allow_sret_T_11 = ~_allow_sret_T_10; // @[CSR.scala:910:{75,79}] wire allow_sret_2 = _allow_sret_T_9 | _allow_sret_T_11; // @[CSR.scala:910:{43,72,75}] wire [4:0] counter_addr_2 = addr_2[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_17 = {27'h0, counter_addr_2}; // @[CSR.scala:911:28, :912:70] wire [31:0] _GEN_18 = read_mcounteren >> _GEN_17; // @[CSR.scala:532:14, :912:70] wire [31:0] _allow_counter_T_35; // @[CSR.scala:912:70] assign _allow_counter_T_35 = _GEN_18; // @[CSR.scala:912:70] wire [31:0] _io_decode_2_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_2_virtual_access_illegal_T_3 = _GEN_18; // @[CSR.scala:912:70, :945:36] wire _allow_counter_T_36 = _allow_counter_T_35[0]; // @[CSR.scala:912:70] wire _allow_counter_T_37 = _allow_counter_T_34 | _allow_counter_T_36; // @[CSR.scala:912:{42,52,70}] wire _allow_counter_T_39 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46] wire _allow_counter_T_40 = _allow_counter_T_39; // @[CSR.scala:913:{27,46}] wire [31:0] _GEN_19 = read_scounteren >> _GEN_17; // @[CSR.scala:536:14, :912:70, :913:75] wire [31:0] _allow_counter_T_41; // @[CSR.scala:913:75] assign _allow_counter_T_41 = _GEN_19; // @[CSR.scala:913:75] wire [31:0] _io_decode_2_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_2_virtual_access_illegal_T_11 = _GEN_19; // @[CSR.scala:913:75, :945:128] wire _allow_counter_T_42 = _allow_counter_T_41[0]; // @[CSR.scala:913:75] wire _allow_counter_T_43 = _allow_counter_T_40 | _allow_counter_T_42; // @[CSR.scala:913:{27,57,75}] wire _allow_counter_T_44 = _allow_counter_T_37 & _allow_counter_T_43; // @[CSR.scala:912:{52,86}, :913:57] wire allow_counter_2 = _allow_counter_T_44; // @[CSR.scala:912:86, :913:91] wire _allow_counter_T_46 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire [31:0] _GEN_20 = 32'h0 >> _GEN_17; // @[CSR.scala:912:70, :914:63] wire [31:0] _allow_counter_T_48; // @[CSR.scala:914:63] assign _allow_counter_T_48 = _GEN_20; // @[CSR.scala:914:63] wire [31:0] _io_decode_2_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_2_virtual_access_illegal_T_6 = _GEN_20; // @[CSR.scala:914:63, :945:71] wire _allow_counter_T_49 = _allow_counter_T_48[0]; // @[CSR.scala:914:63] wire _io_decode_2_fp_illegal_T_3 = _io_decode_2_fp_illegal_T; // @[CSR.scala:915:{39,47}] assign _io_decode_2_fp_illegal_T_6 = _io_decode_2_fp_illegal_T_3; // @[CSR.scala:915:{47,91}] assign io_decode_2_fp_illegal_0 = _io_decode_2_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91] wire _io_decode_2_vector_illegal_T_2 = reg_mstatus_v & _io_decode_2_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}] wire [11:0] io_decode_2_fp_csr_invInputs = ~io_decode_2_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_2_fp_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_2_fp_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_2_fp_csr_T = io_decode_2_fp_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_2_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_2_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_2_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_2_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_2_fp_csr_andMatrixOutputs_lo = {io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_2_fp_csr_andMatrixOutputs_hi = {io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_2_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _io_decode_2_fp_csr_andMatrixOutputs_T = {io_decode_2_fp_csr_andMatrixOutputs_hi, io_decode_2_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_2_fp_csr_andMatrixOutputs_0_2 = &_io_decode_2_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_2_fp_csr_orMatrixOutputs = io_decode_2_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_2_fp_csr_invMatrixOutputs = io_decode_2_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_2_fp_csr_plaOutput = io_decode_2_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_2_fp_csr_0 = _io_decode_2_fp_csr_T; // @[Decode.scala:55:116] wire [11:0] io_decode_2_vector_csr_invInputs = ~io_decode_2_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire [1:0] _csr_addr_legal_T_18 = addr_2[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_24 = addr_2[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_2_virtual_access_illegal_T_1 = addr_2[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_2_virtual_access_illegal_T_18 = addr_2[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_2_virtual_system_illegal_T_9 = addr_2[9:8]; // @[CSR.scala:190:36, :897:27] wire _csr_addr_legal_T_19 = reg_mstatus_prv >= _csr_addr_legal_T_18; // @[CSR.scala:190:36, :395:28, :920:42] wire csr_addr_legal_2 = _csr_addr_legal_T_19; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_20 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_25 = _csr_addr_legal_T_24 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T_596 = addr_2 == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_597 = addr_2 == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_598 = addr_2 == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_599 = addr_2 == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_600 = addr_2 == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_601 = addr_2 == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_602 = addr_2 == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_603 = addr_2 == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_604 = addr_2 == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_605 = addr_2 == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_606 = addr_2 == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_607 = addr_2 == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_608 = addr_2 == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_609 = addr_2 == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_610 = addr_2 == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_611 = addr_2 == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_612 = addr_2 == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_613 = addr_2 == 12'h1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_614 = addr_2 == 12'h2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_615 = addr_2 == 12'h3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_616 = addr_2 == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_617 = addr_2 == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_618 = addr_2 == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_619 = addr_2 == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_620 = addr_2 == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_621 = addr_2 == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_622 = addr_2 == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_623 = addr_2 == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_624 = addr_2 == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_625 = addr_2 == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_626 = addr_2 == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_627 = addr_2 == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_628 = addr_2 == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_629 = addr_2 == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_630 = addr_2 == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_631 = addr_2 == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_632 = addr_2 == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_633 = addr_2 == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_634 = addr_2 == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_635 = addr_2 == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_636 = addr_2 == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_637 = addr_2 == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_638 = addr_2 == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_639 = addr_2 == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_640 = addr_2 == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_641 = addr_2 == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_642 = addr_2 == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_643 = addr_2 == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_644 = addr_2 == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_645 = addr_2 == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_646 = addr_2 == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_647 = addr_2 == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_648 = addr_2 == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_649 = addr_2 == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_650 = addr_2 == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_651 = addr_2 == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_652 = addr_2 == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_653 = addr_2 == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_654 = addr_2 == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_655 = addr_2 == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_656 = addr_2 == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_657 = addr_2 == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_658 = addr_2 == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_659 = addr_2 == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_660 = addr_2 == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_661 = addr_2 == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_662 = addr_2 == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_663 = addr_2 == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_664 = addr_2 == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_665 = addr_2 == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_666 = addr_2 == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_667 = addr_2 == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_668 = addr_2 == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_669 = addr_2 == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_670 = addr_2 == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_671 = addr_2 == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_672 = addr_2 == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_673 = addr_2 == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_674 = addr_2 == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_675 = addr_2 == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_676 = addr_2 == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_677 = addr_2 == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_678 = addr_2 == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_679 = addr_2 == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_680 = addr_2 == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_681 = addr_2 == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_682 = addr_2 == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_683 = addr_2 == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_684 = addr_2 == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_685 = addr_2 == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_686 = addr_2 == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_687 = addr_2 == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_688 = addr_2 == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_689 = addr_2 == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_690 = addr_2 == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_691 = addr_2 == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_692 = addr_2 == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_693 = addr_2 == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_694 = addr_2 == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_695 = addr_2 == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_696 = addr_2 == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_697 = addr_2 == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_698 = addr_2 == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_699 = addr_2 == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_700 = addr_2 == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_701 = addr_2 == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_702 = addr_2 == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_703 = addr_2 == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_704 = addr_2 == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_705 = addr_2 == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_706 = addr_2 == 12'h306; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_707 = addr_2 == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_708 = addr_2 == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_709 = addr_2 == 12'h30A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_710 = addr_2 == 12'h100; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_711 = addr_2 == 12'h144; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_712 = addr_2 == 12'h104; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_713 = addr_2 == 12'h140; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_714 = addr_2 == 12'h142; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_715 = addr_2 == 12'h143; // @[CSR.scala:897:27, :899:93] wire _GEN_21 = addr_2 == 12'h180; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_716; // @[CSR.scala:899:93] assign _csr_exists_T_716 = _GEN_21; // @[CSR.scala:899:93] wire _io_decode_2_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_2_read_illegal_T_3 = _GEN_21; // @[CSR.scala:899:93, :925:14] wire _io_decode_2_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_2_virtual_access_illegal_T_24 = _GEN_21; // @[CSR.scala:899:93, :947:12] wire _csr_exists_T_717 = addr_2 == 12'h141; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_718 = addr_2 == 12'h105; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_719 = addr_2 == 12'h106; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_720 = addr_2 == 12'h303; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_721 = addr_2 == 12'h302; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_722 = addr_2 == 12'h10A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_723 = addr_2 == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_724 = addr_2 == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_725 = addr_2 == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_726 = addr_2 == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_727 = addr_2 == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_728 = addr_2 == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_729 = addr_2 == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_730 = addr_2 == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_731 = addr_2 == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_732 = addr_2 == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_733 = addr_2 == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_734 = addr_2 == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_735 = addr_2 == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_736 = addr_2 == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_737 = addr_2 == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_738 = addr_2 == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_739 = addr_2 == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_740 = addr_2 == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_741 = addr_2 == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_742 = addr_2 == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_743 = addr_2 == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_744 = addr_2 == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_745 = addr_2 == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_746 = _csr_exists_T_596 | _csr_exists_T_597; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_747 = _csr_exists_T_746 | _csr_exists_T_598; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_748 = _csr_exists_T_747 | _csr_exists_T_599; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_749 = _csr_exists_T_748 | _csr_exists_T_600; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_750 = _csr_exists_T_749 | _csr_exists_T_601; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_751 = _csr_exists_T_750 | _csr_exists_T_602; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_752 = _csr_exists_T_751 | _csr_exists_T_603; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_753 = _csr_exists_T_752 | _csr_exists_T_604; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_754 = _csr_exists_T_753 | _csr_exists_T_605; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_755 = _csr_exists_T_754 | _csr_exists_T_606; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_756 = _csr_exists_T_755 | _csr_exists_T_607; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_757 = _csr_exists_T_756 | _csr_exists_T_608; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_758 = _csr_exists_T_757 | _csr_exists_T_609; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_759 = _csr_exists_T_758 | _csr_exists_T_610; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_760 = _csr_exists_T_759 | _csr_exists_T_611; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_761 = _csr_exists_T_760 | _csr_exists_T_612; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_762 = _csr_exists_T_761 | _csr_exists_T_613; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_763 = _csr_exists_T_762 | _csr_exists_T_614; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_764 = _csr_exists_T_763 | _csr_exists_T_615; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_765 = _csr_exists_T_764 | _csr_exists_T_616; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_766 = _csr_exists_T_765 | _csr_exists_T_617; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_767 = _csr_exists_T_766 | _csr_exists_T_618; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_768 = _csr_exists_T_767 | _csr_exists_T_619; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_769 = _csr_exists_T_768 | _csr_exists_T_620; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_770 = _csr_exists_T_769 | _csr_exists_T_621; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_771 = _csr_exists_T_770 | _csr_exists_T_622; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_772 = _csr_exists_T_771 | _csr_exists_T_623; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_773 = _csr_exists_T_772 | _csr_exists_T_624; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_774 = _csr_exists_T_773 | _csr_exists_T_625; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_775 = _csr_exists_T_774 | _csr_exists_T_626; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_776 = _csr_exists_T_775 | _csr_exists_T_627; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_777 = _csr_exists_T_776 | _csr_exists_T_628; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_778 = _csr_exists_T_777 | _csr_exists_T_629; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_779 = _csr_exists_T_778 | _csr_exists_T_630; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_780 = _csr_exists_T_779 | _csr_exists_T_631; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_781 = _csr_exists_T_780 | _csr_exists_T_632; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_782 = _csr_exists_T_781 | _csr_exists_T_633; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_783 = _csr_exists_T_782 | _csr_exists_T_634; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_784 = _csr_exists_T_783 | _csr_exists_T_635; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_785 = _csr_exists_T_784 | _csr_exists_T_636; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_786 = _csr_exists_T_785 | _csr_exists_T_637; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_787 = _csr_exists_T_786 | _csr_exists_T_638; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_788 = _csr_exists_T_787 | _csr_exists_T_639; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_789 = _csr_exists_T_788 | _csr_exists_T_640; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_790 = _csr_exists_T_789 | _csr_exists_T_641; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_791 = _csr_exists_T_790 | _csr_exists_T_642; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_792 = _csr_exists_T_791 | _csr_exists_T_643; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_793 = _csr_exists_T_792 | _csr_exists_T_644; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_794 = _csr_exists_T_793 | _csr_exists_T_645; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_795 = _csr_exists_T_794 | _csr_exists_T_646; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_796 = _csr_exists_T_795 | _csr_exists_T_647; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_797 = _csr_exists_T_796 | _csr_exists_T_648; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_798 = _csr_exists_T_797 | _csr_exists_T_649; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_799 = _csr_exists_T_798 | _csr_exists_T_650; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_800 = _csr_exists_T_799 | _csr_exists_T_651; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_801 = _csr_exists_T_800 | _csr_exists_T_652; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_802 = _csr_exists_T_801 | _csr_exists_T_653; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_803 = _csr_exists_T_802 | _csr_exists_T_654; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_804 = _csr_exists_T_803 | _csr_exists_T_655; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_805 = _csr_exists_T_804 | _csr_exists_T_656; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_806 = _csr_exists_T_805 | _csr_exists_T_657; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_807 = _csr_exists_T_806 | _csr_exists_T_658; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_808 = _csr_exists_T_807 | _csr_exists_T_659; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_809 = _csr_exists_T_808 | _csr_exists_T_660; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_810 = _csr_exists_T_809 | _csr_exists_T_661; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_811 = _csr_exists_T_810 | _csr_exists_T_662; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_812 = _csr_exists_T_811 | _csr_exists_T_663; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_813 = _csr_exists_T_812 | _csr_exists_T_664; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_814 = _csr_exists_T_813 | _csr_exists_T_665; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_815 = _csr_exists_T_814 | _csr_exists_T_666; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_816 = _csr_exists_T_815 | _csr_exists_T_667; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_817 = _csr_exists_T_816 | _csr_exists_T_668; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_818 = _csr_exists_T_817 | _csr_exists_T_669; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_819 = _csr_exists_T_818 | _csr_exists_T_670; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_820 = _csr_exists_T_819 | _csr_exists_T_671; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_821 = _csr_exists_T_820 | _csr_exists_T_672; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_822 = _csr_exists_T_821 | _csr_exists_T_673; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_823 = _csr_exists_T_822 | _csr_exists_T_674; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_824 = _csr_exists_T_823 | _csr_exists_T_675; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_825 = _csr_exists_T_824 | _csr_exists_T_676; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_826 = _csr_exists_T_825 | _csr_exists_T_677; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_827 = _csr_exists_T_826 | _csr_exists_T_678; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_828 = _csr_exists_T_827 | _csr_exists_T_679; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_829 = _csr_exists_T_828 | _csr_exists_T_680; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_830 = _csr_exists_T_829 | _csr_exists_T_681; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_831 = _csr_exists_T_830 | _csr_exists_T_682; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_832 = _csr_exists_T_831 | _csr_exists_T_683; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_833 = _csr_exists_T_832 | _csr_exists_T_684; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_834 = _csr_exists_T_833 | _csr_exists_T_685; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_835 = _csr_exists_T_834 | _csr_exists_T_686; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_836 = _csr_exists_T_835 | _csr_exists_T_687; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_837 = _csr_exists_T_836 | _csr_exists_T_688; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_838 = _csr_exists_T_837 | _csr_exists_T_689; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_839 = _csr_exists_T_838 | _csr_exists_T_690; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_840 = _csr_exists_T_839 | _csr_exists_T_691; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_841 = _csr_exists_T_840 | _csr_exists_T_692; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_842 = _csr_exists_T_841 | _csr_exists_T_693; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_843 = _csr_exists_T_842 | _csr_exists_T_694; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_844 = _csr_exists_T_843 | _csr_exists_T_695; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_845 = _csr_exists_T_844 | _csr_exists_T_696; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_846 = _csr_exists_T_845 | _csr_exists_T_697; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_847 = _csr_exists_T_846 | _csr_exists_T_698; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_848 = _csr_exists_T_847 | _csr_exists_T_699; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_849 = _csr_exists_T_848 | _csr_exists_T_700; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_850 = _csr_exists_T_849 | _csr_exists_T_701; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_851 = _csr_exists_T_850 | _csr_exists_T_702; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_852 = _csr_exists_T_851 | _csr_exists_T_703; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_853 = _csr_exists_T_852 | _csr_exists_T_704; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_854 = _csr_exists_T_853 | _csr_exists_T_705; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_855 = _csr_exists_T_854 | _csr_exists_T_706; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_856 = _csr_exists_T_855 | _csr_exists_T_707; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_857 = _csr_exists_T_856 | _csr_exists_T_708; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_858 = _csr_exists_T_857 | _csr_exists_T_709; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_859 = _csr_exists_T_858 | _csr_exists_T_710; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_860 = _csr_exists_T_859 | _csr_exists_T_711; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_861 = _csr_exists_T_860 | _csr_exists_T_712; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_862 = _csr_exists_T_861 | _csr_exists_T_713; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_863 = _csr_exists_T_862 | _csr_exists_T_714; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_864 = _csr_exists_T_863 | _csr_exists_T_715; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_865 = _csr_exists_T_864 | _csr_exists_T_716; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_866 = _csr_exists_T_865 | _csr_exists_T_717; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_867 = _csr_exists_T_866 | _csr_exists_T_718; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_868 = _csr_exists_T_867 | _csr_exists_T_719; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_869 = _csr_exists_T_868 | _csr_exists_T_720; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_870 = _csr_exists_T_869 | _csr_exists_T_721; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_871 = _csr_exists_T_870 | _csr_exists_T_722; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_872 = _csr_exists_T_871 | _csr_exists_T_723; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_873 = _csr_exists_T_872 | _csr_exists_T_724; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_874 = _csr_exists_T_873 | _csr_exists_T_725; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_875 = _csr_exists_T_874 | _csr_exists_T_726; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_876 = _csr_exists_T_875 | _csr_exists_T_727; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_877 = _csr_exists_T_876 | _csr_exists_T_728; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_878 = _csr_exists_T_877 | _csr_exists_T_729; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_879 = _csr_exists_T_878 | _csr_exists_T_730; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_880 = _csr_exists_T_879 | _csr_exists_T_731; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_881 = _csr_exists_T_880 | _csr_exists_T_732; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_882 = _csr_exists_T_881 | _csr_exists_T_733; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_883 = _csr_exists_T_882 | _csr_exists_T_734; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_884 = _csr_exists_T_883 | _csr_exists_T_735; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_885 = _csr_exists_T_884 | _csr_exists_T_736; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_886 = _csr_exists_T_885 | _csr_exists_T_737; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_887 = _csr_exists_T_886 | _csr_exists_T_738; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_888 = _csr_exists_T_887 | _csr_exists_T_739; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_889 = _csr_exists_T_888 | _csr_exists_T_740; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_890 = _csr_exists_T_889 | _csr_exists_T_741; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_891 = _csr_exists_T_890 | _csr_exists_T_742; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_892 = _csr_exists_T_891 | _csr_exists_T_743; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_893 = _csr_exists_T_892 | _csr_exists_T_744; // @[CSR.scala:899:{93,111}] wire csr_exists_2 = _csr_exists_T_893 | _csr_exists_T_745; // @[CSR.scala:899:{93,111}] wire _io_decode_2_read_illegal_T = ~csr_addr_legal_2; // @[CSR.scala:920:60, :923:28] wire _io_decode_2_read_illegal_T_1 = ~csr_exists_2; // @[CSR.scala:899:111, :924:7] wire _io_decode_2_read_illegal_T_2 = _io_decode_2_read_illegal_T | _io_decode_2_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_2_read_illegal_T_4 = addr_2 == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_2_read_illegal_T_5 = _io_decode_2_read_illegal_T_3 | _io_decode_2_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_2_read_illegal_T_6 = ~allow_sfence_vma_2; // @[CSR.scala:907:70, :925:59] wire _io_decode_2_read_illegal_T_7 = _io_decode_2_read_illegal_T_5 & _io_decode_2_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}] wire _io_decode_2_read_illegal_T_8 = _io_decode_2_read_illegal_T_2 | _io_decode_2_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56] wire _io_decode_2_read_illegal_T_9 = ~allow_counter_2; // @[CSR.scala:913:91, :926:21] wire _io_decode_2_read_illegal_T_10 = is_counter_2 & _io_decode_2_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}] wire _io_decode_2_read_illegal_T_11 = _io_decode_2_read_illegal_T_8 | _io_decode_2_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18] wire [11:0] io_decode_2_read_illegal_invInputs = ~io_decode_2_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_2_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_2_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_2_read_illegal_T_12 = io_decode_2_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_2_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_2_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_2_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_2_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_2_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_2_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_2_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_2_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_2_read_illegal_andMatrixOutputs_lo_lo = {io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_2_read_illegal_andMatrixOutputs_lo_hi = {io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_2_read_illegal_andMatrixOutputs_lo = {io_decode_2_read_illegal_andMatrixOutputs_lo_hi, io_decode_2_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_2_read_illegal_andMatrixOutputs_hi_lo = {io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_2_read_illegal_andMatrixOutputs_hi_hi = {io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_2_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_2_read_illegal_andMatrixOutputs_hi = {io_decode_2_read_illegal_andMatrixOutputs_hi_hi, io_decode_2_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_2_read_illegal_andMatrixOutputs_T = {io_decode_2_read_illegal_andMatrixOutputs_hi, io_decode_2_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_2_read_illegal_andMatrixOutputs_0_2 = &_io_decode_2_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_2_read_illegal_orMatrixOutputs = io_decode_2_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_2_read_illegal_invMatrixOutputs = io_decode_2_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_2_read_illegal_plaOutput = io_decode_2_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_2_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_2_read_illegal_T_14 = _io_decode_2_read_illegal_T_12 & _io_decode_2_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_2_read_illegal_T_15 = _io_decode_2_read_illegal_T_11 | _io_decode_2_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire _io_decode_2_read_illegal_T_18 = _io_decode_2_read_illegal_T_15; // @[CSR.scala:926:36, :927:56] wire [11:0] io_decode_2_read_illegal_invInputs_1 = ~io_decode_2_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] wire _io_decode_2_read_illegal_T_19 = io_decode_2_fp_csr_0 & io_decode_2_fp_illegal_0; // @[CSR.scala:377:7, :929:21] assign _io_decode_2_read_illegal_T_20 = _io_decode_2_read_illegal_T_18 | _io_decode_2_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21] assign io_decode_2_read_illegal_0 = _io_decode_2_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_2_write_illegal_T = addr_2[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_2_write_illegal_T_1 = &_io_decode_2_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_2_write_illegal_0 = _io_decode_2_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_2_write_flush_addr_m = {_io_decode_2_write_illegal_T, addr_2[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_2_write_flush_T = io_decode_2_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_2_write_flush_T_1 = io_decode_2_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_2_write_flush_T_2 = _io_decode_2_write_flush_T & _io_decode_2_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_2_write_flush_T_3 = ~_io_decode_2_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_2_write_flush_0 = _io_decode_2_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_2_system_illegal_T = ~csr_addr_legal_2; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_2_system_illegal_T_1 = ~is_hlsv_2; // @[CSR.scala:903:82, :935:49] wire _io_decode_2_system_illegal_T_2 = _io_decode_2_system_illegal_T & _io_decode_2_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_2_system_illegal_T_3 = ~allow_wfi_2; // @[CSR.scala:906:71, :936:17] wire _io_decode_2_system_illegal_T_4 = is_wfi_2 & _io_decode_2_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}] wire _io_decode_2_system_illegal_T_5 = _io_decode_2_system_illegal_T_2 | _io_decode_2_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14] wire _io_decode_2_system_illegal_T_6 = ~allow_sret_2; // @[CSR.scala:910:72, :937:17] wire _io_decode_2_system_illegal_T_7 = is_ret_2 & _io_decode_2_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}] wire _io_decode_2_system_illegal_T_8 = _io_decode_2_system_illegal_T_5 | _io_decode_2_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14] wire _io_decode_2_system_illegal_T_9 = addr_2[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_2_system_illegal_T_10 = is_ret_2 & _io_decode_2_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_2_system_illegal_T_11 = addr_2[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_2_system_illegal_T_12 = _io_decode_2_system_illegal_T_10 & _io_decode_2_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_2_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_2_system_illegal_T_14 = _io_decode_2_system_illegal_T_12 & _io_decode_2_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_2_system_illegal_T_15 = _io_decode_2_system_illegal_T_8 | _io_decode_2_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_2_system_illegal_T_16 = is_sfence_2 | is_hfence_gvma_2; // @[CSR.scala:903:82, :939:18] wire _io_decode_2_system_illegal_T_17 = ~allow_sfence_vma_2; // @[CSR.scala:907:70, :925:59, :939:40] wire _io_decode_2_system_illegal_T_18 = _io_decode_2_system_illegal_T_16 & _io_decode_2_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}] wire _io_decode_2_system_illegal_T_19 = _io_decode_2_system_illegal_T_15 | _io_decode_2_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37] wire _io_decode_2_system_illegal_T_22 = _io_decode_2_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_2_system_illegal_T_25 = _io_decode_2_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_2_system_illegal_0 = _io_decode_2_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_2_virtual_access_illegal_T = reg_mstatus_v & csr_exists_2; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_2_virtual_access_illegal_T_2 = _io_decode_2_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_2_virtual_access_illegal_T_4 = _io_decode_2_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_2_virtual_access_illegal_T_5 = is_counter_2 & _io_decode_2_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_2_virtual_access_illegal_T_7 = _io_decode_2_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_2_virtual_access_illegal_T_8 = ~_io_decode_2_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_2_virtual_access_illegal_T_10 = ~_io_decode_2_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}] wire _io_decode_2_virtual_access_illegal_T_12 = _io_decode_2_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_2_virtual_access_illegal_T_13 = ~_io_decode_2_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_2_virtual_access_illegal_T_14 = _io_decode_2_virtual_access_illegal_T_10 & _io_decode_2_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}] wire _io_decode_2_virtual_access_illegal_T_15 = _io_decode_2_virtual_access_illegal_T_8 | _io_decode_2_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}] wire _io_decode_2_virtual_access_illegal_T_16 = _io_decode_2_virtual_access_illegal_T_5 & _io_decode_2_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_2_virtual_access_illegal_T_17 = _io_decode_2_virtual_access_illegal_T_2 | _io_decode_2_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_2_virtual_access_illegal_T_19 = _io_decode_2_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_2_virtual_access_illegal_T_21 = ~_io_decode_2_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}] wire _io_decode_2_virtual_access_illegal_T_22 = _io_decode_2_virtual_access_illegal_T_19 & _io_decode_2_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}] wire _io_decode_2_virtual_access_illegal_T_23 = _io_decode_2_virtual_access_illegal_T_17 | _io_decode_2_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34] wire _io_decode_2_virtual_access_illegal_T_28 = _io_decode_2_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_2_virtual_access_illegal_T_26 = _io_decode_2_virtual_access_illegal_T_24 & _io_decode_2_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}] assign _io_decode_2_virtual_access_illegal_T_29 = _io_decode_2_virtual_access_illegal_T & _io_decode_2_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_2_virtual_access_illegal_0 = _io_decode_2_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_2_virtual_system_illegal_T = is_hfence_vvma_2 | is_hfence_gvma_2; // @[CSR.scala:903:82, :950:22] wire _io_decode_2_virtual_system_illegal_T_1 = _io_decode_2_virtual_system_illegal_T | is_hlsv_2; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_2_virtual_system_illegal_T_3 = ~_io_decode_2_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}] wire _io_decode_2_virtual_system_illegal_T_6 = _io_decode_2_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}] wire _io_decode_2_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41] wire _io_decode_2_virtual_system_illegal_T_7 = is_wfi_2 & _io_decode_2_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}] wire _io_decode_2_virtual_system_illegal_T_8 = _io_decode_2_virtual_system_illegal_T_1 | _io_decode_2_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14] wire _io_decode_2_virtual_system_illegal_T_10 = _io_decode_2_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_2_virtual_system_illegal_T_11 = is_ret_2 & _io_decode_2_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_2_virtual_system_illegal_T_13 = ~_io_decode_2_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}] wire _io_decode_2_virtual_system_illegal_T_14 = _io_decode_2_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}] wire _io_decode_2_virtual_system_illegal_T_15 = _io_decode_2_virtual_system_illegal_T_11 & _io_decode_2_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}] wire _io_decode_2_virtual_system_illegal_T_16 = _io_decode_2_virtual_system_illegal_T_8 | _io_decode_2_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44] wire _io_decode_2_virtual_system_illegal_T_18 = ~_io_decode_2_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}] wire _io_decode_2_virtual_system_illegal_T_19 = _io_decode_2_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}] wire _io_decode_2_virtual_system_illegal_T_20 = is_sfence_2 & _io_decode_2_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}] wire _io_decode_2_virtual_system_illegal_T_21 = _io_decode_2_virtual_system_illegal_T_16 | _io_decode_2_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17] assign _io_decode_2_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_2_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_2_virtual_system_illegal_0 = _io_decode_2_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}] wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}] wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}] wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40] wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14] assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14] assign io_trace_0_cause = cause; // @[CSR.scala:377:7, :959:8] assign io_trace_1_cause = cause; // @[CSR.scala:377:7, :959:8] assign io_trace_2_cause = cause; // @[CSR.scala:377:7, :959:8] wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25] wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31] wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32] wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30] wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35] wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33] wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78] wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58] wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36] wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29] wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29] wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31] assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25] assign _io_trace_1_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25] assign _io_trace_2_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25] wire _GEN_22 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53] wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53] assign _causeIsDebugInt_T_1 = _GEN_22; // @[CSR.scala:963:53] wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58] assign _causeIsDebugTrigger_T_2 = _GEN_22; // @[CSR.scala:963:53, :964:58] wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}] wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}] wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}] wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}] wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}] wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62] wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62] wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62] wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}] wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134] wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}] wire _trapToDebug_T = reg_singleStepped | causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56] wire _trapToDebug_T_1 = _trapToDebug_T | causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}] wire _trapToDebug_T_2 = _trapToDebug_T_1 | causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}] wire _trapToDebug_T_3 = _trapToDebug_T_2 | reg_debug; // @[CSR.scala:482:26, :966:{98,119}] wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}] wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37] wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}] wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55] wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}] wire [63:0] _GEN_23 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100] wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_23; // @[CSR.scala:498:14, :970:100] wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100] wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_23; // @[CSR.scala:502:14, :970:{100,132}] wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132] wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}] wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}] wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34] wire [63:0] _GEN_24 = 64'h0 >> _GEN_23; // @[CSR.scala:970:100, :971:80] wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80] assign _delegateVS_T_2 = _GEN_24; // @[CSR.scala:971:80] wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112] assign _delegateVS_T_4 = _GEN_24; // @[CSR.scala:971:{80,112}] wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80] wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112] wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}] wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}] wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15] wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15] wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}] wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33] wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}] wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24] wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}] wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70] wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}] wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}] wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38] wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}] wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}] wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45] wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46] wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46] wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}] wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70] wire _GEN_25 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107] wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107] assign _causeIsRnmiInt_T_4 = _GEN_25; // @[CSR.scala:985:107] wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69] assign _causeIsRnmiBEU_T_3 = _GEN_25; // @[CSR.scala:985:107, :986:69] wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 | _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}] wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}] wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}] wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}] wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}] wire _GEN_26 = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24] wire _io_eret_T; // @[CSR.scala:1000:24] assign _io_eret_T = _GEN_26; // @[CSR.scala:1000:24] wire _exception_T; // @[CSR.scala:1020:29] assign _exception_T = _GEN_26; // @[CSR.scala:1000:24, :1020:29] assign _io_eret_T_1 = _io_eret_T | insn_ret; // @[CSR.scala:893:83, :1000:{24,38}] assign io_eret = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38] wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37] assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}] assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34] wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32] wire _io_status_sd_T_2 = _io_status_sd_T; // @[CSR.scala:1003:{32,37}] assign _io_status_sd_T_4 = _io_status_sd_T_2; // @[CSR.scala:1003:{37,58}] assign io_status_sd_0 = _io_status_sd_T_4; // @[CSR.scala:377:7, :1003:58] wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45] wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}] assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}] assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24] wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60] wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}] wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}] assign _io_status_dv_T_3 = reg_mstatus_v | _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}] assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33] wire _io_gstatus_sd_T_3 = &io_gstatus_vs; // @[CSR.scala:377:7, :1016:78] wire exception = _exception_T | io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}] wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24] assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37] wire _io_trace_1_valid_T = io_retire_0[1]; // @[CSR.scala:377:7, :1029:38, :1621:26] wire _io_trace_2_exception_T = io_retire_0[1]; // @[CSR.scala:377:7, :1029:38, :1620:30] wire [39:0] _epc_T = ~io_pc_0; // @[CSR.scala:377:7, :1664:28] wire [39:0] _epc_T_1 = {_epc_T[39:1], 1'h1}; // @[CSR.scala:1664:{28,31}] wire [39:0] epc = ~_epc_T_1; // @[CSR.scala:1664:{26,31}] wire [39:0] tval = insn_break ? epc : io_tval_0; // @[CSR.scala:377:7, :893:83, :1033:17, :1664:26] wire [1:0] _reg_dcsr_cause_T = causeIsDebugTrigger ? 2'h2 : 2'h1; // @[CSR.scala:964:44, :1041:90] wire [1:0] _reg_dcsr_cause_T_1 = causeIsDebugInt ? 2'h3 : _reg_dcsr_cause_T; // @[CSR.scala:963:39, :1041:{58,90}] wire [2:0] _reg_dcsr_cause_T_2 = reg_singleStepped ? 3'h4 : {1'h0, _reg_dcsr_cause_T_1}; // @[CSR.scala:486:30, :1041:{30,58}] wire [1:0] _reg_mncause_T = {1'h1, causeIsRnmiBEU}; // @[CSR.scala:986:55, :1052:55] wire [63:0] _reg_mncause_T_1 = {62'h2000000000000000, _reg_mncause_T}; // @[CSR.scala:1052:{50,55}] wire [61:0] _reg_vscause_T_1 = cause[63:2]; // @[CSR.scala:959:8, :1060:50] wire [63:0] _reg_vscause_T_2 = {_reg_vscause_T_1, 2'h1}; // @[CSR.scala:1060:{44,50}] wire [63:0] _reg_vscause_T_3 = _reg_vscause_T ? _reg_vscause_T_2 : cause; // @[CSR.scala:959:8, :1060:{25,31,44}] wire _reg_hstatus_spvp_T_1 = reg_mstatus_v ? _reg_hstatus_spvp_T : reg_hstatus_spvp; // @[CSR.scala:395:28, :552:28, :1067:{30,61}] wire _GEN_27 = delegateVS | delegate; // @[CSR.scala:395:28, :970:66, :971:46, :1056:37, :1065:35, :1081:23] wire _en_T_5 = cause == 64'h8000000000000000; // @[CSR.scala:959:8, :1096:88] wire _en_T_11 = cause == 64'h8000000000000001; // @[CSR.scala:959:8, :1096:88] wire en_1 = _en_T_8 & _en_T_11; // @[CSR.scala:1096:{24,79,88}] wire _en_T_17 = cause == 64'h8000000000000002; // @[CSR.scala:959:8, :1096:88] wire _en_T_23 = cause == 64'h8000000000000003; // @[CSR.scala:959:8, :1096:88] wire en_3 = _en_T_20 & _en_T_23; // @[CSR.scala:1096:{24,79,88}] wire _en_T_29 = cause == 64'h8000000000000004; // @[CSR.scala:959:8, :1096:88] wire _en_T_35 = cause == 64'h8000000000000005; // @[CSR.scala:959:8, :1096:88] wire en_5 = _en_T_32 & _en_T_35; // @[CSR.scala:1096:{24,79,88}] wire _en_T_41 = cause == 64'h8000000000000006; // @[CSR.scala:959:8, :1096:88] wire _en_T_47 = cause == 64'h8000000000000007; // @[CSR.scala:959:8, :1096:88] wire en_7 = _en_T_44 & _en_T_47; // @[CSR.scala:1096:{24,79,88}] wire _en_T_53 = cause == 64'h8000000000000008; // @[CSR.scala:959:8, :1096:88] wire _en_T_59 = cause == 64'h8000000000000009; // @[CSR.scala:959:8, :1096:88] wire en_9 = _en_T_56 & _en_T_59; // @[CSR.scala:1096:{24,79,88}] wire _en_T_65 = cause == 64'h800000000000000A; // @[CSR.scala:959:8, :1096:88] wire _en_T_71 = cause == 64'h800000000000000B; // @[CSR.scala:959:8, :1096:88] wire en_11 = _en_T_68 & _en_T_71; // @[CSR.scala:1096:{24,79,88}] wire _en_T_77 = cause == 64'h800000000000000C; // @[CSR.scala:959:8, :1096:88] wire _en_T_83 = cause == 64'h800000000000000D; // @[CSR.scala:959:8, :1096:88] wire _en_T_89 = cause == 64'h800000000000000E; // @[CSR.scala:959:8, :1096:88] wire _en_T_95 = cause == 64'h800000000000000F; // @[CSR.scala:959:8, :1096:88] wire _en_T_96 = cause == 64'h1; // @[CSR.scala:959:8, :1108:35] wire en_16 = exception & _en_T_96; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_97 = cause == 64'h2; // @[CSR.scala:959:8, :1108:35] wire en_17 = exception & _en_T_97; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_98 = cause == 64'h3; // @[CSR.scala:959:8, :1108:35] wire en_18 = exception & _en_T_98; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_99 = cause == 64'h4; // @[CSR.scala:959:8, :1108:35] wire en_19 = exception & _en_T_99; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_100 = cause == 64'h5; // @[CSR.scala:959:8, :1108:35] wire en_20 = exception & _en_T_100; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_101 = cause == 64'h6; // @[CSR.scala:959:8, :1108:35] wire en_21 = exception & _en_T_101; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_102 = cause == 64'h7; // @[CSR.scala:959:8, :1108:35] wire en_22 = exception & _en_T_102; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_103 = cause == 64'h8; // @[CSR.scala:959:8, :1108:35] wire en_23 = exception & _en_T_103; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_104 = cause == 64'h9; // @[CSR.scala:959:8, :1108:35] wire en_24 = exception & _en_T_104; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_105 = cause == 64'hB; // @[CSR.scala:959:8, :1108:35] wire en_25 = exception & _en_T_105; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_106 = cause == 64'hC; // @[CSR.scala:959:8, :1108:35] wire en_26 = exception & _en_T_106; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_107 = cause == 64'hD; // @[CSR.scala:959:8, :1108:35] wire en_27 = exception & _en_T_107; // @[CSR.scala:1020:43, :1108:{26,35}] wire _en_T_108 = cause == 64'hF; // @[CSR.scala:959:8, :1108:35] wire en_28 = exception & _en_T_108; // @[CSR.scala:1020:43, :1108:{26,35}] wire [1:0] ret_prv; // @[CSR.scala:1116:27] wire [39:0] _io_evec_T_3 = {_io_evec_T[39:2], _io_evec_T[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_4 = ~_io_evec_T_3; // @[CSR.scala:1665:{26,31}] wire [39:0] _io_evec_T_5 = ~reg_vsepc; // @[CSR.scala:564:22, :1665:28] wire [39:0] _io_evec_T_8 = {_io_evec_T_5[39:2], _io_evec_T_5[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_9 = ~_io_evec_T_8; // @[CSR.scala:1665:{26,31}] wire _T_266 = io_rw_addr_0[10] & io_rw_addr_0[7]; // @[CSR.scala:377:7, :1134:{43,48,61}] wire _reg_mstatus_v_T_2 = ~(reg_dcsr_prv[1]); // @[CSR.scala:403:25, :1136:72] wire [39:0] _io_evec_T_10 = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [39:0] _io_evec_T_13 = {_io_evec_T_10[39:2], _io_evec_T_10[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_14 = ~_io_evec_T_13; // @[CSR.scala:1665:{26,31}] wire [39:0] _io_evec_T_18 = {_io_evec_T_15[39:2], _io_evec_T_15[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_19 = ~_io_evec_T_18; // @[CSR.scala:1665:{26,31}] assign ret_prv = io_rw_addr_0[9] ? (_T_266 ? reg_dcsr_prv : reg_mstatus_mpp) : {1'h0, reg_mstatus_v ? reg_vsstatus_spp : reg_mstatus_spp}; // @[CSR.scala:377:7, :395:28, :403:25, :562:25, :1116:27, :1117:{43,48}, :1118:29, :1122:17, :1130:17, :1134:{48,66}, :1135:15, :1139:65] wire _reg_mstatus_v_T_8 = ~(reg_mstatus_mpp[1]); // @[CSR.scala:395:28, :1150:80] wire [39:0] _io_evec_T_20 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire [39:0] _io_evec_T_23 = {_io_evec_T_20[39:2], _io_evec_T_20[1:0] | 2'h1}; // @[CSR.scala:1665:{28,31}] wire [39:0] _io_evec_T_24 = ~_io_evec_T_23; // @[CSR.scala:1665:{26,31}] assign io_evec_0 = insn_ret ? (io_rw_addr_0[9] ? (_T_266 ? _io_evec_T_14 : _io_evec_T_24) : reg_mstatus_v ? _io_evec_T_9 : _io_evec_T_4) : tvec[39:0]; // @[CSR.scala:377:7, :395:28, :893:83, :995:17, :996:11, :1115:19, :1117:{43,48}, :1118:29, :1124:17, :1132:17, :1134:{48,66}, :1138:15, :1139:65, :1665:26] assign new_prv = insn_ret ? ret_prv : exception ? (trapToDebug ? (reg_debug ? reg_mstatus_prv : 2'h3) : {~_GEN_27, 1'h1}) : reg_mstatus_prv; // @[CSR.scala:395:28, :397:28, :482:26, :893:83, :966:34, :1020:43, :1035:20, :1036:24, :1037:25, :1044:17, :1046:31, :1056:37, :1064:15, :1065:35, :1078:15, :1081:23, :1091:15, :1115:19, :1116:27, :1154:13] assign _io_csr_stall_T = reg_wfi | io_status_cease_0; // @[CSR.scala:377:7, :575:54, :1161:27] assign io_csr_stall_0 = _io_csr_stall_T; // @[CSR.scala:377:7, :1161:27] reg io_status_cease_r; // @[CSR.scala:1162:31] assign io_status_cease_0 = io_status_cease_r; // @[CSR.scala:377:7, :1162:31] wire [63:0] _io_rw_rdata_T_4 = decoded_addr_94_2 ? 64'h800000000014112D : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_153 = _io_rw_rdata_T_4; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_5 = decoded_addr_100_2 ? read_mstatus : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_6 = decoded_addr_72_2 ? read_mtvec : 64'h0; // @[Mux.scala:30:73] wire [15:0] _io_rw_rdata_T_7 = decoded_addr_108_2 ? read_mip : 16'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_8 = decoded_addr_76_2 ? reg_mie : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_9 = decoded_addr_129_2 ? reg_mscratch : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_10 = decoded_addr_132_2 ? read_mapping_10_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_11 = decoded_addr_136_2 ? read_mapping_11_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_12 = decoded_addr_29_2 ? reg_mcause : 64'h0; // @[Mux.scala:30:73] wire [1:0] _io_rw_rdata_T_13 = decoded_addr_131_2 ? io_hartid_0 : 2'h0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_14 = decoded_addr_49_2 ? debug_csrs_0_2 : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_15 = decoded_addr_89_2 ? debug_csrs_1_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_16 = decoded_addr_57_2 ? reg_dscratch0 : 64'h0; // @[Mux.scala:30:73] wire [4:0] _io_rw_rdata_T_17 = decoded_addr_36_2 ? reg_fflags : 5'h0; // @[Mux.scala:30:73] wire [2:0] _io_rw_rdata_T_18 = decoded_addr_68_2 ? reg_frm : 3'h0; // @[Mux.scala:30:73] wire [7:0] _io_rw_rdata_T_19 = decoded_addr_99_2 ? read_fcsr : 8'h0; // @[Mux.scala:30:73] wire [2:0] _io_rw_rdata_T_20 = decoded_addr_130_2 ? reg_mcountinhibit : 3'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_21 = decoded_addr_103_2 ? value_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_22 = decoded_addr_121_2 ? value : 64'h0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_110 = decoded_addr_35_2 ? read_mcounteren : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_111 = decoded_addr_2_2 ? value_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_112 = decoded_addr_66_2 ? value : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_113 = decoded_addr_42_2 ? {57'h0, lo_4} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_114 = decoded_addr_61_2 ? {hi_7[41:0], lo_5} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_115 = decoded_addr_48_2 ? read_sip : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_116 = decoded_addr_44_2 ? read_sie : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_117 = decoded_addr_15_2 ? reg_sscratch : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_118 = decoded_addr_145_2 ? reg_scause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_119 = decoded_addr_93_2 ? {{24{reg_stval[39]}}, reg_stval} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_120 = decoded_addr_6_2 ? {hi_8, reg_satp_ppn} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_121 = decoded_addr_28_2 ? {{24{_T_30[39]}}, _T_30} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_122 = decoded_addr_25_2 ? read_stvec : 64'h0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_123 = decoded_addr_137_2 ? read_scounteren : 32'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_124 = decoded_addr_123_2 ? read_mideleg : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_125 = decoded_addr_23_2 ? read_medeleg : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_126 = decoded_addr_69_2 ? {57'h0, lo_6} : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_127 = decoded_addr_141_2 ? {hi_18, lo_15} : 64'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_129 = decoded_addr_104_2 ? reg_pmp_0_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_130 = decoded_addr_8_2 ? reg_pmp_1_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_131 = decoded_addr_125_2 ? reg_pmp_2_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_132 = decoded_addr_85_2 ? reg_pmp_3_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_133 = decoded_addr_54_2 ? reg_pmp_4_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_134 = decoded_addr_20_2 ? reg_pmp_5_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_135 = decoded_addr_135_2 ? reg_pmp_6_addr : 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_136 = decoded_addr_115_2 ? reg_pmp_7_addr : 30'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_145 = decoded_addr_18_2 ? reg_custom_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_146 = decoded_addr_3_2 ? reg_custom_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_154 = _io_rw_rdata_T_153 | _io_rw_rdata_T_5; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_155 = _io_rw_rdata_T_154 | _io_rw_rdata_T_6; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_156 = {_io_rw_rdata_T_155[63:16], _io_rw_rdata_T_155[15:0] | _io_rw_rdata_T_7}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_157 = _io_rw_rdata_T_156 | _io_rw_rdata_T_8; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_158 = _io_rw_rdata_T_157 | _io_rw_rdata_T_9; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_159 = _io_rw_rdata_T_158 | _io_rw_rdata_T_10; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_160 = _io_rw_rdata_T_159 | _io_rw_rdata_T_11; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_161 = _io_rw_rdata_T_160 | _io_rw_rdata_T_12; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_162 = {_io_rw_rdata_T_161[63:2], _io_rw_rdata_T_161[1:0] | _io_rw_rdata_T_13}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_163 = {_io_rw_rdata_T_162[63:32], _io_rw_rdata_T_162[31:0] | _io_rw_rdata_T_14}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_164 = _io_rw_rdata_T_163 | _io_rw_rdata_T_15; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_165 = _io_rw_rdata_T_164 | _io_rw_rdata_T_16; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_166 = {_io_rw_rdata_T_165[63:5], _io_rw_rdata_T_165[4:0] | _io_rw_rdata_T_17}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_167 = {_io_rw_rdata_T_166[63:3], _io_rw_rdata_T_166[2:0] | _io_rw_rdata_T_18}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_168 = {_io_rw_rdata_T_167[63:8], _io_rw_rdata_T_167[7:0] | _io_rw_rdata_T_19}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_169 = {_io_rw_rdata_T_168[63:3], _io_rw_rdata_T_168[2:0] | _io_rw_rdata_T_20}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_170 = _io_rw_rdata_T_169 | _io_rw_rdata_T_21; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_171 = _io_rw_rdata_T_170 | _io_rw_rdata_T_22; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_172 = _io_rw_rdata_T_171; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_173 = _io_rw_rdata_T_172; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_174 = _io_rw_rdata_T_173; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_175 = _io_rw_rdata_T_174; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_176 = _io_rw_rdata_T_175; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_177 = _io_rw_rdata_T_176; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_178 = _io_rw_rdata_T_177; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_179 = _io_rw_rdata_T_178; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_180 = _io_rw_rdata_T_179; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_181 = _io_rw_rdata_T_180; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_182 = _io_rw_rdata_T_181; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_183 = _io_rw_rdata_T_182; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_184 = _io_rw_rdata_T_183; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_185 = _io_rw_rdata_T_184; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_186 = _io_rw_rdata_T_185; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_187 = _io_rw_rdata_T_186; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_188 = _io_rw_rdata_T_187; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_189 = _io_rw_rdata_T_188; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_190 = _io_rw_rdata_T_189; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_191 = _io_rw_rdata_T_190; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_192 = _io_rw_rdata_T_191; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_193 = _io_rw_rdata_T_192; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_194 = _io_rw_rdata_T_193; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_195 = _io_rw_rdata_T_194; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_196 = _io_rw_rdata_T_195; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_197 = _io_rw_rdata_T_196; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_198 = _io_rw_rdata_T_197; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_199 = _io_rw_rdata_T_198; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_200 = _io_rw_rdata_T_199; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_201 = _io_rw_rdata_T_200; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_202 = _io_rw_rdata_T_201; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_203 = _io_rw_rdata_T_202; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_204 = _io_rw_rdata_T_203; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_205 = _io_rw_rdata_T_204; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_206 = _io_rw_rdata_T_205; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_207 = _io_rw_rdata_T_206; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_208 = _io_rw_rdata_T_207; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_209 = _io_rw_rdata_T_208; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_210 = _io_rw_rdata_T_209; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_211 = _io_rw_rdata_T_210; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_212 = _io_rw_rdata_T_211; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_213 = _io_rw_rdata_T_212; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_214 = _io_rw_rdata_T_213; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_215 = _io_rw_rdata_T_214; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_216 = _io_rw_rdata_T_215; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_217 = _io_rw_rdata_T_216; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_218 = _io_rw_rdata_T_217; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_219 = _io_rw_rdata_T_218; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_220 = _io_rw_rdata_T_219; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_221 = _io_rw_rdata_T_220; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_222 = _io_rw_rdata_T_221; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_223 = _io_rw_rdata_T_222; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_224 = _io_rw_rdata_T_223; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_225 = _io_rw_rdata_T_224; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_226 = _io_rw_rdata_T_225; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_227 = _io_rw_rdata_T_226; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_228 = _io_rw_rdata_T_227; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_229 = _io_rw_rdata_T_228; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_230 = _io_rw_rdata_T_229; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_231 = _io_rw_rdata_T_230; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_232 = _io_rw_rdata_T_231; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_233 = _io_rw_rdata_T_232; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_234 = _io_rw_rdata_T_233; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_235 = _io_rw_rdata_T_234; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_236 = _io_rw_rdata_T_235; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_237 = _io_rw_rdata_T_236; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_238 = _io_rw_rdata_T_237; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_239 = _io_rw_rdata_T_238; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_240 = _io_rw_rdata_T_239; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_241 = _io_rw_rdata_T_240; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_242 = _io_rw_rdata_T_241; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_243 = _io_rw_rdata_T_242; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_244 = _io_rw_rdata_T_243; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_245 = _io_rw_rdata_T_244; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_246 = _io_rw_rdata_T_245; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_247 = _io_rw_rdata_T_246; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_248 = _io_rw_rdata_T_247; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_249 = _io_rw_rdata_T_248; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_250 = _io_rw_rdata_T_249; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_251 = _io_rw_rdata_T_250; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_252 = _io_rw_rdata_T_251; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_253 = _io_rw_rdata_T_252; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_254 = _io_rw_rdata_T_253; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_255 = _io_rw_rdata_T_254; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_256 = _io_rw_rdata_T_255; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_257 = _io_rw_rdata_T_256; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_258 = _io_rw_rdata_T_257; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_259 = {_io_rw_rdata_T_258[63:32], _io_rw_rdata_T_258[31:0] | _io_rw_rdata_T_110}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_260 = _io_rw_rdata_T_259 | _io_rw_rdata_T_111; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_261 = _io_rw_rdata_T_260 | _io_rw_rdata_T_112; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_262 = _io_rw_rdata_T_261 | _io_rw_rdata_T_113; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_263 = _io_rw_rdata_T_262 | _io_rw_rdata_T_114; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_264 = _io_rw_rdata_T_263 | _io_rw_rdata_T_115; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_265 = _io_rw_rdata_T_264 | _io_rw_rdata_T_116; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_266 = _io_rw_rdata_T_265 | _io_rw_rdata_T_117; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_267 = _io_rw_rdata_T_266 | _io_rw_rdata_T_118; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_268 = _io_rw_rdata_T_267 | _io_rw_rdata_T_119; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_269 = _io_rw_rdata_T_268 | _io_rw_rdata_T_120; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_270 = _io_rw_rdata_T_269 | _io_rw_rdata_T_121; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_271 = _io_rw_rdata_T_270 | _io_rw_rdata_T_122; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_272 = {_io_rw_rdata_T_271[63:32], _io_rw_rdata_T_271[31:0] | _io_rw_rdata_T_123}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_273 = _io_rw_rdata_T_272 | _io_rw_rdata_T_124; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_274 = _io_rw_rdata_T_273 | _io_rw_rdata_T_125; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_275 = _io_rw_rdata_T_274 | _io_rw_rdata_T_126; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_276 = _io_rw_rdata_T_275 | _io_rw_rdata_T_127; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_277 = _io_rw_rdata_T_276; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_278 = {_io_rw_rdata_T_277[63:30], _io_rw_rdata_T_277[29:0] | _io_rw_rdata_T_129}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_279 = {_io_rw_rdata_T_278[63:30], _io_rw_rdata_T_278[29:0] | _io_rw_rdata_T_130}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_280 = {_io_rw_rdata_T_279[63:30], _io_rw_rdata_T_279[29:0] | _io_rw_rdata_T_131}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_281 = {_io_rw_rdata_T_280[63:30], _io_rw_rdata_T_280[29:0] | _io_rw_rdata_T_132}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_282 = {_io_rw_rdata_T_281[63:30], _io_rw_rdata_T_281[29:0] | _io_rw_rdata_T_133}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_283 = {_io_rw_rdata_T_282[63:30], _io_rw_rdata_T_282[29:0] | _io_rw_rdata_T_134}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_284 = {_io_rw_rdata_T_283[63:30], _io_rw_rdata_T_283[29:0] | _io_rw_rdata_T_135}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_285 = {_io_rw_rdata_T_284[63:30], _io_rw_rdata_T_284[29:0] | _io_rw_rdata_T_136}; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_286 = _io_rw_rdata_T_285; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_287 = _io_rw_rdata_T_286; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_288 = _io_rw_rdata_T_287; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_289 = _io_rw_rdata_T_288; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_290 = _io_rw_rdata_T_289; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_291 = _io_rw_rdata_T_290; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_292 = _io_rw_rdata_T_291; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_293 = _io_rw_rdata_T_292; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_294 = _io_rw_rdata_T_293 | _io_rw_rdata_T_145; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_295 = _io_rw_rdata_T_294 | _io_rw_rdata_T_146; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_296 = _io_rw_rdata_T_295; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_297 = _io_rw_rdata_T_296; // @[Mux.scala:30:73] wire [63:0] _io_rw_rdata_T_298 = _io_rw_rdata_T_297; // @[Mux.scala:30:73] assign _io_rw_rdata_WIRE = _io_rw_rdata_T_298; // @[Mux.scala:30:73] assign io_rw_rdata_0 = _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire set_fs_dirty; // @[CSR.scala:1200:33]
Generate the Verilog code corresponding to the following Chisel files. File PermuteSequencer.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import saturn.common._ import saturn.insns._ class PermuteSequencer(exu_insns: Seq[VectorInstruction])(implicit p: Parameters) extends PipeSequencer(new PermuteMicroOp)(p) { def accepts(inst: VectorIssueInst) = { val needs_mask = inst.vmu && (!inst.vm && inst.mop =/= mopUnit) val needs_index = inst.vmu && inst.mop(0) val arith = !inst.vmu && new VectorDecoder(inst.funct3, inst.funct6, inst.rs1, inst.rs2, exu_insns.filter(_.props.contains(UsesPermuteSeq.Y)), Nil).matched needs_mask || needs_index || arith } val valid = RegInit(false.B) val inst = Reg(new BackendIssueInst) val eidx = Reg(UInt(log2Ceil(maxVLMax).W)) val rvs2_mask = Reg(UInt(egsTotal.W)) val rvm_mask = Reg(UInt(egsPerVReg.W)) val head = Reg(Bool()) val slide_offset = Reg(UInt((1+log2Ceil(maxVLMax)).W)) val slide = !inst.vmu && inst.funct3 =/= OPIVV val slide_up = !inst.funct6(0) val rs2 = Mux(inst.rs1_is_rs2, inst.rs1, inst.rs2) val gatherei16 = inst.funct3 === OPIVV && inst.opif6 === OPIFunct6.rgatherei16 val renvm = inst.renvm val renv2 = inst.renv2 val incr_eew = Mux(inst.vmu, inst.mem_idx_size, Mux(gatherei16, 1.U, inst.vconfig.vtype.vsew)) val eff_vl = Mux(slide, Mux(slide_up, inst.vconfig.vl - slide_offset, min(inst.vconfig.vtype.vlMax, inst.vconfig.vl + slide_offset)), inst.vconfig.vl )(log2Ceil(maxVLMax),0) val next_eidx = get_next_eidx(eff_vl, eidx, incr_eew, 0.U, false.B, false.B) val tail = next_eidx === eff_vl io.dis.ready := !valid || (tail && io.iss.fire) && !io.dis_stall when (io.dis.fire) { val iss_inst = io.dis.bits val offset = Mux(iss_inst.isOpi, get_max_offset(Mux(iss_inst.funct3(2), iss_inst.rs1_data, iss_inst.imm5)), 1.U) val slide = !iss_inst.vmu && iss_inst.funct3 =/= OPIVV val slide_up = !iss_inst.funct6(0) val slide_start = Mux(slide_up, 0.U, offset) val vlmax = iss_inst.vconfig.vtype.vlMax val slide_no_read = Mux(slide_up, iss_inst.vconfig.vl <= offset, offset >= vlmax) valid := Mux(!slide, true.B, !slide_no_read) inst := iss_inst eidx := Mux(!slide, iss_inst.vstart, slide_start) slide_offset := offset val rs2 = Mux(iss_inst.rs1_is_rs2, iss_inst.rs1, iss_inst.rs2) val renv2_arch_mask = get_arch_mask(rs2, iss_inst.emul) rvs2_mask := Mux(iss_inst.renv2, FillInterleaved(egsPerVReg, renv2_arch_mask), 0.U) rvm_mask := Mux(iss_inst.renvm, ~(0.U(egsPerVReg.W)), 0.U) head := true.B } .elsewhen (io.iss.fire) { valid := !tail head := false.B } io.vat := inst.vat io.seq_hazard.valid := valid io.seq_hazard.bits.rintent := hazardMultiply(rvs2_mask | rvm_mask) io.seq_hazard.bits.wintent := false.B io.seq_hazard.bits.vat := inst.vat val vs2_read_oh = Mux(renv2, UIntToOH(io.rvs2.req.bits.eg), 0.U) val vm_read_oh = Mux(renvm, UIntToOH(io.rvm.req.bits.eg), 0.U) val raw_hazard = ((vm_read_oh | vs2_read_oh) & io.older_writes) =/= 0.U val data_hazard = raw_hazard val oldest = inst.vat === io.vat_head io.rvs2.req.valid := valid && renv2 io.rvs2.req.bits.eg := getEgId(rs2, eidx, incr_eew, false.B) io.rvs2.req.bits.oldest := oldest io.rvm.req.valid := valid && renvm io.rvm.req.bits.eg := getEgId(0.U, eidx, 0.U, true.B) io.rvm.req.bits.oldest := oldest io.iss.valid := valid && !data_hazard && (!renvm || io.rvm.req.ready) && (!renv2 || io.rvs2.req.ready) io.iss.bits.renv2 := renv2 io.iss.bits.renvm := renvm io.iss.bits.rvs2_data := io.rvs2.resp io.iss.bits.rvs2_eew := incr_eew io.iss.bits.eidx := eidx io.iss.bits.vl := eff_vl io.iss.bits.rvm_data := Mux(renvm, io.rvm.resp, ~(0.U(dLen.W))) io.iss.bits.vmu := inst.vmu io.iss.bits.tail := tail when (io.iss.fire && !tail) { when (next_is_new_eg(eidx, next_eidx, incr_eew, false.B) && vParams.enableChaining.B) { rvs2_mask := rvs2_mask & ~vs2_read_oh } when (next_is_new_eg(eidx, next_eidx, 0.U, true.B) && vParams.enableChaining.B) { rvm_mask := rvm_mask & ~UIntToOH(io.rvm.req.bits.eg) } eidx := next_eidx } io.busy := valid io.head := head } File Parameters.scala: package saturn.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.diplomacy.{BufferParams} import saturn.exu._ object VectorParams { // minParams: // For a very small area-efficient vector unit with iterative // and element-wise functional units def minParams = VectorParams() // refParams // For a standard modestly capable small vector unit with // SIMD functional units def refParams = minParams.copy( vlrobEntries = 4, vlissqEntries = 3, vsissqEntries = 3, vxissqEntries = 3, vatSz = 5, useSegmentedIMul = true, doubleBufferSegments = true, useScalarFPFMA = false, vrfBanking = 4, ) // dspParams // For a wide high-performance vector unit with multi-issue def dspParams = refParams.copy( issStructure = VectorIssueStructure.Shared ) // genParams: // For a vector unit that performs better on less-optimized // code sequences def genParams = dspParams.copy( issStructure = VectorIssueStructure.Split, vlifqEntries = 16, vlrobEntries = 16 ) // multiFMAParams: // Provides a second sequencer and set of functional units for FMA operations def multiFMAParams = genParams.copy( issStructure = VectorIssueStructure.MultiFMA ) // multiMACParams: // Provides a second sequencer and set of functional units for integer MAC operations def multiMACParams = genParams.copy( issStructure = VectorIssueStructure.MultiMAC ) // dmaParams: // For a vector unit that only does memcpys, and no arithmetic def dmaParams = VectorParams( vdqEntries = 2, vliqEntries = 4, vsiqEntries = 4, vlifqEntries = 32, vlrobEntries = 4, vsifqEntries = 32, vlissqEntries = 2, vsissqEntries = 1, vrfBanking = 1, useIterativeIMul = true ) // The parameters below are approximations // hwaParams // For a vector unit with limited sequencer slots akin to Hwacha def hwaParams = genParams.copy( vatSz = 3, // 8 mseq Entries vdqEntries = 1, vlissqEntries = 8, vsissqEntries = 8, vxissqEntries = 8, vpissqEntries = 8, hwachaLimiter = Some(8), // sequencer slots ) // lgvParams // For a vector unit with very long vector lengths def lgvParams = VectorParams( vatSz = 5, vlifqEntries = 32, vsifqEntries = 32, vlrobEntries = 32, vlissqEntries = 8, vsissqEntries = 8, vxissqEntries = 8, vpissqEntries = 8, useSegmentedIMul = true, useScalarFPMisc = false, useScalarFPFMA = false, vrfBanking = 4, issStructure = VectorIssueStructure.Split ) } case class VXSequencerParams( name: String, fus: Seq[FunctionalUnitFactory] ) { def insns = fus.map(_.insns).flatten } case class VXIssuePathParams( name: String, depth: Int, seqs: Seq[VXSequencerParams] ) { def insns = seqs.map(_.insns).flatten } object VXFunctionalUnitGroups { def integerFUs(idivDoesImul: Boolean = false) = Seq( IntegerPipeFactory, ShiftPipeFactory, BitwisePipeFactory, IntegerDivideFactory(idivDoesImul), MaskUnitFactory, PermuteUnitFactory ) def integerMAC(pipeDepth: Int, useSegmented: Boolean) = Seq( IntegerMultiplyFactory(pipeDepth, useSegmented) ) def allIntegerFUs(idivDoesImul: Boolean, imaDepth: Int, useSegmentedImul: Boolean) = ( integerFUs(idivDoesImul) ++ integerMAC(imaDepth, useSegmentedImul) ) def sharedFPFMA(pipeDepth: Int) = Seq( FPFMAFactory(pipeDepth, true) ) def sharedFPMisc = Seq( SharedFPMiscFactory ) def fpFMA(pipeDepth: Int) = Seq( FPFMAFactory(pipeDepth, false) ) def fpMisc = Seq( FPDivSqrtFactory, FPCmpFactory, FPConvFactory ) def allFPFUs(fmaPipeDepth: Int, useScalarFPFMA: Boolean, useScalarFPMisc: Boolean) = ( (if (useScalarFPFMA) sharedFPFMA(fmaPipeDepth) else fpFMA(fmaPipeDepth)) ++ (if (useScalarFPMisc) sharedFPMisc else fpMisc) ) } sealed trait VectorIssueStructure { def generate(params: VectorParams): Seq[VXIssuePathParams] } object VectorIssueStructure { import VXFunctionalUnitGroups._ case object Unified extends VectorIssueStructure { def generate(params: VectorParams) = { val fp_int_path = VXIssuePathParams( name = "fp_int", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("fp_int", ( allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul) ++ allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc) )) ) ) Seq(fp_int_path) } } case object Shared extends VectorIssueStructure { def generate(params: VectorParams) = { val fp_int_path = VXIssuePathParams( name = "fp_int", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)) ) ) Seq(fp_int_path) } } case object Split extends VectorIssueStructure { def generate(params: VectorParams) = { val int_path = VXIssuePathParams( name = "int", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), ) ) val fp_path = VXIssuePathParams( name = "fp", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)) ) ) Seq(int_path, fp_path) } } case object MultiFMA extends VectorIssueStructure { def generate(params: VectorParams) = { require(!params.useScalarFPFMA) val int_path = VXIssuePathParams( name = "int", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), ) ) val fp_path = VXIssuePathParams( name = "fp", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("fp0", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)), VXSequencerParams("fp1", fpFMA(params.fmaPipeDepth)) ) ) Seq(int_path, fp_path) } } case object MultiMAC extends VectorIssueStructure { def generate(params: VectorParams) = { require(!params.useIterativeIMul && params.useSegmentedIMul) val int_path = VXIssuePathParams( name = "int", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("int0", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)), VXSequencerParams("int1", integerMAC(params.imaPipeDepth, params.useSegmentedIMul)) ) ) val fp_path = VXIssuePathParams( name = "fp", depth = params.vxissqEntries, seqs = Seq( VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)) ) ) Seq(int_path, fp_path) } } } case class VectorParams( // In-order dispatch Queue vdqEntries: Int = 4, // Load store instruction queues (in VLSU) vliqEntries: Int = 4, vsiqEntries: Int = 4, // Load store in-flight queues (in VLSU) vlifqEntries: Int = 8, vsifqEntries: Int = 16, vlrobEntries: Int = 2, // Scatter-gather engine params vsgPorts: Int = 8, vsgifqEntries: Int = 4, vsgBuffers: Int = 3, // Load/store/execute/permute/maskindex issue queues vlissqEntries: Int = 0, vsissqEntries: Int = 0, vxissqEntries: Int = 0, vpissqEntries: Int = 0, dLen: Int = 64, vatSz: Int = 3, useSegmentedIMul: Boolean = false, useScalarFPFMA: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions useScalarFPMisc: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions useIterativeIMul: Boolean = false, fmaPipeDepth: Int = 4, imaPipeDepth: Int = 3, // for comparisons only hazardingMultiplier: Int = 0, hwachaLimiter: Option[Int] = None, enableChaining: Boolean = true, latencyInject: Boolean = false, enableDAE: Boolean = true, enableOOO: Boolean = true, enableScalarVectorAddrDisambiguation: Boolean = true, doubleBufferSegments: Boolean = false, vrfBanking: Int = 2, vrfHiccupBuffer: Boolean = true, issStructure: VectorIssueStructure = VectorIssueStructure.Unified, tlBuffer: BufferParams = BufferParams.default, ) { def supported_ex_insns = issStructure.generate(this).map(_.insns).flatten } case object VectorParamsKey extends Field[VectorParams] trait HasVectorParams extends HasVectorConsts { this: HasCoreParameters => implicit val p: Parameters def vParams: VectorParams = p(VectorParamsKey) def dLen = vParams.dLen def dLenB = dLen / 8 def dLenOffBits = log2Ceil(dLenB) def dmemTagBits = log2Ceil(vParams.vlifqEntries.max(vParams.vsifqEntries)) def sgmemTagBits = log2Ceil(vParams.vsgifqEntries) def egsPerVReg = vLen / dLen def egsTotal = (vLen / dLen) * 32 def vrfBankBits = log2Ceil(vParams.vrfBanking) def lsiqIdBits = log2Ceil(vParams.vliqEntries.max(vParams.vsiqEntries)) val debugIdSz = 16 val nRelease = vParams.issStructure match { case VectorIssueStructure.Unified => 3 case VectorIssueStructure.Shared | VectorIssueStructure.Split => 4 case VectorIssueStructure.MultiFMA | VectorIssueStructure.MultiMAC => 5 } def getEgId(vreg: UInt, eidx: UInt, eew: UInt, bitwise: Bool): UInt = { val base = vreg << log2Ceil(egsPerVReg) val off = eidx >> Mux(bitwise, log2Ceil(dLen).U, (log2Ceil(dLenB).U - eew)) base +& off } def getByteId(vreg: UInt, eidx: UInt, eew: UInt): UInt = { Cat(getEgId(vreg, eidx, eew, false.B), (eidx << eew)(log2Ceil(dLenB)-1,0)) } def eewByteMask(eew: UInt) = (0 until (1+log2Ceil(eLen/8))).map { e => Mux(e.U === eew, ((1 << (1 << e)) - 1).U, 0.U) }.reduce(_|_)((eLen/8)-1,0) def eewBitMask(eew: UInt) = FillInterleaved(8, eewByteMask(eew)) def cqOlder(i0: UInt, i1: UInt, tail: UInt) = (i0 < i1) ^ (i0 < tail) ^ (i1 < tail) def dLenSplat(in: UInt, eew: UInt) = { val v = Wire(UInt(64.W)) v := in Mux1H(UIntToOH(eew), (0 until 4).map { i => Fill(dLenB >> i, v((8<<i)-1,0)) }) } def sextElem(in: UInt, in_eew: UInt): UInt = VecInit.tabulate(4)( { eew => Cat(in((8 << eew)-1), in((8 << eew)-1,0)).asSInt })(in_eew)(64,0) def extractElem(in: UInt, in_eew: UInt, eidx: UInt): UInt = { val bytes = in.asTypeOf(Vec(dLenB, UInt(8.W))) VecInit.tabulate(4) { eew => val elem = if (dLen == 64 && eew == 3) { in } else { VecInit(bytes.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq)(eidx(log2Ceil(dLenB)-1-eew,0)) } elem((8 << eew)-1,0) }(in_eew) } def maxPosUInt(sew: Int) = Cat(0.U, ~(0.U(((8 << sew)-1).W))) def minNegUInt(sew: Int) = Cat(1.U, 0.U(((8 << sew)-1).W)) def maxPosSInt(sew: Int) = ((1 << ((8 << sew)-1))-1).S def minNegSInt(sew: Int) = (-1 << ((8 << sew)-1)).S def maxPosFPUInt(sew: Int) = { val expBits = Seq(4, 5, 8, 11)(sew) val fracBits = (8 << sew) - expBits - 1 Cat(0.U, ~(0.U(expBits.W)), 0.U(fracBits.W)) } def minNegFPUInt(sew: Int) = { val expBits = Seq(4, 5, 8, 11)(sew) val fracBits = (8 << sew) - expBits - 1 Cat(1.U, ~(0.U(expBits.W)), 0.U(fracBits.W)) } def get_arch_mask(reg: UInt, emul: UInt) = VecInit.tabulate(4)({ lmul => FillInterleaved(1 << lmul, UIntToOH(reg >> lmul)((32>>lmul)-1,0)) })(emul) def log2_up(f: UInt, max: Int) = VecInit.tabulate(max)({nf => log2Ceil(nf+1).U})(f) def hazardMultiply(mask: UInt): UInt = if (vParams.hazardingMultiplier == 0) { mask } else { require((1 << vParams.hazardingMultiplier) <= egsTotal) VecInit(mask.asBools.grouped(1 << vParams.hazardingMultiplier).map { g => Fill(1 << vParams.hazardingMultiplier, g.orR) }.toSeq).asUInt } } File PipeSequencer.scala: package saturn.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import saturn.common._ abstract class PipeSequencer[T <: Data](issType: T)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val dis = Flipped(Decoupled(new BackendIssueInst)) val dis_stall = Input(Bool()) // used to disable OOO val seq_hazard = Output(Valid(new SequencerHazard)) val vat = Output(UInt(vParams.vatSz.W)) val vat_head = Input(UInt(vParams.vatSz.W)) val older_writes = Input(UInt(egsTotal.W)) val older_reads = Input(UInt(egsTotal.W)) val busy = Output(Bool()) val head = Output(Bool()) val rvs1 = new VectorReadIO val rvs2 = new VectorReadIO val rvd = new VectorReadIO val rvm = new VectorReadIO val perm = new Bundle { val req = Decoupled(new CompactorReq(dLenB)) val data = Input(UInt(dLen.W)) } val iss = Decoupled(issType) val acc = Input(Valid(new VectorWrite(dLen))) }) def accepts(inst: VectorIssueInst): Bool def min(a: UInt, b: UInt) = Mux(a > b, b, a) def get_max_offset(offset: UInt): UInt = min(offset, maxVLMax.U)(log2Ceil(maxVLMax),0) def get_head_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask << (eidx << eew)(dLenOffBits-1,0) def get_tail_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask >> (0.U(dLenOffBits.W) - (eidx << eew)(dLenOffBits-1,0)) def get_vm_mask(mask_resp: UInt, eidx: UInt, eew: UInt) = { val vm_off = ((1 << dLenOffBits) - 1).U(log2Ceil(dLen).W) val vm_eidx = (eidx & ~(vm_off >> eew))(log2Ceil(dLen)-1,0) val vm_resp = (mask_resp >> vm_eidx)(dLenB-1,0) Mux1H(UIntToOH(eew), (0 until 4).map { w => FillInterleaved(1 << w, vm_resp) }) } def get_next_eidx(vl: UInt, eidx: UInt, eew: UInt, sub_dlen: UInt, reads_mask: Bool, elementwise: Bool) = { val next = Wire(UInt((1+log2Ceil(maxVLMax)).W)) next := Mux(elementwise, eidx +& 1.U, Mux(reads_mask, eidx +& dLen.U, (((eidx >> (dLenOffBits.U - eew - sub_dlen)) +& 1.U) << (dLenOffBits.U - eew - sub_dlen)) )) min(vl, next) } def next_is_new_eg(eidx: UInt, next_eidx: UInt, eew: UInt, masked: Bool) = { val offset = Mux(masked, log2Ceil(dLen).U, dLenOffBits.U - eew) (next_eidx >> offset) =/= (eidx >> offset) } io.rvs1.req.valid := false.B io.rvs1.req.bits := DontCare io.rvs2.req.valid := false.B io.rvs2.req.bits := DontCare io.rvd.req.valid := false.B io.rvd.req.bits := DontCare io.rvm.req.valid := false.B io.rvm.req.bits := DontCare io.perm.req.valid := false.B io.perm.req.bits := DontCare }
module PermuteSequencer( // @[PermuteSequencer.scala:9:7] input clock, // @[PermuteSequencer.scala:9:7] input reset, // @[PermuteSequencer.scala:9:7] output io_dis_ready, // @[PipeSequencer.scala:11:14] input io_dis_valid, // @[PipeSequencer.scala:11:14] input [31:0] io_dis_bits_bits, // @[PipeSequencer.scala:11:14] input [7:0] io_dis_bits_vconfig_vl, // @[PipeSequencer.scala:11:14] input [2:0] io_dis_bits_vconfig_vtype_vsew, // @[PipeSequencer.scala:11:14] input io_dis_bits_vconfig_vtype_vlmul_sign, // @[PipeSequencer.scala:11:14] input [1:0] io_dis_bits_vconfig_vtype_vlmul_mag, // @[PipeSequencer.scala:11:14] input [6:0] io_dis_bits_vstart, // @[PipeSequencer.scala:11:14] input [63:0] io_dis_bits_rs1_data, // @[PipeSequencer.scala:11:14] input [2:0] io_dis_bits_vat, // @[PipeSequencer.scala:11:14] input [1:0] io_dis_bits_emul, // @[PipeSequencer.scala:11:14] input io_dis_bits_rs1_is_rs2, // @[PipeSequencer.scala:11:14] input io_dis_bits_renv2, // @[PipeSequencer.scala:11:14] input io_dis_bits_renvm, // @[PipeSequencer.scala:11:14] output io_seq_hazard_valid, // @[PipeSequencer.scala:11:14] output [2:0] io_seq_hazard_bits_vat, // @[PipeSequencer.scala:11:14] output [63:0] io_seq_hazard_bits_rintent, // @[PipeSequencer.scala:11:14] output [2:0] io_vat, // @[PipeSequencer.scala:11:14] input [2:0] io_vat_head, // @[PipeSequencer.scala:11:14] input [63:0] io_older_writes, // @[PipeSequencer.scala:11:14] output io_busy, // @[PipeSequencer.scala:11:14] input io_rvs2_req_ready, // @[PipeSequencer.scala:11:14] output io_rvs2_req_valid, // @[PipeSequencer.scala:11:14] output [5:0] io_rvs2_req_bits_eg, // @[PipeSequencer.scala:11:14] output io_rvs2_req_bits_oldest, // @[PipeSequencer.scala:11:14] input [63:0] io_rvs2_resp, // @[PipeSequencer.scala:11:14] input io_rvm_req_ready, // @[PipeSequencer.scala:11:14] output io_rvm_req_valid, // @[PipeSequencer.scala:11:14] output [5:0] io_rvm_req_bits_eg, // @[PipeSequencer.scala:11:14] output io_rvm_req_bits_oldest, // @[PipeSequencer.scala:11:14] input [63:0] io_rvm_resp, // @[PipeSequencer.scala:11:14] input io_iss_ready, // @[PipeSequencer.scala:11:14] output io_iss_valid, // @[PipeSequencer.scala:11:14] output io_iss_bits_renv2, // @[PipeSequencer.scala:11:14] output io_iss_bits_renvm, // @[PipeSequencer.scala:11:14] output [63:0] io_iss_bits_rvs2_data, // @[PipeSequencer.scala:11:14] output [6:0] io_iss_bits_eidx, // @[PipeSequencer.scala:11:14] output [1:0] io_iss_bits_rvs2_eew, // @[PipeSequencer.scala:11:14] output [63:0] io_iss_bits_rvm_data, // @[PipeSequencer.scala:11:14] output io_iss_bits_vmu, // @[PipeSequencer.scala:11:14] output [7:0] io_iss_bits_vl, // @[PipeSequencer.scala:11:14] output io_iss_bits_tail // @[PipeSequencer.scala:11:14] ); wire io_iss_valid_0; // @[PermuteSequencer.scala:88:{25,41,73}] wire _eidx_6; // @[Parameters.scala:343:{20,26}] wire [5:0] _io_rvs2_req_bits_eg_T; // @[Parameters.scala:344:10] reg valid; // @[PermuteSequencer.scala:17:22] reg [31:0] inst_bits; // @[PermuteSequencer.scala:18:18] reg [7:0] inst_vconfig_vl; // @[PermuteSequencer.scala:18:18] reg [2:0] inst_vconfig_vtype_vsew; // @[PermuteSequencer.scala:18:18] reg inst_vconfig_vtype_vlmul_sign; // @[PermuteSequencer.scala:18:18] reg [1:0] inst_vconfig_vtype_vlmul_mag; // @[PermuteSequencer.scala:18:18] reg [2:0] inst_vat; // @[PermuteSequencer.scala:18:18] reg inst_rs1_is_rs2; // @[PermuteSequencer.scala:18:18] reg inst_renv2; // @[PermuteSequencer.scala:18:18] reg inst_renvm; // @[PermuteSequencer.scala:18:18] reg [6:0] eidx; // @[PermuteSequencer.scala:19:18] reg [63:0] rvs2_mask; // @[PermuteSequencer.scala:20:22] reg [1:0] rvm_mask; // @[PermuteSequencer.scala:21:21] reg [7:0] slide_offset; // @[PermuteSequencer.scala:23:25] wire [2:0] incr_eew = inst_bits[6:0] == 7'h7 | inst_bits[6:0] == 7'h27 ? {1'h0, inst_bits[13:12]} : ~(|(inst_bits[14:12])) & (~(|(inst_bits[14:12])) | inst_bits[14:12] == 3'h3 | inst_bits[14:12] == 3'h4 ? {1'h0, inst_bits[31:26]} : 7'h40) == 7'hE ? 3'h1 : inst_vconfig_vtype_vsew; // @[Bundles.scala:56:20, :58:26, :72:20, :75:20, :84:{18,35}] wire [7:0] _eff_vl_T_9 = 8'h80 >> {1'h0, inst_vconfig_vtype_vsew} + {1'h0, inst_vconfig_vtype_vlmul_sign, ~inst_vconfig_vtype_vlmul_mag}; // @[PermuteSequencer.scala:18:18] wire [7:0] _eff_vl_T_10 = inst_vconfig_vl + slide_offset; // @[PermuteSequencer.scala:18:18, :23:25, :34:97] wire [7:0] eff_vl = ~(inst_bits[6:0] == 7'h7 | inst_bits[6:0] == 7'h27) & (|(inst_bits[14:12])) ? (inst_bits[26] ? (_eff_vl_T_9 > _eff_vl_T_10 ? _eff_vl_T_10 : _eff_vl_T_9) : inst_vconfig_vl - slide_offset) : inst_vconfig_vl; // @[Bundles.scala:56:20, :72:20, :75:20] wire [2:0] _offset_T_13 = 3'h3 - incr_eew; // @[PipeSequencer.scala:54:33] wire [6:0] _GEN = {4'h0, _offset_T_13}; // @[PipeSequencer.scala:54:{15,33}] wire [14:0] _next_eidx_next_T_14 = {7'h0, {1'h0, eidx >> _GEN} + 8'h1} << _offset_T_13; // @[PipeSequencer.scala:54:{15,33,52,60}] wire [7:0] next_eidx = eff_vl > _next_eidx_next_T_14[7:0] ? _next_eidx_next_T_14[7:0] : eff_vl; // @[PipeSequencer.scala:40:{34,37}, :52:10, :54:60] wire tail = next_eidx == eff_vl; // @[PipeSequencer.scala:40:34] wire _io_dis_ready_T_1 = io_iss_ready & io_iss_valid_0; // @[Decoupled.scala:51:35] wire io_dis_ready_0 = ~valid | tail & _io_dis_ready_T_1; // @[Decoupled.scala:51:35] wire [63:0] vs2_read_oh = inst_renv2 ? 64'h1 << _io_rvs2_req_bits_eg_T : 64'h0; // @[OneHot.scala:58:35] wire [63:0] _rvm_mask_T_2 = 64'h1 << _eidx_6; // @[OneHot.scala:58:35] wire oldest = inst_vat == io_vat_head; // @[PermuteSequencer.scala:18:18, :79:25] wire [6:0] io_rvs2_req_bits_eg_off = eidx >> _GEN; // @[Parameters.scala:343:20] assign _io_rvs2_req_bits_eg_T = {inst_rs1_is_rs2 ? inst_bits[19:15] : inst_bits[24:20], 1'h0} + io_rvs2_req_bits_eg_off[5:0]; // @[Parameters.scala:343:20, :344:10] assign _eidx_6 = eidx[6]; // @[Parameters.scala:343:{20,26}] assign io_iss_valid_0 = valid & (((inst_renvm ? _rvm_mask_T_2 : 64'h0) | vs2_read_oh) & io_older_writes) == 64'h0 & (~inst_renvm | io_rvm_req_ready) & (~inst_renv2 | io_rvs2_req_ready); // @[OneHot.scala:58:35] wire _GEN_0 = io_dis_ready_0 & io_dis_valid; // @[Decoupled.scala:51:35] wire [63:0] _offset_T_9 = io_dis_bits_bits[14] ? io_dis_bits_rs1_data : {59'h0, io_dis_bits_bits[19:15]}; // @[Bundles.scala:72:20, :73:18] wire [7:0] offset = io_dis_bits_bits[14:12] == 3'h0 | io_dis_bits_bits[14:12] == 3'h3 | io_dis_bits_bits[14:12] == 3'h4 ? (_offset_T_9 > 64'h80 ? 8'h80 : _offset_T_9[7:0]) : 8'h1; // @[Bundles.scala:72:20] wire slide_1 = ~(io_dis_bits_bits[6:0] == 7'h7 | io_dis_bits_bits[6:0] == 7'h27) & (|(io_dis_bits_bits[14:12])); // @[Bundles.scala:56:20, :72:20] wire _GEN_1 = _io_dis_ready_T_1 & next_eidx != eff_vl; // @[Decoupled.scala:51:35] wire [4:0] rs2_1 = io_dis_bits_rs1_is_rs2 ? io_dis_bits_bits[19:15] : io_dis_bits_bits[24:20]; // @[Bundles.scala:69:17, :73:18] wire [3:0][31:0] _GEN_2 = {{{{8{&(rs2_1[4:3])}}, {8{rs2_1[4:3] == 2'h2}}, {8{rs2_1[4:3] == 2'h1}}, {8{rs2_1[4:3] == 2'h0}}}}, {{{4{&(rs2_1[4:2])}}, {4{rs2_1[4:2] == 3'h6}}, {4{rs2_1[4:2] == 3'h5}}, {4{rs2_1[4:2] == 3'h4}}, {4{rs2_1[4:2] == 3'h3}}, {4{rs2_1[4:2] == 3'h2}}, {4{rs2_1[4:2] == 3'h1}}, {4{rs2_1[4:2] == 3'h0}}}}, {{{2{&(rs2_1[4:1])}}, {2{rs2_1[4:1] == 4'hE}}, {2{rs2_1[4:1] == 4'hD}}, {2{rs2_1[4:1] == 4'hC}}, {2{rs2_1[4:1] == 4'hB}}, {2{rs2_1[4:1] == 4'hA}}, {2{rs2_1[4:1] == 4'h9}}, {2{rs2_1[4:1] == 4'h8}}, {2{rs2_1[4:1] == 4'h7}}, {2{rs2_1[4:1] == 4'h6}}, {2{rs2_1[4:1] == 4'h5}}, {2{rs2_1[4:1] == 4'h4}}, {2{rs2_1[4:1] == 4'h3}}, {2{rs2_1[4:1] == 4'h2}}, {2{rs2_1[4:1] == 4'h1}}, {2{rs2_1[4:1] == 4'h0}}}}, {32'h1 << rs2_1}}; // @[OneHot.scala:58:35] always @(posedge clock) begin // @[PermuteSequencer.scala:9:7] if (reset) // @[PermuteSequencer.scala:9:7] valid <= 1'h0; // @[PermuteSequencer.scala:17:22] else if (_GEN_0) // @[Decoupled.scala:51:35] valid <= ~slide_1 | ~(io_dis_bits_bits[26] ? offset >= 8'h80 >> {1'h0, io_dis_bits_vconfig_vtype_vsew} + {1'h0, io_dis_bits_vconfig_vtype_vlmul_sign, ~io_dis_bits_vconfig_vtype_vlmul_mag} : io_dis_bits_vconfig_vl <= offset); // @[Bundles.scala:75:20] else if (_io_dis_ready_T_1) // @[Decoupled.scala:51:35] valid <= next_eidx != eff_vl; // @[PipeSequencer.scala:40:34] if (_GEN_0) begin // @[Decoupled.scala:51:35] inst_bits <= io_dis_bits_bits; // @[PermuteSequencer.scala:18:18] inst_vconfig_vl <= io_dis_bits_vconfig_vl; // @[PermuteSequencer.scala:18:18] inst_vconfig_vtype_vsew <= io_dis_bits_vconfig_vtype_vsew; // @[PermuteSequencer.scala:18:18] inst_vconfig_vtype_vlmul_sign <= io_dis_bits_vconfig_vtype_vlmul_sign; // @[PermuteSequencer.scala:18:18] inst_vconfig_vtype_vlmul_mag <= io_dis_bits_vconfig_vtype_vlmul_mag; // @[PermuteSequencer.scala:18:18] inst_vat <= io_dis_bits_vat; // @[PermuteSequencer.scala:18:18] inst_rs1_is_rs2 <= io_dis_bits_rs1_is_rs2; // @[PermuteSequencer.scala:18:18] inst_renv2 <= io_dis_bits_renv2; // @[PermuteSequencer.scala:18:18] inst_renvm <= io_dis_bits_renvm; // @[PermuteSequencer.scala:18:18] slide_offset <= offset; // @[PermuteSequencer.scala:23:25, :44:21] end if (_GEN_1) // @[PermuteSequencer.scala:99:21] eidx <= next_eidx[6:0]; // @[PipeSequencer.scala:40:34] else if (_GEN_0) // @[Decoupled.scala:51:35] eidx <= slide_1 ? (io_dis_bits_bits[26] ? offset[6:0] : 7'h0) : io_dis_bits_vstart; // @[Bundles.scala:75:20] if (~_GEN_1 | next_eidx >> _offset_T_13 == {1'h0, eidx >> _GEN}) begin // @[PipeSequencer.scala:40:34, :54:{15,33}, :60:{16,27,37}] if (_GEN_0) // @[Decoupled.scala:51:35] rvs2_mask <= io_dis_bits_renv2 ? {{2{_GEN_2[io_dis_bits_emul][31]}}, {2{_GEN_2[io_dis_bits_emul][30]}}, {2{_GEN_2[io_dis_bits_emul][29]}}, {2{_GEN_2[io_dis_bits_emul][28]}}, {2{_GEN_2[io_dis_bits_emul][27]}}, {2{_GEN_2[io_dis_bits_emul][26]}}, {2{_GEN_2[io_dis_bits_emul][25]}}, {2{_GEN_2[io_dis_bits_emul][24]}}, {2{_GEN_2[io_dis_bits_emul][23]}}, {2{_GEN_2[io_dis_bits_emul][22]}}, {2{_GEN_2[io_dis_bits_emul][21]}}, {2{_GEN_2[io_dis_bits_emul][20]}}, {2{_GEN_2[io_dis_bits_emul][19]}}, {2{_GEN_2[io_dis_bits_emul][18]}}, {2{_GEN_2[io_dis_bits_emul][17]}}, {2{_GEN_2[io_dis_bits_emul][16]}}, {2{_GEN_2[io_dis_bits_emul][15]}}, {2{_GEN_2[io_dis_bits_emul][14]}}, {2{_GEN_2[io_dis_bits_emul][13]}}, {2{_GEN_2[io_dis_bits_emul][12]}}, {2{_GEN_2[io_dis_bits_emul][11]}}, {2{_GEN_2[io_dis_bits_emul][10]}}, {2{_GEN_2[io_dis_bits_emul][9]}}, {2{_GEN_2[io_dis_bits_emul][8]}}, {2{_GEN_2[io_dis_bits_emul][7]}}, {2{_GEN_2[io_dis_bits_emul][6]}}, {2{_GEN_2[io_dis_bits_emul][5]}}, {2{_GEN_2[io_dis_bits_emul][4]}}, {2{_GEN_2[io_dis_bits_emul][3]}}, {2{_GEN_2[io_dis_bits_emul][2]}}, {2{_GEN_2[io_dis_bits_emul][1]}}, {2{_GEN_2[io_dis_bits_emul][0]}}} : 64'h0; // @[PermuteSequencer.scala:20:22, :59:{21,53}] end else // @[PermuteSequencer.scala:42:22, :99:31, :100:91] rvs2_mask <= rvs2_mask & ~vs2_read_oh; // @[PermuteSequencer.scala:20:22, :73:24, :101:{30,32}] if (~_GEN_1 | {6'h0, next_eidx[7:6]} == {7'h0, _eidx_6}) begin // @[Parameters.scala:342:21, :343:{20,26}, :344:10] if (_GEN_0) // @[Decoupled.scala:51:35] rvm_mask <= {2{io_dis_bits_renvm}}; // @[PermuteSequencer.scala:21:21, :60:20] end else // @[PermuteSequencer.scala:42:22, :99:31, :103:85] rvm_mask <= ~(_rvm_mask_T_2[1:0]) & rvm_mask; // @[OneHot.scala:58:35] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_EntryData_52( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_121( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_138 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_60( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module cc_banks_2( // @[DescribedSRAM.scala:17:26] input [13:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [31:0] RW0_wdata, output [31:0] RW0_rdata ); cc_banks_0_ext cc_banks_0_ext ( // @[DescribedSRAM.scala:17:26] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata) ); // @[DescribedSRAM.scala:17:26] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File recFNFromFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ object recFNFromFN { def apply(expWidth: Int, sigWidth: Int, in: Bits) = { val rawIn = rawFloatFromFN(expWidth, sigWidth, in) rawIn.sign ## (Mux(rawIn.isZero, 0.U(3.W), rawIn.sExp(expWidth, expWidth - 2)) | Mux(rawIn.isNaN, 1.U, 0.U)) ## rawIn.sExp(expWidth - 3, 0) ## rawIn.sig(sigWidth - 2, 0) } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } } File fNFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ object fNFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits) = { val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2 val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in) val isSubnormal = rawIn.sExp < minNormExp.S val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0) val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0) val expOut = Mux(isSubnormal, 0.U, rawIn.sExp(expWidth - 1, 0) - ((BigInt(1)<<(expWidth - 1)) + 1).U ) | Fill(expWidth, rawIn.isNaN || rawIn.isInf) val fractOut = Mux(isSubnormal, denormFract, Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0)) ) Cat(rawIn.sign, expOut, fractOut) } } File Pipeline.scala: package gemmini import chisel3._ import chisel3.util._ class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module { val io = IO(new Bundle { val in = Flipped(Decoupled(gen)) val out = Decoupled(gen) val busy = Output(Bool()) }) require(comb.size == latency+1, "length of combinational is incorrect") if (latency == 0) { io.in.ready := io.out.ready io.out.valid := io.in.valid io.out.bits := comb.head(io.in.bits) io.busy := io.in.valid } else { val stages = Reg(Vec(latency, gen)) val valids = RegInit(VecInit(Seq.fill(latency)(false.B))) val stalling = VecInit(Seq.fill(latency)(false.B)) io.busy := io.in.valid || valids.reduce(_||_) // Stall signals io.in.ready := !stalling.head stalling.last := valids.last && !io.out.ready (stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) => s1 := v1 && s2 } // Valid signals // When the pipeline stage ahead of you isn't stalling, then make yourself invalid io.out.valid := valids.last when(io.out.ready) { valids.last := false.B } (valids.init, stalling.tail).zipped.foreach { case (v1, s2) => when(!s2) { v1 := false.B } } // When the pipeline stage behind you is valid then become true when(io.in.fire) { valids.head := true.B } (valids.tail, valids.init).zipped.foreach { case (v2, v1) => when(v1) { v2 := true.B } } // Stages when(io.in.fire) { stages.head := comb.head(io.in.bits) } io.out.bits := comb.last(stages.last) ((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) => when(!s2) { st2 := c1(st1) } } } } object Pipeline { def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)(comb)) p.io.in <> in p.io.out } def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)()) p.io.in <> in p.io.out } } File AccumulatorScale.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ class AccumulatorReadRespWithFullData[T <: Data: Arithmetic, U <: Data](fullDataType: Vec[Vec[T]], scale_t: U) extends Bundle { val resp = new AccumulatorReadResp(fullDataType, scale_t) val full_data = fullDataType.cloneType } class AccumulatorScaleResp[T <: Data: Arithmetic](fullDataType: Vec[Vec[T]], rDataType: Vec[Vec[T]]) extends Bundle { val full_data = fullDataType.cloneType val data = rDataType.cloneType val acc_bank_id = UInt(2.W) val fromDMA = Bool() } class AccumulatorScaleIO[T <: Data: Arithmetic, U <: Data]( fullDataType: Vec[Vec[T]], scale_t: U, rDataType: Vec[Vec[T]] ) extends Bundle { val in = Flipped(Decoupled(new NormalizedOutput[T,U](fullDataType, scale_t))) val out = Decoupled(new AccumulatorScaleResp[T](fullDataType, rDataType)) } class AccScaleDataWithIndex[T <: Data: Arithmetic, U <: Data](t: T, u: U) extends Bundle { val scale = u.cloneType val act = UInt(Activation.bitwidth.W) val igelu_qb = t.cloneType val igelu_qc = t.cloneType val iexp_qln2 = t.cloneType val iexp_qln2_inv = t.cloneType val mean = t.cloneType val max = t.cloneType val inv_stddev = u.cloneType val inv_sum_exp = u.cloneType val data = t.cloneType val full_data = t.cloneType val id = UInt(2.W) // TODO hardcoded val index = UInt() } class AccScalePipe[T <: Data, U <: Data](t: T, rDataType: Vec[Vec[T]], scale_func: (T, U) => T, scale_t: U, latency: Int, has_nonlinear_activations: Boolean, has_normalizations: Boolean) (implicit ev: Arithmetic[T]) extends Module { val u = scale_t val io = IO(new Bundle { val in = Input(Valid(new AccScaleDataWithIndex(t, u)(ev))) val out = Output(Valid(new AccScaleDataWithIndex(t, u)(ev))) }) import ev._ val out = WireInit(io.in) val e = io.in.bits.data val act = io.in.bits.act // make sure no normalizations gets passed in if no functional units present assert(has_normalizations.B || (!io.in.fire) || (act =/= Activation.LAYERNORM && act =/= Activation.SOFTMAX && act =/= Activation.IGELU)) val e_act = MuxCase(e, Seq( (has_nonlinear_activations.B && act === Activation.RELU) -> e.relu, (has_nonlinear_activations.B && has_normalizations.B && act === Activation.LAYERNORM) -> (e - io.in.bits.mean), (has_nonlinear_activations.B && has_normalizations.B && act === Activation.IGELU) -> AccumulatorScale.igelu(e, io.in.bits.igelu_qb, io.in.bits.igelu_qc), (has_nonlinear_activations.B && has_normalizations.B && act === Activation.SOFTMAX) -> AccumulatorScale.iexp(e - io.in.bits.max, io.in.bits.iexp_qln2, io.in.bits.iexp_qln2_inv, io.in.bits.igelu_qb, io.in.bits.igelu_qc), )) val e_scaled = scale_func(e_act, MuxCase(io.in.bits.scale, Seq( (has_nonlinear_activations.B && has_normalizations.B && act === Activation.LAYERNORM) -> io.in.bits.inv_stddev, (has_nonlinear_activations.B && has_normalizations.B && act === Activation.SOFTMAX) -> io.in.bits.inv_sum_exp.asTypeOf(scale_t) )).asTypeOf(scale_t)) val e_clipped = e_scaled.clippedToWidthOf(rDataType.head.head) out.bits.data := e_clipped io.out := Pipe(out, latency) } class AccumulatorScale[T <: Data, U <: Data]( fullDataType: Vec[Vec[T]], rDataType: Vec[Vec[T]], scale_t: U, read_small_data: Boolean, read_full_data: Boolean, scale_func: (T, U) => T, num_scale_units: Int, latency: Int, has_nonlinear_activations: Boolean, has_normalizations: Boolean)(implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new AccumulatorScaleIO[T,U]( fullDataType, scale_t, rDataType )(ev)) val t = io.in.bits.acc_read_resp.data(0)(0).cloneType val acc_read_data = io.in.bits.acc_read_resp.data val out = Wire(Decoupled(new AccumulatorScaleResp[T]( fullDataType, rDataType)(ev))) if (num_scale_units == -1) { val data = io.in.bits.acc_read_resp.data val act = io.in.bits.acc_read_resp.act val igelu_qb = io.in.bits.acc_read_resp.igelu_qb val igelu_qc = io.in.bits.acc_read_resp.igelu_qc val iexp_qln2 = io.in.bits.acc_read_resp.iexp_qln2 val iexp_qln2_inv = io.in.bits.acc_read_resp.iexp_qln2_inv val scale = io.in.bits.acc_read_resp.scale val activated_data = VecInit(data.map(v => VecInit(v.map { e => val e_act = MuxCase(e, Seq( (has_nonlinear_activations.B && act === Activation.RELU) -> e.relu, (has_nonlinear_activations.B && has_normalizations.B && act === Activation.LAYERNORM) -> (e - io.in.bits.mean), (has_nonlinear_activations.B && has_normalizations.B && act === Activation.IGELU) -> AccumulatorScale.igelu(e, igelu_qb, igelu_qc), (has_nonlinear_activations.B && has_normalizations.B && act === Activation.SOFTMAX) -> AccumulatorScale.iexp(e - io.in.bits.max, iexp_qln2, iexp_qln2_inv, igelu_qb, igelu_qc), )) val e_scaled = scale_func(e_act, MuxCase(scale, Seq( (has_nonlinear_activations.B && has_normalizations.B && act === Activation.LAYERNORM) -> io.in.bits.inv_stddev, (has_nonlinear_activations.B && has_normalizations.B && act === Activation.SOFTMAX) -> io.in.bits.inv_sum_exp.asTypeOf(scale_t) )).asTypeOf(scale_t)) val e_clipped = e_scaled.clippedToWidthOf(rDataType.head.head) e_clipped }))) val in = Wire(Decoupled(new AccumulatorReadRespWithFullData(fullDataType, scale_t)(ev))) in.valid := io.in.valid io.in.ready := in.ready in.bits.resp := io.in.bits.acc_read_resp in.bits.full_data := acc_read_data in.bits.resp.data := activated_data val pipe_out = Pipeline(in, latency) out.valid := pipe_out.valid pipe_out.ready := out.ready out.bits.full_data := pipe_out.bits.full_data out.bits.data := pipe_out.bits.resp.data out.bits.fromDMA := pipe_out.bits.resp.fromDMA out.bits.acc_bank_id := pipe_out.bits.resp.acc_bank_id } else { val width = acc_read_data.size * acc_read_data(0).size val nEntries = 3 /*val regs = Reg(Vec(nEntries, Valid(new AccumulatorReadResp[T,U]( fullDataType, scale_t)(ev))))*/ val regs = Reg(Vec(nEntries, Valid(new NormalizedOutput[T,U]( fullDataType, scale_t)(ev)))) val out_regs = Reg(Vec(nEntries, new AccumulatorScaleResp[T]( fullDataType, rDataType)(ev))) val fired_masks = Reg(Vec(nEntries, Vec(width, Bool()))) val completed_masks = Reg(Vec(nEntries, Vec(width, Bool()))) val head_oh = RegInit(1.U(nEntries.W)) val tail_oh = RegInit(1.U(nEntries.W)) out.valid := Mux1H(head_oh.asBools, (regs zip completed_masks).map({case (r, c) => r.valid && c.reduce(_&&_)})) out.bits := Mux1H(head_oh.asBools, out_regs) when (out.fire) { for (i <- 0 until nEntries) { when (head_oh(i)) { regs(i).valid := false.B } } head_oh := (head_oh << 1).asUInt | head_oh(nEntries-1) } io.in.ready := !Mux1H(tail_oh.asBools, regs.map(_.valid)) || (tail_oh === head_oh && out.fire) when (io.in.fire) { for (i <- 0 until nEntries) { when (tail_oh(i)) { regs(i).valid := true.B regs(i).bits := io.in.bits out_regs(i).fromDMA := io.in.bits.acc_read_resp.fromDMA out_regs(i).acc_bank_id := io.in.bits.acc_read_resp.acc_bank_id fired_masks(i).foreach(_ := false.B) completed_masks(i).foreach(_ := false.B) } } tail_oh := (tail_oh << 1).asUInt | tail_oh(nEntries-1) } val num_units_with_norm = 4 // TODO: move to configs val inputs_norm = Seq.fill(width*nEntries) { Wire(Decoupled(new AccScaleDataWithIndex(t, scale_t)(ev))) } val inputs_non_norm = Seq.fill(width*nEntries) { Wire(Decoupled(new AccScaleDataWithIndex(t, scale_t)(ev))) } val norm_mask = regs.map(r => r.valid && ( (r.bits.acc_read_resp.act === Activation.SOFTMAX) || (r.bits.acc_read_resp.act === Activation.LAYERNORM) || (r.bits.acc_read_resp.act === Activation.IGELU) )) // input: norm_mask // output: {b2, b1, b0} <-> b_i = whether entry i should use functional units with norm (1 = should) val static_assignment_policy = Wire(Vec(1 << nEntries, UInt(nEntries.W))) println("static policy for " + num_units_with_norm + " norm units:") for (i <- 0 until (1 << nEntries)) { val binaryString = String.format("%" + nEntries + "s", i.toBinaryString) .replace(' ', '0').toCharArray.toList val num_norm : Int = binaryString.count(_ == '1') val ratio_of_norm_entries = num_norm.toFloat / nEntries.toFloat val ratio_of_norm_units = num_units_with_norm.toFloat / num_scale_units.toFloat if (ratio_of_norm_entries >= ratio_of_norm_units) { // use norm units for all norm entries static_assignment_policy(i.U) := i.U println("input pattern " + binaryString.mkString("") + ": " + binaryString.mkString("")) } else { def flip_n_zeros (s: List[Char], n: Int): List[Char] = { if (s.nonEmpty) { if ((s.head == '0') && (n > 0)) '1' :: flip_n_zeros(s.tail, n - 1) else s.head :: flip_n_zeros(s.tail, n) } else { assert(n == 0, "cannot flip " + n + " zeros in an empty string") List.empty } } val flippedString = flip_n_zeros( binaryString, Math.round(ratio_of_norm_units * nEntries) - num_norm) val flipped = Integer.parseInt(flippedString.mkString(""), 2) static_assignment_policy(i.U) := flipped.U println("input pattern " + binaryString.mkString("") + ": " + flipped.toBinaryString) } } // val inputs = Seq.fill(width*nEntries) { Wire(Decoupled(new AccScaleDataWithIndex(t, scale_t)(ev))) } val current_policy = Wire(UInt(nEntries.W)) val norm_mask_int = Wire(UInt(nEntries.W)) norm_mask_int := VecInit(norm_mask).asUInt dontTouch(norm_mask_int) current_policy := static_assignment_policy(norm_mask_int) for (i <- 0 until nEntries) { for (w <- 0 until width) { val input = inputs_norm(i*width+w) val acc_read_resp = regs(i).bits.acc_read_resp input.valid := regs(i).valid && !fired_masks(i)(w) && /*norm_mask(i)*/ current_policy(i) input.bits.data := acc_read_resp.data(w / acc_read_data(0).size)(w % acc_read_data(0).size) input.bits.full_data := acc_read_resp.data(w / acc_read_data(0).size)(w % acc_read_data(0).size) input.bits.scale := acc_read_resp.scale input.bits.act := acc_read_resp.act input.bits.igelu_qb := acc_read_resp.igelu_qb input.bits.igelu_qc := acc_read_resp.igelu_qc input.bits.iexp_qln2 := acc_read_resp.iexp_qln2 input.bits.iexp_qln2_inv := acc_read_resp.iexp_qln2_inv input.bits.mean := regs(i).bits.mean input.bits.max := regs(i).bits.max input.bits.inv_stddev := regs(i).bits.inv_stddev input.bits.inv_sum_exp := regs(i).bits.inv_sum_exp input.bits.id := i.U input.bits.index := w.U when (input.fire) { fired_masks(i)(w) := true.B } } } for (i <- 0 until nEntries) { for (w <- 0 until width) { val input = inputs_non_norm(i*width+w) val acc_read_resp = regs(i).bits.acc_read_resp input.valid := regs(i).valid && !fired_masks(i)(w) && (!current_policy(i)) input.bits.data := acc_read_resp.data(w / acc_read_data(0).size)(w % acc_read_data(0).size) input.bits.full_data := acc_read_resp.data(w / acc_read_data(0).size)(w % acc_read_data(0).size) input.bits.scale := acc_read_resp.scale input.bits.act := acc_read_resp.act input.bits.igelu_qb := DontCare input.bits.igelu_qc := DontCare input.bits.iexp_qln2 := DontCare input.bits.iexp_qln2_inv := DontCare input.bits.mean := DontCare input.bits.max := DontCare input.bits.inv_stddev := DontCare input.bits.inv_sum_exp := DontCare input.bits.id := i.U input.bits.index := w.U if (num_scale_units == num_units_with_norm) { input.ready := false.B } when (input.fire) { fired_masks(i)(w) := true.B } } } for (i <- 0 until num_scale_units) { val norm_supported = (i < num_units_with_norm) && has_normalizations val arbIn = if (norm_supported) // for norm units, prioritize norm operations inputs_norm.zipWithIndex.filter({ case (_, w) => w % num_units_with_norm == i }).map(_._1) else inputs_non_norm.zipWithIndex.filter({ case (_, w) => w % (num_scale_units - num_units_with_norm) == (i - num_units_with_norm) }).map(_._1) val arb = Module(new RRArbiter(new AccScaleDataWithIndex(t, scale_t)(ev), arbIn.length)) arb.io.in <> arbIn arb.io.out.ready := true.B val arbOut = Reg(Valid(new AccScaleDataWithIndex(t, scale_t)(ev))) arbOut.valid := arb.io.out.valid arbOut.bits := arb.io.out.bits when (reset.asBool) { arbOut.valid := false.B } val pipe = Module(new AccScalePipe(t, rDataType, scale_func, scale_t, latency, has_nonlinear_activations, norm_supported)) pipe.io.in := arbOut val pipe_out = pipe.io.out for (j <- 0 until nEntries) { for (w <- 0 until width) { val id0 = w % acc_read_data(0).size val id1 = w / acc_read_data(0).size if ((j*width+w) % num_units_with_norm == i) { when (pipe_out.fire && pipe_out.bits.id === j.U && pipe_out.bits.index === w.U) { out_regs(j).data (id1)(id0) := pipe_out.bits.data out_regs(j).full_data(id1)(id0) := pipe_out.bits.full_data completed_masks(j)(w) := true.B } } if (num_scale_units > num_units_with_norm) { if ((j*width+w) % (num_scale_units - num_units_with_norm) == (i - num_units_with_norm)) { val id0 = w % acc_read_data(0).size val id1 = w / acc_read_data(0).size when (pipe_out.fire && pipe_out.bits.id === j.U && pipe_out.bits.index === w.U) { out_regs(j).data (id1)(id0) := pipe_out.bits.data out_regs(j).full_data(id1)(id0) := pipe_out.bits.full_data completed_masks(j)(w) := true.B } } } } } } when (reset.asBool) { regs.foreach(_.valid := false.B) } } io.out <> out if (read_small_data) io.out.bits.data := out.bits.data else io.out.bits.data := DontCare if (read_full_data) io.out.bits.full_data := out.bits.full_data else io.out.bits.full_data := DontCare } object AccumulatorScale { def igelu[T <: Data](q: T, qb: T, qc: T)(implicit ev: Arithmetic[T]): T = { import ev._ val zero = q.zero val one = q.identity def neg(x: T) = zero-x val q_sign = Mux(q.zero > q, neg(one), one) val q_abs = Mux(q.zero > q, neg(q), q) val q_clipped = Mux(q_abs > neg(qb), neg(qb), q_abs) val q_poly = qc.mac(q_clipped + qb, q_clipped + qb).withWidthOf(q) val q_erf = (q_sign * q_poly).withWidthOf(q) (q * (q_erf + qc)).withWidthOf(q) } def iexp[T <: Data](q: T, qln2: T, qln2_inv: T, qb: T, qc: T)(implicit ev: Arithmetic[T]): T = { import ev._ val zero = q.zero def neg(x: T) = zero-x // qln2_inv needs scale to be 1 / (2 ** 16) / S // qln2_inv / S / (2 ** 16) = 1 / ln2 // q * qln2_inv = x / S / ln2 * S * (2 ** 16) = x / ln2 * (2 ** 16) val neg_q_iexp = neg(q) val z_iexp = (neg_q_iexp * qln2_inv).asUInt.do_>>(16).asTypeOf(q) // q is non-positive val z_iexp_saturated = Wire(z_iexp.cloneType) z_iexp_saturated := Mux((5 until 16).map(z_iexp.asUInt(_)).reduce(_ | _), 32.S.asTypeOf(z_iexp), z_iexp) val qp_iexp = q.mac(z_iexp, qln2).withWidthOf(q) val q_poly_iexp = qc.mac(qp_iexp + qb, qp_iexp + qb).withWidthOf(q) // we dont want a rounding shift // TODO: z overflow (q_poly_iexp.asUInt.do_>>(z_iexp_saturated.asUInt)).asTypeOf(q) }} File rawFloatFromFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ object rawFloatFromFN { def apply(expWidth: Int, sigWidth: Int, in: Bits) = { val sign = in(expWidth + sigWidth - 1) val expIn = in(expWidth + sigWidth - 2, sigWidth - 1) val fractIn = in(sigWidth - 2, 0) val isZeroExpIn = (expIn === 0.U) val isZeroFractIn = (fractIn === 0.U) val normDist = countLeadingZeros(fractIn) val subnormFract = (fractIn << normDist) (sigWidth - 3, 0) << 1 val adjustedExp = Mux(isZeroExpIn, normDist ^ ((BigInt(1) << (expWidth + 1)) - 1).U, expIn ) + ((BigInt(1) << (expWidth - 1)).U | Mux(isZeroExpIn, 2.U, 1.U)) val isZero = isZeroExpIn && isZeroFractIn val isSpecial = adjustedExp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && !isZeroFractIn out.isInf := isSpecial && isZeroFractIn out.isZero := isZero out.sign := sign out.sExp := adjustedExp(expWidth, 0).zext out.sig := 0.U(1.W) ## !isZero ## Mux(isZeroExpIn, subnormFract, fractIn) out } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module AccumulatorScale( // @[AccumulatorScale.scala:88:7] input clock, // @[AccumulatorScale.scala:88:7] input reset, // @[AccumulatorScale.scala:88:7] output io_in_ready, // @[AccumulatorScale.scala:99:14] input io_in_valid, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_0_0_bits, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_1_0_bits, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_2_0_bits, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_3_0_bits, // @[AccumulatorScale.scala:99:14] input io_in_bits_acc_read_resp_fromDMA, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_scale_bits, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_igelu_qb_bits, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_igelu_qc_bits, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_iexp_qln2_bits, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_iexp_qln2_inv_bits, // @[AccumulatorScale.scala:99:14] input [2:0] io_in_bits_acc_read_resp_act, // @[AccumulatorScale.scala:99:14] input [1:0] io_in_bits_acc_read_resp_acc_bank_id, // @[AccumulatorScale.scala:99:14] input io_out_ready, // @[AccumulatorScale.scala:99:14] output io_out_valid, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_0_0_bits, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_1_0_bits, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_2_0_bits, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_3_0_bits, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_data_0_0_bits, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_data_1_0_bits, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_data_2_0_bits, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_data_3_0_bits, // @[AccumulatorScale.scala:99:14] output [1:0] io_out_bits_acc_bank_id, // @[AccumulatorScale.scala:99:14] output io_out_bits_fromDMA // @[AccumulatorScale.scala:99:14] ); wire activated_data_e_clipped_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_self_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_self_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire [31:0] _activated_data_e_act_z_iexp_WIRE_3; // @[AccumulatorScale.scala:398:67] wire activated_data_e_act_z_iexp_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_z_iexp_t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_19_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_18_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_17_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_14_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_16_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_13_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_self_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_self_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_15_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_14_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_m2_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_m1_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_13_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_12_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_11_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_10_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_10_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_9_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_15_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_clipped_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_self_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_self_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire [31:0] _activated_data_e_act_z_iexp_WIRE_2; // @[AccumulatorScale.scala:398:67] wire activated_data_e_act_z_iexp_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_z_iexp_t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_14_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_13_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_12_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_10_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_11_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_9_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_self_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_self_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_11_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_10_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_m2_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_m1_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_9_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_8_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_8_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_10_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_clipped_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire [31:0] _activated_data_e_act_z_iexp_WIRE_1; // @[AccumulatorScale.scala:398:67] wire activated_data_e_act_z_iexp_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_z_iexp_t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_9_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_8_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_m2_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_m1_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_clipped_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [31:0] _activated_data_e_act_z_iexp_WIRE; // @[AccumulatorScale.scala:398:67] wire activated_data_e_act_z_iexp_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_z_iexp_t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_erf_t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_m2_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_m1_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _activated_data_e_clipped_resizer_3_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _activated_data_e_scaled_muladder_3_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_scaled_t_resizer_3_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_q_poly_iexp_resizer_3_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_11_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_q_poly_iexp_m2_resizer_3_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_q_poly_iexp_m1_resizer_3_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_10_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_iexp_t_resizer_7_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_9_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_iexp_t_resizer_6_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_qp_iexp_resizer_3_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_qp_iexp_muladder_3_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_qp_iexp_m2_resizer_3_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_qp_iexp_m1_resizer_3_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_z_iexp_muladder_3_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_z_iexp_t_resizer_3_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_neg_q_iexp_muladder_3_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_neg_q_iexp_t_resizer_3_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_muladder_15_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_resizer_3_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_muladder_14_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_t_resizer_14_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_muladder_13_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_t_resizer_13_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_erf_resizer_3_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_erf_muladder_3_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_q_erf_t_resizer_3_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_q_poly_resizer_3_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_poly_muladder_11_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_q_poly_m2_resizer_3_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_q_poly_m1_resizer_3_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_q_poly_muladder_10_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_t_resizer_7_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_poly_muladder_9_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_t_resizer_6_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_clipped_muladder_7_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_11_io_out; // @[Arithmetic.scala:409:31] wire _activated_data_e_act_q_clipped_comparator_3_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_10_io_out; // @[Arithmetic.scala:469:31] wire [32:0] _activated_data_e_act_q_clipped_muladder_6_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_9_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_abs_muladder_3_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_abs_t_resizer_7_io_out; // @[Arithmetic.scala:409:31] wire _activated_data_e_act_q_abs_comparator_3_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_abs_t_resizer_6_io_out; // @[Arithmetic.scala:469:31] wire _activated_data_e_act_q_sign_comparator_3_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_sign_t_resizer_6_io_out; // @[Arithmetic.scala:469:31] wire [32:0] _activated_data_e_act_muladder_12_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_clipped_resizer_2_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _activated_data_e_scaled_muladder_2_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_scaled_t_resizer_2_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_q_poly_iexp_resizer_2_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_8_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_q_poly_iexp_m2_resizer_2_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_q_poly_iexp_m1_resizer_2_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_7_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_iexp_t_resizer_5_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_6_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_iexp_t_resizer_4_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_qp_iexp_resizer_2_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_qp_iexp_muladder_2_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_qp_iexp_m2_resizer_2_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_qp_iexp_m1_resizer_2_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_z_iexp_muladder_2_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_z_iexp_t_resizer_2_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_neg_q_iexp_muladder_2_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_neg_q_iexp_t_resizer_2_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_muladder_11_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_resizer_2_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_muladder_10_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_t_resizer_10_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_muladder_9_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_t_resizer_9_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_erf_resizer_2_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_erf_muladder_2_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_q_erf_t_resizer_2_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_q_poly_resizer_2_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_poly_muladder_8_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_q_poly_m2_resizer_2_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_q_poly_m1_resizer_2_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_q_poly_muladder_7_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_t_resizer_5_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_poly_muladder_6_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_t_resizer_4_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_clipped_muladder_5_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_8_io_out; // @[Arithmetic.scala:409:31] wire _activated_data_e_act_q_clipped_comparator_2_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_7_io_out; // @[Arithmetic.scala:469:31] wire [32:0] _activated_data_e_act_q_clipped_muladder_4_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_6_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_abs_muladder_2_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_abs_t_resizer_5_io_out; // @[Arithmetic.scala:409:31] wire _activated_data_e_act_q_abs_comparator_2_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_abs_t_resizer_4_io_out; // @[Arithmetic.scala:469:31] wire _activated_data_e_act_q_sign_comparator_2_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_sign_t_resizer_4_io_out; // @[Arithmetic.scala:469:31] wire [32:0] _activated_data_e_act_muladder_8_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_clipped_resizer_1_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _activated_data_e_scaled_muladder_1_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_scaled_t_resizer_1_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_q_poly_iexp_resizer_1_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_5_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_q_poly_iexp_m2_resizer_1_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_q_poly_iexp_m1_resizer_1_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_4_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_iexp_t_resizer_3_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_3_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_iexp_t_resizer_2_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_qp_iexp_resizer_1_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_qp_iexp_muladder_1_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_qp_iexp_m2_resizer_1_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_qp_iexp_m1_resizer_1_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_z_iexp_muladder_1_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_z_iexp_t_resizer_1_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_neg_q_iexp_muladder_1_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_neg_q_iexp_t_resizer_1_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_muladder_7_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_resizer_1_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_muladder_6_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_t_resizer_6_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_muladder_5_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_t_resizer_5_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_erf_resizer_1_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_erf_muladder_1_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_q_erf_t_resizer_1_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_q_poly_resizer_1_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_poly_muladder_5_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_q_poly_m2_resizer_1_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_q_poly_m1_resizer_1_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_q_poly_muladder_4_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_t_resizer_3_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_poly_muladder_3_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_t_resizer_2_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_clipped_muladder_3_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_5_io_out; // @[Arithmetic.scala:409:31] wire _activated_data_e_act_q_clipped_comparator_1_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_4_io_out; // @[Arithmetic.scala:469:31] wire [32:0] _activated_data_e_act_q_clipped_muladder_2_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_3_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_abs_muladder_1_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_abs_t_resizer_3_io_out; // @[Arithmetic.scala:409:31] wire _activated_data_e_act_q_abs_comparator_1_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_abs_t_resizer_2_io_out; // @[Arithmetic.scala:469:31] wire _activated_data_e_act_q_sign_comparator_1_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_sign_t_resizer_2_io_out; // @[Arithmetic.scala:469:31] wire [32:0] _activated_data_e_act_muladder_4_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_clipped_resizer_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _activated_data_e_scaled_muladder_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_scaled_t_resizer_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_q_poly_iexp_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_2_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_q_poly_iexp_m2_resizer_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_q_poly_iexp_m1_resizer_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_1_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_iexp_t_resizer_1_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_poly_iexp_muladder_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_iexp_t_resizer_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_qp_iexp_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_qp_iexp_muladder_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_qp_iexp_m2_resizer_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_qp_iexp_m1_resizer_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_z_iexp_muladder_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_z_iexp_t_resizer_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_neg_q_iexp_muladder_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_neg_q_iexp_t_resizer_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_muladder_3_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_muladder_2_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_t_resizer_2_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_muladder_1_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_t_resizer_1_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_erf_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_erf_muladder_io_out; // @[Arithmetic.scala:342:30] wire [32:0] _activated_data_e_act_q_erf_t_resizer_io_out; // @[Arithmetic.scala:336:32] wire [32:0] _activated_data_e_act_q_poly_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _activated_data_e_act_q_poly_muladder_2_io_out; // @[Arithmetic.scala:376:30] wire [32:0] _activated_data_e_act_q_poly_m2_resizer_io_out; // @[Arithmetic.scala:369:32] wire [32:0] _activated_data_e_act_q_poly_m1_resizer_io_out; // @[Arithmetic.scala:362:32] wire [32:0] _activated_data_e_act_q_poly_muladder_1_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_t_resizer_1_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_poly_muladder_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_poly_t_resizer_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_clipped_muladder_1_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_2_io_out; // @[Arithmetic.scala:409:31] wire _activated_data_e_act_q_clipped_comparator_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_1_io_out; // @[Arithmetic.scala:469:31] wire [32:0] _activated_data_e_act_q_clipped_muladder_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_clipped_t_resizer_io_out; // @[Arithmetic.scala:409:31] wire [32:0] _activated_data_e_act_q_abs_muladder_io_out; // @[Arithmetic.scala:416:30] wire [32:0] _activated_data_e_act_q_abs_t_resizer_1_io_out; // @[Arithmetic.scala:409:31] wire _activated_data_e_act_q_abs_comparator_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_abs_t_resizer_io_out; // @[Arithmetic.scala:469:31] wire _activated_data_e_act_q_sign_comparator_io_gt; // @[Arithmetic.scala:475:32] wire [32:0] _activated_data_e_act_q_sign_t_resizer_io_out; // @[Arithmetic.scala:469:31] wire [32:0] _activated_data_e_act_muladder_io_out; // @[Arithmetic.scala:416:30] wire io_in_valid_0 = io_in_valid; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_0_0_bits_0 = io_in_bits_acc_read_resp_data_0_0_bits; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_1_0_bits_0 = io_in_bits_acc_read_resp_data_1_0_bits; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_2_0_bits_0 = io_in_bits_acc_read_resp_data_2_0_bits; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_3_0_bits_0 = io_in_bits_acc_read_resp_data_3_0_bits; // @[AccumulatorScale.scala:88:7] wire io_in_bits_acc_read_resp_fromDMA_0 = io_in_bits_acc_read_resp_fromDMA; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_scale_bits_0 = io_in_bits_acc_read_resp_scale_bits; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_igelu_qb_bits_0 = io_in_bits_acc_read_resp_igelu_qb_bits; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_igelu_qc_bits_0 = io_in_bits_acc_read_resp_igelu_qc_bits; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_iexp_qln2_bits_0 = io_in_bits_acc_read_resp_iexp_qln2_bits; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0 = io_in_bits_acc_read_resp_iexp_qln2_inv_bits; // @[AccumulatorScale.scala:88:7] wire [2:0] io_in_bits_acc_read_resp_act_0 = io_in_bits_acc_read_resp_act; // @[AccumulatorScale.scala:88:7] wire [1:0] io_in_bits_acc_read_resp_acc_bank_id_0 = io_in_bits_acc_read_resp_acc_bank_id; // @[AccumulatorScale.scala:88:7] wire io_out_ready_0 = io_out_ready; // @[AccumulatorScale.scala:88:7] wire [6:0] _activated_data_e_act_one_T = 7'h7F; // @[Arithmetic.scala:519:52] wire [6:0] _activated_data_e_act_one_T_3 = 7'h7F; // @[Arithmetic.scala:519:52] wire [6:0] _activated_data_e_act_one_T_6 = 7'h7F; // @[Arithmetic.scala:519:52] wire [6:0] _activated_data_e_act_one_T_9 = 7'h7F; // @[Arithmetic.scala:519:52] wire [31:0] _activated_data_e_act_one_T_1 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] activated_data_e_act_one_bits = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_WIRE = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_T_2 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_T_4 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] activated_data_e_act_one_1_bits = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_WIRE_1 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_T_5 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_T_7 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] activated_data_e_act_one_2_bits = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_WIRE_2 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_T_8 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_T_10 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] activated_data_e_act_one_3_bits = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_WIRE_3 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [31:0] _activated_data_e_act_one_T_11 = 32'h3F800000; // @[Arithmetic.scala:519:{41,115}] wire [30:0] _activated_data_e_act_q_sign_neg_t_T_1 = 31'h3F800000; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_q_sign_neg_t_T_5 = 31'h3F800000; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_q_sign_neg_t_T_9 = 31'h3F800000; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_q_sign_neg_t_T_13 = 31'h3F800000; // @[Arithmetic.scala:433:39] wire [8:0] activated_data_e_act_one_hi = 9'h7F; // @[rawFloatFromFN.scala:54:10] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_6 = 9'h7F; // @[rawFloatFromFN.scala:54:10] wire [8:0] activated_data_e_act_one_hi_1 = 9'h7F; // @[rawFloatFromFN.scala:54:10] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_16 = 9'h7F; // @[rawFloatFromFN.scala:54:10] wire [8:0] activated_data_e_act_one_hi_2 = 9'h7F; // @[rawFloatFromFN.scala:54:10] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_26 = 9'h7F; // @[rawFloatFromFN.scala:54:10] wire [8:0] activated_data_e_act_one_hi_3 = 9'h7F; // @[rawFloatFromFN.scala:54:10] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_36 = 9'h7F; // @[rawFloatFromFN.scala:54:10] wire [7:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_8 = 8'h81; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_18 = 8'h81; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_28 = 8'h81; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_38 = 8'h81; // @[rawFloatFromFN.scala:58:9] wire [3:0] _activated_data_e_act_q_sign_t_rec_T_12 = 4'hC; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_sign_t_rec_T_28 = 4'hC; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_sign_t_rec_T_44 = 4'hC; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_sign_t_rec_T_60 = 4'hC; // @[recFNFromFN.scala:47:20] wire [5:0] _activated_data_e_act_q_sign_t_rec_T_13 = 6'h0; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_t_rec_T_29 = 6'h0; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_t_rec_T_45 = 6'h0; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_t_rec_T_61 = 6'h0; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_sign_t_rec_T_14 = 10'h300; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_sign_t_rec_T_30 = 10'h300; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_sign_t_rec_T_46 = 10'h300; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_sign_t_rec_T_62 = 10'h300; // @[recFNFromFN.scala:49:45] wire [32:0] activated_data_e_act_q_sign_t_rec_1 = 33'h180000000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_sign_t_rec_3 = 33'h180000000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_sign_t_rec_5 = 33'h180000000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_sign_t_rec_7 = 33'h180000000; // @[recFNFromFN.scala:50:41] wire [8:0] activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_1 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_2 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] activated_data_e_act_q_sign_result_bits_rawIn_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_3 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_6 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] activated_data_e_act_q_sign_result_bits_rawIn_exp_1 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_5 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_10 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] activated_data_e_act_q_sign_result_bits_rawIn_exp_2 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_7 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_14 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] activated_data_e_act_q_sign_result_bits_rawIn_exp_3 = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_8 = 3'h4; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_9 = 3'h4; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_11 = 3'h4; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_result_bits_rawIn_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_24 = 3'h4; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_25 = 3'h4; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_27 = 3'h4; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_result_bits_rawIn_isZero_T_1 = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_40 = 3'h4; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_41 = 3'h4; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_43 = 3'h4; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_result_bits_rawIn_isZero_T_2 = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_56 = 3'h4; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_57 = 3'h4; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_59 = 3'h4; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_result_bits_rawIn_isZero_T_3 = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_9 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] activated_data_e_act_q_sign_t_rec_rawIn_1_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_3 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] activated_data_e_act_q_sign_result_bits_rawIn_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_19 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] activated_data_e_act_q_sign_t_rec_rawIn_3_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_7 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] activated_data_e_act_q_sign_result_bits_rawIn_1_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sExp_T_1 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_29 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] activated_data_e_act_q_sign_t_rec_rawIn_5_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_11 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] activated_data_e_act_q_sign_result_bits_rawIn_2_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sExp_T_2 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_39 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] activated_data_e_act_q_sign_t_rec_rawIn_7_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_15 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] activated_data_e_act_q_sign_result_bits_rawIn_3_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sExp_T_3 = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_7 = 2'h1; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_5 = 2'h1; // @[rawFloatFromFN.scala:70:16] wire [1:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_17 = 2'h1; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_13 = 2'h1; // @[rawFloatFromFN.scala:70:16] wire [1:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_5 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_27 = 2'h1; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_21 = 2'h1; // @[rawFloatFromFN.scala:70:16] wire [1:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_9 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_37 = 2'h1; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_29 = 2'h1; // @[rawFloatFromFN.scala:70:16] wire [1:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_13 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [24:0] activated_data_e_act_q_sign_t_rec_rawIn_1_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_7 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] activated_data_e_act_q_sign_result_bits_rawIn_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] activated_data_e_act_q_sign_t_rec_rawIn_3_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_15 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] activated_data_e_act_q_sign_result_bits_rawIn_1_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_7 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] activated_data_e_act_q_sign_t_rec_rawIn_5_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_23 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] activated_data_e_act_q_sign_result_bits_rawIn_2_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_11 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] activated_data_e_act_q_sign_t_rec_rawIn_7_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_31 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] activated_data_e_act_q_sign_result_bits_rawIn_3_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_15 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [5:0] _activated_data_e_act_q_sign_result_bits_denormShiftDist_T_1 = 6'h1; // @[fNFromRecFN.scala:52:35] wire [5:0] _activated_data_e_act_q_sign_result_bits_denormShiftDist_T_3 = 6'h1; // @[fNFromRecFN.scala:52:35] wire [5:0] _activated_data_e_act_q_sign_result_bits_denormShiftDist_T_5 = 6'h1; // @[fNFromRecFN.scala:52:35] wire [5:0] _activated_data_e_act_q_sign_result_bits_denormShiftDist_T_7 = 6'h1; // @[fNFromRecFN.scala:52:35] wire [4:0] activated_data_e_act_q_sign_result_bits_denormShiftDist = 5'h1; // @[fNFromRecFN.scala:52:35] wire [4:0] activated_data_e_act_q_sign_result_bits_denormShiftDist_1 = 5'h1; // @[fNFromRecFN.scala:52:35] wire [4:0] activated_data_e_act_q_sign_result_bits_denormShiftDist_2 = 5'h1; // @[fNFromRecFN.scala:52:35] wire [4:0] activated_data_e_act_q_sign_result_bits_denormShiftDist_3 = 5'h1; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_sign_result_bits_denormFract_T = 24'h400000; // @[fNFromRecFN.scala:53:38] wire [23:0] _activated_data_e_act_q_sign_result_bits_denormFract_T_2 = 24'h400000; // @[fNFromRecFN.scala:53:38] wire [23:0] _activated_data_e_act_q_sign_result_bits_denormFract_T_4 = 24'h400000; // @[fNFromRecFN.scala:53:38] wire [23:0] _activated_data_e_act_q_sign_result_bits_denormFract_T_6 = 24'h400000; // @[fNFromRecFN.scala:53:38] wire [23:0] _activated_data_e_act_q_sign_result_bits_denormFract_T_1 = 24'h200000; // @[fNFromRecFN.scala:53:42] wire [23:0] _activated_data_e_act_q_sign_result_bits_denormFract_T_3 = 24'h200000; // @[fNFromRecFN.scala:53:42] wire [23:0] _activated_data_e_act_q_sign_result_bits_denormFract_T_5 = 24'h200000; // @[fNFromRecFN.scala:53:42] wire [23:0] _activated_data_e_act_q_sign_result_bits_denormFract_T_7 = 24'h200000; // @[fNFromRecFN.scala:53:42] wire [22:0] activated_data_e_act_q_sign_result_bits_denormFract = 23'h200000; // @[fNFromRecFN.scala:53:60] wire [22:0] activated_data_e_act_q_sign_result_bits_denormFract_1 = 23'h200000; // @[fNFromRecFN.scala:53:60] wire [22:0] activated_data_e_act_q_sign_result_bits_denormFract_2 = 23'h200000; // @[fNFromRecFN.scala:53:60] wire [22:0] activated_data_e_act_q_sign_result_bits_denormFract_3 = 23'h200000; // @[fNFromRecFN.scala:53:60] wire [7:0] activated_data_e_act_q_sign_t_rec_rawIn_expIn_1 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_2 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_3 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_result_bits_expOut = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_t_rec_rawIn_expIn_3 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_8 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_9 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_result_bits_expOut_1 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_t_rec_rawIn_expIn_5 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_14 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_15 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_result_bits_expOut_2 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_t_rec_rawIn_expIn_7 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_20 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_21 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_result_bits_expOut_3 = 8'h7F; // @[rawFloatFromFN.scala:45:19] wire [8:0] _activated_data_e_act_q_sign_result_bits_expOut_T_1 = 9'h17F; // @[fNFromRecFN.scala:58:45] wire [8:0] activated_data_e_act_q_sign_result_bits_hi = 9'h17F; // @[fNFromRecFN.scala:66:12] wire [8:0] _activated_data_e_act_q_sign_result_bits_expOut_T_7 = 9'h17F; // @[fNFromRecFN.scala:58:45] wire [8:0] activated_data_e_act_q_sign_result_bits_hi_1 = 9'h17F; // @[fNFromRecFN.scala:66:12] wire [8:0] _activated_data_e_act_q_sign_result_bits_expOut_T_13 = 9'h17F; // @[fNFromRecFN.scala:58:45] wire [8:0] activated_data_e_act_q_sign_result_bits_hi_2 = 9'h17F; // @[fNFromRecFN.scala:66:12] wire [8:0] _activated_data_e_act_q_sign_result_bits_expOut_T_19 = 9'h17F; // @[fNFromRecFN.scala:58:45] wire [8:0] activated_data_e_act_q_sign_result_bits_hi_3 = 9'h17F; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_T_2 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_sign_neg_t_bits = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_WIRE = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_T_3 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_sign_result_bits = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_result_bits_T = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_T_6 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_sign_neg_t_1_bits = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_WIRE_1 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_T_7 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_sign_result_1_bits = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_result_bits_T_1 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_T_10 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_sign_neg_t_2_bits = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_WIRE_2 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_T_11 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_sign_result_2_bits = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_result_bits_T_2 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_T_14 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_sign_neg_t_3_bits = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_WIRE_3 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_neg_t_T_15 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_sign_result_3_bits = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_q_sign_result_bits_T_3 = 32'hBF800000; // @[fNFromRecFN.scala:66:12] wire [30:0] _activated_data_e_act_neg_t_T_1 = 31'h0; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_neg_t_T_5 = 31'h0; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_neg_t_T_9 = 31'h0; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_neg_t_T_13 = 31'h0; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_neg_t_T_17 = 31'h0; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_neg_t_T_21 = 31'h0; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_neg_t_T_25 = 31'h0; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_neg_t_T_29 = 31'h0; // @[Arithmetic.scala:433:39] wire [31:0] _activated_data_e_act_neg_t_T_2 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] activated_data_e_act_neg_t_bits = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_WIRE = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_3 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_6 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] activated_data_e_act_neg_t_1_bits = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_WIRE_1 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_7 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_10 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] activated_data_e_act_neg_t_2_bits = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_WIRE_2 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_11 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_14 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] activated_data_e_act_neg_t_3_bits = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_WIRE_3 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_15 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_18 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] activated_data_e_act_neg_t_4_bits = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_WIRE_4 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_19 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_22 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] activated_data_e_act_neg_t_5_bits = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_WIRE_5 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_23 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_26 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] activated_data_e_act_neg_t_6_bits = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_WIRE_6 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_27 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_30 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] activated_data_e_act_neg_t_7_bits = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_WIRE_7 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_t_T_31 = 32'h80000000; // @[Arithmetic.scala:433:{24,65}] wire [3:0] _activated_data_e_act_t_rec_T_4 = 4'h8; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_t_rec_T_28 = 4'h8; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_t_rec_T_36 = 4'h8; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_t_rec_T_60 = 4'h8; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_t_rec_T_68 = 4'h8; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_t_rec_T_92 = 4'h8; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_t_rec_T_100 = 4'h8; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_t_rec_T_124 = 4'h8; // @[recFNFromFN.scala:47:20] wire [9:0] _activated_data_e_act_t_rec_T_6 = 10'h22B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_t_rec_T_30 = 10'h22B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_t_rec_T_38 = 10'h22B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_t_rec_T_62 = 10'h22B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_t_rec_T_70 = 10'h22B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_t_rec_T_94 = 10'h22B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_t_rec_T_102 = 10'h22B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_t_rec_T_126 = 10'h22B; // @[recFNFromFN.scala:49:45] wire [32:0] activated_data_e_act_t_rec = 33'h115800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_t_rec_3 = 33'h115800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_t_rec_4 = 33'h115800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_t_rec_7 = 33'h115800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_t_rec_8 = 33'h115800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_t_rec_11 = 33'h115800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_t_rec_12 = 33'h115800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_t_rec_15 = 33'h115800000; // @[recFNFromFN.scala:50:41] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_self_rec_rawIn_expIn = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_self_rec_rawIn_expIn_1 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T = 8'h0; // @[fNFromRecFN.scala:58:27] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_5 = 8'h0; // @[fNFromRecFN.scala:60:21] wire [7:0] activated_data_e_act_q_abs_self_rec_rawIn_expIn = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_abs_self_rec_rawIn_expIn_1 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_2 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_3 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_expIn = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_4 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_self_rec_rawIn_expIn_2 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_self_rec_rawIn_expIn_3 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_6 = 8'h0; // @[fNFromRecFN.scala:58:27] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_11 = 8'h0; // @[fNFromRecFN.scala:60:21] wire [7:0] activated_data_e_act_q_abs_self_rec_rawIn_expIn_2 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_abs_self_rec_rawIn_expIn_3 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_3 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_5 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_7 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_expIn_1 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_8 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_self_rec_rawIn_expIn_4 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_self_rec_rawIn_expIn_5 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_12 = 8'h0; // @[fNFromRecFN.scala:58:27] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_17 = 8'h0; // @[fNFromRecFN.scala:60:21] wire [7:0] activated_data_e_act_q_abs_self_rec_rawIn_expIn_4 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_abs_self_rec_rawIn_expIn_5 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_6 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_8 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_11 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_expIn_2 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_12 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_self_rec_rawIn_expIn_6 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_self_rec_rawIn_expIn_7 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_18 = 8'h0; // @[fNFromRecFN.scala:58:27] wire [7:0] _activated_data_e_act_q_sign_result_bits_expOut_T_23 = 8'h0; // @[fNFromRecFN.scala:60:21] wire [7:0] activated_data_e_act_q_abs_self_rec_rawIn_expIn_6 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_abs_self_rec_rawIn_expIn_7 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_9 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_11 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_15 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_expIn_3 = 8'h0; // @[rawFloatFromFN.scala:45:19] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_23 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_24 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_25 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_26 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_27 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_28 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_29 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_30 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_31 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_32 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_33 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_34 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_35 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_36 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_37 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_38 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_39 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_40 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_41 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_42 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_43 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_23 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_24 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_25 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_26 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_27 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_28 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_29 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_30 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_31 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_32 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_33 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_34 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_35 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_36 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_37 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_38 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_39 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_40 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_41 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_42 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_43 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_self_rec_rawIn_normDist = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_67 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_68 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_69 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_70 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_71 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_72 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_73 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_74 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_75 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_76 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_77 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_78 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_79 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_80 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_81 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_82 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_83 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_84 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_85 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_86 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_87 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_t_rec_rawIn_normDist_1 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_67 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_68 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_69 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_70 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_71 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_72 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_73 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_74 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_75 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_76 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_77 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_78 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_79 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_80 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_81 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_82 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_83 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_84 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_85 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_86 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_87 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_self_rec_rawIn_normDist_1 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_23 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_24 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_25 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_26 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_27 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_28 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_29 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_30 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_31 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_32 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_33 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_34 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_35 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_36 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_37 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_38 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_39 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_40 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_41 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_42 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_43 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_self_rec_rawIn_normDist = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_67 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_68 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_69 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_70 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_71 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_72 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_73 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_74 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_75 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_76 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_77 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_78 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_79 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_80 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_81 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_82 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_83 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_84 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_85 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_86 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_87 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_self_rec_rawIn_normDist_1 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_23 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_24 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_25 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_26 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_27 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_28 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_29 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_30 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_31 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_32 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_33 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_34 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_35 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_36 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_37 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_38 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_39 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_40 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_41 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_42 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_43 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_111 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_112 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_113 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_114 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_115 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_116 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_117 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_118 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_119 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_120 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_121 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_122 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_123 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_124 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_125 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_126 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_127 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_128 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_129 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_130 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_131 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_2 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_155 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_156 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_157 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_158 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_159 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_160 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_161 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_162 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_163 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_164 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_165 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_166 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_167 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_168 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_169 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_170 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_171 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_172 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_173 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_174 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_175 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_3 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_23 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_24 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_25 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_26 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_27 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_28 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_29 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_30 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_31 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_32 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_33 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_34 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_35 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_36 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_37 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_38 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_39 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_40 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_41 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_42 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_43 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_199 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_200 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_201 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_202 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_203 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_204 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_205 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_206 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_207 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_208 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_209 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_210 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_211 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_212 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_213 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_214 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_215 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_216 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_217 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_218 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_219 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_4 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_111 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_112 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_113 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_114 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_115 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_116 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_117 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_118 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_119 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_120 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_121 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_122 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_123 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_124 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_125 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_126 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_127 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_128 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_129 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_130 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_131 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_self_rec_rawIn_normDist_2 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_155 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_156 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_157 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_158 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_159 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_160 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_161 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_162 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_163 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_164 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_165 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_166 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_167 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_168 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_169 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_170 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_171 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_172 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_173 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_174 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_175 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_t_rec_rawIn_normDist_3 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_155 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_156 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_157 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_158 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_159 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_160 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_161 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_162 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_163 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_164 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_165 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_166 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_167 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_168 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_169 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_170 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_171 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_172 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_173 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_174 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_175 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_self_rec_rawIn_normDist_3 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_111 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_112 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_113 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_114 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_115 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_116 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_117 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_118 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_119 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_120 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_121 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_122 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_123 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_124 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_125 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_126 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_127 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_128 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_129 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_130 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_131 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_self_rec_rawIn_normDist_2 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_155 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_156 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_157 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_158 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_159 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_160 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_161 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_162 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_163 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_164 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_165 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_166 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_167 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_168 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_169 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_170 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_171 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_172 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_173 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_174 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_175 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_self_rec_rawIn_normDist_3 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_155 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_156 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_157 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_158 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_159 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_160 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_161 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_162 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_163 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_164 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_165 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_166 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_167 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_168 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_169 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_170 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_171 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_172 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_173 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_174 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_175 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_3 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_243 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_244 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_245 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_246 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_247 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_248 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_249 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_250 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_251 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_252 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_253 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_254 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_255 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_256 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_257 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_258 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_259 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_260 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_261 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_262 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_263 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_5 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_331 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_332 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_333 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_334 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_335 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_336 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_337 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_338 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_339 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_340 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_341 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_342 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_343 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_344 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_345 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_346 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_347 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_348 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_349 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_350 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_351 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_7 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_67 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_68 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_69 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_70 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_71 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_72 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_73 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_74 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_75 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_76 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_77 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_78 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_79 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_80 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_81 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_82 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_83 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_84 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_85 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_86 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_87 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_1 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_375 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_376 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_377 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_378 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_379 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_380 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_381 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_382 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_383 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_384 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_385 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_386 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_387 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_388 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_389 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_390 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_391 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_392 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_393 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_394 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_395 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_8 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_199 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_200 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_201 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_202 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_203 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_204 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_205 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_206 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_207 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_208 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_209 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_210 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_211 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_212 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_213 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_214 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_215 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_216 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_217 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_218 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_219 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_self_rec_rawIn_normDist_4 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_243 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_244 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_245 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_246 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_247 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_248 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_249 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_250 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_251 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_252 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_253 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_254 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_255 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_256 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_257 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_258 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_259 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_260 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_261 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_262 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_263 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_t_rec_rawIn_normDist_5 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_243 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_244 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_245 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_246 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_247 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_248 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_249 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_250 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_251 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_252 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_253 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_254 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_255 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_256 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_257 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_258 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_259 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_260 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_261 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_262 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_263 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_self_rec_rawIn_normDist_5 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_199 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_200 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_201 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_202 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_203 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_204 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_205 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_206 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_207 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_208 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_209 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_210 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_211 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_212 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_213 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_214 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_215 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_216 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_217 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_218 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_219 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_self_rec_rawIn_normDist_4 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_243 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_244 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_245 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_246 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_247 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_248 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_249 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_250 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_251 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_252 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_253 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_254 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_255 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_256 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_257 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_258 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_259 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_260 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_261 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_262 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_263 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_self_rec_rawIn_normDist_5 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_287 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_288 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_289 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_290 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_291 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_292 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_293 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_294 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_295 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_296 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_297 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_298 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_299 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_300 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_301 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_302 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_303 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_304 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_305 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_306 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_307 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_6 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_375 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_376 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_377 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_378 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_379 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_380 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_381 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_382 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_383 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_384 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_385 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_386 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_387 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_388 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_389 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_390 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_391 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_392 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_393 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_394 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_395 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_8 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_507 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_508 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_509 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_510 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_511 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_512 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_513 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_514 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_515 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_516 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_517 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_518 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_519 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_520 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_521 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_522 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_523 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_524 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_525 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_526 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_527 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_11 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_111 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_112 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_113 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_114 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_115 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_116 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_117 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_118 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_119 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_120 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_121 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_122 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_123 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_124 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_125 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_126 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_127 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_128 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_129 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_130 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_131 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_2 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_551 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_552 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_553 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_554 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_555 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_556 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_557 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_558 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_559 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_560 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_561 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_562 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_563 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_564 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_565 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_566 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_567 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_568 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_569 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_570 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_571 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_12 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_287 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_288 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_289 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_290 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_291 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_292 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_293 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_294 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_295 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_296 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_297 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_298 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_299 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_300 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_301 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_302 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_303 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_304 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_305 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_306 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_307 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_self_rec_rawIn_normDist_6 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_331 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_332 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_333 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_334 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_335 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_336 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_337 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_338 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_339 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_340 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_341 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_342 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_343 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_344 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_345 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_346 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_347 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_348 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_349 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_350 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_351 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_t_rec_rawIn_normDist_7 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_331 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_332 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_333 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_334 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_335 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_336 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_337 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_338 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_339 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_340 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_341 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_342 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_343 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_344 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_345 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_346 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_347 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_348 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_349 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_350 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_351 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_self_rec_rawIn_normDist_7 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_287 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_288 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_289 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_290 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_291 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_292 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_293 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_294 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_295 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_296 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_297 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_298 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_299 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_300 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_301 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_302 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_303 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_304 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_305 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_306 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_307 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_self_rec_rawIn_normDist_6 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_331 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_332 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_333 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_334 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_335 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_336 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_337 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_338 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_339 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_340 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_341 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_342 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_343 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_344 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_345 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_346 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_347 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_348 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_349 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_350 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_351 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_self_rec_rawIn_normDist_7 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_419 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_420 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_421 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_422 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_423 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_424 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_425 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_426 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_427 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_428 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_429 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_430 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_431 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_432 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_433 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_434 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_435 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_436 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_437 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_438 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_439 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_9 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_507 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_508 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_509 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_510 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_511 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_512 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_513 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_514 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_515 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_516 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_517 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_518 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_519 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_520 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_521 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_522 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_523 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_524 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_525 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_526 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_527 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_11 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_683 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_684 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_685 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_686 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_687 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_688 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_689 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_690 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_691 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_692 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_693 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_694 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_695 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_696 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_697 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_698 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_699 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_700 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_701 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_702 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_703 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_15 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_155 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_156 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_157 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_158 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_159 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_160 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_161 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_162 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_163 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_164 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_165 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_166 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_167 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_168 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_169 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_170 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_171 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_172 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_173 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_174 = 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_175 = 5'h16; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_3 = 5'h16; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_2 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_2 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_2 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_4 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_6 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_T = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_8 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_4 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_6 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_6 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_4 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_6 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_6 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_10 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_14 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_T_2 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_16 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_8 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_10 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_10 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_8 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_10 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_12 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_16 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_22 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_T_4 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_24 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_12 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_14 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_14 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_12 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_14 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_18 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_22 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_30 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [53:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_T_6 = 54'h0; // @[rawFloatFromFN.scala:52:33] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_1 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_1 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_3 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_3 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_1 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_3 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_1 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_5 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_7 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_T_1 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_9 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_5 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_7 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_7 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_5 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_7 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_7 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_11 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_15 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_T_3 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_17 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_9 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_11 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_11 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_9 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_11 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_13 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_17 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_23 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_T_5 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_25 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_13 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_15 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_T_15 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_13 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_T_15 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_19 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_23 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_31 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [21:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_T_7 = 22'h0; // @[rawFloatFromFN.scala:52:46] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_1 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_1 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_5 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_5 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_6 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_1 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_5 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_6 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_1 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_10 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_11 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_15 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_16 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_1 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_20 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_21 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_10 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_11 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_15 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_15 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_16 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_10 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_11 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_15 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_16 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_15 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_16 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_25 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_26 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_35 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_36 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_5 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_6 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_40 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_41 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_20 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_21 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_25 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_25 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_26 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_20 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_21 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_25 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_26 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_30 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_31 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_40 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_41 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_55 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_56 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_10 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_11 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_60 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_61 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_30 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_31 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_35 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_35 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_36 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_30 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_31 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_35 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_36 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_45 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_46 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_55 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_56 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_75 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_76 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_15 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_16 = 9'h1E9; // @[rawFloatFromFN.scala:54:10, :55:18] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_2 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_2 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T_1 = 2'h2; // @[rawFloatFromFN.scala:61:32] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_7 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_result_bits_rawIn_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_2 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_7 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_2 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_12 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_17 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_2 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_22 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_12 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T_3 = 2'h2; // @[rawFloatFromFN.scala:61:32] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_17 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_result_bits_rawIn_isSpecial_T_1 = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_12 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_17 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_17 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_27 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_37 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_7 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_42 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_22 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T_5 = 2'h2; // @[rawFloatFromFN.scala:61:32] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_27 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_result_bits_rawIn_isSpecial_T_2 = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_22 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_27 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_32 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_42 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_57 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_12 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_62 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_32 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T_7 = 2'h2; // @[rawFloatFromFN.scala:61:32] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_37 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_sign_result_bits_rawIn_isSpecial_T_3 = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_32 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_37 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_47 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_57 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_77 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_17 = 2'h2; // @[rawFloatFromFN.scala:58:14] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_3 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_3 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_8 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_3 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_8 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_3 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_13 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_18 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_3 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_23 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_13 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_18 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_13 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_18 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_18 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_28 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_38 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_8 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_43 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_23 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_28 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_23 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_28 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_33 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_43 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_58 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_13 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_63 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_33 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_38 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_33 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_38 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_48 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_58 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_78 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [7:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_18 = 8'h82; // @[rawFloatFromFN.scala:58:9] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_4 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_4 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_9 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_4 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_9 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_4 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_14 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_19 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_4 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_24 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_14 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_19 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_14 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_19 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_19 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_29 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_39 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_9 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_44 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_24 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_29 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_24 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_29 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_34 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_44 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_59 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_14 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_64 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_34 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_T_39 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_34 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_T_39 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_49 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_59 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_79 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_T_19 = 10'h26B; // @[rawFloatFromFN.scala:57:9] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_1 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_2 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_1 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_2 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_2 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_4 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_3 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_6 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sExp_T = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_4 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_8 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_2 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_4 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_3 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_6 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_2 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_4 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_3 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_6 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_3 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_6 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_5 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_10 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_7 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_14 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_1 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sExp_T_2 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_8 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_16 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_4 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_8 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_5 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_10 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_4 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_8 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_5 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_10 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_6 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_12 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_8 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_16 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_11 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_22 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_2 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sExp_T_4 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_12 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_24 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_6 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_12 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_sign_self_rec_rawIn_adjustedExp_7 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_14 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_6 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_12 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_abs_self_rec_rawIn_adjustedExp_7 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_14 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_9 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_18 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_11 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_22 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_15 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_30 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_adjustedExp_3 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [8:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sExp_T_6 = 9'h6B; // @[rawFloatFromFN.scala:57:9, :68:28] wire [9:0] activated_data_e_act_t_rec_rawIn_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_1 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_sign_self_rec_rawIn_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_1 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_sign_self_rec_rawIn_1_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_3 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_abs_self_rec_rawIn_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_1 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_abs_self_rec_rawIn_1_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_3 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_1 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_2_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_5 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_t_rec_rawIn_3_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_7 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sExp_T_1 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_t_rec_rawIn_4_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_9 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_sign_self_rec_rawIn_2_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_5 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_sign_self_rec_rawIn_3_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_7 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_abs_self_rec_rawIn_2_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_5 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_abs_self_rec_rawIn_3_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_7 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_3_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_7 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_5_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_11 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_t_rec_rawIn_7_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_15 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_1_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sExp_T_3 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_t_rec_rawIn_8_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_17 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_sign_self_rec_rawIn_4_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_9 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_sign_self_rec_rawIn_5_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_11 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_abs_self_rec_rawIn_4_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_9 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_abs_self_rec_rawIn_5_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_11 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_6_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_13 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_8_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_17 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_t_rec_rawIn_11_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_23 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_2_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sExp_T_5 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_t_rec_rawIn_12_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_25 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_sign_self_rec_rawIn_6_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_13 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_sign_self_rec_rawIn_7_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sExp_T_15 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_abs_self_rec_rawIn_6_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_13 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_abs_self_rec_rawIn_7_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sExp_T_15 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_9_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_19 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_11_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_23 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_t_rec_rawIn_15_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_31 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_3_sExp = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sExp_T_7 = 10'h6B; // @[rawFloatFromFN.scala:63:19, :68:42] wire [24:0] activated_data_e_act_t_rec_rawIn_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_3 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_sign_self_rec_rawIn_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_3 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_sign_self_rec_rawIn_1_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_7 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_abs_self_rec_rawIn_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_3 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_abs_self_rec_rawIn_1_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_7 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_3 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_2_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_11 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_t_rec_rawIn_3_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_15 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_3 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_t_rec_rawIn_4_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_19 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_sign_self_rec_rawIn_2_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_11 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_sign_self_rec_rawIn_3_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_15 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_abs_self_rec_rawIn_2_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_11 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_abs_self_rec_rawIn_3_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_15 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_3_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_15 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_5_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_23 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_t_rec_rawIn_7_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_31 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_1_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_7 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_t_rec_rawIn_8_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_35 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_sign_self_rec_rawIn_4_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_19 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_sign_self_rec_rawIn_5_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_23 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_abs_self_rec_rawIn_4_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_19 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_abs_self_rec_rawIn_5_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_23 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_6_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_27 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_8_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_35 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_t_rec_rawIn_11_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_47 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_2_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_11 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_t_rec_rawIn_12_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_51 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_sign_self_rec_rawIn_6_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_27 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_sign_self_rec_rawIn_7_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_31 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_abs_self_rec_rawIn_6_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_27 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_abs_self_rec_rawIn_7_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_31 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_9_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_39 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_11_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_47 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_t_rec_rawIn_15_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_63 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_3_sig = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [24:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_15 = 25'h0; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_t_rec_T = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_self_rec_T = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_8 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_self_rec_T = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_8 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_16 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_24 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_32 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_16 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_24 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_16 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_24 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_24 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_40 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_56 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_8 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_64 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_32 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_40 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_32 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_40 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_48 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_64 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_88 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_16 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_96 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_48 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_56 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_48 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_56 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_72 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_88 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_120 = 3'h1; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_24 = 3'h1; // @[recFNFromFN.scala:48:50] wire [3:0] _activated_data_e_act_q_sign_self_rec_T_4 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_sign_self_rec_T_12 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_abs_self_rec_T_4 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_abs_self_rec_T_12 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_4 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_20 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_neg_q_iexp_self_rec_T_4 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_sign_self_rec_T_20 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_sign_self_rec_T_28 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_abs_self_rec_T_20 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_abs_self_rec_T_28 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_28 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_44 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_neg_q_iexp_self_rec_T_12 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_sign_self_rec_T_36 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_sign_self_rec_T_44 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_abs_self_rec_T_36 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_abs_self_rec_T_44 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_52 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_68 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_neg_q_iexp_self_rec_T_20 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_sign_self_rec_T_52 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_sign_self_rec_T_60 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_abs_self_rec_T_52 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_abs_self_rec_T_60 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_76 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_92 = 4'h0; // @[recFNFromFN.scala:47:20] wire [3:0] _activated_data_e_act_neg_q_iexp_self_rec_T_28 = 4'h0; // @[recFNFromFN.scala:47:20] wire [5:0] _activated_data_e_act_t_rec_T_5 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_self_rec_T_5 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_self_rec_T_13 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_abs_self_rec_T_5 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_abs_self_rec_T_13 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_5 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_21 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_t_rec_T_29 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_neg_q_iexp_self_rec_T_5 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_t_rec_T_37 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_self_rec_T_21 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_self_rec_T_29 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_abs_self_rec_T_21 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_abs_self_rec_T_29 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_29 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_45 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_t_rec_T_61 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_neg_q_iexp_self_rec_T_13 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_t_rec_T_69 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_self_rec_T_37 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_self_rec_T_45 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_abs_self_rec_T_37 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_abs_self_rec_T_45 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_53 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_69 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_t_rec_T_93 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_neg_q_iexp_self_rec_T_21 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_t_rec_T_101 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_self_rec_T_53 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_sign_self_rec_T_61 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_abs_self_rec_T_53 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_abs_self_rec_T_61 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_77 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_93 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_t_rec_T_125 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [5:0] _activated_data_e_act_neg_q_iexp_self_rec_T_29 = 6'h2B; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_sign_self_rec_T_6 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_sign_self_rec_T_14 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_abs_self_rec_T_6 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_abs_self_rec_T_14 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_6 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_22 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_T_6 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_sign_self_rec_T_22 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_sign_self_rec_T_30 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_abs_self_rec_T_22 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_abs_self_rec_T_30 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_30 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_46 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_T_14 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_sign_self_rec_T_38 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_sign_self_rec_T_46 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_abs_self_rec_T_38 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_abs_self_rec_T_46 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_54 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_70 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_T_22 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_sign_self_rec_T_54 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_sign_self_rec_T_62 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_abs_self_rec_T_54 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_abs_self_rec_T_62 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_78 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_94 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [9:0] _activated_data_e_act_neg_q_iexp_self_rec_T_30 = 10'h2B; // @[recFNFromFN.scala:49:45] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_2 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_t_rec_T_7 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_fractIn = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_subnormFract = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_2 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_self_rec_T_7 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_fractIn_1 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_1 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_6 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_t_rec_T_15 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_fractIn_1 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_1 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_6 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_self_rec_T_15 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _activated_data_e_act_q_sign_result_bits_fractOut_T = 23'h0; // @[fNFromRecFN.scala:64:48] wire [22:0] _activated_data_e_act_q_sign_result_bits_fractOut_T_1 = 23'h0; // @[fNFromRecFN.scala:64:20] wire [22:0] activated_data_e_act_q_sign_result_bits_fractOut = 23'h0; // @[fNFromRecFN.scala:62:16] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_fractIn = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_subnormFract = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_2 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_abs_self_rec_T_7 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_fractIn_1 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_1 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_6 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_abs_self_rec_T_15 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_2 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_7 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_2 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_2 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_10 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_23 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_3 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_3 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_14 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_t_rec_T_31 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_fractIn = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_2 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_neg_q_iexp_self_rec_T_7 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_4 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_4 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_18 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_t_rec_T_39 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_fractIn_2 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_2 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_10 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_self_rec_T_23 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_fractIn_3 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_3 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_14 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_t_rec_T_31 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_fractIn_3 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_3 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_14 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_self_rec_T_31 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_6 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _activated_data_e_act_q_sign_result_bits_fractOut_T_2 = 23'h0; // @[fNFromRecFN.scala:64:48] wire [22:0] _activated_data_e_act_q_sign_result_bits_fractOut_T_3 = 23'h0; // @[fNFromRecFN.scala:64:20] wire [22:0] activated_data_e_act_q_sign_result_bits_fractOut_1 = 23'h0; // @[fNFromRecFN.scala:62:16] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_fractIn_2 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_2 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_10 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_abs_self_rec_T_23 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_fractIn_3 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_3 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_14 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_abs_self_rec_T_31 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_3 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_3 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_14 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_31 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_5 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_5 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_22 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_47 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_7 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_7 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_30 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_t_rec_T_63 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_fractIn_1 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_1 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_6 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_neg_q_iexp_self_rec_T_15 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_8 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_8 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_34 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_t_rec_T_71 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_fractIn_4 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_4 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_18 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_self_rec_T_39 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_fractIn_5 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_5 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_22 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_t_rec_T_47 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_fractIn_5 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_5 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_22 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_self_rec_T_47 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_10 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _activated_data_e_act_q_sign_result_bits_fractOut_T_4 = 23'h0; // @[fNFromRecFN.scala:64:48] wire [22:0] _activated_data_e_act_q_sign_result_bits_fractOut_T_5 = 23'h0; // @[fNFromRecFN.scala:64:20] wire [22:0] activated_data_e_act_q_sign_result_bits_fractOut_2 = 23'h0; // @[fNFromRecFN.scala:62:16] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_fractIn_4 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_4 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_18 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_abs_self_rec_T_39 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_fractIn_5 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_5 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_22 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_abs_self_rec_T_47 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_6 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_6 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_26 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_55 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_8 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_8 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_34 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_71 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_11 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_11 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_46 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_t_rec_T_95 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_fractIn_2 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_2 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_10 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_neg_q_iexp_self_rec_T_23 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_12 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_12 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_50 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_t_rec_T_103 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_fractIn_6 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_6 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_26 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_self_rec_T_55 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_fractIn_7 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_7 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_30 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_t_rec_T_63 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_fractIn_7 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_self_rec_rawIn_subnormFract_7 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_30 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_sign_self_rec_T_63 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_14 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _activated_data_e_act_q_sign_result_bits_fractOut_T_6 = 23'h0; // @[fNFromRecFN.scala:64:48] wire [22:0] _activated_data_e_act_q_sign_result_bits_fractOut_T_7 = 23'h0; // @[fNFromRecFN.scala:64:20] wire [22:0] activated_data_e_act_q_sign_result_bits_fractOut_3 = 23'h0; // @[fNFromRecFN.scala:62:16] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_fractIn_6 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_6 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_26 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_abs_self_rec_T_55 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_fractIn_7 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_self_rec_rawIn_subnormFract_7 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_30 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_abs_self_rec_T_63 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_9 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_9 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_38 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_79 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_11 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_11 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_46 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_95 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_15 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_15 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_62 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_t_rec_T_127 = 23'h0; // @[recFNFromFN.scala:51:22] wire [22:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_fractIn_3 = 23'h0; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_neg_q_iexp_self_rec_rawIn_subnormFract_3 = 23'h0; // @[rawFloatFromFN.scala:52:64] wire [22:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_14 = 23'h0; // @[rawFloatFromFN.scala:70:33] wire [22:0] _activated_data_e_act_neg_q_iexp_self_rec_T_31 = 23'h0; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_sign_self_rec = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_sign_self_rec_1 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_abs_self_rec = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_abs_self_rec_1 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_clipped_self_rec = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_clipped_self_rec_2 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_neg_q_iexp_self_rec = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_sign_self_rec_2 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_sign_self_rec_3 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_abs_self_rec_2 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_abs_self_rec_3 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_clipped_self_rec_3 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_clipped_self_rec_5 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_neg_q_iexp_self_rec_1 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_sign_self_rec_4 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_sign_self_rec_5 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_abs_self_rec_4 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_abs_self_rec_5 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_clipped_self_rec_6 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_clipped_self_rec_8 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_neg_q_iexp_self_rec_2 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_sign_self_rec_6 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_sign_self_rec_7 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_abs_self_rec_6 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_abs_self_rec_7 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_clipped_self_rec_9 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_q_clipped_self_rec_11 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [32:0] activated_data_e_act_neg_q_iexp_self_rec_3 = 33'h15800000; // @[recFNFromFN.scala:50:41] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_bits = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_1_bits = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_2_bits = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_3_bits = 32'h20; // @[AccumulatorScale.scala:400:92] wire [4:0] _activated_data_e_act_q_sign_result_bits_denormShiftDist_T = 5'h0; // @[fNFromRecFN.scala:52:47] wire [4:0] _activated_data_e_act_q_sign_result_bits_denormShiftDist_T_2 = 5'h0; // @[fNFromRecFN.scala:52:47] wire [4:0] _activated_data_e_act_q_sign_result_bits_denormShiftDist_T_4 = 5'h0; // @[fNFromRecFN.scala:52:47] wire [4:0] _activated_data_e_act_q_sign_result_bits_denormShiftDist_T_6 = 5'h0; // @[fNFromRecFN.scala:52:47] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_1 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_T = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_1 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_T_1 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_5 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_T = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_1 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_T_1 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_5 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_1 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_2 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_9 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_3 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_13 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_isSpecial_T = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_1 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_4 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_17 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_T_2 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_9 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_T_3 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_13 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_T_2 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_9 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_T_3 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_13 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_3 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_13 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_5 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_21 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_7 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_29 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_isSpecial_T_1 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_5 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_8 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_33 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_T_4 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_17 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_T_5 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_21 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_T_4 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_17 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_T_5 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_21 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_6 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_25 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_8 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_33 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_11 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_45 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_isSpecial_T_2 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_9 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_12 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_49 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_T_6 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_25 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_T_7 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_29 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_T_6 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_25 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_T_7 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_29 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_9 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_37 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_11 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_45 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_15 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_61 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_isSpecial_T_3 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire [1:0] _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_13 = 2'h0; // @[rawFloatFromFN.scala:61:32, :70:16] wire _activated_data_e_act_T_2 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_4 = 1'h0; // @[AccumulatorScale.scala:119:62] wire activated_data_e_act_t_sgn = 1'h0; // @[Arithmetic.scala:432:27] wire _activated_data_e_act_t_rec_rawIn_normDist_T = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_2 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_3 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_4 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_5 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_6 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_7 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_8 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_9 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_10 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_11 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_12 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_13 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_14 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_15 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_16 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_17 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_18 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_19 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_20 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_21 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_22 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_t_rec_rawIn_isSpecial = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_t_rec_rawIn_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_1 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_rawIn_out_sig_T = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_t_rec_T_2 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_act_T_5 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_7 = 1'h0; // @[AccumulatorScale.scala:121:62] wire activated_data_e_act_q_sign_self_rec_rawIn_sign = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_2 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_3 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_4 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_5 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_6 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_7 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_8 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_9 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_10 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_11 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_12 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_13 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_14 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_15 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_16 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_17 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_18 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_19 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_20 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_21 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_22 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_self_rec_rawIn_isSpecial = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_self_rec_rawIn_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_sign_0 = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_1 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isInf_T = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_sign_self_rec_T_2 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_t_sgn = 1'h0; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_1 = 1'h0; // @[rawFloatFromFN.scala:48:30] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_44 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_45 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_46 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_47 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_48 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_49 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_50 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_51 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_52 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_53 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_54 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_55 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_56 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_57 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_58 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_59 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_60 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_61 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_62 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_63 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_64 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_65 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_66 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_t_rec_rawIn_isZero_1 = 1'h0; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_1 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_t_rec_rawIn_1_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_1_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_1_isZero = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_2 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_3 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_1 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_t_rec_T_10 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_self_rec_rawIn_sign_1 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_44 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_45 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_46 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_47 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_48 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_49 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_50 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_51 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_52 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_53 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_54 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_55 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_56 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_57 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_58 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_59 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_60 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_61 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_62 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_63 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_64 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_65 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_66 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_1 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_self_rec_rawIn_1_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_1_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_1_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_2 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_3 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isInf_T_1 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_4 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_sign_self_rec_T_10 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_result_bits_rawIn_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire activated_data_e_act_q_sign_result_bits_rawIn_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire activated_data_e_act_q_sign_result_bits_rawIn_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_sign_result_bits_rawIn_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_sign_result_bits_rawIn_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire activated_data_e_act_q_sign_result_bits_isSubnormal = 1'h0; // @[fNFromRecFN.scala:51:38] wire _activated_data_e_act_q_sign_result_bits_expOut_T_4 = 1'h0; // @[fNFromRecFN.scala:60:44] wire activated_data_e_act_q_abs_self_rec_rawIn_sign = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_2 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_3 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_4 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_5 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_6 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_7 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_8 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_9 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_10 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_11 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_12 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_13 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_14 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_15 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_16 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_17 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_18 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_19 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_20 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_21 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_22 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_abs_self_rec_rawIn_isSpecial = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_abs_self_rec_rawIn_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_sign_0 = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_1 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isInf_T = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_abs_self_rec_T_2 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_abs_self_rec_rawIn_sign_1 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_44 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_45 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_46 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_47 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_48 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_49 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_50 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_51 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_52 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_53 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_54 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_55 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_56 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_57 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_58 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_59 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_60 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_61 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_62 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_63 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_64 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_65 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_66 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_1 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_abs_self_rec_rawIn_1_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_1_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_1_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_2 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_3 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isInf_T_1 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_4 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_abs_self_rec_T_10 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_2 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_3 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_4 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_5 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_6 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_7 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_8 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_9 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_10 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_11 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_12 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_13 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_14 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_15 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_16 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_17 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_18 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_19 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_20 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_21 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_22 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_clipped_self_rec_rawIn_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_0 = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_1 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_clipped_self_rec_T_2 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_2 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_88 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_89 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_90 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_91 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_92 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_93 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_94 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_95 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_96 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_97 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_98 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_99 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_100 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_101 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_102 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_103 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_104 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_105 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_106 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_107 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_108 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_109 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_110 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_2 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_clipped_self_rec_rawIn_2_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_2_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_2_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_4 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_5 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_2 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_8 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_clipped_self_rec_T_18 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_act_T_8 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_10 = 1'h0; // @[AccumulatorScale.scala:123:62] wire activated_data_e_act_t_sgn_1 = 1'h0; // @[Arithmetic.scala:432:27] wire _activated_data_e_act_t_rec_rawIn_normDist_T_132 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_133 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_134 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_135 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_136 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_137 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_138 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_139 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_140 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_141 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_142 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_143 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_144 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_145 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_146 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_147 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_148 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_149 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_150 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_151 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_152 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_153 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_154 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_t_rec_rawIn_isSpecial_3 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_t_rec_rawIn_3_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_3_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_6 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_7 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_3 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_12 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_t_rec_T_26 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_sign = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_2 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_3 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_4 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_5 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_6 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_7 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_8 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_9 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_10 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_11 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_12 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_13 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_14 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_15 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_16 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_17 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_18 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_19 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_20 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_21 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_22 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isSpecial = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_sign_0 = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isNaN_T = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isNaN_T_1 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isInf_T = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_neg_q_iexp_self_rec_T_2 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_scaled_T = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_2 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_3 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_5 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_18 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_20 = 1'h0; // @[AccumulatorScale.scala:119:62] wire activated_data_e_act_t_sgn_2 = 1'h0; // @[Arithmetic.scala:432:27] wire _activated_data_e_act_t_rec_rawIn_normDist_T_176 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_177 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_178 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_179 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_180 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_181 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_182 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_183 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_184 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_185 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_186 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_187 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_188 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_189 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_190 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_191 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_192 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_193 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_194 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_195 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_196 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_197 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_198 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_t_rec_rawIn_isSpecial_4 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_t_rec_rawIn_4_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_4_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_8 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_9 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_4 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_16 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_t_rec_T_34 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_act_T_21 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_23 = 1'h0; // @[AccumulatorScale.scala:121:62] wire activated_data_e_act_q_sign_self_rec_rawIn_sign_2 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_88 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_89 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_90 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_91 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_92 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_93 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_94 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_95 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_96 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_97 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_98 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_99 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_100 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_101 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_102 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_103 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_104 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_105 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_106 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_107 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_108 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_109 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_110 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_2 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_self_rec_rawIn_2_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_2_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_2_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_4 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_5 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isInf_T_2 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_8 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_sign_self_rec_T_18 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_t_sgn_1 = 1'h0; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_3 = 1'h0; // @[rawFloatFromFN.scala:48:30] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_132 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_133 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_134 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_135 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_136 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_137 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_138 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_139 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_140 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_141 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_142 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_143 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_144 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_145 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_146 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_147 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_148 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_149 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_150 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_151 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_152 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_153 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_154 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_t_rec_rawIn_isZero_3 = 1'h0; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_3 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_t_rec_rawIn_3_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_3_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_3_isZero = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_6 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_7 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_3 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_t_rec_T_26 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_self_rec_rawIn_sign_3 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_132 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_133 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_134 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_135 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_136 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_137 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_138 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_139 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_140 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_141 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_142 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_143 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_144 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_145 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_146 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_147 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_148 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_149 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_150 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_151 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_152 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_153 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_154 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_3 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_self_rec_rawIn_3_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_3_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_3_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_6 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_7 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isInf_T_3 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_12 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_sign_self_rec_T_26 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_result_bits_rawIn_isZero_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire activated_data_e_act_q_sign_result_bits_rawIn_isSpecial_1 = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire activated_data_e_act_q_sign_result_bits_rawIn_1_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_sign_result_bits_rawIn_1_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_sign_result_bits_rawIn_1_isZero = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isNaN_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isNaN_T_3 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_3 = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_5 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire activated_data_e_act_q_sign_result_bits_isSubnormal_1 = 1'h0; // @[fNFromRecFN.scala:51:38] wire _activated_data_e_act_q_sign_result_bits_expOut_T_10 = 1'h0; // @[fNFromRecFN.scala:60:44] wire activated_data_e_act_q_abs_self_rec_rawIn_sign_2 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_88 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_89 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_90 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_91 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_92 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_93 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_94 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_95 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_96 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_97 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_98 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_99 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_100 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_101 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_102 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_103 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_104 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_105 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_106 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_107 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_108 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_109 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_110 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_2 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_abs_self_rec_rawIn_2_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_2_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_2_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_4 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_5 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isInf_T_2 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_8 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_abs_self_rec_T_18 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_abs_self_rec_rawIn_sign_3 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_132 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_133 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_134 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_135 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_136 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_137 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_138 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_139 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_140 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_141 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_142 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_143 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_144 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_145 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_146 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_147 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_148 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_149 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_150 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_151 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_152 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_153 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_154 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_3 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_abs_self_rec_rawIn_3_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_3_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_3_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_6 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_7 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isInf_T_3 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_12 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_abs_self_rec_T_26 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_3 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_132 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_133 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_134 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_135 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_136 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_137 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_138 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_139 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_140 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_141 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_142 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_143 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_144 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_145 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_146 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_147 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_148 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_149 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_150 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_151 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_152 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_153 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_154 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_3 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_clipped_self_rec_rawIn_3_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_3_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_3_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_6 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_7 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_3 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_12 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_clipped_self_rec_T_26 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_5 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_220 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_221 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_222 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_223 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_224 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_225 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_226 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_227 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_228 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_229 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_230 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_231 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_232 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_233 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_234 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_235 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_236 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_237 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_238 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_239 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_240 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_241 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_242 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_5 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_clipped_self_rec_rawIn_5_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_5_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_5_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_10 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_11 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_5 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_20 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_clipped_self_rec_T_42 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_act_T_24 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_26 = 1'h0; // @[AccumulatorScale.scala:123:62] wire activated_data_e_act_t_sgn_3 = 1'h0; // @[Arithmetic.scala:432:27] wire _activated_data_e_act_t_rec_rawIn_normDist_T_308 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_309 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_310 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_311 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_312 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_313 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_314 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_315 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_316 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_317 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_318 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_319 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_320 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_321 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_322 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_323 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_324 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_325 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_326 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_327 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_328 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_329 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_330 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_t_rec_rawIn_isSpecial_7 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_t_rec_rawIn_7_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_7_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_14 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_15 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_7 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_28 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_t_rec_T_58 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_sign_1 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_44 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_45 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_46 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_47 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_48 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_49 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_50 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_51 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_52 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_53 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_54 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_55 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_56 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_57 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_58 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_59 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_60 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_61 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_62 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_63 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_64 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_65 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_66 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isSpecial_1 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_1_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_1_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_1_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isNaN_T_2 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isNaN_T_3 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isInf_T_1 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_4 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_neg_q_iexp_self_rec_T_10 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_scaled_T_10 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_12 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_13 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_15 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_34 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_36 = 1'h0; // @[AccumulatorScale.scala:119:62] wire activated_data_e_act_t_sgn_4 = 1'h0; // @[Arithmetic.scala:432:27] wire _activated_data_e_act_t_rec_rawIn_normDist_T_352 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_353 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_354 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_355 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_356 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_357 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_358 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_359 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_360 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_361 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_362 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_363 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_364 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_365 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_366 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_367 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_368 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_369 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_370 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_371 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_372 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_373 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_374 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_t_rec_rawIn_isSpecial_8 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_t_rec_rawIn_8_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_8_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_16 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_17 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_8 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_32 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_t_rec_T_66 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_act_T_37 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_39 = 1'h0; // @[AccumulatorScale.scala:121:62] wire activated_data_e_act_q_sign_self_rec_rawIn_sign_4 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_176 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_177 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_178 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_179 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_180 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_181 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_182 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_183 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_184 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_185 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_186 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_187 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_188 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_189 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_190 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_191 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_192 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_193 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_194 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_195 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_196 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_197 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_198 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_4 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_self_rec_rawIn_4_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_4_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_4_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_8 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_9 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isInf_T_4 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_16 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_sign_self_rec_T_34 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_t_sgn_2 = 1'h0; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_5 = 1'h0; // @[rawFloatFromFN.scala:48:30] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_220 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_221 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_222 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_223 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_224 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_225 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_226 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_227 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_228 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_229 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_230 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_231 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_232 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_233 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_234 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_235 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_236 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_237 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_238 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_239 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_240 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_241 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_242 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_t_rec_rawIn_isZero_5 = 1'h0; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_5 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_t_rec_rawIn_5_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_5_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_5_isZero = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_10 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_11 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_5 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_t_rec_T_42 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_self_rec_rawIn_sign_5 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_220 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_221 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_222 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_223 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_224 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_225 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_226 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_227 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_228 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_229 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_230 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_231 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_232 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_233 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_234 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_235 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_236 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_237 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_238 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_239 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_240 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_241 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_242 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_5 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_self_rec_rawIn_5_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_5_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_5_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_10 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_11 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isInf_T_5 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_20 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_sign_self_rec_T_42 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_result_bits_rawIn_isZero_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire activated_data_e_act_q_sign_result_bits_rawIn_isSpecial_2 = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire activated_data_e_act_q_sign_result_bits_rawIn_2_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_sign_result_bits_rawIn_2_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_sign_result_bits_rawIn_2_isZero = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isNaN_T_4 = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isNaN_T_5 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_6 = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_8 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire activated_data_e_act_q_sign_result_bits_isSubnormal_2 = 1'h0; // @[fNFromRecFN.scala:51:38] wire _activated_data_e_act_q_sign_result_bits_expOut_T_16 = 1'h0; // @[fNFromRecFN.scala:60:44] wire activated_data_e_act_q_abs_self_rec_rawIn_sign_4 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_176 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_177 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_178 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_179 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_180 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_181 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_182 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_183 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_184 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_185 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_186 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_187 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_188 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_189 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_190 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_191 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_192 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_193 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_194 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_195 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_196 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_197 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_198 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_4 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_abs_self_rec_rawIn_4_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_4_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_4_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_8 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_9 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isInf_T_4 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_16 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_abs_self_rec_T_34 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_abs_self_rec_rawIn_sign_5 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_220 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_221 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_222 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_223 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_224 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_225 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_226 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_227 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_228 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_229 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_230 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_231 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_232 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_233 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_234 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_235 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_236 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_237 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_238 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_239 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_240 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_241 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_242 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_5 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_abs_self_rec_rawIn_5_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_5_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_5_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_10 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_11 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isInf_T_5 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_20 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_abs_self_rec_T_42 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_6 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_264 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_265 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_266 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_267 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_268 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_269 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_270 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_271 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_272 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_273 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_274 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_275 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_276 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_277 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_278 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_279 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_280 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_281 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_282 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_283 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_284 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_285 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_286 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_6 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_clipped_self_rec_rawIn_6_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_6_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_6_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_12 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_13 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_6 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_24 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_clipped_self_rec_T_50 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_8 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_352 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_353 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_354 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_355 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_356 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_357 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_358 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_359 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_360 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_361 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_362 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_363 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_364 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_365 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_366 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_367 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_368 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_369 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_370 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_371 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_372 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_373 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_374 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_8 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_clipped_self_rec_rawIn_8_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_8_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_8_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_16 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_17 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_8 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_32 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_clipped_self_rec_T_66 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_act_T_40 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_42 = 1'h0; // @[AccumulatorScale.scala:123:62] wire activated_data_e_act_t_sgn_5 = 1'h0; // @[Arithmetic.scala:432:27] wire _activated_data_e_act_t_rec_rawIn_normDist_T_484 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_485 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_486 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_487 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_488 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_489 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_490 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_491 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_492 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_493 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_494 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_495 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_496 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_497 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_498 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_499 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_500 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_501 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_502 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_503 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_504 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_505 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_506 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_t_rec_rawIn_isSpecial_11 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_t_rec_rawIn_11_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_11_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_22 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_23 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_11 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_44 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_t_rec_T_90 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_sign_2 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_88 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_89 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_90 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_91 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_92 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_93 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_94 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_95 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_96 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_97 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_98 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_99 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_100 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_101 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_102 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_103 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_104 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_105 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_106 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_107 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_108 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_109 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_110 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isSpecial_2 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_2_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_2_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_2_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isNaN_T_4 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isNaN_T_5 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isInf_T_2 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_8 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_neg_q_iexp_self_rec_T_18 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_scaled_T_20 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_22 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_23 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_25 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_50 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_52 = 1'h0; // @[AccumulatorScale.scala:119:62] wire activated_data_e_act_t_sgn_6 = 1'h0; // @[Arithmetic.scala:432:27] wire _activated_data_e_act_t_rec_rawIn_normDist_T_528 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_529 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_530 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_531 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_532 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_533 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_534 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_535 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_536 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_537 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_538 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_539 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_540 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_541 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_542 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_543 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_544 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_545 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_546 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_547 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_548 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_549 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_550 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_t_rec_rawIn_isSpecial_12 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_t_rec_rawIn_12_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_12_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_24 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_25 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_12 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_48 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_t_rec_T_98 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_act_T_53 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_55 = 1'h0; // @[AccumulatorScale.scala:121:62] wire activated_data_e_act_q_sign_self_rec_rawIn_sign_6 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_264 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_265 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_266 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_267 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_268 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_269 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_270 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_271 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_272 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_273 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_274 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_275 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_276 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_277 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_278 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_279 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_280 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_281 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_282 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_283 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_284 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_285 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_286 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_6 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_self_rec_rawIn_6_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_6_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_6_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_12 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_13 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isInf_T_6 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_24 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_sign_self_rec_T_50 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_t_sgn_3 = 1'h0; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_7 = 1'h0; // @[rawFloatFromFN.scala:48:30] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_308 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_309 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_310 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_311 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_312 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_313 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_314 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_315 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_316 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_317 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_318 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_319 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_320 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_321 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_322 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_323 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_324 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_325 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_326 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_327 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_328 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_329 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_330 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_t_rec_rawIn_isZero_7 = 1'h0; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_7 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_t_rec_rawIn_7_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_7_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_7_isZero = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_14 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_15 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_7 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_t_rec_T_58 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_self_rec_rawIn_sign_7 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_308 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_309 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_310 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_311 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_312 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_313 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_314 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_315 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_316 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_317 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_318 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_319 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_320 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_321 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_322 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_323 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_324 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_325 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_326 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_327 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_328 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_329 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_sign_self_rec_rawIn_normDist_T_330 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_sign_self_rec_rawIn_isSpecial_7 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_sign_self_rec_rawIn_7_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_7_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_7_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_14 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isNaN_T_15 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_isInf_T_7 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_self_rec_rawIn_out_sig_T_28 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_sign_self_rec_T_58 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_sign_result_bits_rawIn_isZero_3 = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire activated_data_e_act_q_sign_result_bits_rawIn_isSpecial_3 = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire activated_data_e_act_q_sign_result_bits_rawIn_3_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_sign_result_bits_rawIn_3_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_sign_result_bits_rawIn_3_isZero = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isNaN_T_6 = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isNaN_T_7 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_9 = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_11 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire activated_data_e_act_q_sign_result_bits_isSubnormal_3 = 1'h0; // @[fNFromRecFN.scala:51:38] wire _activated_data_e_act_q_sign_result_bits_expOut_T_22 = 1'h0; // @[fNFromRecFN.scala:60:44] wire activated_data_e_act_q_abs_self_rec_rawIn_sign_6 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_264 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_265 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_266 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_267 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_268 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_269 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_270 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_271 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_272 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_273 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_274 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_275 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_276 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_277 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_278 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_279 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_280 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_281 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_282 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_283 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_284 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_285 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_286 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_6 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_abs_self_rec_rawIn_6_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_6_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_6_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_12 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_13 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isInf_T_6 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_24 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_abs_self_rec_T_50 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_abs_self_rec_rawIn_sign_7 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_308 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_309 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_310 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_311 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_312 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_313 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_314 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_315 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_316 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_317 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_318 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_319 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_320 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_321 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_322 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_323 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_324 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_325 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_326 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_327 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_328 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_329 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_abs_self_rec_rawIn_normDist_T_330 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_abs_self_rec_rawIn_isSpecial_7 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_abs_self_rec_rawIn_7_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_7_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_7_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_14 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isNaN_T_15 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_isInf_T_7 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_self_rec_rawIn_out_sig_T_28 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_abs_self_rec_T_58 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_9 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_396 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_397 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_398 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_399 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_400 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_401 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_402 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_403 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_404 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_405 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_406 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_407 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_408 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_409 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_410 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_411 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_412 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_413 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_414 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_415 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_416 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_417 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_418 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_9 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_clipped_self_rec_rawIn_9_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_9_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_9_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_18 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_19 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_9 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_36 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_clipped_self_rec_T_74 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_11 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_484 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_485 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_486 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_487 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_488 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_489 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_490 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_491 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_492 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_493 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_494 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_495 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_496 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_497 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_498 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_499 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_500 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_501 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_502 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_503 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_504 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_505 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_506 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_11 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_q_clipped_self_rec_rawIn_11_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_11_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_11_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_22 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_23 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_11 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_44 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_q_clipped_self_rec_T_90 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_act_T_56 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_58 = 1'h0; // @[AccumulatorScale.scala:123:62] wire activated_data_e_act_t_sgn_7 = 1'h0; // @[Arithmetic.scala:432:27] wire _activated_data_e_act_t_rec_rawIn_normDist_T_660 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_661 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_662 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_663 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_664 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_665 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_666 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_667 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_668 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_669 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_670 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_671 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_672 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_673 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_674 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_675 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_676 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_677 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_678 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_679 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_680 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_681 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_t_rec_rawIn_normDist_T_682 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_t_rec_rawIn_isSpecial_15 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_t_rec_rawIn_15_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_15_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_30 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_31 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_15 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_60 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_t_rec_T_122 = 1'h0; // @[recFNFromFN.scala:49:20] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_sign_3 = 1'h0; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_132 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_133 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_134 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_135 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_136 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_137 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_138 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_139 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_140 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_141 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_142 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_143 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_144 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_145 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_146 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_147 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_148 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_149 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_150 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_151 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_152 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_153 = 1'h0; // @[primitives.scala:91:52] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_normDist_T_154 = 1'h0; // @[primitives.scala:91:52] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isSpecial_3 = 1'h0; // @[rawFloatFromFN.scala:61:57] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_3_isNaN = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_3_isInf = 1'h0; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_3_sign = 1'h0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isNaN_T_6 = 1'h0; // @[rawFloatFromFN.scala:64:31] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isNaN_T_7 = 1'h0; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_isInf_T_3 = 1'h0; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_neg_q_iexp_self_rec_rawIn_out_sig_T_12 = 1'h0; // @[rawFloatFromFN.scala:70:19] wire _activated_data_e_act_neg_q_iexp_self_rec_T_26 = 1'h0; // @[recFNFromFN.scala:49:20] wire _activated_data_e_scaled_T_30 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_32 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_33 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_35 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_neg_t_T = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_t_rec_rawIn_sign = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_t_rec_rawIn_isZero = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_t_rec_rawIn_isZero_0 = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_sign_0 = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroExpIn = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroFractIn = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_self_rec_rawIn_isZero = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_self_rec_rawIn_isZero_0 = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_neg_t_T = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_q_sign_t_rec_rawIn_sign_1 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_1 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_t_rec_rawIn_1_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_4 = 1'h1; // @[rawFloatFromFN.scala:70:19] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroExpIn_1 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroFractIn_1 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_self_rec_rawIn_isZero_1 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_self_rec_rawIn_1_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_result_bits_rawIn_sign = 1'h1; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:57:36] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:59:25] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:61:35] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroExpIn = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroFractIn = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_abs_self_rec_rawIn_isZero = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_abs_self_rec_rawIn_isZero_0 = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroExpIn_1 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroFractIn_1 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_abs_self_rec_rawIn_isZero_1 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_abs_self_rec_rawIn_1_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_0 = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_2 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_2 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_2 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_2_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_t_T_4 = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_t_rec_rawIn_sign_3 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_3 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_3 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_t_rec_rawIn_isZero_3 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_t_rec_rawIn_3_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_3_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZeroExpIn = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZeroFractIn = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZero = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZero_0 = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_t_T_8 = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_t_rec_rawIn_sign_4 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_4 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_4 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_t_rec_rawIn_isZero_4 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_t_rec_rawIn_4_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_4_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroExpIn_2 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroFractIn_2 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_self_rec_rawIn_isZero_2 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_self_rec_rawIn_2_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_neg_t_T_4 = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_q_sign_t_rec_rawIn_sign_3 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_3 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_t_rec_rawIn_3_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_12 = 1'h1; // @[rawFloatFromFN.scala:70:19] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroExpIn_3 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroFractIn_3 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_self_rec_rawIn_isZero_3 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_self_rec_rawIn_3_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_result_bits_rawIn_1_sign = 1'h1; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:57:36] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_sign_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:59:25] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:61:35] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroExpIn_2 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroFractIn_2 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_abs_self_rec_rawIn_isZero_2 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_abs_self_rec_rawIn_2_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroExpIn_3 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroFractIn_3 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_abs_self_rec_rawIn_isZero_3 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_abs_self_rec_rawIn_3_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_3 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_3 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_3 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_3_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_5 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_5 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_5 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_5_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_t_T_12 = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_t_rec_rawIn_sign_7 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_7 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_7 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_t_rec_rawIn_isZero_7 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_t_rec_rawIn_7_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_7_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZeroExpIn_1 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZeroFractIn_1 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZero_1 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_1_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_t_T_16 = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_t_rec_rawIn_sign_8 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_8 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_8 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_t_rec_rawIn_isZero_8 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_t_rec_rawIn_8_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_8_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroExpIn_4 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroFractIn_4 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_self_rec_rawIn_isZero_4 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_self_rec_rawIn_4_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_neg_t_T_8 = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_q_sign_t_rec_rawIn_sign_5 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_5 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_t_rec_rawIn_5_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_20 = 1'h1; // @[rawFloatFromFN.scala:70:19] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroExpIn_5 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroFractIn_5 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_self_rec_rawIn_isZero_5 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_self_rec_rawIn_5_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_result_bits_rawIn_2_sign = 1'h1; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_7 = 1'h1; // @[rawFloatFromRecFN.scala:57:36] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_sign_T_2 = 1'h1; // @[rawFloatFromRecFN.scala:59:25] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:61:35] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroExpIn_4 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroFractIn_4 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_abs_self_rec_rawIn_isZero_4 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_abs_self_rec_rawIn_4_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroExpIn_5 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroFractIn_5 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_abs_self_rec_rawIn_isZero_5 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_abs_self_rec_rawIn_5_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_6 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_6 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_6 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_6_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_8 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_8 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_8 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_8_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_t_T_20 = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_t_rec_rawIn_sign_11 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_11 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_11 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_t_rec_rawIn_isZero_11 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_t_rec_rawIn_11_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_11_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZeroExpIn_2 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZeroFractIn_2 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZero_2 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_2_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_t_T_24 = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_t_rec_rawIn_sign_12 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_12 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_12 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_t_rec_rawIn_isZero_12 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_t_rec_rawIn_12_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_12_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroExpIn_6 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroFractIn_6 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_self_rec_rawIn_isZero_6 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_self_rec_rawIn_6_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_neg_t_T_12 = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_q_sign_t_rec_rawIn_sign_7 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_7 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_t_rec_rawIn_7_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_28 = 1'h1; // @[rawFloatFromFN.scala:70:19] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroExpIn_7 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_sign_self_rec_rawIn_isZeroFractIn_7 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_sign_self_rec_rawIn_isZero_7 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_sign_self_rec_rawIn_7_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_sign_result_bits_rawIn_3_sign = 1'h1; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_isInf_T_10 = 1'h1; // @[rawFloatFromRecFN.scala:57:36] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_sign_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:59:25] wire _activated_data_e_act_q_sign_result_bits_rawIn_out_sig_T_12 = 1'h1; // @[rawFloatFromRecFN.scala:61:35] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroExpIn_6 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroFractIn_6 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_abs_self_rec_rawIn_isZero_6 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_abs_self_rec_rawIn_6_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroExpIn_7 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_abs_self_rec_rawIn_isZeroFractIn_7 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_abs_self_rec_rawIn_isZero_7 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_abs_self_rec_rawIn_7_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_9 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_9 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_9 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_9_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_11 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_11 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_11 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_11_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_t_T_28 = 1'h1; // @[Arithmetic.scala:433:25] wire activated_data_e_act_t_rec_rawIn_sign_15 = 1'h1; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_15 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_15 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_t_rec_rawIn_isZero_15 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_t_rec_rawIn_15_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_t_rec_rawIn_15_sign = 1'h1; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZeroExpIn_3 = 1'h1; // @[rawFloatFromFN.scala:48:30] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZeroFractIn_3 = 1'h1; // @[rawFloatFromFN.scala:49:34] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_isZero_3 = 1'h1; // @[rawFloatFromFN.scala:60:30] wire activated_data_e_act_neg_q_iexp_self_rec_rawIn_3_isZero = 1'h1; // @[rawFloatFromFN.scala:63:19] wire [2:0] _activated_data_e_act_t_rec_T_1 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_t_rec_T_3 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_1 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_3 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_9 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_11 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_1 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_3 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_9 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_11 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_1 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_3 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_17 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_19 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_t_rec_T_25 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_t_rec_T_27 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_1 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_3 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_t_rec_T_33 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_t_rec_T_35 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_17 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_19 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_25 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_27 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_17 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_19 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_25 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_27 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_25 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_27 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_41 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_43 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_t_rec_T_57 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_t_rec_T_59 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_9 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_11 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_t_rec_T_65 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_t_rec_T_67 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_33 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_35 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_41 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_43 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_33 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_35 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_41 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_43 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_49 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_51 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_65 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_67 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_t_rec_T_89 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_t_rec_T_91 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_17 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_19 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_t_rec_T_97 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_t_rec_T_99 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_49 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_51 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_57 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_sign_self_rec_T_59 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_49 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_51 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_57 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_abs_self_rec_T_59 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_73 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_75 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_89 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_91 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_t_rec_T_121 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_t_rec_T_123 = 3'h0; // @[recFNFromFN.scala:48:76] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_25 = 3'h0; // @[recFNFromFN.scala:48:15] wire [2:0] _activated_data_e_act_neg_q_iexp_self_rec_T_27 = 3'h0; // @[recFNFromFN.scala:48:76] wire [31:0] io_in_bits_mean_bits = 32'h0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_max_bits = 32'h0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_inv_stddev_bits = 32'h0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_inv_sum_exp_bits = 32'h0; // @[AccumulatorScale.scala:88:7] wire [31:0] activated_data_e_act_zero_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_act_q_sign_WIRE_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_act_q_abs_WIRE_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] activated_data_e_act_zero_1_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_scaled_WIRE_bits = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] _activated_data_e_scaled_WIRE_1 = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] _activated_data_e_scaled_T_6 = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] activated_data_e_act_zero_2_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_act_q_sign_WIRE_1_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_act_q_abs_WIRE_1_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] activated_data_e_act_zero_3_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_scaled_WIRE_4_bits = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] _activated_data_e_scaled_WIRE_5 = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] _activated_data_e_scaled_T_16 = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] activated_data_e_act_zero_4_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_act_q_sign_WIRE_2_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_act_q_abs_WIRE_2_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] activated_data_e_act_zero_5_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_scaled_WIRE_8_bits = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] _activated_data_e_scaled_WIRE_9 = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] _activated_data_e_scaled_T_26 = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] activated_data_e_act_zero_6_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_act_q_sign_WIRE_3_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_act_q_abs_WIRE_3_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] activated_data_e_act_zero_7_bits = 32'h0; // @[Arithmetic.scala:518:46] wire [31:0] _activated_data_e_scaled_WIRE_12_bits = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] _activated_data_e_scaled_WIRE_13 = 32'h0; // @[AccumulatorScale.scala:131:42] wire [31:0] _activated_data_e_scaled_T_36 = 32'h0; // @[AccumulatorScale.scala:131:42] wire in_ready; // @[AccumulatorScale.scala:139:18] wire in_valid = io_in_valid_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_13_bits = io_in_bits_acc_read_resp_data_0_0_bits_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_0_0_bits = io_in_bits_acc_read_resp_data_0_0_bits_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_29_bits = io_in_bits_acc_read_resp_data_1_0_bits_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_1_0_bits = io_in_bits_acc_read_resp_data_1_0_bits_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_45_bits = io_in_bits_acc_read_resp_data_2_0_bits_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_2_0_bits = io_in_bits_acc_read_resp_data_2_0_bits_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_61_bits = io_in_bits_acc_read_resp_data_3_0_bits_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_3_0_bits = io_in_bits_acc_read_resp_data_3_0_bits_0; // @[AccumulatorScale.scala:88:7, :139:18] wire in_bits_resp_fromDMA = io_in_bits_acc_read_resp_fromDMA_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_scaled_T_7_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_17_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_27_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_37_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] in_bits_resp_scale_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] in_bits_resp_igelu_qb_bits = io_in_bits_acc_read_resp_igelu_qb_bits_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] in_bits_resp_igelu_qc_bits = io_in_bits_acc_read_resp_igelu_qc_bits_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] in_bits_resp_iexp_qln2_bits = io_in_bits_acc_read_resp_iexp_qln2_bits_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] in_bits_resp_iexp_qln2_inv_bits = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [2:0] in_bits_resp_act = io_in_bits_acc_read_resp_act_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [1:0] in_bits_resp_acc_bank_id = io_in_bits_acc_read_resp_acc_bank_id_0; // @[AccumulatorScale.scala:88:7, :139:18] wire out_ready = io_out_ready_0; // @[AccumulatorScale.scala:88:7, :104:17] wire out_valid; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_0_0_bits; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_1_0_bits; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_2_0_bits; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_3_0_bits; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_data_0_0_bits; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_data_1_0_bits; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_data_2_0_bits; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_data_3_0_bits; // @[AccumulatorScale.scala:104:17] wire [1:0] out_bits_acc_bank_id; // @[AccumulatorScale.scala:104:17] wire out_bits_fromDMA; // @[AccumulatorScale.scala:104:17] wire io_in_ready_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_0_0_bits_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_1_0_bits_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_2_0_bits_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_3_0_bits_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_data_0_0_bits_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_data_1_0_bits_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_data_2_0_bits_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_data_3_0_bits_0; // @[AccumulatorScale.scala:88:7] wire [1:0] io_out_bits_acc_bank_id_0; // @[AccumulatorScale.scala:88:7] wire io_out_bits_fromDMA_0; // @[AccumulatorScale.scala:88:7] wire io_out_valid_0; // @[AccumulatorScale.scala:88:7] assign io_out_valid_0 = out_valid; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_0_0_bits_0 = out_bits_full_data_0_0_bits; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_1_0_bits_0 = out_bits_full_data_1_0_bits; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_2_0_bits_0 = out_bits_full_data_2_0_bits; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_3_0_bits_0 = out_bits_full_data_3_0_bits; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_0_0_bits_0 = out_bits_data_0_0_bits; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_1_0_bits_0 = out_bits_data_1_0_bits; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_2_0_bits_0 = out_bits_data_2_0_bits; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_3_0_bits_0 = out_bits_data_3_0_bits; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_acc_bank_id_0 = out_bits_acc_bank_id; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_fromDMA_0 = out_bits_fromDMA; // @[AccumulatorScale.scala:88:7, :104:17] wire _GEN = io_in_bits_acc_read_resp_act_0 == 3'h1; // @[recFNFromFN.scala:48:50] wire _activated_data_e_act_T; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_16; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_16 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_32; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_32 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_48; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_48 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_1 = _activated_data_e_act_T; // @[AccumulatorScale.scala:118:{38,45}] wire activated_data_e_act_raw_sign = io_in_bits_acc_read_resp_data_0_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign = io_in_bits_acc_read_resp_data_0_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_sign_t_rec_rawIn_sign = io_in_bits_acc_read_resp_data_0_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_rec_rawIn_sign = io_in_bits_acc_read_resp_data_0_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_sgn = io_in_bits_acc_read_resp_data_0_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_2 = io_in_bits_acc_read_resp_data_0_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_4 = io_in_bits_acc_read_resp_data_0_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_raw_sign_0 = activated_data_e_act_raw_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_raw_expIn = io_in_bits_acc_read_resp_data_0_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn = io_in_bits_acc_read_resp_data_0_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_t_rec_rawIn_expIn = io_in_bits_acc_read_resp_data_0_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_abs_t_rec_rawIn_expIn = io_in_bits_acc_read_resp_data_0_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_2 = io_in_bits_acc_read_resp_data_0_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_4 = io_in_bits_acc_read_resp_data_0_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_raw_fractIn = io_in_bits_acc_read_resp_data_0_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn = io_in_bits_acc_read_resp_data_0_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_fractIn = io_in_bits_acc_read_resp_data_0_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_fractIn = io_in_bits_acc_read_resp_data_0_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_2 = io_in_bits_acc_read_resp_data_0_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_4 = io_in_bits_acc_read_resp_data_0_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_raw_isZeroExpIn = activated_data_e_act_raw_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_raw_isZeroFractIn = activated_data_e_act_raw_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_raw_normDist_T = activated_data_e_act_raw_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_1 = activated_data_e_act_raw_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_2 = activated_data_e_act_raw_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_3 = activated_data_e_act_raw_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_4 = activated_data_e_act_raw_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_5 = activated_data_e_act_raw_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_6 = activated_data_e_act_raw_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_7 = activated_data_e_act_raw_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_8 = activated_data_e_act_raw_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_9 = activated_data_e_act_raw_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_10 = activated_data_e_act_raw_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_11 = activated_data_e_act_raw_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_12 = activated_data_e_act_raw_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_13 = activated_data_e_act_raw_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_14 = activated_data_e_act_raw_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_15 = activated_data_e_act_raw_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_16 = activated_data_e_act_raw_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_17 = activated_data_e_act_raw_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_18 = activated_data_e_act_raw_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_19 = activated_data_e_act_raw_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_20 = activated_data_e_act_raw_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_21 = activated_data_e_act_raw_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_22 = activated_data_e_act_raw_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_raw_normDist_T_23 = _activated_data_e_act_raw_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_24 = _activated_data_e_act_raw_normDist_T_2 ? 5'h14 : _activated_data_e_act_raw_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_25 = _activated_data_e_act_raw_normDist_T_3 ? 5'h13 : _activated_data_e_act_raw_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_26 = _activated_data_e_act_raw_normDist_T_4 ? 5'h12 : _activated_data_e_act_raw_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_27 = _activated_data_e_act_raw_normDist_T_5 ? 5'h11 : _activated_data_e_act_raw_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_28 = _activated_data_e_act_raw_normDist_T_6 ? 5'h10 : _activated_data_e_act_raw_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_29 = _activated_data_e_act_raw_normDist_T_7 ? 5'hF : _activated_data_e_act_raw_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_30 = _activated_data_e_act_raw_normDist_T_8 ? 5'hE : _activated_data_e_act_raw_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_31 = _activated_data_e_act_raw_normDist_T_9 ? 5'hD : _activated_data_e_act_raw_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_32 = _activated_data_e_act_raw_normDist_T_10 ? 5'hC : _activated_data_e_act_raw_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_33 = _activated_data_e_act_raw_normDist_T_11 ? 5'hB : _activated_data_e_act_raw_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_34 = _activated_data_e_act_raw_normDist_T_12 ? 5'hA : _activated_data_e_act_raw_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_35 = _activated_data_e_act_raw_normDist_T_13 ? 5'h9 : _activated_data_e_act_raw_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_36 = _activated_data_e_act_raw_normDist_T_14 ? 5'h8 : _activated_data_e_act_raw_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_37 = _activated_data_e_act_raw_normDist_T_15 ? 5'h7 : _activated_data_e_act_raw_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_38 = _activated_data_e_act_raw_normDist_T_16 ? 5'h6 : _activated_data_e_act_raw_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_39 = _activated_data_e_act_raw_normDist_T_17 ? 5'h5 : _activated_data_e_act_raw_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_40 = _activated_data_e_act_raw_normDist_T_18 ? 5'h4 : _activated_data_e_act_raw_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_41 = _activated_data_e_act_raw_normDist_T_19 ? 5'h3 : _activated_data_e_act_raw_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_42 = _activated_data_e_act_raw_normDist_T_20 ? 5'h2 : _activated_data_e_act_raw_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_43 = _activated_data_e_act_raw_normDist_T_21 ? 5'h1 : _activated_data_e_act_raw_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_raw_normDist = _activated_data_e_act_raw_normDist_T_22 ? 5'h0 : _activated_data_e_act_raw_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_raw_subnormFract_T = {31'h0, activated_data_e_act_raw_fractIn} << activated_data_e_act_raw_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_raw_subnormFract_T_1 = _activated_data_e_act_raw_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_raw_subnormFract = {_activated_data_e_act_raw_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_raw_adjustedExp_T = {4'hF, ~activated_data_e_act_raw_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_raw_adjustedExp_T_1 = activated_data_e_act_raw_isZeroExpIn ? _activated_data_e_act_raw_adjustedExp_T : {1'h0, activated_data_e_act_raw_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_raw_adjustedExp_T_2 = activated_data_e_act_raw_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_raw_adjustedExp_T_3 = {6'h20, _activated_data_e_act_raw_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_raw_adjustedExp_T_4 = {1'h0, _activated_data_e_act_raw_adjustedExp_T_1} + {2'h0, _activated_data_e_act_raw_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_raw_adjustedExp = _activated_data_e_act_raw_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_raw_out_sExp_T = activated_data_e_act_raw_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_raw_isZero = activated_data_e_act_raw_isZeroExpIn & activated_data_e_act_raw_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_raw_isZero_0 = activated_data_e_act_raw_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_raw_isSpecial_T = activated_data_e_act_raw_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_raw_isSpecial = &_activated_data_e_act_raw_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_raw_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_raw_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire [9:0] _activated_data_e_act_raw_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_raw_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_raw_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_raw_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_raw_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_raw_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_raw_out_isNaN_T = ~activated_data_e_act_raw_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_raw_out_isNaN_T_1 = activated_data_e_act_raw_isSpecial & _activated_data_e_act_raw_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_raw_isNaN = _activated_data_e_act_raw_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_raw_out_isInf_T = activated_data_e_act_raw_isSpecial & activated_data_e_act_raw_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_raw_isInf = _activated_data_e_act_raw_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_raw_out_sExp_T_1 = {1'h0, _activated_data_e_act_raw_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_raw_sExp = _activated_data_e_act_raw_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_raw_out_sig_T = ~activated_data_e_act_raw_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_raw_out_sig_T_1 = {1'h0, _activated_data_e_act_raw_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_raw_out_sig_T_2 = activated_data_e_act_raw_isZeroExpIn ? activated_data_e_act_raw_subnormFract : activated_data_e_act_raw_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_raw_out_sig_T_3 = {_activated_data_e_act_raw_out_sig_T_1, _activated_data_e_act_raw_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_raw_sig = _activated_data_e_act_raw_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [31:0] _activated_data_e_act_result_bits_T_2; // @[Arithmetic.scala:514:27] wire [31:0] activated_data_e_act_result_bits; // @[Arithmetic.scala:513:26] wire _activated_data_e_act_result_bits_T = ~activated_data_e_act_raw_isZero_0; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_result_bits_T_1 = _activated_data_e_act_result_bits_T & activated_data_e_act_raw_sign_0; // @[rawFloatFromFN.scala:63:19] assign _activated_data_e_act_result_bits_T_2 = _activated_data_e_act_result_bits_T_1 ? 32'h0 : io_in_bits_acc_read_resp_data_0_0_bits_0; // @[Arithmetic.scala:514:{27,40}] assign activated_data_e_act_result_bits = _activated_data_e_act_result_bits_T_2; // @[Arithmetic.scala:513:26, :514:27] wire _GEN_0 = io_in_bits_acc_read_resp_act_0 == 3'h2; // @[AccumulatorScale.scala:88:7, :119:69] wire _activated_data_e_act_T_3; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_3 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_1; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_1 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_19; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_19 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_11; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_11 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_35; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_35 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_21; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_21 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_51; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_51 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_31; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_31 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire activated_data_e_act_self_rec_rawIn_sign_0 = activated_data_e_act_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn = activated_data_e_act_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn = activated_data_e_act_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T = activated_data_e_act_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_1 = activated_data_e_act_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_2 = activated_data_e_act_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_3 = activated_data_e_act_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_4 = activated_data_e_act_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_5 = activated_data_e_act_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_6 = activated_data_e_act_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_7 = activated_data_e_act_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_8 = activated_data_e_act_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_9 = activated_data_e_act_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_10 = activated_data_e_act_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_11 = activated_data_e_act_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_12 = activated_data_e_act_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_13 = activated_data_e_act_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_14 = activated_data_e_act_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_15 = activated_data_e_act_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_16 = activated_data_e_act_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_17 = activated_data_e_act_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_18 = activated_data_e_act_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_19 = activated_data_e_act_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_20 = activated_data_e_act_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_21 = activated_data_e_act_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_22 = activated_data_e_act_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_23 = _activated_data_e_act_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_24 = _activated_data_e_act_self_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_25 = _activated_data_e_act_self_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_26 = _activated_data_e_act_self_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_27 = _activated_data_e_act_self_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_28 = _activated_data_e_act_self_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_29 = _activated_data_e_act_self_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_30 = _activated_data_e_act_self_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_31 = _activated_data_e_act_self_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_32 = _activated_data_e_act_self_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_33 = _activated_data_e_act_self_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_34 = _activated_data_e_act_self_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_35 = _activated_data_e_act_self_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_36 = _activated_data_e_act_self_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_37 = _activated_data_e_act_self_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_38 = _activated_data_e_act_self_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_39 = _activated_data_e_act_self_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_40 = _activated_data_e_act_self_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_41 = _activated_data_e_act_self_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_42 = _activated_data_e_act_self_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_43 = _activated_data_e_act_self_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist = _activated_data_e_act_self_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn} << activated_data_e_act_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_self_rec_rawIn_isZeroExpIn ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T = activated_data_e_act_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero = activated_data_e_act_self_rec_rawIn_isZeroExpIn & activated_data_e_act_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_isZero_0 = activated_data_e_act_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T = activated_data_e_act_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial = &_activated_data_e_act_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_2 = activated_data_e_act_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_self_rec_rawIn_isSpecial & _activated_data_e_act_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T = activated_data_e_act_self_rec_rawIn_isSpecial & activated_data_e_act_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T = ~activated_data_e_act_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_2 = activated_data_e_act_self_rec_rawIn_isZeroExpIn ? activated_data_e_act_self_rec_rawIn_subnormFract : activated_data_e_act_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_1, _activated_data_e_act_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T = activated_data_e_act_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_1 = activated_data_e_act_self_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_3 = {_activated_data_e_act_self_rec_T_1[2:1], _activated_data_e_act_self_rec_T_1[0] | _activated_data_e_act_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_4 = {activated_data_e_act_self_rec_rawIn_sign_0, _activated_data_e_act_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_5 = activated_data_e_act_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_6 = {_activated_data_e_act_self_rec_T_4, _activated_data_e_act_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_7 = activated_data_e_act_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec = {_activated_data_e_act_self_rec_T_6, _activated_data_e_act_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_1_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp = _activated_data_e_act_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T = activated_data_e_act_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero = _activated_data_e_act_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_isZero_0 = activated_data_e_act_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T = activated_data_e_act_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial = &_activated_data_e_act_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T = activated_data_e_act_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T = activated_data_e_act_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_result_bits_rawIn_isSpecial & _activated_data_e_act_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_2 = activated_data_e_act_result_bits_rawIn_isSpecial & _activated_data_e_act_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T = _activated_data_e_act_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T = ~activated_data_e_act_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_2 = _activated_data_e_act_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_1, _activated_data_e_act_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal = $signed(activated_data_e_act_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T = activated_data_e_act_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist = _activated_data_e_act_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T = activated_data_e_act_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_1 = _activated_data_e_act_result_bits_denormFract_T >> activated_data_e_act_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract = _activated_data_e_act_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T = activated_data_e_act_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_1 = {1'h0, _activated_data_e_act_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_2 = _activated_data_e_act_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_3 = activated_data_e_act_result_bits_isSubnormal ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_4 = activated_data_e_act_result_bits_rawIn_isNaN | activated_data_e_act_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_5 = {8{_activated_data_e_act_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut = _activated_data_e_act_result_bits_expOut_T_3 | _activated_data_e_act_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T = activated_data_e_act_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_1 = activated_data_e_act_result_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut = activated_data_e_act_result_bits_isSubnormal ? activated_data_e_act_result_bits_denormFract : _activated_data_e_act_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi = {activated_data_e_act_result_bits_rawIn_sign, activated_data_e_act_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_3 = {activated_data_e_act_result_bits_hi, activated_data_e_act_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_1_bits = _activated_data_e_act_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire _GEN_1 = io_in_bits_acc_read_resp_act_0 == 3'h3; // @[AccumulatorScale.scala:88:7, :121:69] wire _activated_data_e_act_T_6; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_6 = _GEN_1; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_22; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_22 = _GEN_1; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_38; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_38 = _GEN_1; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_54; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_54 = _GEN_1; // @[AccumulatorScale.scala:121:69] wire activated_data_e_act_q_sign_t_rec_rawIn_sign_0 = activated_data_e_act_q_sign_t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn = activated_data_e_act_q_sign_t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn = activated_data_e_act_q_sign_t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_1 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_2 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_3 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_4 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_5 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_6 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_7 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_8 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_9 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_10 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_11 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_12 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_13 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_14 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_15 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_16 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_17 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_18 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_19 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_20 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_21 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_22 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_t_rec_rawIn_normDist = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_sign_t_rec_rawIn_fractIn} << activated_data_e_act_q_sign_t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_subnormFract = {_activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_sign_t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_sign_t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp = _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T = activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_sign_t_rec_rawIn_isZero = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn & activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_sign_t_rec_rawIn_isZero_0 = activated_data_e_act_q_sign_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T = activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_sign_t_rec_rawIn_isSpecial = &_activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_t_rec_T_2 = activated_data_e_act_q_sign_t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_sign_t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_sign_t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_sign_t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_sign_t_rec_rawIn_isSpecial & _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_sign_t_rec_rawIn_isNaN = _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T = activated_data_e_act_q_sign_t_rec_rawIn_isSpecial & activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_sign_t_rec_rawIn_isInf = _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_sign_t_rec_rawIn_sExp = _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T = ~activated_data_e_act_q_sign_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_sign_t_rec_rawIn_subnormFract : activated_data_e_act_q_sign_t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_sign_t_rec_rawIn_sig = _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_sign_t_rec_T = activated_data_e_act_q_sign_t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_1 = activated_data_e_act_q_sign_t_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_sign_t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_3 = {_activated_data_e_act_q_sign_t_rec_T_1[2:1], _activated_data_e_act_q_sign_t_rec_T_1[0] | _activated_data_e_act_q_sign_t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_sign_t_rec_T_4 = {activated_data_e_act_q_sign_t_rec_rawIn_sign_0, _activated_data_e_act_q_sign_t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_sign_t_rec_T_5 = activated_data_e_act_q_sign_t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_sign_t_rec_T_6 = {_activated_data_e_act_q_sign_t_rec_T_4, _activated_data_e_act_q_sign_t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_sign_t_rec_T_7 = activated_data_e_act_q_sign_t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_sign_t_rec = {_activated_data_e_act_q_sign_t_rec_T_6, _activated_data_e_act_q_sign_t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] activated_data_e_act_q_sign_bits = {_activated_data_e_act_q_sign_comparator_io_gt, 31'h3F800000}; // @[Arithmetic.scala:475:32] wire activated_data_e_act_q_abs_t_rec_rawIn_sign_0 = activated_data_e_act_q_abs_t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn = activated_data_e_act_q_abs_t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn = activated_data_e_act_q_abs_t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_1 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_2 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_3 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_4 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_5 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_6 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_7 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_8 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_9 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_10 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_11 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_12 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_13 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_14 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_15 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_16 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_17 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_18 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_19 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_20 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_21 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_22 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_t_rec_rawIn_normDist = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_abs_t_rec_rawIn_fractIn} << activated_data_e_act_q_abs_t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_subnormFract = {_activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_abs_t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_abs_t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp = _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_abs_t_rec_rawIn_isZero = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_abs_t_rec_rawIn_isZero_0 = activated_data_e_act_q_abs_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_abs_t_rec_rawIn_isSpecial = &_activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_t_rec_T_2 = activated_data_e_act_q_abs_t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_abs_t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_abs_t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_abs_t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial & _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_abs_t_rec_rawIn_isNaN = _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_abs_t_rec_rawIn_isInf = _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_abs_t_rec_rawIn_sExp = _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T = ~activated_data_e_act_q_abs_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_abs_t_rec_rawIn_subnormFract : activated_data_e_act_q_abs_t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_abs_t_rec_rawIn_sig = _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_abs_t_rec_T = activated_data_e_act_q_abs_t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_1 = activated_data_e_act_q_abs_t_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_abs_t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_3 = {_activated_data_e_act_q_abs_t_rec_T_1[2:1], _activated_data_e_act_q_abs_t_rec_T_1[0] | _activated_data_e_act_q_abs_t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_abs_t_rec_T_4 = {activated_data_e_act_q_abs_t_rec_rawIn_sign_0, _activated_data_e_act_q_abs_t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_abs_t_rec_T_5 = activated_data_e_act_q_abs_t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_abs_t_rec_T_6 = {_activated_data_e_act_q_abs_t_rec_T_4, _activated_data_e_act_q_abs_t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_abs_t_rec_T_7 = activated_data_e_act_q_abs_t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_abs_t_rec = {_activated_data_e_act_q_abs_t_rec_T_6, _activated_data_e_act_q_abs_t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _activated_data_e_act_q_abs_neg_t_T = ~activated_data_e_act_q_abs_t_sgn; // @[Arithmetic.scala:432:27, :433:25] wire [30:0] _activated_data_e_act_q_abs_neg_t_T_1 = io_in_bits_acc_read_resp_data_0_0_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [31:0] _activated_data_e_act_q_abs_neg_t_T_2 = {_activated_data_e_act_q_abs_neg_t_T, _activated_data_e_act_q_abs_neg_t_T_1}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_abs_neg_t_WIRE = _activated_data_e_act_q_abs_neg_t_T_2; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_abs_neg_t_T_3; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_abs_neg_t_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_abs_neg_t_T_3 = _activated_data_e_act_q_abs_neg_t_WIRE; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_abs_neg_t_bits = _activated_data_e_act_q_abs_neg_t_T_3; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_abs_t_rec_rawIn_sign_1 = activated_data_e_act_q_abs_neg_t_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_rec_rawIn_1_sign = activated_data_e_act_q_abs_t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_abs_t_rec_rawIn_expIn_1 = activated_data_e_act_q_abs_neg_t_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1 = activated_data_e_act_q_abs_neg_t_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_abs_t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_44 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_45 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_46 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_47 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_48 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_49 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_50 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_51 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_52 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_53 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_54 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_55 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_56 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_57 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_58 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_59 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_60 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_61 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_62 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_63 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_64 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_65 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_66 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_t_rec_rawIn_normDist_1 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1} << activated_data_e_act_q_abs_t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_abs_t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_abs_t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_abs_t_rec_rawIn_isZero_1 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_abs_t_rec_rawIn_1_isZero = activated_data_e_act_q_abs_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_t_rec_T_10 = activated_data_e_act_q_abs_t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_abs_t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_abs_t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_abs_t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_abs_t_rec_rawIn_1_isNaN = _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_1 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_abs_t_rec_rawIn_1_isInf = _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_abs_t_rec_rawIn_1_sExp = _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_1 : activated_data_e_act_q_abs_t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_abs_t_rec_rawIn_1_sig = _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_8 = activated_data_e_act_q_abs_t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_9 = activated_data_e_act_q_abs_t_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_abs_t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_11 = {_activated_data_e_act_q_abs_t_rec_T_9[2:1], _activated_data_e_act_q_abs_t_rec_T_9[0] | _activated_data_e_act_q_abs_t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_abs_t_rec_T_12 = {activated_data_e_act_q_abs_t_rec_rawIn_1_sign, _activated_data_e_act_q_abs_t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_abs_t_rec_T_13 = activated_data_e_act_q_abs_t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_abs_t_rec_T_14 = {_activated_data_e_act_q_abs_t_rec_T_12, _activated_data_e_act_q_abs_t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_abs_t_rec_T_15 = activated_data_e_act_q_abs_t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_abs_t_rec_1 = {_activated_data_e_act_q_abs_t_rec_T_14, _activated_data_e_act_q_abs_t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_abs_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_abs_result_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_abs_result_bits_rawIn_exp = _activated_data_e_act_q_abs_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_abs_result_bits_rawIn_isZero_T = activated_data_e_act_q_abs_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_abs_result_bits_rawIn_isZero = _activated_data_e_act_q_abs_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_abs_result_bits_rawIn_isZero_0 = activated_data_e_act_q_abs_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_T = activated_data_e_act_q_abs_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_abs_result_bits_rawIn_isSpecial = &_activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_abs_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_abs_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_abs_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_abs_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_abs_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T = activated_data_e_act_q_abs_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T = activated_data_e_act_q_abs_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_q_abs_result_bits_rawIn_isSpecial & _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_abs_result_bits_rawIn_isNaN = _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_2 = activated_data_e_act_q_abs_result_bits_rawIn_isSpecial & _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_abs_result_bits_rawIn_isInf = _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T = _activated_data_e_act_q_abs_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_abs_result_bits_rawIn_sign = _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_q_abs_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_abs_result_bits_rawIn_sExp = _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T = ~activated_data_e_act_q_abs_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_2 = _activated_data_e_act_q_abs_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_1, _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_abs_result_bits_rawIn_sig = _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_abs_result_bits_isSubnormal = $signed(activated_data_e_act_q_abs_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_abs_result_bits_denormShiftDist_T = activated_data_e_act_q_abs_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_q_abs_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_abs_result_bits_denormShiftDist = _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_abs_result_bits_denormFract_T = activated_data_e_act_q_abs_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_abs_result_bits_denormFract_T_1 = _activated_data_e_act_q_abs_result_bits_denormFract_T >> activated_data_e_act_q_abs_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_abs_result_bits_denormFract = _activated_data_e_act_q_abs_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T = activated_data_e_act_q_abs_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_abs_result_bits_expOut_T_1 = {1'h0, _activated_data_e_act_q_abs_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_2 = _activated_data_e_act_q_abs_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_3 = activated_data_e_act_q_abs_result_bits_isSubnormal ? 8'h0 : _activated_data_e_act_q_abs_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_abs_result_bits_expOut_T_4 = activated_data_e_act_q_abs_result_bits_rawIn_isNaN | activated_data_e_act_q_abs_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_5 = {8{_activated_data_e_act_q_abs_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_abs_result_bits_expOut = _activated_data_e_act_q_abs_result_bits_expOut_T_3 | _activated_data_e_act_q_abs_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_abs_result_bits_fractOut_T = activated_data_e_act_q_abs_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_abs_result_bits_fractOut_T_1 = activated_data_e_act_q_abs_result_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_q_abs_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_abs_result_bits_fractOut = activated_data_e_act_q_abs_result_bits_isSubnormal ? activated_data_e_act_q_abs_result_bits_denormFract : _activated_data_e_act_q_abs_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_abs_result_bits_hi = {activated_data_e_act_q_abs_result_bits_rawIn_sign, activated_data_e_act_q_abs_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_abs_result_bits_T = {activated_data_e_act_q_abs_result_bits_hi, activated_data_e_act_q_abs_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_abs_result_bits = _activated_data_e_act_q_abs_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_abs_bits = _activated_data_e_act_q_abs_comparator_io_gt ? activated_data_e_act_q_abs_result_bits : io_in_bits_acc_read_resp_data_0_0_bits_0; // @[Arithmetic.scala:426:26, :475:32] wire activated_data_e_act_q_clipped_t_sgn = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_clipped_t_sgn_1 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_poly_t_rec_rawIn_sign = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_t_rec_rawIn_sign_1 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_1 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_sgn_2 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_clipped_t_sgn_3 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_poly_t_rec_rawIn_sign_2 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_t_rec_rawIn_sign_3 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_2 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_3 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_sgn_4 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_clipped_t_sgn_5 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_poly_t_rec_rawIn_sign_4 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_t_rec_rawIn_sign_5 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_4 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_5 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_sgn_6 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_clipped_t_sgn_7 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[Arithmetic.scala:432:27] wire activated_data_e_act_q_poly_t_rec_rawIn_sign_6 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_t_rec_rawIn_sign_7 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_6 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_7 = io_in_bits_acc_read_resp_igelu_qb_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_q_clipped_neg_t_T = ~activated_data_e_act_q_clipped_t_sgn; // @[Arithmetic.scala:432:27, :433:25] wire [30:0] _activated_data_e_act_q_clipped_neg_t_T_1 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_q_clipped_neg_t_T_5 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_q_clipped_neg_t_T_9 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_q_clipped_neg_t_T_13 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_q_clipped_neg_t_T_17 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_q_clipped_neg_t_T_21 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_q_clipped_neg_t_T_25 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [30:0] _activated_data_e_act_q_clipped_neg_t_T_29 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_2 = {_activated_data_e_act_q_clipped_neg_t_T, _activated_data_e_act_q_clipped_neg_t_T_1}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_WIRE = _activated_data_e_act_q_clipped_neg_t_T_2; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_3; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_clipped_neg_t_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_clipped_neg_t_T_3 = _activated_data_e_act_q_clipped_neg_t_WIRE; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_clipped_neg_t_bits = _activated_data_e_act_q_clipped_neg_t_T_3; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign = activated_data_e_act_q_clipped_neg_t_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_0 = activated_data_e_act_q_clipped_t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn = activated_data_e_act_q_clipped_neg_t_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn = activated_data_e_act_q_clipped_neg_t_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn = activated_data_e_act_q_clipped_t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_1 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_2 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_3 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_4 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_5 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_6 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_7 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_8 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_9 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_10 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_11 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_12 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_13 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_14 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_15 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_16 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_17 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_18 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_19 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_20 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_21 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_22 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_0 = activated_data_e_act_q_clipped_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_2 = activated_data_e_act_q_clipped_t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T = activated_data_e_act_q_clipped_t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_1 = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_3 = {_activated_data_e_act_q_clipped_t_rec_T_1[2:1], _activated_data_e_act_q_clipped_t_rec_T_1[0] | _activated_data_e_act_q_clipped_t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_4 = {activated_data_e_act_q_clipped_t_rec_rawIn_sign_0, _activated_data_e_act_q_clipped_t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_5 = activated_data_e_act_q_clipped_t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_6 = {_activated_data_e_act_q_clipped_t_rec_T_4, _activated_data_e_act_q_clipped_t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_7 = activated_data_e_act_q_clipped_t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec = {_activated_data_e_act_q_clipped_t_rec_T_6, _activated_data_e_act_q_clipped_t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_clipped_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_result_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_clipped_result_bits_rawIn_exp = _activated_data_e_act_q_clipped_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T = activated_data_e_act_q_clipped_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isZero = _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_clipped_result_bits_rawIn_isZero_0 = activated_data_e_act_q_clipped_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T = activated_data_e_act_q_clipped_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial = &_activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_clipped_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_clipped_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_clipped_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T = activated_data_e_act_q_clipped_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T = activated_data_e_act_q_clipped_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_clipped_result_bits_rawIn_isNaN = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_2 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_clipped_result_bits_rawIn_isInf = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T = _activated_data_e_act_q_clipped_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_clipped_result_bits_rawIn_sign = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_q_clipped_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_clipped_result_bits_rawIn_sExp = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T = ~activated_data_e_act_q_clipped_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_2 = _activated_data_e_act_q_clipped_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_1, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_clipped_result_bits_rawIn_sig = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_clipped_result_bits_isSubnormal = $signed(activated_data_e_act_q_clipped_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T = activated_data_e_act_q_clipped_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_clipped_result_bits_denormShiftDist = _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T = activated_data_e_act_q_clipped_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_1 = _activated_data_e_act_q_clipped_result_bits_denormFract_T >> activated_data_e_act_q_clipped_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_clipped_result_bits_denormFract = _activated_data_e_act_q_clipped_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T = activated_data_e_act_q_clipped_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_1 = {1'h0, _activated_data_e_act_q_clipped_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_2 = _activated_data_e_act_q_clipped_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_3 = activated_data_e_act_q_clipped_result_bits_isSubnormal ? 8'h0 : _activated_data_e_act_q_clipped_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_clipped_result_bits_expOut_T_4 = activated_data_e_act_q_clipped_result_bits_rawIn_isNaN | activated_data_e_act_q_clipped_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_5 = {8{_activated_data_e_act_q_clipped_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_clipped_result_bits_expOut = _activated_data_e_act_q_clipped_result_bits_expOut_T_3 | _activated_data_e_act_q_clipped_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T = activated_data_e_act_q_clipped_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_1 = activated_data_e_act_q_clipped_result_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_q_clipped_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_clipped_result_bits_fractOut = activated_data_e_act_q_clipped_result_bits_isSubnormal ? activated_data_e_act_q_clipped_result_bits_denormFract : _activated_data_e_act_q_clipped_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_clipped_result_bits_hi = {activated_data_e_act_q_clipped_result_bits_rawIn_sign, activated_data_e_act_q_clipped_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_clipped_result_bits_T = {activated_data_e_act_q_clipped_result_bits_hi, activated_data_e_act_q_clipped_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_clipped_result_bits = _activated_data_e_act_q_clipped_result_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_1 = activated_data_e_act_q_clipped_result_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_1_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_1 = activated_data_e_act_q_clipped_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1 = activated_data_e_act_q_clipped_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_44 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_45 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_46 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_47 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_48 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_49 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_50 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_51 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_52 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_53 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_54 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_55 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_56 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_57 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_58 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_59 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_60 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_61 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_62 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_63 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_64 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_65 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_66 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_1 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_1 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_1_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_10 = activated_data_e_act_q_clipped_t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_1_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_1 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_1_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_1_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_1 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_1_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_8 = activated_data_e_act_q_clipped_t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_9 = activated_data_e_act_q_clipped_t_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_11 = {_activated_data_e_act_q_clipped_t_rec_T_9[2:1], _activated_data_e_act_q_clipped_t_rec_T_9[0] | _activated_data_e_act_q_clipped_t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_12 = {activated_data_e_act_q_clipped_t_rec_rawIn_1_sign, _activated_data_e_act_q_clipped_t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_13 = activated_data_e_act_q_clipped_t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_14 = {_activated_data_e_act_q_clipped_t_rec_T_12, _activated_data_e_act_q_clipped_t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_15 = activated_data_e_act_q_clipped_t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_1 = {_activated_data_e_act_q_clipped_t_rec_T_14, _activated_data_e_act_q_clipped_t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_1 = activated_data_e_act_q_abs_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_self_rec_rawIn_1_sign = activated_data_e_act_q_clipped_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_1 = activated_data_e_act_q_abs_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1 = activated_data_e_act_q_abs_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_clipped_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_44 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_45 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_46 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_47 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_48 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_49 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_50 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_51 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_52 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_53 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_54 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_55 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_56 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_57 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_58 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_59 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_60 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_61 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_62 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_63 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_64 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_65 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_66 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_1 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1} << activated_data_e_act_q_clipped_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_clipped_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_clipped_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_1 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_1_isZero = activated_data_e_act_q_clipped_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_T_10 = activated_data_e_act_q_clipped_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_self_rec_rawIn_1_isNaN = _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_1 & activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_self_rec_rawIn_1_isInf = _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_self_rec_rawIn_1_sExp = _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_clipped_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_1 : activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_self_rec_rawIn_1_sig = _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_8 = activated_data_e_act_q_clipped_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_9 = activated_data_e_act_q_clipped_self_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_clipped_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_11 = {_activated_data_e_act_q_clipped_self_rec_T_9[2:1], _activated_data_e_act_q_clipped_self_rec_T_9[0] | _activated_data_e_act_q_clipped_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_12 = {activated_data_e_act_q_clipped_self_rec_rawIn_1_sign, _activated_data_e_act_q_clipped_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_13 = activated_data_e_act_q_clipped_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_14 = {_activated_data_e_act_q_clipped_self_rec_T_12, _activated_data_e_act_q_clipped_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_15 = activated_data_e_act_q_clipped_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_self_rec_1 = {_activated_data_e_act_q_clipped_self_rec_T_14, _activated_data_e_act_q_clipped_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _activated_data_e_act_q_clipped_neg_t_T_4 = ~activated_data_e_act_q_clipped_t_sgn_1; // @[Arithmetic.scala:432:27, :433:25] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_6 = {_activated_data_e_act_q_clipped_neg_t_T_4, _activated_data_e_act_q_clipped_neg_t_T_5}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_WIRE_1 = _activated_data_e_act_q_clipped_neg_t_T_6; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_7; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_clipped_neg_t_1_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_clipped_neg_t_T_7 = _activated_data_e_act_q_clipped_neg_t_WIRE_1; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_clipped_neg_t_1_bits = _activated_data_e_act_q_clipped_neg_t_T_7; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_2 = activated_data_e_act_q_clipped_neg_t_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_2_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_2 = activated_data_e_act_q_clipped_neg_t_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2 = activated_data_e_act_q_clipped_neg_t_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_88 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_89 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_90 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_91 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_92 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_93 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_94 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_95 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_96 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_97 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_98 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_99 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_100 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_101 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_102 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_103 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_104 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_105 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_106 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_107 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_108 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_109 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_110 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_2 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_2 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_2_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_18 = activated_data_e_act_q_clipped_t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_2_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_2 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_2_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_2_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_2 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_2_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_16 = activated_data_e_act_q_clipped_t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_17 = activated_data_e_act_q_clipped_t_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_19 = {_activated_data_e_act_q_clipped_t_rec_T_17[2:1], _activated_data_e_act_q_clipped_t_rec_T_17[0] | _activated_data_e_act_q_clipped_t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_20 = {activated_data_e_act_q_clipped_t_rec_rawIn_2_sign, _activated_data_e_act_q_clipped_t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_21 = activated_data_e_act_q_clipped_t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_22 = {_activated_data_e_act_q_clipped_t_rec_T_20, _activated_data_e_act_q_clipped_t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_23 = activated_data_e_act_q_clipped_t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_2 = {_activated_data_e_act_q_clipped_t_rec_T_22, _activated_data_e_act_q_clipped_t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_clipped_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_result_1_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_clipped_result_bits_rawIn_exp_1 = _activated_data_e_act_q_clipped_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_1 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isZero_1 = _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_clipped_result_bits_rawIn_1_isZero = activated_data_e_act_q_clipped_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_1 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_1 = &_activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_clipped_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_clipped_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_clipped_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_3 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_clipped_result_bits_rawIn_1_isNaN = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_5 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_clipped_result_bits_rawIn_1_isInf = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_1 = _activated_data_e_act_q_clipped_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_clipped_result_bits_rawIn_1_sign = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_q_clipped_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_clipped_result_bits_rawIn_1_sExp = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_q_clipped_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_6 = _activated_data_e_act_q_clipped_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_5, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_clipped_result_bits_rawIn_1_sig = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_clipped_result_bits_isSubnormal_1 = $signed(activated_data_e_act_q_clipped_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_2 = activated_data_e_act_q_clipped_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_clipped_result_bits_denormShiftDist_1 = _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_2 = activated_data_e_act_q_clipped_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_3 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_2 >> activated_data_e_act_q_clipped_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_clipped_result_bits_denormFract_1 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_6 = activated_data_e_act_q_clipped_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_7 = {1'h0, _activated_data_e_act_q_clipped_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_8 = _activated_data_e_act_q_clipped_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_9 = activated_data_e_act_q_clipped_result_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_q_clipped_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_clipped_result_bits_expOut_T_10 = activated_data_e_act_q_clipped_result_bits_rawIn_1_isNaN | activated_data_e_act_q_clipped_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_11 = {8{_activated_data_e_act_q_clipped_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_clipped_result_bits_expOut_1 = _activated_data_e_act_q_clipped_result_bits_expOut_T_9 | _activated_data_e_act_q_clipped_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_2 = activated_data_e_act_q_clipped_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_3 = activated_data_e_act_q_clipped_result_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_clipped_result_bits_fractOut_1 = activated_data_e_act_q_clipped_result_bits_isSubnormal_1 ? activated_data_e_act_q_clipped_result_bits_denormFract_1 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_clipped_result_bits_hi_1 = {activated_data_e_act_q_clipped_result_bits_rawIn_1_sign, activated_data_e_act_q_clipped_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_clipped_result_bits_T_1 = {activated_data_e_act_q_clipped_result_bits_hi_1, activated_data_e_act_q_clipped_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_clipped_result_1_bits = _activated_data_e_act_q_clipped_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_bits = _activated_data_e_act_q_clipped_comparator_io_gt ? activated_data_e_act_q_clipped_result_1_bits : activated_data_e_act_q_abs_bits; // @[Arithmetic.scala:426:26, :475:32] wire activated_data_e_act_q_poly_t_rec_rawIn_sign_0 = activated_data_e_act_q_poly_t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_t_rec_rawIn_expIn = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_t_rec_rawIn_expIn_1 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_1 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_t_rec_rawIn_expIn_2 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_t_rec_rawIn_expIn_3 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_2 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_3 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_t_rec_rawIn_expIn_4 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_t_rec_rawIn_expIn_5 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_4 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_5 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_t_rec_rawIn_expIn_6 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_t_rec_rawIn_expIn_7 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_6 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_7 = io_in_bits_acc_read_resp_igelu_qb_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_fractIn = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7 = io_in_bits_acc_read_resp_igelu_qb_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn = activated_data_e_act_q_poly_t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn = activated_data_e_act_q_poly_t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_1 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_2 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_3 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_4 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_5 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_6 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_7 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_8 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_9 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_10 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_11 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_12 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_13 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_14 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_15 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_16 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_17 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_18 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_19 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_20 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_21 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_22 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_t_rec_rawIn_normDist = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_poly_t_rec_rawIn_fractIn} << activated_data_e_act_q_poly_t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_subnormFract = {_activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_poly_t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_poly_t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp = _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_t_rec_rawIn_isZero = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_t_rec_rawIn_isZero_0 = activated_data_e_act_q_poly_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_t_rec_rawIn_isSpecial = &_activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_t_rec_T_2 = activated_data_e_act_q_poly_t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial & _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_t_rec_rawIn_isNaN = _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_t_rec_rawIn_isInf = _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_t_rec_rawIn_sExp = _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T = ~activated_data_e_act_q_poly_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_poly_t_rec_rawIn_subnormFract : activated_data_e_act_q_poly_t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_t_rec_rawIn_sig = _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_t_rec_T = activated_data_e_act_q_poly_t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_1 = activated_data_e_act_q_poly_t_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_poly_t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_3 = {_activated_data_e_act_q_poly_t_rec_T_1[2:1], _activated_data_e_act_q_poly_t_rec_T_1[0] | _activated_data_e_act_q_poly_t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_t_rec_T_4 = {activated_data_e_act_q_poly_t_rec_rawIn_sign_0, _activated_data_e_act_q_poly_t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_t_rec_T_5 = activated_data_e_act_q_poly_t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_t_rec_T_6 = {_activated_data_e_act_q_poly_t_rec_T_4, _activated_data_e_act_q_poly_t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_t_rec_T_7 = activated_data_e_act_q_poly_t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_t_rec = {_activated_data_e_act_q_poly_t_rec_T_6, _activated_data_e_act_q_poly_t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_sign = activated_data_e_act_q_clipped_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_1 = activated_data_e_act_q_clipped_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_0 = activated_data_e_act_q_poly_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn = activated_data_e_act_q_clipped_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_1 = activated_data_e_act_q_clipped_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn = activated_data_e_act_q_clipped_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1 = activated_data_e_act_q_clipped_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn = activated_data_e_act_q_poly_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn = activated_data_e_act_q_poly_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_1 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_2 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_3 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_4 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_5 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_6 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_7 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_8 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_9 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_10 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_11 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_12 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_13 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_14 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_15 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_16 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_17 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_18 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_19 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_20 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_21 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_22 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn} << activated_data_e_act_q_poly_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_0 = activated_data_e_act_q_poly_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_2 = activated_data_e_act_q_poly_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract : activated_data_e_act_q_poly_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T = activated_data_e_act_q_poly_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_1 = activated_data_e_act_q_poly_self_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_3 = {_activated_data_e_act_q_poly_self_rec_T_1[2:1], _activated_data_e_act_q_poly_self_rec_T_1[0] | _activated_data_e_act_q_poly_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_4 = {activated_data_e_act_q_poly_self_rec_rawIn_sign_0, _activated_data_e_act_q_poly_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_5 = activated_data_e_act_q_poly_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_6 = {_activated_data_e_act_q_poly_self_rec_T_4, _activated_data_e_act_q_poly_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_7 = activated_data_e_act_q_poly_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec = {_activated_data_e_act_q_poly_self_rec_T_6, _activated_data_e_act_q_poly_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_result_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp = _activated_data_e_act_q_poly_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T = activated_data_e_act_q_poly_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_0 = activated_data_e_act_q_poly_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T = activated_data_e_act_q_poly_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T = activated_data_e_act_q_poly_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T = activated_data_e_act_q_poly_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T = _activated_data_e_act_q_poly_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_2 = _activated_data_e_act_q_poly_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal = $signed(activated_data_e_act_q_poly_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T = activated_data_e_act_q_poly_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T = activated_data_e_act_q_poly_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_1 = _activated_data_e_act_q_poly_result_bits_denormFract_T >> activated_data_e_act_q_poly_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract = _activated_data_e_act_q_poly_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T = activated_data_e_act_q_poly_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_1 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_2 = _activated_data_e_act_q_poly_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_3 = activated_data_e_act_q_poly_result_bits_isSubnormal ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_4 = activated_data_e_act_q_poly_result_bits_rawIn_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_5 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut = _activated_data_e_act_q_poly_result_bits_expOut_T_3 | _activated_data_e_act_q_poly_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T = activated_data_e_act_q_poly_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_1 = activated_data_e_act_q_poly_result_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut = activated_data_e_act_q_poly_result_bits_isSubnormal ? activated_data_e_act_q_poly_result_bits_denormFract : _activated_data_e_act_q_poly_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi = {activated_data_e_act_q_poly_result_bits_rawIn_sign, activated_data_e_act_q_poly_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T = {activated_data_e_act_q_poly_result_bits_hi, activated_data_e_act_q_poly_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_result_bits = _activated_data_e_act_q_poly_result_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_t_rec_rawIn_1_sign = activated_data_e_act_q_poly_t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_poly_t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_44 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_45 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_46 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_47 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_48 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_49 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_50 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_51 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_52 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_53 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_54 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_55 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_56 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_57 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_58 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_59 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_60 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_61 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_62 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_63 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_64 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_65 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_66 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_t_rec_rawIn_normDist_1 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1} << activated_data_e_act_q_poly_t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_poly_t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_poly_t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_t_rec_rawIn_isZero_1 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_t_rec_rawIn_1_isZero = activated_data_e_act_q_poly_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_t_rec_T_10 = activated_data_e_act_q_poly_t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_t_rec_rawIn_1_isNaN = _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_1 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_t_rec_rawIn_1_isInf = _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_t_rec_rawIn_1_sExp = _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_1 : activated_data_e_act_q_poly_t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_t_rec_rawIn_1_sig = _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_8 = activated_data_e_act_q_poly_t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_9 = activated_data_e_act_q_poly_t_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_poly_t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_11 = {_activated_data_e_act_q_poly_t_rec_T_9[2:1], _activated_data_e_act_q_poly_t_rec_T_9[0] | _activated_data_e_act_q_poly_t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_t_rec_T_12 = {activated_data_e_act_q_poly_t_rec_rawIn_1_sign, _activated_data_e_act_q_poly_t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_t_rec_T_13 = activated_data_e_act_q_poly_t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_t_rec_T_14 = {_activated_data_e_act_q_poly_t_rec_T_12, _activated_data_e_act_q_poly_t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_t_rec_T_15 = activated_data_e_act_q_poly_t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_t_rec_1 = {_activated_data_e_act_q_poly_t_rec_T_14, _activated_data_e_act_q_poly_t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_1_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_44 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_45 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_46 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_47 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_48 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_49 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_50 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_51 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_52 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_53 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_54 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_55 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_56 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_57 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_58 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_59 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_60 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_61 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_62 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_63 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_64 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_65 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_66 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_1 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_1 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_1_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_10 = activated_data_e_act_q_poly_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_1_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_1 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_1_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_1_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_1 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_1_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_8 = activated_data_e_act_q_poly_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_9 = activated_data_e_act_q_poly_self_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_11 = {_activated_data_e_act_q_poly_self_rec_T_9[2:1], _activated_data_e_act_q_poly_self_rec_T_9[0] | _activated_data_e_act_q_poly_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_12 = {activated_data_e_act_q_poly_self_rec_rawIn_1_sign, _activated_data_e_act_q_poly_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_13 = activated_data_e_act_q_poly_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_14 = {_activated_data_e_act_q_poly_self_rec_T_12, _activated_data_e_act_q_poly_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_15 = activated_data_e_act_q_poly_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_1 = {_activated_data_e_act_q_poly_self_rec_T_14, _activated_data_e_act_q_poly_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_result_1_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_1 = _activated_data_e_act_q_poly_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_1 = activated_data_e_act_q_poly_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_1 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_1_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_q_poly_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_1_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_5 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_1_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_1 = _activated_data_e_act_q_poly_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_1_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_1_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_6 = _activated_data_e_act_q_poly_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_1_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_1 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_2 = activated_data_e_act_q_poly_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_1 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_2 = activated_data_e_act_q_poly_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_3 = _activated_data_e_act_q_poly_result_bits_denormFract_T_2 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_1 = _activated_data_e_act_q_poly_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_6 = activated_data_e_act_q_poly_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_7 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_8 = _activated_data_e_act_q_poly_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_9 = activated_data_e_act_q_poly_result_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_10 = activated_data_e_act_q_poly_result_bits_rawIn_1_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_11 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_1 = _activated_data_e_act_q_poly_result_bits_expOut_T_9 | _activated_data_e_act_q_poly_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_2 = activated_data_e_act_q_poly_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_3 = activated_data_e_act_q_poly_result_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_1 = activated_data_e_act_q_poly_result_bits_isSubnormal_1 ? activated_data_e_act_q_poly_result_bits_denormFract_1 : _activated_data_e_act_q_poly_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_1 = {activated_data_e_act_q_poly_result_bits_rawIn_1_sign, activated_data_e_act_q_poly_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_1 = {activated_data_e_act_q_poly_result_bits_hi_1, activated_data_e_act_q_poly_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_result_1_bits = _activated_data_e_act_q_poly_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_m1_rec_rawIn_sign = activated_data_e_act_q_poly_result_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_m1_rec_rawIn_sign_0 = activated_data_e_act_q_poly_m1_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_m1_rec_rawIn_expIn = activated_data_e_act_q_poly_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_m1_rec_rawIn_fractIn = activated_data_e_act_q_poly_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn = activated_data_e_act_q_poly_m1_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_1 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_2 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_3 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_4 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_5 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_6 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_7 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_8 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_9 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_10 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_11 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_12 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_13 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_14 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_15 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_16 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_17 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_18 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_19 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_20 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_21 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_22 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_m1_rec_rawIn_normDist = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_poly_m1_rec_rawIn_fractIn} << activated_data_e_act_q_poly_m1_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract = {_activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_poly_m1_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_poly_m1_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp = _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T = activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZero = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn & activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZero_0 = activated_data_e_act_q_poly_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_T = activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial = &_activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_m1_rec_T_2 = activated_data_e_act_q_poly_m1_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_m1_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_m1_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_m1_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial & _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_m1_rec_rawIn_isNaN = _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T = activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial & activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_m1_rec_rawIn_isInf = _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_m1_rec_rawIn_sExp = _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T = ~activated_data_e_act_q_poly_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract : activated_data_e_act_q_poly_m1_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_m1_rec_rawIn_sig = _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T = activated_data_e_act_q_poly_m1_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_1 = activated_data_e_act_q_poly_m1_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_poly_m1_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_3 = {_activated_data_e_act_q_poly_m1_rec_T_1[2:1], _activated_data_e_act_q_poly_m1_rec_T_1[0] | _activated_data_e_act_q_poly_m1_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_m1_rec_T_4 = {activated_data_e_act_q_poly_m1_rec_rawIn_sign_0, _activated_data_e_act_q_poly_m1_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_m1_rec_T_5 = activated_data_e_act_q_poly_m1_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_m1_rec_T_6 = {_activated_data_e_act_q_poly_m1_rec_T_4, _activated_data_e_act_q_poly_m1_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_m1_rec_T_7 = activated_data_e_act_q_poly_m1_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_m1_rec = {_activated_data_e_act_q_poly_m1_rec_T_6, _activated_data_e_act_q_poly_m1_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_m2_rec_rawIn_sign = activated_data_e_act_q_poly_result_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_m2_rec_rawIn_sign_0 = activated_data_e_act_q_poly_m2_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_m2_rec_rawIn_expIn = activated_data_e_act_q_poly_result_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_m2_rec_rawIn_fractIn = activated_data_e_act_q_poly_result_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn = activated_data_e_act_q_poly_m2_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_1 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_2 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_3 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_4 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_5 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_6 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_7 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_8 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_9 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_10 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_11 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_12 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_13 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_14 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_15 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_16 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_17 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_18 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_19 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_20 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_21 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_22 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_m2_rec_rawIn_normDist = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_poly_m2_rec_rawIn_fractIn} << activated_data_e_act_q_poly_m2_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract = {_activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_poly_m2_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_poly_m2_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp = _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T = activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZero = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn & activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZero_0 = activated_data_e_act_q_poly_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_T = activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial = &_activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_m2_rec_T_2 = activated_data_e_act_q_poly_m2_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_m2_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_m2_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_m2_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial & _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_m2_rec_rawIn_isNaN = _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T = activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial & activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_m2_rec_rawIn_isInf = _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_m2_rec_rawIn_sExp = _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T = ~activated_data_e_act_q_poly_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract : activated_data_e_act_q_poly_m2_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_m2_rec_rawIn_sig = _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T = activated_data_e_act_q_poly_m2_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_1 = activated_data_e_act_q_poly_m2_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_poly_m2_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_3 = {_activated_data_e_act_q_poly_m2_rec_T_1[2:1], _activated_data_e_act_q_poly_m2_rec_T_1[0] | _activated_data_e_act_q_poly_m2_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_m2_rec_T_4 = {activated_data_e_act_q_poly_m2_rec_rawIn_sign_0, _activated_data_e_act_q_poly_m2_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_m2_rec_T_5 = activated_data_e_act_q_poly_m2_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_m2_rec_T_6 = {_activated_data_e_act_q_poly_m2_rec_T_4, _activated_data_e_act_q_poly_m2_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_m2_rec_T_7 = activated_data_e_act_q_poly_m2_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_m2_rec = {_activated_data_e_act_q_poly_m2_rec_T_6, _activated_data_e_act_q_poly_m2_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_2 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_sign_1 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_2 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_6 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_sign_5 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_6 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_10 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_sign_9 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_10 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_14 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_sign_13 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_14 = io_in_bits_acc_read_resp_igelu_qc_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_2_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_2 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_1 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_2 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_6 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_5 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_6 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_10 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_9 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_10 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_14 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_13 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_14 = io_in_bits_acc_read_resp_igelu_qc_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_1 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_5 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_9 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_13 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14 = io_in_bits_acc_read_resp_igelu_qc_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_88 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_89 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_90 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_91 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_92 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_93 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_94 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_95 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_96 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_97 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_98 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_99 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_100 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_101 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_102 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_103 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_104 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_105 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_106 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_107 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_108 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_109 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_110 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_2 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_2 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_2_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_18 = activated_data_e_act_q_poly_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_2_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_2 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_2_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_2_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_2 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_2_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_16 = activated_data_e_act_q_poly_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_17 = activated_data_e_act_q_poly_self_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_19 = {_activated_data_e_act_q_poly_self_rec_T_17[2:1], _activated_data_e_act_q_poly_self_rec_T_17[0] | _activated_data_e_act_q_poly_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_20 = {activated_data_e_act_q_poly_self_rec_rawIn_2_sign, _activated_data_e_act_q_poly_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_21 = activated_data_e_act_q_poly_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_22 = {_activated_data_e_act_q_poly_self_rec_T_20, _activated_data_e_act_q_poly_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_23 = activated_data_e_act_q_poly_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_2 = {_activated_data_e_act_q_poly_self_rec_T_22, _activated_data_e_act_q_poly_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_out_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_out_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_q_poly_out_bits_rawIn_exp = _activated_data_e_act_q_poly_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_out_bits_rawIn_isZero_T = activated_data_e_act_q_poly_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_out_bits_rawIn_isZero = _activated_data_e_act_q_poly_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_out_bits_rawIn_isZero_0 = activated_data_e_act_q_poly_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_T = activated_data_e_act_q_poly_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_out_bits_rawIn_isSpecial = &_activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T = activated_data_e_act_q_poly_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T = activated_data_e_act_q_poly_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_out_bits_rawIn_isSpecial & _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_out_bits_rawIn_isNaN = _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_out_bits_rawIn_isSpecial & _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_out_bits_rawIn_isInf = _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T = _activated_data_e_act_q_poly_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_out_bits_rawIn_sign = _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_q_poly_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_out_bits_rawIn_sExp = _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T = ~activated_data_e_act_q_poly_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_2 = _activated_data_e_act_q_poly_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_out_bits_rawIn_sig = _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_out_bits_isSubnormal = $signed(activated_data_e_act_q_poly_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_out_bits_denormShiftDist_T = activated_data_e_act_q_poly_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_out_bits_denormShiftDist = _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_out_bits_denormFract_T = activated_data_e_act_q_poly_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_out_bits_denormFract_T_1 = _activated_data_e_act_q_poly_out_bits_denormFract_T >> activated_data_e_act_q_poly_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_out_bits_denormFract = _activated_data_e_act_q_poly_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T = activated_data_e_act_q_poly_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_out_bits_expOut_T_1 = {1'h0, _activated_data_e_act_q_poly_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_2 = _activated_data_e_act_q_poly_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_3 = activated_data_e_act_q_poly_out_bits_isSubnormal ? 8'h0 : _activated_data_e_act_q_poly_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_out_bits_expOut_T_4 = activated_data_e_act_q_poly_out_bits_rawIn_isNaN | activated_data_e_act_q_poly_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_5 = {8{_activated_data_e_act_q_poly_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_out_bits_expOut = _activated_data_e_act_q_poly_out_bits_expOut_T_3 | _activated_data_e_act_q_poly_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_out_bits_fractOut_T = activated_data_e_act_q_poly_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_out_bits_fractOut_T_1 = activated_data_e_act_q_poly_out_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_q_poly_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_out_bits_fractOut = activated_data_e_act_q_poly_out_bits_isSubnormal ? activated_data_e_act_q_poly_out_bits_denormFract : _activated_data_e_act_q_poly_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_out_bits_hi = {activated_data_e_act_q_poly_out_bits_rawIn_sign, activated_data_e_act_q_poly_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_out_bits_T = {activated_data_e_act_q_poly_out_bits_hi, activated_data_e_act_q_poly_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_out_bits = _activated_data_e_act_q_poly_out_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_3 = activated_data_e_act_q_poly_out_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_3_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_3 = activated_data_e_act_q_poly_out_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3 = activated_data_e_act_q_poly_out_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_132 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_133 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_134 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_135 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_136 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_137 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_138 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_139 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_140 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_141 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_142 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_143 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_144 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_145 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_146 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_147 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_148 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_149 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_150 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_151 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_152 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_153 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_154 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_3 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_3 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_3_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_26 = activated_data_e_act_q_poly_self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_3_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_3 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_3_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_3_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_3 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_3_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_24 = activated_data_e_act_q_poly_self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_25 = activated_data_e_act_q_poly_self_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_27 = {_activated_data_e_act_q_poly_self_rec_T_25[2:1], _activated_data_e_act_q_poly_self_rec_T_25[0] | _activated_data_e_act_q_poly_self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_28 = {activated_data_e_act_q_poly_self_rec_rawIn_3_sign, _activated_data_e_act_q_poly_self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_29 = activated_data_e_act_q_poly_self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_30 = {_activated_data_e_act_q_poly_self_rec_T_28, _activated_data_e_act_q_poly_self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_31 = activated_data_e_act_q_poly_self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_3 = {_activated_data_e_act_q_poly_self_rec_T_30, _activated_data_e_act_q_poly_self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_2 = _activated_data_e_act_q_poly_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_2 = activated_data_e_act_q_poly_result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_2 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_2_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_q_poly_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_6 = activated_data_e_act_q_poly_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_2_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_8 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_2_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_2 = _activated_data_e_act_q_poly_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_2_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_2_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_10 = _activated_data_e_act_q_poly_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_2_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_2 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_4 = activated_data_e_act_q_poly_result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_2 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_4 = activated_data_e_act_q_poly_result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_5 = _activated_data_e_act_q_poly_result_bits_denormFract_T_4 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_2 = _activated_data_e_act_q_poly_result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_12 = activated_data_e_act_q_poly_result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_13 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_14 = _activated_data_e_act_q_poly_result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_15 = activated_data_e_act_q_poly_result_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_16 = activated_data_e_act_q_poly_result_bits_rawIn_2_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_17 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_2 = _activated_data_e_act_q_poly_result_bits_expOut_T_15 | _activated_data_e_act_q_poly_result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_4 = activated_data_e_act_q_poly_result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_5 = activated_data_e_act_q_poly_result_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_2 = activated_data_e_act_q_poly_result_bits_isSubnormal_2 ? activated_data_e_act_q_poly_result_bits_denormFract_2 : _activated_data_e_act_q_poly_result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_2 = {activated_data_e_act_q_poly_result_bits_rawIn_2_sign, activated_data_e_act_q_poly_result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_2 = {activated_data_e_act_q_poly_result_bits_hi_2, activated_data_e_act_q_poly_result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_bits = _activated_data_e_act_q_poly_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_erf_t_rec_rawIn_sign = activated_data_e_act_q_poly_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_t_rec_rawIn_sign_0 = activated_data_e_act_q_erf_t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_t_rec_rawIn_expIn = activated_data_e_act_q_poly_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_t_rec_rawIn_fractIn = activated_data_e_act_q_poly_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn = activated_data_e_act_q_erf_t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn = activated_data_e_act_q_erf_t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_1 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_2 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_3 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_4 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_5 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_6 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_7 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_8 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_9 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_10 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_11 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_12 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_13 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_14 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_15 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_16 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_17 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_18 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_19 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_20 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_21 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_22 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_t_rec_rawIn_normDist = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_erf_t_rec_rawIn_fractIn} << activated_data_e_act_q_erf_t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_t_rec_rawIn_subnormFract = {_activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_erf_t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_erf_t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp = _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T = activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_t_rec_rawIn_isZero = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn & activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_t_rec_rawIn_isZero_0 = activated_data_e_act_q_erf_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_T = activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_t_rec_rawIn_isSpecial = &_activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_t_rec_T_2 = activated_data_e_act_q_erf_t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_erf_t_rec_rawIn_isSpecial & _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_t_rec_rawIn_isNaN = _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T = activated_data_e_act_q_erf_t_rec_rawIn_isSpecial & activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_t_rec_rawIn_isInf = _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_t_rec_rawIn_sExp = _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T = ~activated_data_e_act_q_erf_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_erf_t_rec_rawIn_subnormFract : activated_data_e_act_q_erf_t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_t_rec_rawIn_sig = _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_t_rec_T = activated_data_e_act_q_erf_t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_1 = activated_data_e_act_q_erf_t_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_erf_t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_3 = {_activated_data_e_act_q_erf_t_rec_T_1[2:1], _activated_data_e_act_q_erf_t_rec_T_1[0] | _activated_data_e_act_q_erf_t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_t_rec_T_4 = {activated_data_e_act_q_erf_t_rec_rawIn_sign_0, _activated_data_e_act_q_erf_t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_t_rec_T_5 = activated_data_e_act_q_erf_t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_t_rec_T_6 = {_activated_data_e_act_q_erf_t_rec_T_4, _activated_data_e_act_q_erf_t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_t_rec_T_7 = activated_data_e_act_q_erf_t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_t_rec = {_activated_data_e_act_q_erf_t_rec_T_6, _activated_data_e_act_q_erf_t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_erf_self_rec_rawIn_sign = activated_data_e_act_q_sign_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_self_rec_rawIn_sign_0 = activated_data_e_act_q_erf_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_self_rec_rawIn_expIn = activated_data_e_act_q_sign_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_fractIn = activated_data_e_act_q_sign_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn = activated_data_e_act_q_erf_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn = activated_data_e_act_q_erf_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_1 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_2 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_3 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_4 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_5 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_6 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_7 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_8 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_9 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_10 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_11 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_12 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_13 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_14 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_15 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_16 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_17 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_18 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_19 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_20 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_21 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_22 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_self_rec_rawIn_normDist = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_erf_self_rec_rawIn_fractIn} << activated_data_e_act_q_erf_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_subnormFract = {_activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_erf_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_erf_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp = _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_self_rec_rawIn_isZero = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_self_rec_rawIn_isZero_0 = activated_data_e_act_q_erf_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_self_rec_rawIn_isSpecial = &_activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_self_rec_T_2 = activated_data_e_act_q_erf_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial & _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_self_rec_rawIn_isNaN = _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_self_rec_rawIn_isInf = _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_self_rec_rawIn_sExp = _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T = ~activated_data_e_act_q_erf_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_erf_self_rec_rawIn_subnormFract : activated_data_e_act_q_erf_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_self_rec_rawIn_sig = _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_self_rec_T = activated_data_e_act_q_erf_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_1 = activated_data_e_act_q_erf_self_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_erf_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_3 = {_activated_data_e_act_q_erf_self_rec_T_1[2:1], _activated_data_e_act_q_erf_self_rec_T_1[0] | _activated_data_e_act_q_erf_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_self_rec_T_4 = {activated_data_e_act_q_erf_self_rec_rawIn_sign_0, _activated_data_e_act_q_erf_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_self_rec_T_5 = activated_data_e_act_q_erf_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_self_rec_T_6 = {_activated_data_e_act_q_erf_self_rec_T_4, _activated_data_e_act_q_erf_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_self_rec_T_7 = activated_data_e_act_q_erf_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_self_rec = {_activated_data_e_act_q_erf_self_rec_T_6, _activated_data_e_act_q_erf_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_erf_out_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_erf_out_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_q_erf_out_bits_rawIn_exp = _activated_data_e_act_q_erf_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_erf_out_bits_rawIn_isZero_T = activated_data_e_act_q_erf_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_erf_out_bits_rawIn_isZero = _activated_data_e_act_q_erf_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_erf_out_bits_rawIn_isZero_0 = activated_data_e_act_q_erf_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_T = activated_data_e_act_q_erf_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_erf_out_bits_rawIn_isSpecial = &_activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_erf_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_erf_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_erf_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T = activated_data_e_act_q_erf_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T = activated_data_e_act_q_erf_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_q_erf_out_bits_rawIn_isSpecial & _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_erf_out_bits_rawIn_isNaN = _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_2 = activated_data_e_act_q_erf_out_bits_rawIn_isSpecial & _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_erf_out_bits_rawIn_isInf = _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T = _activated_data_e_act_q_erf_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_erf_out_bits_rawIn_sign = _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_q_erf_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_erf_out_bits_rawIn_sExp = _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T = ~activated_data_e_act_q_erf_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_2 = _activated_data_e_act_q_erf_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_1, _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_erf_out_bits_rawIn_sig = _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_erf_out_bits_isSubnormal = $signed(activated_data_e_act_q_erf_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_erf_out_bits_denormShiftDist_T = activated_data_e_act_q_erf_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_q_erf_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_erf_out_bits_denormShiftDist = _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_erf_out_bits_denormFract_T = activated_data_e_act_q_erf_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_erf_out_bits_denormFract_T_1 = _activated_data_e_act_q_erf_out_bits_denormFract_T >> activated_data_e_act_q_erf_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_erf_out_bits_denormFract = _activated_data_e_act_q_erf_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T = activated_data_e_act_q_erf_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_erf_out_bits_expOut_T_1 = {1'h0, _activated_data_e_act_q_erf_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_2 = _activated_data_e_act_q_erf_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_3 = activated_data_e_act_q_erf_out_bits_isSubnormal ? 8'h0 : _activated_data_e_act_q_erf_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_erf_out_bits_expOut_T_4 = activated_data_e_act_q_erf_out_bits_rawIn_isNaN | activated_data_e_act_q_erf_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_5 = {8{_activated_data_e_act_q_erf_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_erf_out_bits_expOut = _activated_data_e_act_q_erf_out_bits_expOut_T_3 | _activated_data_e_act_q_erf_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_erf_out_bits_fractOut_T = activated_data_e_act_q_erf_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_erf_out_bits_fractOut_T_1 = activated_data_e_act_q_erf_out_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_q_erf_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_erf_out_bits_fractOut = activated_data_e_act_q_erf_out_bits_isSubnormal ? activated_data_e_act_q_erf_out_bits_denormFract : _activated_data_e_act_q_erf_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_erf_out_bits_hi = {activated_data_e_act_q_erf_out_bits_rawIn_sign, activated_data_e_act_q_erf_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_erf_out_bits_T = {activated_data_e_act_q_erf_out_bits_hi, activated_data_e_act_q_erf_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_erf_out_bits = _activated_data_e_act_q_erf_out_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_erf_self_rec_rawIn_sign_1 = activated_data_e_act_q_erf_out_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_self_rec_rawIn_1_sign = activated_data_e_act_q_erf_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_self_rec_rawIn_expIn_1 = activated_data_e_act_q_erf_out_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1 = activated_data_e_act_q_erf_out_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_erf_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_44 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_45 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_46 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_47 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_48 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_49 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_50 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_51 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_52 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_53 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_54 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_55 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_56 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_57 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_58 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_59 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_60 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_61 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_62 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_63 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_64 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_65 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_66 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_self_rec_rawIn_normDist_1 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1} << activated_data_e_act_q_erf_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_erf_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_erf_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_self_rec_rawIn_isZero_1 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_self_rec_rawIn_1_isZero = activated_data_e_act_q_erf_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_self_rec_T_10 = activated_data_e_act_q_erf_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_self_rec_rawIn_1_isNaN = _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_1 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_self_rec_rawIn_1_isInf = _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_self_rec_rawIn_1_sExp = _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_1 : activated_data_e_act_q_erf_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_self_rec_rawIn_1_sig = _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_8 = activated_data_e_act_q_erf_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_9 = activated_data_e_act_q_erf_self_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_erf_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_11 = {_activated_data_e_act_q_erf_self_rec_T_9[2:1], _activated_data_e_act_q_erf_self_rec_T_9[0] | _activated_data_e_act_q_erf_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_self_rec_T_12 = {activated_data_e_act_q_erf_self_rec_rawIn_1_sign, _activated_data_e_act_q_erf_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_self_rec_T_13 = activated_data_e_act_q_erf_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_self_rec_T_14 = {_activated_data_e_act_q_erf_self_rec_T_12, _activated_data_e_act_q_erf_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_self_rec_T_15 = activated_data_e_act_q_erf_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_self_rec_1 = {_activated_data_e_act_q_erf_self_rec_T_14, _activated_data_e_act_q_erf_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_erf_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_erf_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_erf_result_bits_rawIn_exp = _activated_data_e_act_q_erf_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_erf_result_bits_rawIn_isZero_T = activated_data_e_act_q_erf_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_erf_result_bits_rawIn_isZero = _activated_data_e_act_q_erf_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_erf_result_bits_rawIn_isZero_0 = activated_data_e_act_q_erf_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_T = activated_data_e_act_q_erf_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_erf_result_bits_rawIn_isSpecial = &_activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_erf_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_erf_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_erf_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T = activated_data_e_act_q_erf_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T = activated_data_e_act_q_erf_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_q_erf_result_bits_rawIn_isSpecial & _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_erf_result_bits_rawIn_isNaN = _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_2 = activated_data_e_act_q_erf_result_bits_rawIn_isSpecial & _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_erf_result_bits_rawIn_isInf = _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T = _activated_data_e_act_q_erf_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_erf_result_bits_rawIn_sign = _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_q_erf_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_erf_result_bits_rawIn_sExp = _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T = ~activated_data_e_act_q_erf_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_2 = _activated_data_e_act_q_erf_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_1, _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_erf_result_bits_rawIn_sig = _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_erf_result_bits_isSubnormal = $signed(activated_data_e_act_q_erf_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_erf_result_bits_denormShiftDist_T = activated_data_e_act_q_erf_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_q_erf_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_erf_result_bits_denormShiftDist = _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_erf_result_bits_denormFract_T = activated_data_e_act_q_erf_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_erf_result_bits_denormFract_T_1 = _activated_data_e_act_q_erf_result_bits_denormFract_T >> activated_data_e_act_q_erf_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_erf_result_bits_denormFract = _activated_data_e_act_q_erf_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T = activated_data_e_act_q_erf_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_erf_result_bits_expOut_T_1 = {1'h0, _activated_data_e_act_q_erf_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_2 = _activated_data_e_act_q_erf_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_3 = activated_data_e_act_q_erf_result_bits_isSubnormal ? 8'h0 : _activated_data_e_act_q_erf_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_erf_result_bits_expOut_T_4 = activated_data_e_act_q_erf_result_bits_rawIn_isNaN | activated_data_e_act_q_erf_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_5 = {8{_activated_data_e_act_q_erf_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_erf_result_bits_expOut = _activated_data_e_act_q_erf_result_bits_expOut_T_3 | _activated_data_e_act_q_erf_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_erf_result_bits_fractOut_T = activated_data_e_act_q_erf_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_erf_result_bits_fractOut_T_1 = activated_data_e_act_q_erf_result_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_q_erf_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_erf_result_bits_fractOut = activated_data_e_act_q_erf_result_bits_isSubnormal ? activated_data_e_act_q_erf_result_bits_denormFract : _activated_data_e_act_q_erf_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_erf_result_bits_hi = {activated_data_e_act_q_erf_result_bits_rawIn_sign, activated_data_e_act_q_erf_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_erf_result_bits_T = {activated_data_e_act_q_erf_result_bits_hi, activated_data_e_act_q_erf_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_erf_bits = _activated_data_e_act_q_erf_result_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_t_rec_rawIn_1_sign = activated_data_e_act_t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_t_rec_rawIn_normDist_T_44 = activated_data_e_act_t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_45 = activated_data_e_act_t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_46 = activated_data_e_act_t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_47 = activated_data_e_act_t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_48 = activated_data_e_act_t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_49 = activated_data_e_act_t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_50 = activated_data_e_act_t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_51 = activated_data_e_act_t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_52 = activated_data_e_act_t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_53 = activated_data_e_act_t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_54 = activated_data_e_act_t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_55 = activated_data_e_act_t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_56 = activated_data_e_act_t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_57 = activated_data_e_act_t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_58 = activated_data_e_act_t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_59 = activated_data_e_act_t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_60 = activated_data_e_act_t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_61 = activated_data_e_act_t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_62 = activated_data_e_act_t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_63 = activated_data_e_act_t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_64 = activated_data_e_act_t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_65 = activated_data_e_act_t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_66 = activated_data_e_act_t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_67 = _activated_data_e_act_t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_68 = _activated_data_e_act_t_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_69 = _activated_data_e_act_t_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_70 = _activated_data_e_act_t_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_71 = _activated_data_e_act_t_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_72 = _activated_data_e_act_t_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_73 = _activated_data_e_act_t_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_74 = _activated_data_e_act_t_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_75 = _activated_data_e_act_t_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_76 = _activated_data_e_act_t_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_77 = _activated_data_e_act_t_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_78 = _activated_data_e_act_t_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_79 = _activated_data_e_act_t_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_80 = _activated_data_e_act_t_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_81 = _activated_data_e_act_t_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_82 = _activated_data_e_act_t_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_83 = _activated_data_e_act_t_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_84 = _activated_data_e_act_t_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_85 = _activated_data_e_act_t_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_86 = _activated_data_e_act_t_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_87 = _activated_data_e_act_t_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_1 = _activated_data_e_act_t_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_t_rec_rawIn_fractIn_1} << activated_data_e_act_t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_1 = {_activated_data_e_act_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_t_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_1 = _activated_data_e_act_t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_2 = activated_data_e_act_t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_t_rec_rawIn_isZero_1 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_t_rec_rawIn_1_isZero = activated_data_e_act_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_1 = activated_data_e_act_t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_t_rec_rawIn_isSpecial_1 = &_activated_data_e_act_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_T_10 = activated_data_e_act_t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_t_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_t_rec_rawIn_isSpecial_1 & _activated_data_e_act_t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_t_rec_rawIn_1_isNaN = _activated_data_e_act_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_t_rec_rawIn_out_isInf_T_1 = activated_data_e_act_t_rec_rawIn_isSpecial_1 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_t_rec_rawIn_1_isInf = _activated_data_e_act_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_t_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_t_rec_rawIn_1_sExp = _activated_data_e_act_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_6 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_t_rec_rawIn_subnormFract_1 : activated_data_e_act_t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_t_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_t_rec_rawIn_out_sig_T_5, _activated_data_e_act_t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_t_rec_rawIn_1_sig = _activated_data_e_act_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_t_rec_T_8 = activated_data_e_act_t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_9 = activated_data_e_act_t_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_t_rec_T_11 = {_activated_data_e_act_t_rec_T_9[2:1], _activated_data_e_act_t_rec_T_9[0] | _activated_data_e_act_t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_t_rec_T_12 = {activated_data_e_act_t_rec_rawIn_1_sign, _activated_data_e_act_t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_t_rec_T_13 = activated_data_e_act_t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_t_rec_T_14 = {_activated_data_e_act_t_rec_T_12, _activated_data_e_act_t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_t_rec_T_15 = activated_data_e_act_t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_t_rec_1 = {_activated_data_e_act_t_rec_T_14, _activated_data_e_act_t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_self_rec_rawIn_sign_1 = activated_data_e_act_q_erf_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_1_sign = activated_data_e_act_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_1 = activated_data_e_act_q_erf_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_1 = activated_data_e_act_q_erf_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_44 = activated_data_e_act_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_45 = activated_data_e_act_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_46 = activated_data_e_act_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_47 = activated_data_e_act_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_48 = activated_data_e_act_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_49 = activated_data_e_act_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_50 = activated_data_e_act_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_51 = activated_data_e_act_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_52 = activated_data_e_act_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_53 = activated_data_e_act_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_54 = activated_data_e_act_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_55 = activated_data_e_act_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_56 = activated_data_e_act_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_57 = activated_data_e_act_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_58 = activated_data_e_act_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_59 = activated_data_e_act_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_60 = activated_data_e_act_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_61 = activated_data_e_act_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_62 = activated_data_e_act_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_63 = activated_data_e_act_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_64 = activated_data_e_act_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_65 = activated_data_e_act_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_66 = activated_data_e_act_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_67 = _activated_data_e_act_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_68 = _activated_data_e_act_self_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_69 = _activated_data_e_act_self_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_70 = _activated_data_e_act_self_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_71 = _activated_data_e_act_self_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_72 = _activated_data_e_act_self_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_73 = _activated_data_e_act_self_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_74 = _activated_data_e_act_self_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_75 = _activated_data_e_act_self_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_76 = _activated_data_e_act_self_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_77 = _activated_data_e_act_self_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_78 = _activated_data_e_act_self_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_79 = _activated_data_e_act_self_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_80 = _activated_data_e_act_self_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_81 = _activated_data_e_act_self_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_82 = _activated_data_e_act_self_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_83 = _activated_data_e_act_self_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_84 = _activated_data_e_act_self_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_85 = _activated_data_e_act_self_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_86 = _activated_data_e_act_self_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_87 = _activated_data_e_act_self_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_1 = _activated_data_e_act_self_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_1} << activated_data_e_act_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_1 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_1 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_2 = activated_data_e_act_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_1 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_1_isZero = activated_data_e_act_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_1 = activated_data_e_act_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_1 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_10 = activated_data_e_act_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_self_rec_rawIn_isSpecial_1 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_1_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_1 = activated_data_e_act_self_rec_rawIn_isSpecial_1 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_1_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_1_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_6 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_self_rec_rawIn_subnormFract_1 : activated_data_e_act_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_5, _activated_data_e_act_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_1_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_8 = activated_data_e_act_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_9 = activated_data_e_act_self_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_11 = {_activated_data_e_act_self_rec_T_9[2:1], _activated_data_e_act_self_rec_T_9[0] | _activated_data_e_act_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_12 = {activated_data_e_act_self_rec_rawIn_1_sign, _activated_data_e_act_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_13 = activated_data_e_act_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_14 = {_activated_data_e_act_self_rec_T_12, _activated_data_e_act_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_15 = activated_data_e_act_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_1 = {_activated_data_e_act_self_rec_T_14, _activated_data_e_act_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_4; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_2_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_1 = _activated_data_e_act_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_1 = activated_data_e_act_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_1 = _activated_data_e_act_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_1_isZero = activated_data_e_act_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_1 = activated_data_e_act_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_1 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_3 = activated_data_e_act_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_1_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_5 = activated_data_e_act_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_1_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_1 = _activated_data_e_act_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_1_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_1_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_6 = _activated_data_e_act_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_5, _activated_data_e_act_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_1_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_1 = $signed(activated_data_e_act_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_2 = activated_data_e_act_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_1 = _activated_data_e_act_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_2 = activated_data_e_act_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_3 = _activated_data_e_act_result_bits_denormFract_T_2 >> activated_data_e_act_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_1 = _activated_data_e_act_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_6 = activated_data_e_act_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_7 = {1'h0, _activated_data_e_act_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_8 = _activated_data_e_act_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_9 = activated_data_e_act_result_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_10 = activated_data_e_act_result_bits_rawIn_1_isNaN | activated_data_e_act_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_11 = {8{_activated_data_e_act_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_1 = _activated_data_e_act_result_bits_expOut_T_9 | _activated_data_e_act_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_2 = activated_data_e_act_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_3 = activated_data_e_act_result_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_1 = activated_data_e_act_result_bits_isSubnormal_1 ? activated_data_e_act_result_bits_denormFract_1 : _activated_data_e_act_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_1 = {activated_data_e_act_result_bits_rawIn_1_sign, activated_data_e_act_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_4 = {activated_data_e_act_result_bits_hi_1, activated_data_e_act_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_2_bits = _activated_data_e_act_result_bits_T_4; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_t_rec_rawIn_sign_2 = activated_data_e_act_result_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_2_sign = activated_data_e_act_t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_2 = activated_data_e_act_result_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_2 = activated_data_e_act_result_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_t_rec_rawIn_normDist_T_88 = activated_data_e_act_t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_89 = activated_data_e_act_t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_90 = activated_data_e_act_t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_91 = activated_data_e_act_t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_92 = activated_data_e_act_t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_93 = activated_data_e_act_t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_94 = activated_data_e_act_t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_95 = activated_data_e_act_t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_96 = activated_data_e_act_t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_97 = activated_data_e_act_t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_98 = activated_data_e_act_t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_99 = activated_data_e_act_t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_100 = activated_data_e_act_t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_101 = activated_data_e_act_t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_102 = activated_data_e_act_t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_103 = activated_data_e_act_t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_104 = activated_data_e_act_t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_105 = activated_data_e_act_t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_106 = activated_data_e_act_t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_107 = activated_data_e_act_t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_108 = activated_data_e_act_t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_109 = activated_data_e_act_t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_110 = activated_data_e_act_t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_111 = _activated_data_e_act_t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_112 = _activated_data_e_act_t_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_113 = _activated_data_e_act_t_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_114 = _activated_data_e_act_t_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_115 = _activated_data_e_act_t_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_116 = _activated_data_e_act_t_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_117 = _activated_data_e_act_t_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_118 = _activated_data_e_act_t_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_119 = _activated_data_e_act_t_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_120 = _activated_data_e_act_t_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_121 = _activated_data_e_act_t_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_122 = _activated_data_e_act_t_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_123 = _activated_data_e_act_t_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_124 = _activated_data_e_act_t_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_125 = _activated_data_e_act_t_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_126 = _activated_data_e_act_t_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_127 = _activated_data_e_act_t_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_128 = _activated_data_e_act_t_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_129 = _activated_data_e_act_t_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_130 = _activated_data_e_act_t_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_131 = _activated_data_e_act_t_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_2 = _activated_data_e_act_t_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_t_rec_rawIn_fractIn_2} << activated_data_e_act_t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_2 = {_activated_data_e_act_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_t_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_2 = _activated_data_e_act_t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_4 = activated_data_e_act_t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_t_rec_rawIn_isZero_2 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_t_rec_rawIn_2_isZero = activated_data_e_act_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_2 = activated_data_e_act_t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_t_rec_rawIn_isSpecial_2 = &_activated_data_e_act_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_T_18 = activated_data_e_act_t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_t_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_t_rec_rawIn_isSpecial_2 & _activated_data_e_act_t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_t_rec_rawIn_2_isNaN = _activated_data_e_act_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_t_rec_rawIn_out_isInf_T_2 = activated_data_e_act_t_rec_rawIn_isSpecial_2 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_t_rec_rawIn_2_isInf = _activated_data_e_act_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_t_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_t_rec_rawIn_2_sExp = _activated_data_e_act_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_10 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_t_rec_rawIn_subnormFract_2 : activated_data_e_act_t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_t_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_t_rec_rawIn_out_sig_T_9, _activated_data_e_act_t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_t_rec_rawIn_2_sig = _activated_data_e_act_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_t_rec_T_16 = activated_data_e_act_t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_17 = activated_data_e_act_t_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_t_rec_T_19 = {_activated_data_e_act_t_rec_T_17[2:1], _activated_data_e_act_t_rec_T_17[0] | _activated_data_e_act_t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_t_rec_T_20 = {activated_data_e_act_t_rec_rawIn_2_sign, _activated_data_e_act_t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_t_rec_T_21 = activated_data_e_act_t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_t_rec_T_22 = {_activated_data_e_act_t_rec_T_20, _activated_data_e_act_t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_t_rec_T_23 = activated_data_e_act_t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_t_rec_2 = {_activated_data_e_act_t_rec_T_22, _activated_data_e_act_t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_self_rec_rawIn_2_sign = activated_data_e_act_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_88 = activated_data_e_act_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_89 = activated_data_e_act_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_90 = activated_data_e_act_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_91 = activated_data_e_act_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_92 = activated_data_e_act_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_93 = activated_data_e_act_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_94 = activated_data_e_act_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_95 = activated_data_e_act_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_96 = activated_data_e_act_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_97 = activated_data_e_act_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_98 = activated_data_e_act_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_99 = activated_data_e_act_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_100 = activated_data_e_act_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_101 = activated_data_e_act_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_102 = activated_data_e_act_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_103 = activated_data_e_act_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_104 = activated_data_e_act_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_105 = activated_data_e_act_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_106 = activated_data_e_act_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_107 = activated_data_e_act_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_108 = activated_data_e_act_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_109 = activated_data_e_act_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_110 = activated_data_e_act_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_111 = _activated_data_e_act_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_112 = _activated_data_e_act_self_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_113 = _activated_data_e_act_self_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_114 = _activated_data_e_act_self_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_115 = _activated_data_e_act_self_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_116 = _activated_data_e_act_self_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_117 = _activated_data_e_act_self_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_118 = _activated_data_e_act_self_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_119 = _activated_data_e_act_self_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_120 = _activated_data_e_act_self_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_121 = _activated_data_e_act_self_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_122 = _activated_data_e_act_self_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_123 = _activated_data_e_act_self_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_124 = _activated_data_e_act_self_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_125 = _activated_data_e_act_self_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_126 = _activated_data_e_act_self_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_127 = _activated_data_e_act_self_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_128 = _activated_data_e_act_self_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_129 = _activated_data_e_act_self_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_130 = _activated_data_e_act_self_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_131 = _activated_data_e_act_self_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_2 = _activated_data_e_act_self_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_2} << activated_data_e_act_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_2 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_2 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_4 = activated_data_e_act_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_2 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_2_isZero = activated_data_e_act_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_2 = activated_data_e_act_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_2 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_18 = activated_data_e_act_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_self_rec_rawIn_isSpecial_2 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_2_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_2 = activated_data_e_act_self_rec_rawIn_isSpecial_2 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_2_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_2_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_10 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_self_rec_rawIn_subnormFract_2 : activated_data_e_act_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_9, _activated_data_e_act_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_2_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_16 = activated_data_e_act_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_17 = activated_data_e_act_self_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_19 = {_activated_data_e_act_self_rec_T_17[2:1], _activated_data_e_act_self_rec_T_17[0] | _activated_data_e_act_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_20 = {activated_data_e_act_self_rec_rawIn_2_sign, _activated_data_e_act_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_21 = activated_data_e_act_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_22 = {_activated_data_e_act_self_rec_T_20, _activated_data_e_act_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_23 = activated_data_e_act_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_2 = {_activated_data_e_act_self_rec_T_22, _activated_data_e_act_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_out_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_out_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_out_bits_rawIn_exp = _activated_data_e_act_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_out_bits_rawIn_isZero_T = activated_data_e_act_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_out_bits_rawIn_isZero = _activated_data_e_act_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_out_bits_rawIn_isZero_0 = activated_data_e_act_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_out_bits_rawIn_isSpecial_T = activated_data_e_act_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_out_bits_rawIn_isSpecial = &_activated_data_e_act_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_out_bits_rawIn_out_isNaN_T = activated_data_e_act_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T = activated_data_e_act_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_out_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_out_bits_rawIn_isSpecial & _activated_data_e_act_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_out_bits_rawIn_isNaN = _activated_data_e_act_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_out_bits_rawIn_out_isInf_T_2 = activated_data_e_act_out_bits_rawIn_isSpecial & _activated_data_e_act_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_out_bits_rawIn_isInf = _activated_data_e_act_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_out_bits_rawIn_out_sign_T = _activated_data_e_act_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_out_bits_rawIn_sign = _activated_data_e_act_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_out_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_out_bits_rawIn_sExp = _activated_data_e_act_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_out_bits_rawIn_out_sig_T = ~activated_data_e_act_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_2 = _activated_data_e_act_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_out_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_out_bits_rawIn_out_sig_T_1, _activated_data_e_act_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_out_bits_rawIn_sig = _activated_data_e_act_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_out_bits_isSubnormal = $signed(activated_data_e_act_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_out_bits_denormShiftDist_T = activated_data_e_act_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_out_bits_denormShiftDist = _activated_data_e_act_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_out_bits_denormFract_T = activated_data_e_act_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_out_bits_denormFract_T_1 = _activated_data_e_act_out_bits_denormFract_T >> activated_data_e_act_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_out_bits_denormFract = _activated_data_e_act_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_out_bits_expOut_T = activated_data_e_act_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_out_bits_expOut_T_1 = {1'h0, _activated_data_e_act_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_out_bits_expOut_T_2 = _activated_data_e_act_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_out_bits_expOut_T_3 = activated_data_e_act_out_bits_isSubnormal ? 8'h0 : _activated_data_e_act_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_out_bits_expOut_T_4 = activated_data_e_act_out_bits_rawIn_isNaN | activated_data_e_act_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_out_bits_expOut_T_5 = {8{_activated_data_e_act_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_out_bits_expOut = _activated_data_e_act_out_bits_expOut_T_3 | _activated_data_e_act_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_out_bits_fractOut_T = activated_data_e_act_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_out_bits_fractOut_T_1 = activated_data_e_act_out_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_out_bits_fractOut = activated_data_e_act_out_bits_isSubnormal ? activated_data_e_act_out_bits_denormFract : _activated_data_e_act_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_out_bits_hi = {activated_data_e_act_out_bits_rawIn_sign, activated_data_e_act_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_out_bits_T = {activated_data_e_act_out_bits_hi, activated_data_e_act_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_out_bits = _activated_data_e_act_out_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_self_rec_rawIn_sign_3 = activated_data_e_act_out_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_3_sign = activated_data_e_act_self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_3 = activated_data_e_act_out_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_3 = activated_data_e_act_out_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_132 = activated_data_e_act_self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_133 = activated_data_e_act_self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_134 = activated_data_e_act_self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_135 = activated_data_e_act_self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_136 = activated_data_e_act_self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_137 = activated_data_e_act_self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_138 = activated_data_e_act_self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_139 = activated_data_e_act_self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_140 = activated_data_e_act_self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_141 = activated_data_e_act_self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_142 = activated_data_e_act_self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_143 = activated_data_e_act_self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_144 = activated_data_e_act_self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_145 = activated_data_e_act_self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_146 = activated_data_e_act_self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_147 = activated_data_e_act_self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_148 = activated_data_e_act_self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_149 = activated_data_e_act_self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_150 = activated_data_e_act_self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_151 = activated_data_e_act_self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_152 = activated_data_e_act_self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_153 = activated_data_e_act_self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_154 = activated_data_e_act_self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_155 = _activated_data_e_act_self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_156 = _activated_data_e_act_self_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_157 = _activated_data_e_act_self_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_158 = _activated_data_e_act_self_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_159 = _activated_data_e_act_self_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_160 = _activated_data_e_act_self_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_161 = _activated_data_e_act_self_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_162 = _activated_data_e_act_self_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_163 = _activated_data_e_act_self_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_164 = _activated_data_e_act_self_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_165 = _activated_data_e_act_self_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_166 = _activated_data_e_act_self_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_167 = _activated_data_e_act_self_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_168 = _activated_data_e_act_self_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_169 = _activated_data_e_act_self_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_170 = _activated_data_e_act_self_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_171 = _activated_data_e_act_self_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_172 = _activated_data_e_act_self_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_173 = _activated_data_e_act_self_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_174 = _activated_data_e_act_self_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_175 = _activated_data_e_act_self_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_3 = _activated_data_e_act_self_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_3} << activated_data_e_act_self_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_3 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_3 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_6 = activated_data_e_act_self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_3 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_3_isZero = activated_data_e_act_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_3 = activated_data_e_act_self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_3 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_26 = activated_data_e_act_self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_self_rec_rawIn_isSpecial_3 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_3_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_3 = activated_data_e_act_self_rec_rawIn_isSpecial_3 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_3_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_3_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_14 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_self_rec_rawIn_subnormFract_3 : activated_data_e_act_self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_13, _activated_data_e_act_self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_3_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_24 = activated_data_e_act_self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_25 = activated_data_e_act_self_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_27 = {_activated_data_e_act_self_rec_T_25[2:1], _activated_data_e_act_self_rec_T_25[0] | _activated_data_e_act_self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_28 = {activated_data_e_act_self_rec_rawIn_3_sign, _activated_data_e_act_self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_29 = activated_data_e_act_self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_30 = {_activated_data_e_act_self_rec_T_28, _activated_data_e_act_self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_31 = activated_data_e_act_self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_3 = {_activated_data_e_act_self_rec_T_30, _activated_data_e_act_self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_5; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_3_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_2 = _activated_data_e_act_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_2 = activated_data_e_act_result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_2 = _activated_data_e_act_result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_2_isZero = activated_data_e_act_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_2 = activated_data_e_act_result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_2 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_6 = activated_data_e_act_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_2_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_8 = activated_data_e_act_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_2_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_2 = _activated_data_e_act_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_2_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_2_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_10 = _activated_data_e_act_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_9, _activated_data_e_act_result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_2_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_2 = $signed(activated_data_e_act_result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_4 = activated_data_e_act_result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_2 = _activated_data_e_act_result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_4 = activated_data_e_act_result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_5 = _activated_data_e_act_result_bits_denormFract_T_4 >> activated_data_e_act_result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_2 = _activated_data_e_act_result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_12 = activated_data_e_act_result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_13 = {1'h0, _activated_data_e_act_result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_14 = _activated_data_e_act_result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_15 = activated_data_e_act_result_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_16 = activated_data_e_act_result_bits_rawIn_2_isNaN | activated_data_e_act_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_17 = {8{_activated_data_e_act_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_2 = _activated_data_e_act_result_bits_expOut_T_15 | _activated_data_e_act_result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_4 = activated_data_e_act_result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_5 = activated_data_e_act_result_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_2 = activated_data_e_act_result_bits_isSubnormal_2 ? activated_data_e_act_result_bits_denormFract_2 : _activated_data_e_act_result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_2 = {activated_data_e_act_result_bits_rawIn_2_sign, activated_data_e_act_result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_5 = {activated_data_e_act_result_bits_hi_2, activated_data_e_act_result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_3_bits = _activated_data_e_act_result_bits_T_5; // @[fNFromRecFN.scala:66:12] wire _GEN_2 = io_in_bits_acc_read_resp_act_0 == 3'h4; // @[AccumulatorScale.scala:88:7, :123:69] wire _activated_data_e_act_T_9; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_9 = _GEN_2; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_4; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_4 = _GEN_2; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_25; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_25 = _GEN_2; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_14; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_14 = _GEN_2; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_41; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_41 = _GEN_2; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_24; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_24 = _GEN_2; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_57; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_57 = _GEN_2; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_34; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_34 = _GEN_2; // @[AccumulatorScale.scala:123:69, :130:69] wire activated_data_e_act_self_rec_rawIn_4_sign = activated_data_e_act_self_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_self_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_self_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_176 = activated_data_e_act_self_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_177 = activated_data_e_act_self_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_178 = activated_data_e_act_self_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_179 = activated_data_e_act_self_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_180 = activated_data_e_act_self_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_181 = activated_data_e_act_self_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_182 = activated_data_e_act_self_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_183 = activated_data_e_act_self_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_184 = activated_data_e_act_self_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_185 = activated_data_e_act_self_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_186 = activated_data_e_act_self_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_187 = activated_data_e_act_self_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_188 = activated_data_e_act_self_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_189 = activated_data_e_act_self_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_190 = activated_data_e_act_self_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_191 = activated_data_e_act_self_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_192 = activated_data_e_act_self_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_193 = activated_data_e_act_self_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_194 = activated_data_e_act_self_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_195 = activated_data_e_act_self_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_196 = activated_data_e_act_self_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_197 = activated_data_e_act_self_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_198 = activated_data_e_act_self_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_199 = _activated_data_e_act_self_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_200 = _activated_data_e_act_self_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_201 = _activated_data_e_act_self_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_202 = _activated_data_e_act_self_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_203 = _activated_data_e_act_self_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_204 = _activated_data_e_act_self_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_205 = _activated_data_e_act_self_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_206 = _activated_data_e_act_self_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_207 = _activated_data_e_act_self_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_208 = _activated_data_e_act_self_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_209 = _activated_data_e_act_self_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_210 = _activated_data_e_act_self_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_211 = _activated_data_e_act_self_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_212 = _activated_data_e_act_self_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_213 = _activated_data_e_act_self_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_214 = _activated_data_e_act_self_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_215 = _activated_data_e_act_self_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_216 = _activated_data_e_act_self_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_217 = _activated_data_e_act_self_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_218 = _activated_data_e_act_self_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_219 = _activated_data_e_act_self_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_4 = _activated_data_e_act_self_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_4} << activated_data_e_act_self_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_4 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_4 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_8 = activated_data_e_act_self_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_4 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_4_isZero = activated_data_e_act_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_4 = activated_data_e_act_self_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_4 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_34 = activated_data_e_act_self_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_self_rec_rawIn_isSpecial_4 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_4_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_4 = activated_data_e_act_self_rec_rawIn_isSpecial_4 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_4_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_4_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_18 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_self_rec_rawIn_subnormFract_4 : activated_data_e_act_self_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_17, _activated_data_e_act_self_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_4_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_32 = activated_data_e_act_self_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_33 = activated_data_e_act_self_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_35 = {_activated_data_e_act_self_rec_T_33[2:1], _activated_data_e_act_self_rec_T_33[0] | _activated_data_e_act_self_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_36 = {activated_data_e_act_self_rec_rawIn_4_sign, _activated_data_e_act_self_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_37 = activated_data_e_act_self_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_38 = {_activated_data_e_act_self_rec_T_36, _activated_data_e_act_self_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_39 = activated_data_e_act_self_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_4 = {_activated_data_e_act_self_rec_T_38, _activated_data_e_act_self_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_6; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_4_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_3 = _activated_data_e_act_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_3 = activated_data_e_act_result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_3 = _activated_data_e_act_result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_3_isZero = activated_data_e_act_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_3 = activated_data_e_act_result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_3 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_9 = activated_data_e_act_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_3_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_11 = activated_data_e_act_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_3_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_3 = _activated_data_e_act_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_3_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_3_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_14 = _activated_data_e_act_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_13, _activated_data_e_act_result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_3_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_3 = $signed(activated_data_e_act_result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_6 = activated_data_e_act_result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_3 = _activated_data_e_act_result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_6 = activated_data_e_act_result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_7 = _activated_data_e_act_result_bits_denormFract_T_6 >> activated_data_e_act_result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_3 = _activated_data_e_act_result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_18 = activated_data_e_act_result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_19 = {1'h0, _activated_data_e_act_result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_20 = _activated_data_e_act_result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_21 = activated_data_e_act_result_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_22 = activated_data_e_act_result_bits_rawIn_3_isNaN | activated_data_e_act_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_23 = {8{_activated_data_e_act_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_3 = _activated_data_e_act_result_bits_expOut_T_21 | _activated_data_e_act_result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_6 = activated_data_e_act_result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_7 = activated_data_e_act_result_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_3 = activated_data_e_act_result_bits_isSubnormal_3 ? activated_data_e_act_result_bits_denormFract_3 : _activated_data_e_act_result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_3 = {activated_data_e_act_result_bits_rawIn_3_sign, activated_data_e_act_result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_6 = {activated_data_e_act_result_bits_hi_3, activated_data_e_act_result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_4_bits = _activated_data_e_act_result_bits_T_6; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_neg_q_iexp_t_sgn = activated_data_e_act_result_4_bits[31]; // @[Arithmetic.scala:426:26, :432:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_sign = activated_data_e_act_result_4_bits[31]; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_neg_q_iexp_neg_t_T = ~activated_data_e_act_neg_q_iexp_t_sgn; // @[Arithmetic.scala:432:27, :433:25] wire [30:0] _activated_data_e_act_neg_q_iexp_neg_t_T_1 = activated_data_e_act_result_4_bits[30:0]; // @[Arithmetic.scala:426:26, :433:39] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_T_2 = {_activated_data_e_act_neg_q_iexp_neg_t_T, _activated_data_e_act_neg_q_iexp_neg_t_T_1}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_WIRE = _activated_data_e_act_neg_q_iexp_neg_t_T_2; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_T_3; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_neg_q_iexp_neg_t_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_neg_q_iexp_neg_t_T_3 = _activated_data_e_act_neg_q_iexp_neg_t_WIRE; // @[Arithmetic.scala:433:65] assign activated_data_e_act_neg_q_iexp_neg_t_bits = _activated_data_e_act_neg_q_iexp_neg_t_T_3; // @[Arithmetic.scala:433:65] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_sign = activated_data_e_act_neg_q_iexp_neg_t_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_sign_0 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn = activated_data_e_act_neg_q_iexp_neg_t_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn = activated_data_e_act_neg_q_iexp_neg_t_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn = activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_1 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_2 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_3 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_4 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_5 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_6 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_7 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_8 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_9 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_10 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_11 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_12 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_13 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_14 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_15 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_16 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_17 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_18 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_19 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_20 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_21 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_22 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_23 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_24 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_25 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_26 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_27 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_28 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_29 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_30 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_31 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_32 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_33 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_34 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_35 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_36 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_37 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_38 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_39 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_40 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_41 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_42 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_43 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn} << activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract = {_activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn ? _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T = activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn & activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_0 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_T = activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial = &_activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_neg_q_iexp_t_rec_T_2 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T = ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial & _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_isNaN = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial & activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_isInf = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_sExp = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T = ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_2 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn ? activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract : activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_1, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_sig = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T = activated_data_e_act_neg_q_iexp_t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_1 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_neg_q_iexp_t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_3 = {_activated_data_e_act_neg_q_iexp_t_rec_T_1[2:1], _activated_data_e_act_neg_q_iexp_t_rec_T_1[0] | _activated_data_e_act_neg_q_iexp_t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_neg_q_iexp_t_rec_T_4 = {activated_data_e_act_neg_q_iexp_t_rec_rawIn_sign_0, _activated_data_e_act_neg_q_iexp_t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_neg_q_iexp_t_rec_T_5 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_T_6 = {_activated_data_e_act_neg_q_iexp_t_rec_T_4, _activated_data_e_act_neg_q_iexp_t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_neg_q_iexp_t_rec_T_7 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_neg_q_iexp_t_rec = {_activated_data_e_act_neg_q_iexp_t_rec_T_6, _activated_data_e_act_neg_q_iexp_t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_neg_q_iexp_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_neg_q_iexp_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp = _activated_data_e_act_neg_q_iexp_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_T = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_0 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_T = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial = &_activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial & _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_isNaN = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_2 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial & _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_isInf = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T = _activated_data_e_act_neg_q_iexp_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_sign = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_sExp = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T = ~activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_2 = _activated_data_e_act_neg_q_iexp_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_1, _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_sig = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_neg_q_iexp_result_bits_isSubnormal = $signed(activated_data_e_act_neg_q_iexp_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T = activated_data_e_act_neg_q_iexp_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist = _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T = activated_data_e_act_neg_q_iexp_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_1 = _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T >> activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_neg_q_iexp_result_bits_denormFract = _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T = activated_data_e_act_neg_q_iexp_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_1 = {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_2 = _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_3 = activated_data_e_act_neg_q_iexp_result_bits_isSubnormal ? 8'h0 : _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_4 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isNaN | activated_data_e_act_neg_q_iexp_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_5 = {8{_activated_data_e_act_neg_q_iexp_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_neg_q_iexp_result_bits_expOut = _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_3 | _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T = activated_data_e_act_neg_q_iexp_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_1 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_neg_q_iexp_result_bits_fractOut = activated_data_e_act_neg_q_iexp_result_bits_isSubnormal ? activated_data_e_act_neg_q_iexp_result_bits_denormFract : _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_neg_q_iexp_result_bits_hi = {activated_data_e_act_neg_q_iexp_result_bits_rawIn_sign, activated_data_e_act_neg_q_iexp_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_neg_q_iexp_result_bits_T = {activated_data_e_act_neg_q_iexp_result_bits_hi, activated_data_e_act_neg_q_iexp_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_neg_q_iexp_bits = _activated_data_e_act_neg_q_iexp_result_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_z_iexp_t_rec_rawIn_sign = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_z_iexp_t_rec_rawIn_sign_1 = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_z_iexp_t_rec_rawIn_sign_2 = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_z_iexp_t_rec_rawIn_sign_3 = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_z_iexp_t_rec_rawIn_sign_0 = activated_data_e_act_z_iexp_t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_z_iexp_t_rec_rawIn_expIn = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_z_iexp_t_rec_rawIn_expIn_1 = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_z_iexp_t_rec_rawIn_expIn_2 = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_z_iexp_t_rec_rawIn_expIn_3 = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_z_iexp_t_rec_rawIn_fractIn = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1 = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2 = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3 = io_in_bits_acc_read_resp_iexp_qln2_inv_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn = activated_data_e_act_z_iexp_t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_1 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_2 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_3 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_4 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_5 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_6 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_7 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_8 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_9 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_10 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_11 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_12 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_13 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_14 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_15 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_16 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_17 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_18 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_19 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_20 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_21 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_22 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_23 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_24 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_25 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_26 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_27 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_28 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_29 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_30 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_31 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_32 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_33 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_34 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_35 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_36 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_37 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_38 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_39 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_40 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_41 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_42 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_43 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_z_iexp_t_rec_rawIn_normDist = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_z_iexp_t_rec_rawIn_fractIn} << activated_data_e_act_z_iexp_t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract = {_activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_z_iexp_t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn ? _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_z_iexp_t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp = _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T = activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZero = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn & activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZero_0 = activated_data_e_act_z_iexp_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_T = activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial = &_activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_z_iexp_t_rec_T_2 = activated_data_e_act_z_iexp_t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_z_iexp_t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_z_iexp_t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_z_iexp_t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T = ~activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial & _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_z_iexp_t_rec_rawIn_isNaN = _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T = activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial & activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_z_iexp_t_rec_rawIn_isInf = _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_z_iexp_t_rec_rawIn_sExp = _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T = ~activated_data_e_act_z_iexp_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_2 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn ? activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract : activated_data_e_act_z_iexp_t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_1, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_z_iexp_t_rec_rawIn_sig = _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T = activated_data_e_act_z_iexp_t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_1 = activated_data_e_act_z_iexp_t_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_z_iexp_t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_3 = {_activated_data_e_act_z_iexp_t_rec_T_1[2:1], _activated_data_e_act_z_iexp_t_rec_T_1[0] | _activated_data_e_act_z_iexp_t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_z_iexp_t_rec_T_4 = {activated_data_e_act_z_iexp_t_rec_rawIn_sign_0, _activated_data_e_act_z_iexp_t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_z_iexp_t_rec_T_5 = activated_data_e_act_z_iexp_t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_z_iexp_t_rec_T_6 = {_activated_data_e_act_z_iexp_t_rec_T_4, _activated_data_e_act_z_iexp_t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_z_iexp_t_rec_T_7 = activated_data_e_act_z_iexp_t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_z_iexp_t_rec = {_activated_data_e_act_z_iexp_t_rec_T_6, _activated_data_e_act_z_iexp_t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_z_iexp_self_rec_rawIn_sign = activated_data_e_act_neg_q_iexp_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_z_iexp_self_rec_rawIn_sign_0 = activated_data_e_act_z_iexp_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_z_iexp_self_rec_rawIn_expIn = activated_data_e_act_neg_q_iexp_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_z_iexp_self_rec_rawIn_fractIn = activated_data_e_act_neg_q_iexp_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn = activated_data_e_act_z_iexp_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_1 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_2 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_3 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_4 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_5 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_6 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_7 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_8 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_9 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_10 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_11 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_12 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_13 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_14 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_15 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_16 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_17 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_18 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_19 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_20 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_21 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_22 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_23 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_24 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_25 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_26 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_27 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_28 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_29 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_30 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_31 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_32 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_33 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_34 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_35 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_36 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_37 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_38 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_39 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_40 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_41 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_42 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_43 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_z_iexp_self_rec_rawIn_normDist = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_z_iexp_self_rec_rawIn_fractIn} << activated_data_e_act_z_iexp_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract = {_activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_z_iexp_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn ? _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_z_iexp_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp = _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T = activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZero = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn & activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZero_0 = activated_data_e_act_z_iexp_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_T = activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial = &_activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_z_iexp_self_rec_T_2 = activated_data_e_act_z_iexp_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_z_iexp_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_z_iexp_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_z_iexp_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T = ~activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial & _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_z_iexp_self_rec_rawIn_isNaN = _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T = activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial & activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_z_iexp_self_rec_rawIn_isInf = _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_z_iexp_self_rec_rawIn_sExp = _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T = ~activated_data_e_act_z_iexp_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_2 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn ? activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract : activated_data_e_act_z_iexp_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_1, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_z_iexp_self_rec_rawIn_sig = _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T = activated_data_e_act_z_iexp_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_1 = activated_data_e_act_z_iexp_self_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_z_iexp_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_3 = {_activated_data_e_act_z_iexp_self_rec_T_1[2:1], _activated_data_e_act_z_iexp_self_rec_T_1[0] | _activated_data_e_act_z_iexp_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_z_iexp_self_rec_T_4 = {activated_data_e_act_z_iexp_self_rec_rawIn_sign_0, _activated_data_e_act_z_iexp_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_z_iexp_self_rec_T_5 = activated_data_e_act_z_iexp_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_z_iexp_self_rec_T_6 = {_activated_data_e_act_z_iexp_self_rec_T_4, _activated_data_e_act_z_iexp_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_z_iexp_self_rec_T_7 = activated_data_e_act_z_iexp_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_z_iexp_self_rec = {_activated_data_e_act_z_iexp_self_rec_T_6, _activated_data_e_act_z_iexp_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_z_iexp_out_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_z_iexp_out_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_z_iexp_out_bits_rawIn_exp = _activated_data_e_act_z_iexp_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_z_iexp_out_bits_rawIn_isZero_T = activated_data_e_act_z_iexp_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_z_iexp_out_bits_rawIn_isZero = _activated_data_e_act_z_iexp_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_z_iexp_out_bits_rawIn_isZero_0 = activated_data_e_act_z_iexp_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_T = activated_data_e_act_z_iexp_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial = &_activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_z_iexp_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_z_iexp_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_z_iexp_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_z_iexp_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_z_iexp_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T = activated_data_e_act_z_iexp_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T = activated_data_e_act_z_iexp_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial & _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_z_iexp_out_bits_rawIn_isNaN = _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_2 = activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial & _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_z_iexp_out_bits_rawIn_isInf = _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T = _activated_data_e_act_z_iexp_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_z_iexp_out_bits_rawIn_sign = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_z_iexp_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_z_iexp_out_bits_rawIn_sExp = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T = ~activated_data_e_act_z_iexp_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_2 = _activated_data_e_act_z_iexp_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_1, _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_z_iexp_out_bits_rawIn_sig = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_z_iexp_out_bits_isSubnormal = $signed(activated_data_e_act_z_iexp_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T = activated_data_e_act_z_iexp_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_z_iexp_out_bits_denormShiftDist = _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_z_iexp_out_bits_denormFract_T = activated_data_e_act_z_iexp_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_z_iexp_out_bits_denormFract_T_1 = _activated_data_e_act_z_iexp_out_bits_denormFract_T >> activated_data_e_act_z_iexp_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_z_iexp_out_bits_denormFract = _activated_data_e_act_z_iexp_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T = activated_data_e_act_z_iexp_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_1 = {1'h0, _activated_data_e_act_z_iexp_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_2 = _activated_data_e_act_z_iexp_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_3 = activated_data_e_act_z_iexp_out_bits_isSubnormal ? 8'h0 : _activated_data_e_act_z_iexp_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_z_iexp_out_bits_expOut_T_4 = activated_data_e_act_z_iexp_out_bits_rawIn_isNaN | activated_data_e_act_z_iexp_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_5 = {8{_activated_data_e_act_z_iexp_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_z_iexp_out_bits_expOut = _activated_data_e_act_z_iexp_out_bits_expOut_T_3 | _activated_data_e_act_z_iexp_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_z_iexp_out_bits_fractOut_T = activated_data_e_act_z_iexp_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_z_iexp_out_bits_fractOut_T_1 = activated_data_e_act_z_iexp_out_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_z_iexp_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_z_iexp_out_bits_fractOut = activated_data_e_act_z_iexp_out_bits_isSubnormal ? activated_data_e_act_z_iexp_out_bits_denormFract : _activated_data_e_act_z_iexp_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_z_iexp_out_bits_hi = {activated_data_e_act_z_iexp_out_bits_rawIn_sign, activated_data_e_act_z_iexp_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_z_iexp_out_bits_T = {activated_data_e_act_z_iexp_out_bits_hi, activated_data_e_act_z_iexp_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_z_iexp_out_bits = _activated_data_e_act_z_iexp_out_bits_T; // @[fNFromRecFN.scala:66:12] wire [15:0] _activated_data_e_act_z_iexp_T = activated_data_e_act_z_iexp_out_bits[31:16]; // @[Arithmetic.scala:350:23] wire [31:0] _activated_data_e_act_z_iexp_T_1; // @[AccumulatorScale.scala:398:67] wire [31:0] activated_data_e_act_z_iexp_bits; // @[AccumulatorScale.scala:398:67] assign _activated_data_e_act_z_iexp_T_1 = _activated_data_e_act_z_iexp_WIRE; // @[AccumulatorScale.scala:398:67] assign _activated_data_e_act_z_iexp_WIRE = {16'h0, _activated_data_e_act_z_iexp_T}; // @[AccumulatorScale.scala:398:{54,67}] assign activated_data_e_act_z_iexp_bits = _activated_data_e_act_z_iexp_T_1; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_21_bits; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_bits; // @[AccumulatorScale.scala:399:32] wire _activated_data_e_act_z_iexp_saturated_T = activated_data_e_act_z_iexp_bits[5]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_1 = activated_data_e_act_z_iexp_bits[6]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_2 = activated_data_e_act_z_iexp_bits[7]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_3 = activated_data_e_act_z_iexp_bits[8]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_4 = activated_data_e_act_z_iexp_bits[9]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_5 = activated_data_e_act_z_iexp_bits[10]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_6 = activated_data_e_act_z_iexp_bits[11]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_7 = activated_data_e_act_z_iexp_bits[12]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_8 = activated_data_e_act_z_iexp_bits[13]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_9 = activated_data_e_act_z_iexp_bits[14]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_10 = activated_data_e_act_z_iexp_bits[15]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_11 = _activated_data_e_act_z_iexp_saturated_T | _activated_data_e_act_z_iexp_saturated_T_1; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_12 = _activated_data_e_act_z_iexp_saturated_T_11 | _activated_data_e_act_z_iexp_saturated_T_2; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_13 = _activated_data_e_act_z_iexp_saturated_T_12 | _activated_data_e_act_z_iexp_saturated_T_3; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_14 = _activated_data_e_act_z_iexp_saturated_T_13 | _activated_data_e_act_z_iexp_saturated_T_4; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_15 = _activated_data_e_act_z_iexp_saturated_T_14 | _activated_data_e_act_z_iexp_saturated_T_5; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_16 = _activated_data_e_act_z_iexp_saturated_T_15 | _activated_data_e_act_z_iexp_saturated_T_6; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_17 = _activated_data_e_act_z_iexp_saturated_T_16 | _activated_data_e_act_z_iexp_saturated_T_7; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_18 = _activated_data_e_act_z_iexp_saturated_T_17 | _activated_data_e_act_z_iexp_saturated_T_8; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_19 = _activated_data_e_act_z_iexp_saturated_T_18 | _activated_data_e_act_z_iexp_saturated_T_9; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_20 = _activated_data_e_act_z_iexp_saturated_T_19 | _activated_data_e_act_z_iexp_saturated_T_10; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_21_bits = _activated_data_e_act_z_iexp_saturated_T_20 ? 32'h20 : activated_data_e_act_z_iexp_bits; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_bits = _activated_data_e_act_z_iexp_saturated_T_21_bits; // @[AccumulatorScale.scala:399:32, :400:28] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_sign = activated_data_e_act_z_iexp_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_sign_0 = activated_data_e_act_qp_iexp_m1_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn = activated_data_e_act_z_iexp_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn = activated_data_e_act_z_iexp_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn = activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_1 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_2 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_3 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_4 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_5 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_6 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_7 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_8 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_9 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_10 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_11 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_12 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_13 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_14 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_15 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_16 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_17 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_18 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_19 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_20 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_21 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_22 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_23 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_24 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_25 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_26 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_27 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_28 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_29 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_30 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_31 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_32 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_33 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_34 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_35 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_36 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_37 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_38 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_39 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_40 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_41 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_42 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_43 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn} << activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract = {_activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn ? _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp = _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T = activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn & activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_0 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_T = activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial = &_activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_m1_rec_T_2 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T = ~activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial & _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_isNaN = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T = activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial & activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_isInf = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_sExp = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T = ~activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_2 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn ? activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract : activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_1, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_sig = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T = activated_data_e_act_qp_iexp_m1_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_1 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_qp_iexp_m1_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_3 = {_activated_data_e_act_qp_iexp_m1_rec_T_1[2:1], _activated_data_e_act_qp_iexp_m1_rec_T_1[0] | _activated_data_e_act_qp_iexp_m1_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_m1_rec_T_4 = {activated_data_e_act_qp_iexp_m1_rec_rawIn_sign_0, _activated_data_e_act_qp_iexp_m1_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_m1_rec_T_5 = activated_data_e_act_qp_iexp_m1_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_T_6 = {_activated_data_e_act_qp_iexp_m1_rec_T_4, _activated_data_e_act_qp_iexp_m1_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_m1_rec_T_7 = activated_data_e_act_qp_iexp_m1_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_m1_rec = {_activated_data_e_act_qp_iexp_m1_rec_T_6, _activated_data_e_act_qp_iexp_m1_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_sign = io_in_bits_acc_read_resp_iexp_qln2_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_sign_1 = io_in_bits_acc_read_resp_iexp_qln2_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_sign_2 = io_in_bits_acc_read_resp_iexp_qln2_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_sign_3 = io_in_bits_acc_read_resp_iexp_qln2_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_sign_0 = activated_data_e_act_qp_iexp_m2_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn = io_in_bits_acc_read_resp_iexp_qln2_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn_1 = io_in_bits_acc_read_resp_iexp_qln2_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn_2 = io_in_bits_acc_read_resp_iexp_qln2_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn_3 = io_in_bits_acc_read_resp_iexp_qln2_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn = io_in_bits_acc_read_resp_iexp_qln2_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1 = io_in_bits_acc_read_resp_iexp_qln2_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2 = io_in_bits_acc_read_resp_iexp_qln2_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3 = io_in_bits_acc_read_resp_iexp_qln2_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn = activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_1 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_2 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_3 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_4 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_5 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_6 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_7 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_8 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_9 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_10 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_11 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_12 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_13 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_14 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_15 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_16 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_17 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_18 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_19 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_20 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_21 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_22 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_23 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_24 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_25 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_26 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_27 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_28 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_29 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_30 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_31 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_32 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_33 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_34 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_35 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_36 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_37 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_38 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_39 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_40 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_41 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_42 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_43 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn} << activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract = {_activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn ? _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp = _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T = activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn & activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_0 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_T = activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial = &_activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_m2_rec_T_2 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T = ~activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial & _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_isNaN = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T = activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial & activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_isInf = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_sExp = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T = ~activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_2 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn ? activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract : activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_1, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_sig = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T = activated_data_e_act_qp_iexp_m2_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_1 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_qp_iexp_m2_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_3 = {_activated_data_e_act_qp_iexp_m2_rec_T_1[2:1], _activated_data_e_act_qp_iexp_m2_rec_T_1[0] | _activated_data_e_act_qp_iexp_m2_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_m2_rec_T_4 = {activated_data_e_act_qp_iexp_m2_rec_rawIn_sign_0, _activated_data_e_act_qp_iexp_m2_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_m2_rec_T_5 = activated_data_e_act_qp_iexp_m2_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_T_6 = {_activated_data_e_act_qp_iexp_m2_rec_T_4, _activated_data_e_act_qp_iexp_m2_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_m2_rec_T_7 = activated_data_e_act_qp_iexp_m2_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_m2_rec = {_activated_data_e_act_qp_iexp_m2_rec_T_6, _activated_data_e_act_qp_iexp_m2_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_qp_iexp_self_rec_rawIn_sign_0 = activated_data_e_act_qp_iexp_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_self_rec_rawIn_expIn = activated_data_e_act_result_4_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn = activated_data_e_act_result_4_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn = activated_data_e_act_qp_iexp_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_1 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_2 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_3 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_4 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_5 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_6 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_7 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_8 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_9 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_10 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_11 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_12 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_13 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_14 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_15 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_16 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_17 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_18 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_19 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_20 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_21 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_22 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_23 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_24 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_25 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_26 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_27 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_28 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_29 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_30 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_31 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_32 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_33 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_34 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_35 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_36 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_37 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_38 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_39 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_40 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_41 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_42 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_43 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_self_rec_rawIn_normDist = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn} << activated_data_e_act_qp_iexp_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract = {_activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_qp_iexp_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn ? _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp = _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZero = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_0 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial = &_activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_self_rec_T_2 = activated_data_e_act_qp_iexp_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial & _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_isNaN = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_self_rec_rawIn_isInf = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_sExp = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_2 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn ? activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract : activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_1, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_sig = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T = activated_data_e_act_qp_iexp_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_1 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_qp_iexp_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_3 = {_activated_data_e_act_qp_iexp_self_rec_T_1[2:1], _activated_data_e_act_qp_iexp_self_rec_T_1[0] | _activated_data_e_act_qp_iexp_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_self_rec_T_4 = {activated_data_e_act_qp_iexp_self_rec_rawIn_sign_0, _activated_data_e_act_qp_iexp_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_self_rec_T_5 = activated_data_e_act_qp_iexp_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_T_6 = {_activated_data_e_act_qp_iexp_self_rec_T_4, _activated_data_e_act_qp_iexp_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_T_7 = activated_data_e_act_qp_iexp_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_self_rec = {_activated_data_e_act_qp_iexp_self_rec_T_6, _activated_data_e_act_qp_iexp_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_qp_iexp_out_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_qp_iexp_out_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_qp_iexp_out_bits_rawIn_exp = _activated_data_e_act_qp_iexp_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_T = activated_data_e_act_qp_iexp_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isZero = _activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_0 = activated_data_e_act_qp_iexp_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_T = activated_data_e_act_qp_iexp_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial = &_activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_qp_iexp_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_qp_iexp_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T = activated_data_e_act_qp_iexp_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T = activated_data_e_act_qp_iexp_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial & _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_isNaN = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_2 = activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial & _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_isInf = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T = _activated_data_e_act_qp_iexp_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_qp_iexp_out_bits_rawIn_sign = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_qp_iexp_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_qp_iexp_out_bits_rawIn_sExp = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T = ~activated_data_e_act_qp_iexp_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_2 = _activated_data_e_act_qp_iexp_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_1, _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_sig = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_qp_iexp_out_bits_isSubnormal = $signed(activated_data_e_act_qp_iexp_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T = activated_data_e_act_qp_iexp_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_qp_iexp_out_bits_denormShiftDist = _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_qp_iexp_out_bits_denormFract_T = activated_data_e_act_qp_iexp_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_qp_iexp_out_bits_denormFract_T_1 = _activated_data_e_act_qp_iexp_out_bits_denormFract_T >> activated_data_e_act_qp_iexp_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_qp_iexp_out_bits_denormFract = _activated_data_e_act_qp_iexp_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T = activated_data_e_act_qp_iexp_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_1 = {1'h0, _activated_data_e_act_qp_iexp_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_2 = _activated_data_e_act_qp_iexp_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_3 = activated_data_e_act_qp_iexp_out_bits_isSubnormal ? 8'h0 : _activated_data_e_act_qp_iexp_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_qp_iexp_out_bits_expOut_T_4 = activated_data_e_act_qp_iexp_out_bits_rawIn_isNaN | activated_data_e_act_qp_iexp_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_5 = {8{_activated_data_e_act_qp_iexp_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_qp_iexp_out_bits_expOut = _activated_data_e_act_qp_iexp_out_bits_expOut_T_3 | _activated_data_e_act_qp_iexp_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_fractOut_T = activated_data_e_act_qp_iexp_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_fractOut_T_1 = activated_data_e_act_qp_iexp_out_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_qp_iexp_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_qp_iexp_out_bits_fractOut = activated_data_e_act_qp_iexp_out_bits_isSubnormal ? activated_data_e_act_qp_iexp_out_bits_denormFract : _activated_data_e_act_qp_iexp_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_qp_iexp_out_bits_hi = {activated_data_e_act_qp_iexp_out_bits_rawIn_sign, activated_data_e_act_qp_iexp_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_qp_iexp_out_bits_T = {activated_data_e_act_qp_iexp_out_bits_hi, activated_data_e_act_qp_iexp_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_qp_iexp_out_bits = _activated_data_e_act_qp_iexp_out_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_qp_iexp_self_rec_rawIn_sign_1 = activated_data_e_act_qp_iexp_out_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_self_rec_rawIn_1_sign = activated_data_e_act_qp_iexp_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_1 = activated_data_e_act_qp_iexp_out_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1 = activated_data_e_act_qp_iexp_out_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_44 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_45 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_46 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_47 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_48 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_49 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_50 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_51 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_52 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_53 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_54 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_55 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_56 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_57 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_58 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_59 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_60 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_61 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_62 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_63 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_64 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_65 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_66 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_67 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_68 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_69 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_70 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_71 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_72 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_73 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_74 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_75 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_76 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_77 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_78 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_79 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_80 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_81 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_82 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_83 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_84 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_85 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_86 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_87 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_1 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1} << activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_1 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_1 = _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_2 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_1 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_1_isZero = activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_1 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_1 = &_activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_self_rec_T_10 = activated_data_e_act_qp_iexp_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_1 & _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_1_isNaN = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_1 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_1 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_self_rec_rawIn_1_isInf = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_1_sExp = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_6 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_1 : activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_5, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_1_sig = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_8 = activated_data_e_act_qp_iexp_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_9 = activated_data_e_act_qp_iexp_self_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_11 = {_activated_data_e_act_qp_iexp_self_rec_T_9[2:1], _activated_data_e_act_qp_iexp_self_rec_T_9[0] | _activated_data_e_act_qp_iexp_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_self_rec_T_12 = {activated_data_e_act_qp_iexp_self_rec_rawIn_1_sign, _activated_data_e_act_qp_iexp_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_self_rec_T_13 = activated_data_e_act_qp_iexp_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_T_14 = {_activated_data_e_act_qp_iexp_self_rec_T_12, _activated_data_e_act_qp_iexp_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_T_15 = activated_data_e_act_qp_iexp_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_self_rec_1 = {_activated_data_e_act_qp_iexp_self_rec_T_14, _activated_data_e_act_qp_iexp_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_qp_iexp_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_qp_iexp_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_qp_iexp_result_bits_rawIn_exp = _activated_data_e_act_qp_iexp_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_T = activated_data_e_act_qp_iexp_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isZero = _activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_0 = activated_data_e_act_qp_iexp_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_T = activated_data_e_act_qp_iexp_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial = &_activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_qp_iexp_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_qp_iexp_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T = activated_data_e_act_qp_iexp_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T = activated_data_e_act_qp_iexp_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial & _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_isNaN = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_2 = activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial & _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_isInf = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T = _activated_data_e_act_qp_iexp_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_qp_iexp_result_bits_rawIn_sign = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_qp_iexp_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_qp_iexp_result_bits_rawIn_sExp = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T = ~activated_data_e_act_qp_iexp_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_2 = _activated_data_e_act_qp_iexp_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_1, _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_sig = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_qp_iexp_result_bits_isSubnormal = $signed(activated_data_e_act_qp_iexp_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T = activated_data_e_act_qp_iexp_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_qp_iexp_result_bits_denormShiftDist = _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_qp_iexp_result_bits_denormFract_T = activated_data_e_act_qp_iexp_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_qp_iexp_result_bits_denormFract_T_1 = _activated_data_e_act_qp_iexp_result_bits_denormFract_T >> activated_data_e_act_qp_iexp_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_qp_iexp_result_bits_denormFract = _activated_data_e_act_qp_iexp_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T = activated_data_e_act_qp_iexp_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_1 = {1'h0, _activated_data_e_act_qp_iexp_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_2 = _activated_data_e_act_qp_iexp_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_3 = activated_data_e_act_qp_iexp_result_bits_isSubnormal ? 8'h0 : _activated_data_e_act_qp_iexp_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_qp_iexp_result_bits_expOut_T_4 = activated_data_e_act_qp_iexp_result_bits_rawIn_isNaN | activated_data_e_act_qp_iexp_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_5 = {8{_activated_data_e_act_qp_iexp_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_qp_iexp_result_bits_expOut = _activated_data_e_act_qp_iexp_result_bits_expOut_T_3 | _activated_data_e_act_qp_iexp_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_fractOut_T = activated_data_e_act_qp_iexp_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_fractOut_T_1 = activated_data_e_act_qp_iexp_result_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_qp_iexp_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_qp_iexp_result_bits_fractOut = activated_data_e_act_qp_iexp_result_bits_isSubnormal ? activated_data_e_act_qp_iexp_result_bits_denormFract : _activated_data_e_act_qp_iexp_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_qp_iexp_result_bits_hi = {activated_data_e_act_qp_iexp_result_bits_rawIn_sign, activated_data_e_act_qp_iexp_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_qp_iexp_result_bits_T = {activated_data_e_act_qp_iexp_result_bits_hi, activated_data_e_act_qp_iexp_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_qp_iexp_bits = _activated_data_e_act_qp_iexp_result_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_0 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn = activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_1 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_2 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_3 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_4 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_5 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_6 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_7 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_8 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_9 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_10 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_11 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_12 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_13 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_14 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_15 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_16 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_17 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_18 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_19 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_20 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_21 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_22 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn} << activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_0 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial = &_activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_t_rec_T_2 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial & _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_isNaN = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_isInf = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_sExp = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract : activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_sig = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_1 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_poly_iexp_t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_3 = {_activated_data_e_act_q_poly_iexp_t_rec_T_1[2:1], _activated_data_e_act_q_poly_iexp_t_rec_T_1[0] | _activated_data_e_act_q_poly_iexp_t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_t_rec_T_4 = {activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_0, _activated_data_e_act_q_poly_iexp_t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_t_rec_T_5 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_T_6 = {_activated_data_e_act_q_poly_iexp_t_rec_T_4, _activated_data_e_act_q_poly_iexp_t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_T_7 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_t_rec = {_activated_data_e_act_q_poly_iexp_t_rec_T_6, _activated_data_e_act_q_poly_iexp_t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign = activated_data_e_act_qp_iexp_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_1 = activated_data_e_act_qp_iexp_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_0 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn = activated_data_e_act_qp_iexp_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_1 = activated_data_e_act_qp_iexp_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn = activated_data_e_act_qp_iexp_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1 = activated_data_e_act_qp_iexp_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_1 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_2 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_3 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_4 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_5 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_6 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_7 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_8 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_9 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_10 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_11 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_12 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_13 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_14 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_15 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_16 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_17 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_18 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_19 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_20 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_21 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_22 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_0 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_2 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_1 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_3 = {_activated_data_e_act_q_poly_iexp_self_rec_T_1[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_1[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_4 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_0, _activated_data_e_act_q_poly_iexp_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_5 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_6 = {_activated_data_e_act_q_poly_iexp_self_rec_T_4, _activated_data_e_act_q_poly_iexp_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_7 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec = {_activated_data_e_act_q_poly_iexp_self_rec_T_6, _activated_data_e_act_q_poly_iexp_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_result_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp = _activated_data_e_act_q_poly_iexp_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_0 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T = _activated_data_e_act_q_poly_iexp_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_2 = _activated_data_e_act_q_poly_iexp_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T = activated_data_e_act_q_poly_iexp_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T = activated_data_e_act_q_poly_iexp_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_1 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T = activated_data_e_act_q_poly_iexp_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_2 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_3 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_4 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_5 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_3 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T = activated_data_e_act_q_poly_iexp_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_1 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal ? activated_data_e_act_q_poly_iexp_result_bits_denormFract : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T = {activated_data_e_act_q_poly_iexp_result_bits_hi, activated_data_e_act_q_poly_iexp_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_result_bits = _activated_data_e_act_q_poly_iexp_result_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_sign = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_44 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_45 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_46 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_47 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_48 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_49 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_50 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_51 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_52 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_53 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_54 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_55 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_56 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_57 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_58 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_59 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_60 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_61 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_62 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_63 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_64 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_65 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_66 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_1 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1} << activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_1 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_isZero = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_t_rec_T_10 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_isNaN = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_1 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_isInf = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_sExp = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_1 : activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_sig = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_8 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_9 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_11 = {_activated_data_e_act_q_poly_iexp_t_rec_T_9[2:1], _activated_data_e_act_q_poly_iexp_t_rec_T_9[0] | _activated_data_e_act_q_poly_iexp_t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_t_rec_T_12 = {activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_sign, _activated_data_e_act_q_poly_iexp_t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_t_rec_T_13 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_T_14 = {_activated_data_e_act_q_poly_iexp_t_rec_T_12, _activated_data_e_act_q_poly_iexp_t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_T_15 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_t_rec_1 = {_activated_data_e_act_q_poly_iexp_t_rec_T_14, _activated_data_e_act_q_poly_iexp_t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_44 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_45 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_46 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_47 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_48 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_49 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_50 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_51 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_52 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_53 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_54 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_55 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_56 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_57 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_58 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_59 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_60 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_61 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_62 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_63 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_64 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_65 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_66 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_1 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_1 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_10 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_1 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_1 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_8 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_9 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_11 = {_activated_data_e_act_q_poly_iexp_self_rec_T_9[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_9[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_12 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_13 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_14 = {_activated_data_e_act_q_poly_iexp_self_rec_T_12, _activated_data_e_act_q_poly_iexp_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_15 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_1 = {_activated_data_e_act_q_poly_iexp_self_rec_T_14, _activated_data_e_act_q_poly_iexp_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_result_1_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_1 = _activated_data_e_act_q_poly_iexp_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_1 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_1 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_5 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_1 = _activated_data_e_act_q_poly_iexp_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_6 = _activated_data_e_act_q_poly_iexp_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_1 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_2 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_1 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_2 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_3 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_2 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_1 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_6 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_7 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_8 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_9 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_10 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_11 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_1 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_9 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_2 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_3 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_1 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_1 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_1 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_1 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_1_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_1 = {activated_data_e_act_q_poly_iexp_result_bits_hi_1, activated_data_e_act_q_poly_iexp_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_result_1_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sign = activated_data_e_act_q_poly_iexp_result_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sign_0 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn = activated_data_e_act_q_poly_iexp_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn = activated_data_e_act_q_poly_iexp_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_1 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_2 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_3 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_4 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_5 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_6 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_7 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_8 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_9 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_10 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_11 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_12 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_13 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_14 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_15 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_16 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_17 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_18 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_19 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_20 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_21 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_22 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn} << activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract = {_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn & activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_0 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_T = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial = &_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_m1_rec_T_2 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial & _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isNaN = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial & activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isInf = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sExp = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T = ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract : activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sig = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_1 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_poly_iexp_m1_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_3 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_1[2:1], _activated_data_e_act_q_poly_iexp_m1_rec_T_1[0] | _activated_data_e_act_q_poly_iexp_m1_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_4 = {activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sign_0, _activated_data_e_act_q_poly_iexp_m1_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_5 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_6 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_4, _activated_data_e_act_q_poly_iexp_m1_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_7 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_m1_rec = {_activated_data_e_act_q_poly_iexp_m1_rec_T_6, _activated_data_e_act_q_poly_iexp_m1_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sign = activated_data_e_act_q_poly_iexp_result_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sign_0 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn = activated_data_e_act_q_poly_iexp_result_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn = activated_data_e_act_q_poly_iexp_result_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_1 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_2 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_3 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_4 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_5 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_6 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_7 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_8 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_9 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_10 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_11 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_12 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_13 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_14 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_15 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_16 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_17 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_18 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_19 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_20 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_21 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_22 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_23 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_24 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_25 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_26 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_27 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_28 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_29 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_30 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_31 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_32 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_33 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_34 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_35 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_36 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_37 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_38 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_39 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_40 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_41 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_42 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_43 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn} << activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_1 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract = {_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_1 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn ? _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_2 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn & activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_0 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_T = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial = &_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_m2_rec_T_2 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T = ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial & _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isNaN = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial & activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isInf = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sExp = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T = ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_2 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn ? activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract : activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sig = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_1 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_act_q_poly_iexp_m2_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_3 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_1[2:1], _activated_data_e_act_q_poly_iexp_m2_rec_T_1[0] | _activated_data_e_act_q_poly_iexp_m2_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_4 = {activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sign_0, _activated_data_e_act_q_poly_iexp_m2_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_5 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_6 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_4, _activated_data_e_act_q_poly_iexp_m2_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_7 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_m2_rec = {_activated_data_e_act_q_poly_iexp_m2_rec_T_6, _activated_data_e_act_q_poly_iexp_m2_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_88 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_89 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_90 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_91 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_92 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_93 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_94 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_95 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_96 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_97 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_98 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_99 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_100 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_101 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_102 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_103 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_104 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_105 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_106 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_107 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_108 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_109 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_110 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_2 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_2 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_18 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_2 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_2 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_16 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_17 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_19 = {_activated_data_e_act_q_poly_iexp_self_rec_T_17[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_17[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_20 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_21 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_22 = {_activated_data_e_act_q_poly_iexp_self_rec_T_20, _activated_data_e_act_q_poly_iexp_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_23 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_2 = {_activated_data_e_act_q_poly_iexp_self_rec_T_22, _activated_data_e_act_q_poly_iexp_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_out_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_out_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp = _activated_data_e_act_q_poly_iexp_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_T = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_0 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_T = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial = &_activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_1 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial & _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_isNaN = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial & _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_isInf = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T = _activated_data_e_act_q_poly_iexp_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_sign = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_sExp = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T = ~activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_2 = _activated_data_e_act_q_poly_iexp_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_3 = {_activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_1, _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_sig = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_out_bits_isSubnormal = $signed(activated_data_e_act_q_poly_iexp_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T = activated_data_e_act_q_poly_iexp_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist = _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T = activated_data_e_act_q_poly_iexp_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_1 = _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T >> activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_out_bits_denormFract = _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T = activated_data_e_act_q_poly_iexp_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_1 = {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_2 = _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_3 = activated_data_e_act_q_poly_iexp_out_bits_isSubnormal ? 8'h0 : _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_4 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isNaN | activated_data_e_act_q_poly_iexp_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_5 = {8{_activated_data_e_act_q_poly_iexp_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_out_bits_expOut = _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_3 | _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T = activated_data_e_act_q_poly_iexp_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_1 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_out_bits_fractOut = activated_data_e_act_q_poly_iexp_out_bits_isSubnormal ? activated_data_e_act_q_poly_iexp_out_bits_denormFract : _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_out_bits_hi = {activated_data_e_act_q_poly_iexp_out_bits_rawIn_sign, activated_data_e_act_q_poly_iexp_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_out_bits_T = {activated_data_e_act_q_poly_iexp_out_bits_hi, activated_data_e_act_q_poly_iexp_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_out_bits = _activated_data_e_act_q_poly_iexp_out_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_3 = activated_data_e_act_q_poly_iexp_out_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_3 = activated_data_e_act_q_poly_iexp_out_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3 = activated_data_e_act_q_poly_iexp_out_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_132 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_133 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_134 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_135 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_136 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_137 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_138 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_139 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_140 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_141 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_142 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_143 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_144 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_145 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_146 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_147 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_148 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_149 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_150 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_151 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_152 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_153 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_154 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_3 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_3 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_26 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_3 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_3 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_24 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_25 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_27 = {_activated_data_e_act_q_poly_iexp_self_rec_T_25[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_25[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_28 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_29 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_30 = {_activated_data_e_act_q_poly_iexp_self_rec_T_28, _activated_data_e_act_q_poly_iexp_self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_31 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_3 = {_activated_data_e_act_q_poly_iexp_self_rec_T_30, _activated_data_e_act_q_poly_iexp_self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_2 = _activated_data_e_act_q_poly_iexp_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_2 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_2 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_6 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_8 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_2 = _activated_data_e_act_q_poly_iexp_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_10 = _activated_data_e_act_q_poly_iexp_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_2 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_4 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_2 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_4 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_5 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_4 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_2 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_12 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_13 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_14 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_15 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_16 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_17 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_2 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_15 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_4 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_5 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_2 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_2 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_2 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_2 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_2_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_2 = {activated_data_e_act_q_poly_iexp_result_bits_hi_2, activated_data_e_act_q_poly_iexp_result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_T_11 = activated_data_e_act_q_poly_iexp_bits >> activated_data_e_act_z_iexp_saturated_bits; // @[Arithmetic.scala:491:26] wire [31:0] _activated_data_e_act_WIRE_1 = _activated_data_e_act_T_11; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_T_12; // @[AccumulatorScale.scala:405:65] assign _activated_data_e_act_T_12 = _activated_data_e_act_WIRE_1; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_WIRE_bits = _activated_data_e_act_T_12; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_14_bits = _activated_data_e_act_T_13_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_15_bits = _activated_data_e_act_T_14_bits; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_bits = _activated_data_e_act_T_1 ? activated_data_e_act_result_bits : _activated_data_e_act_T_15_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_8_bits = _activated_data_e_scaled_T_7_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_3 = _activated_data_e_scaled_T_8_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_9; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_9 = _activated_data_e_scaled_WIRE_3; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_2_bits = _activated_data_e_scaled_T_9; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_t_rec_rawIn_sign = _activated_data_e_scaled_WIRE_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_t_rec_rawIn_sign_0 = activated_data_e_scaled_t_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_t_rec_rawIn_expIn = _activated_data_e_scaled_WIRE_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_t_rec_rawIn_fractIn = _activated_data_e_scaled_WIRE_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_t_rec_rawIn_isZeroExpIn = activated_data_e_scaled_t_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_t_rec_rawIn_isZeroFractIn = activated_data_e_scaled_t_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T = activated_data_e_scaled_t_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_1 = activated_data_e_scaled_t_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_2 = activated_data_e_scaled_t_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_3 = activated_data_e_scaled_t_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_4 = activated_data_e_scaled_t_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_5 = activated_data_e_scaled_t_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_6 = activated_data_e_scaled_t_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_7 = activated_data_e_scaled_t_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_8 = activated_data_e_scaled_t_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_9 = activated_data_e_scaled_t_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_10 = activated_data_e_scaled_t_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_11 = activated_data_e_scaled_t_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_12 = activated_data_e_scaled_t_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_13 = activated_data_e_scaled_t_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_14 = activated_data_e_scaled_t_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_15 = activated_data_e_scaled_t_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_16 = activated_data_e_scaled_t_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_17 = activated_data_e_scaled_t_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_18 = activated_data_e_scaled_t_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_19 = activated_data_e_scaled_t_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_20 = activated_data_e_scaled_t_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_21 = activated_data_e_scaled_t_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_22 = activated_data_e_scaled_t_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_23 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_24 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_25 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_26 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_27 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_28 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_29 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_scaled_t_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_30 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_scaled_t_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_31 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_scaled_t_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_32 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_scaled_t_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_33 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_scaled_t_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_34 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_scaled_t_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_35 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_36 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_37 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_38 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_39 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_40 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_41 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_42 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_43 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_t_rec_rawIn_normDist = _activated_data_e_scaled_t_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_t_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_scaled_t_rec_rawIn_fractIn} << activated_data_e_scaled_t_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_t_rec_rawIn_subnormFract_T_1 = _activated_data_e_scaled_t_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_t_rec_rawIn_subnormFract = {_activated_data_e_scaled_t_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_scaled_t_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_1 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn ? _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_scaled_t_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_2 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_scaled_t_rec_rawIn_adjustedExp = _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_out_sExp_T = activated_data_e_scaled_t_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_t_rec_rawIn_isZero = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn & activated_data_e_scaled_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_t_rec_rawIn_isZero_0 = activated_data_e_scaled_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_isSpecial_T = activated_data_e_scaled_t_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_t_rec_rawIn_isSpecial = &_activated_data_e_scaled_t_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_t_rec_T_2 = activated_data_e_scaled_t_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_t_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_t_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_t_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T = ~activated_data_e_scaled_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_1 = activated_data_e_scaled_t_rec_rawIn_isSpecial & _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_t_rec_rawIn_isNaN = _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_t_rec_rawIn_out_isInf_T = activated_data_e_scaled_t_rec_rawIn_isSpecial & activated_data_e_scaled_t_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_t_rec_rawIn_isInf = _activated_data_e_scaled_t_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_t_rec_rawIn_sExp = _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_t_rec_rawIn_out_sig_T = ~activated_data_e_scaled_t_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_2 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn ? activated_data_e_scaled_t_rec_rawIn_subnormFract : activated_data_e_scaled_t_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_t_rec_rawIn_out_sig_T_3 = {_activated_data_e_scaled_t_rec_rawIn_out_sig_T_1, _activated_data_e_scaled_t_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_t_rec_rawIn_sig = _activated_data_e_scaled_t_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_t_rec_T = activated_data_e_scaled_t_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_t_rec_T_1 = activated_data_e_scaled_t_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_scaled_t_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_t_rec_T_3 = {_activated_data_e_scaled_t_rec_T_1[2:1], _activated_data_e_scaled_t_rec_T_1[0] | _activated_data_e_scaled_t_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_t_rec_T_4 = {activated_data_e_scaled_t_rec_rawIn_sign_0, _activated_data_e_scaled_t_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_t_rec_T_5 = activated_data_e_scaled_t_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_t_rec_T_6 = {_activated_data_e_scaled_t_rec_T_4, _activated_data_e_scaled_t_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_t_rec_T_7 = activated_data_e_scaled_t_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_t_rec = {_activated_data_e_scaled_t_rec_T_6, _activated_data_e_scaled_t_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_scaled_self_rec_rawIn_sign = activated_data_e_act_bits[31]; // @[Mux.scala:126:16] wire activated_data_e_scaled_self_rec_rawIn_sign_0 = activated_data_e_scaled_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_self_rec_rawIn_expIn = activated_data_e_act_bits[30:23]; // @[Mux.scala:126:16] wire [22:0] activated_data_e_scaled_self_rec_rawIn_fractIn = activated_data_e_act_bits[22:0]; // @[Mux.scala:126:16] wire activated_data_e_scaled_self_rec_rawIn_isZeroExpIn = activated_data_e_scaled_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_self_rec_rawIn_isZeroFractIn = activated_data_e_scaled_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T = activated_data_e_scaled_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_1 = activated_data_e_scaled_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_2 = activated_data_e_scaled_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_3 = activated_data_e_scaled_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_4 = activated_data_e_scaled_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_5 = activated_data_e_scaled_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_6 = activated_data_e_scaled_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_7 = activated_data_e_scaled_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_8 = activated_data_e_scaled_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_9 = activated_data_e_scaled_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_10 = activated_data_e_scaled_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_11 = activated_data_e_scaled_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_12 = activated_data_e_scaled_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_13 = activated_data_e_scaled_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_14 = activated_data_e_scaled_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_15 = activated_data_e_scaled_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_16 = activated_data_e_scaled_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_17 = activated_data_e_scaled_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_18 = activated_data_e_scaled_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_19 = activated_data_e_scaled_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_20 = activated_data_e_scaled_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_21 = activated_data_e_scaled_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_22 = activated_data_e_scaled_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_23 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_24 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_25 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_26 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_27 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_28 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_29 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_scaled_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_30 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_scaled_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_31 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_scaled_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_32 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_scaled_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_33 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_scaled_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_34 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_scaled_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_35 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_36 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_37 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_38 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_39 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_40 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_41 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_42 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_43 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_self_rec_rawIn_normDist = _activated_data_e_scaled_self_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_self_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_scaled_self_rec_rawIn_fractIn} << activated_data_e_scaled_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_self_rec_rawIn_subnormFract_T_1 = _activated_data_e_scaled_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_self_rec_rawIn_subnormFract = {_activated_data_e_scaled_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_scaled_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_1 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn ? _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_scaled_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_2 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_scaled_self_rec_rawIn_adjustedExp = _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_out_sExp_T = activated_data_e_scaled_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_self_rec_rawIn_isZero = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn & activated_data_e_scaled_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_self_rec_rawIn_isZero_0 = activated_data_e_scaled_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_isSpecial_T = activated_data_e_scaled_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_self_rec_rawIn_isSpecial = &_activated_data_e_scaled_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_self_rec_T_2 = activated_data_e_scaled_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T = ~activated_data_e_scaled_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_1 = activated_data_e_scaled_self_rec_rawIn_isSpecial & _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_self_rec_rawIn_isNaN = _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_self_rec_rawIn_out_isInf_T = activated_data_e_scaled_self_rec_rawIn_isSpecial & activated_data_e_scaled_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_self_rec_rawIn_isInf = _activated_data_e_scaled_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_self_rec_rawIn_sExp = _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_self_rec_rawIn_out_sig_T = ~activated_data_e_scaled_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_2 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn ? activated_data_e_scaled_self_rec_rawIn_subnormFract : activated_data_e_scaled_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_self_rec_rawIn_out_sig_T_3 = {_activated_data_e_scaled_self_rec_rawIn_out_sig_T_1, _activated_data_e_scaled_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_self_rec_rawIn_sig = _activated_data_e_scaled_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_self_rec_T = activated_data_e_scaled_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_self_rec_T_1 = activated_data_e_scaled_self_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_scaled_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_self_rec_T_3 = {_activated_data_e_scaled_self_rec_T_1[2:1], _activated_data_e_scaled_self_rec_T_1[0] | _activated_data_e_scaled_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_self_rec_T_4 = {activated_data_e_scaled_self_rec_rawIn_sign_0, _activated_data_e_scaled_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_self_rec_T_5 = activated_data_e_scaled_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_self_rec_T_6 = {_activated_data_e_scaled_self_rec_T_4, _activated_data_e_scaled_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_self_rec_T_7 = activated_data_e_scaled_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_self_rec = {_activated_data_e_scaled_self_rec_T_6, _activated_data_e_scaled_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_out_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_scaled_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_scaled_out_bits_rawIn_exp = _activated_data_e_scaled_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_out_bits_rawIn_isZero_T = activated_data_e_scaled_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_out_bits_rawIn_isZero = _activated_data_e_scaled_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_out_bits_rawIn_isZero_0 = activated_data_e_scaled_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_out_bits_rawIn_isSpecial_T = activated_data_e_scaled_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_out_bits_rawIn_isSpecial = &_activated_data_e_scaled_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T = activated_data_e_scaled_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T = activated_data_e_scaled_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_1 = activated_data_e_scaled_out_bits_rawIn_isSpecial & _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_out_bits_rawIn_isNaN = _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_scaled_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_2 = activated_data_e_scaled_out_bits_rawIn_isSpecial & _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_out_bits_rawIn_isInf = _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_out_bits_rawIn_out_sign_T = _activated_data_e_scaled_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_out_bits_rawIn_sign = _activated_data_e_scaled_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_out_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_scaled_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_out_bits_rawIn_sExp = _activated_data_e_scaled_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_out_bits_rawIn_out_sig_T = ~activated_data_e_scaled_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_scaled_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_2 = _activated_data_e_scaled_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_out_bits_rawIn_out_sig_T_3 = {_activated_data_e_scaled_out_bits_rawIn_out_sig_T_1, _activated_data_e_scaled_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_out_bits_rawIn_sig = _activated_data_e_scaled_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_scaled_out_bits_isSubnormal = $signed(activated_data_e_scaled_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_scaled_out_bits_denormShiftDist_T = activated_data_e_scaled_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_scaled_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_scaled_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_scaled_out_bits_denormShiftDist = _activated_data_e_scaled_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_scaled_out_bits_denormFract_T = activated_data_e_scaled_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_scaled_out_bits_denormFract_T_1 = _activated_data_e_scaled_out_bits_denormFract_T >> activated_data_e_scaled_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_scaled_out_bits_denormFract = _activated_data_e_scaled_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T = activated_data_e_scaled_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_scaled_out_bits_expOut_T_1 = {1'h0, _activated_data_e_scaled_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_2 = _activated_data_e_scaled_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_3 = activated_data_e_scaled_out_bits_isSubnormal ? 8'h0 : _activated_data_e_scaled_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_scaled_out_bits_expOut_T_4 = activated_data_e_scaled_out_bits_rawIn_isNaN | activated_data_e_scaled_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_5 = {8{_activated_data_e_scaled_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_scaled_out_bits_expOut = _activated_data_e_scaled_out_bits_expOut_T_3 | _activated_data_e_scaled_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_scaled_out_bits_fractOut_T = activated_data_e_scaled_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_scaled_out_bits_fractOut_T_1 = activated_data_e_scaled_out_bits_rawIn_isInf ? 23'h0 : _activated_data_e_scaled_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_scaled_out_bits_fractOut = activated_data_e_scaled_out_bits_isSubnormal ? activated_data_e_scaled_out_bits_denormFract : _activated_data_e_scaled_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_scaled_out_bits_hi = {activated_data_e_scaled_out_bits_rawIn_sign, activated_data_e_scaled_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_scaled_out_bits_T = {activated_data_e_scaled_out_bits_hi, activated_data_e_scaled_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_scaled_bits = _activated_data_e_scaled_out_bits_T; // @[fNFromRecFN.scala:66:12] wire activated_data_e_clipped_self_rec_rawIn_sign = activated_data_e_scaled_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_clipped_self_rec_rawIn_sign_0 = activated_data_e_clipped_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_clipped_self_rec_rawIn_expIn = activated_data_e_scaled_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_clipped_self_rec_rawIn_fractIn = activated_data_e_scaled_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_clipped_self_rec_rawIn_isZeroExpIn = activated_data_e_clipped_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_clipped_self_rec_rawIn_isZeroFractIn = activated_data_e_clipped_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T = activated_data_e_clipped_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_1 = activated_data_e_clipped_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_2 = activated_data_e_clipped_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_3 = activated_data_e_clipped_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_4 = activated_data_e_clipped_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_5 = activated_data_e_clipped_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_6 = activated_data_e_clipped_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_7 = activated_data_e_clipped_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_8 = activated_data_e_clipped_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_9 = activated_data_e_clipped_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_10 = activated_data_e_clipped_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_11 = activated_data_e_clipped_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_12 = activated_data_e_clipped_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_13 = activated_data_e_clipped_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_14 = activated_data_e_clipped_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_15 = activated_data_e_clipped_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_16 = activated_data_e_clipped_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_17 = activated_data_e_clipped_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_18 = activated_data_e_clipped_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_19 = activated_data_e_clipped_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_20 = activated_data_e_clipped_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_21 = activated_data_e_clipped_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_22 = activated_data_e_clipped_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_23 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_24 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_25 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_26 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_27 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_28 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_29 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_clipped_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_30 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_clipped_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_31 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_clipped_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_32 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_clipped_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_33 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_clipped_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_34 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_clipped_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_35 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_36 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_37 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_38 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_39 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_40 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_41 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_42 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_43 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_clipped_self_rec_rawIn_normDist = _activated_data_e_clipped_self_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_clipped_self_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_clipped_self_rec_rawIn_fractIn} << activated_data_e_clipped_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_clipped_self_rec_rawIn_subnormFract_T_1 = _activated_data_e_clipped_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_clipped_self_rec_rawIn_subnormFract = {_activated_data_e_clipped_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_clipped_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_1 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn ? _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_clipped_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_2 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_clipped_self_rec_rawIn_adjustedExp = _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_out_sExp_T = activated_data_e_clipped_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_clipped_self_rec_rawIn_isZero = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn & activated_data_e_clipped_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_clipped_self_rec_rawIn_isZero_0 = activated_data_e_clipped_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_isSpecial_T = activated_data_e_clipped_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_clipped_self_rec_rawIn_isSpecial = &_activated_data_e_clipped_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_clipped_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_clipped_self_rec_T_2 = activated_data_e_clipped_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_clipped_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_clipped_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_clipped_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T = ~activated_data_e_clipped_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_1 = activated_data_e_clipped_self_rec_rawIn_isSpecial & _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_clipped_self_rec_rawIn_isNaN = _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_clipped_self_rec_rawIn_out_isInf_T = activated_data_e_clipped_self_rec_rawIn_isSpecial & activated_data_e_clipped_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_clipped_self_rec_rawIn_isInf = _activated_data_e_clipped_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_clipped_self_rec_rawIn_sExp = _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_clipped_self_rec_rawIn_out_sig_T = ~activated_data_e_clipped_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_2 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn ? activated_data_e_clipped_self_rec_rawIn_subnormFract : activated_data_e_clipped_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_clipped_self_rec_rawIn_out_sig_T_3 = {_activated_data_e_clipped_self_rec_rawIn_out_sig_T_1, _activated_data_e_clipped_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_clipped_self_rec_rawIn_sig = _activated_data_e_clipped_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_clipped_self_rec_T = activated_data_e_clipped_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_clipped_self_rec_T_1 = activated_data_e_clipped_self_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_clipped_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_clipped_self_rec_T_3 = {_activated_data_e_clipped_self_rec_T_1[2:1], _activated_data_e_clipped_self_rec_T_1[0] | _activated_data_e_clipped_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_clipped_self_rec_T_4 = {activated_data_e_clipped_self_rec_rawIn_sign_0, _activated_data_e_clipped_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_clipped_self_rec_T_5 = activated_data_e_clipped_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_clipped_self_rec_T_6 = {_activated_data_e_clipped_self_rec_T_4, _activated_data_e_clipped_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_clipped_self_rec_T_7 = activated_data_e_clipped_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_clipped_self_rec = {_activated_data_e_clipped_self_rec_T_6, _activated_data_e_clipped_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_clipped_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_clipped_bits; // @[Arithmetic.scala:505:26] wire [31:0] _activated_data_WIRE_0_bits = activated_data_e_clipped_bits; // @[Arithmetic.scala:505:26] wire [8:0] activated_data_e_clipped_result_bits_rawIn_exp = _activated_data_e_clipped_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_clipped_result_bits_rawIn_isZero_T = activated_data_e_clipped_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_clipped_result_bits_rawIn_isZero = _activated_data_e_clipped_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_clipped_result_bits_rawIn_isZero_0 = activated_data_e_clipped_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_clipped_result_bits_rawIn_isSpecial_T = activated_data_e_clipped_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_clipped_result_bits_rawIn_isSpecial = &_activated_data_e_clipped_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_clipped_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_clipped_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_clipped_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_clipped_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_clipped_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_clipped_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_clipped_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T = activated_data_e_clipped_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T = activated_data_e_clipped_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_1 = activated_data_e_clipped_result_bits_rawIn_isSpecial & _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_clipped_result_bits_rawIn_isNaN = _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_1 = ~_activated_data_e_clipped_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_2 = activated_data_e_clipped_result_bits_rawIn_isSpecial & _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_clipped_result_bits_rawIn_isInf = _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_clipped_result_bits_rawIn_out_sign_T = _activated_data_e_clipped_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_clipped_result_bits_rawIn_sign = _activated_data_e_clipped_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_clipped_result_bits_rawIn_out_sExp_T = {1'h0, activated_data_e_clipped_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_clipped_result_bits_rawIn_sExp = _activated_data_e_clipped_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_clipped_result_bits_rawIn_out_sig_T = ~activated_data_e_clipped_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_clipped_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_2 = _activated_data_e_clipped_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_clipped_result_bits_rawIn_out_sig_T_3 = {_activated_data_e_clipped_result_bits_rawIn_out_sig_T_1, _activated_data_e_clipped_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_clipped_result_bits_rawIn_sig = _activated_data_e_clipped_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_clipped_result_bits_isSubnormal = $signed(activated_data_e_clipped_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_clipped_result_bits_denormShiftDist_T = activated_data_e_clipped_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_clipped_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _activated_data_e_clipped_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_clipped_result_bits_denormShiftDist = _activated_data_e_clipped_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_clipped_result_bits_denormFract_T = activated_data_e_clipped_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_clipped_result_bits_denormFract_T_1 = _activated_data_e_clipped_result_bits_denormFract_T >> activated_data_e_clipped_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_clipped_result_bits_denormFract = _activated_data_e_clipped_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T = activated_data_e_clipped_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_clipped_result_bits_expOut_T_1 = {1'h0, _activated_data_e_clipped_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_2 = _activated_data_e_clipped_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_3 = activated_data_e_clipped_result_bits_isSubnormal ? 8'h0 : _activated_data_e_clipped_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_clipped_result_bits_expOut_T_4 = activated_data_e_clipped_result_bits_rawIn_isNaN | activated_data_e_clipped_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_5 = {8{_activated_data_e_clipped_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_clipped_result_bits_expOut = _activated_data_e_clipped_result_bits_expOut_T_3 | _activated_data_e_clipped_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_clipped_result_bits_fractOut_T = activated_data_e_clipped_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_clipped_result_bits_fractOut_T_1 = activated_data_e_clipped_result_bits_rawIn_isInf ? 23'h0 : _activated_data_e_clipped_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_clipped_result_bits_fractOut = activated_data_e_clipped_result_bits_isSubnormal ? activated_data_e_clipped_result_bits_denormFract : _activated_data_e_clipped_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_clipped_result_bits_hi = {activated_data_e_clipped_result_bits_rawIn_sign, activated_data_e_clipped_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_clipped_result_bits_T = {activated_data_e_clipped_result_bits_hi, activated_data_e_clipped_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_clipped_bits = _activated_data_e_clipped_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_0_0_bits = _activated_data_WIRE_0_bits; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_17 = _activated_data_e_act_T_16; // @[AccumulatorScale.scala:118:{38,45}] wire activated_data_e_act_raw_sign_1 = io_in_bits_acc_read_resp_data_1_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_5 = io_in_bits_acc_read_resp_data_1_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_sign_t_rec_rawIn_sign_2 = io_in_bits_acc_read_resp_data_1_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_rec_rawIn_sign_2 = io_in_bits_acc_read_resp_data_1_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_sgn_1 = io_in_bits_acc_read_resp_data_1_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_7 = io_in_bits_acc_read_resp_data_1_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_9 = io_in_bits_acc_read_resp_data_1_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_raw_1_sign = activated_data_e_act_raw_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_raw_expIn_1 = io_in_bits_acc_read_resp_data_1_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_5 = io_in_bits_acc_read_resp_data_1_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_t_rec_rawIn_expIn_2 = io_in_bits_acc_read_resp_data_1_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_abs_t_rec_rawIn_expIn_2 = io_in_bits_acc_read_resp_data_1_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_7 = io_in_bits_acc_read_resp_data_1_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_9 = io_in_bits_acc_read_resp_data_1_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_raw_fractIn_1 = io_in_bits_acc_read_resp_data_1_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_5 = io_in_bits_acc_read_resp_data_1_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2 = io_in_bits_acc_read_resp_data_1_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2 = io_in_bits_acc_read_resp_data_1_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_7 = io_in_bits_acc_read_resp_data_1_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_9 = io_in_bits_acc_read_resp_data_1_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_raw_isZeroExpIn_1 = activated_data_e_act_raw_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_raw_isZeroFractIn_1 = activated_data_e_act_raw_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_raw_normDist_T_44 = activated_data_e_act_raw_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_45 = activated_data_e_act_raw_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_46 = activated_data_e_act_raw_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_47 = activated_data_e_act_raw_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_48 = activated_data_e_act_raw_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_49 = activated_data_e_act_raw_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_50 = activated_data_e_act_raw_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_51 = activated_data_e_act_raw_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_52 = activated_data_e_act_raw_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_53 = activated_data_e_act_raw_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_54 = activated_data_e_act_raw_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_55 = activated_data_e_act_raw_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_56 = activated_data_e_act_raw_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_57 = activated_data_e_act_raw_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_58 = activated_data_e_act_raw_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_59 = activated_data_e_act_raw_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_60 = activated_data_e_act_raw_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_61 = activated_data_e_act_raw_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_62 = activated_data_e_act_raw_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_63 = activated_data_e_act_raw_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_64 = activated_data_e_act_raw_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_65 = activated_data_e_act_raw_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_66 = activated_data_e_act_raw_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_raw_normDist_T_67 = _activated_data_e_act_raw_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_68 = _activated_data_e_act_raw_normDist_T_46 ? 5'h14 : _activated_data_e_act_raw_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_69 = _activated_data_e_act_raw_normDist_T_47 ? 5'h13 : _activated_data_e_act_raw_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_70 = _activated_data_e_act_raw_normDist_T_48 ? 5'h12 : _activated_data_e_act_raw_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_71 = _activated_data_e_act_raw_normDist_T_49 ? 5'h11 : _activated_data_e_act_raw_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_72 = _activated_data_e_act_raw_normDist_T_50 ? 5'h10 : _activated_data_e_act_raw_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_73 = _activated_data_e_act_raw_normDist_T_51 ? 5'hF : _activated_data_e_act_raw_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_74 = _activated_data_e_act_raw_normDist_T_52 ? 5'hE : _activated_data_e_act_raw_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_75 = _activated_data_e_act_raw_normDist_T_53 ? 5'hD : _activated_data_e_act_raw_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_76 = _activated_data_e_act_raw_normDist_T_54 ? 5'hC : _activated_data_e_act_raw_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_77 = _activated_data_e_act_raw_normDist_T_55 ? 5'hB : _activated_data_e_act_raw_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_78 = _activated_data_e_act_raw_normDist_T_56 ? 5'hA : _activated_data_e_act_raw_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_79 = _activated_data_e_act_raw_normDist_T_57 ? 5'h9 : _activated_data_e_act_raw_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_80 = _activated_data_e_act_raw_normDist_T_58 ? 5'h8 : _activated_data_e_act_raw_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_81 = _activated_data_e_act_raw_normDist_T_59 ? 5'h7 : _activated_data_e_act_raw_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_82 = _activated_data_e_act_raw_normDist_T_60 ? 5'h6 : _activated_data_e_act_raw_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_83 = _activated_data_e_act_raw_normDist_T_61 ? 5'h5 : _activated_data_e_act_raw_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_84 = _activated_data_e_act_raw_normDist_T_62 ? 5'h4 : _activated_data_e_act_raw_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_85 = _activated_data_e_act_raw_normDist_T_63 ? 5'h3 : _activated_data_e_act_raw_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_86 = _activated_data_e_act_raw_normDist_T_64 ? 5'h2 : _activated_data_e_act_raw_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_87 = _activated_data_e_act_raw_normDist_T_65 ? 5'h1 : _activated_data_e_act_raw_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_raw_normDist_1 = _activated_data_e_act_raw_normDist_T_66 ? 5'h0 : _activated_data_e_act_raw_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_raw_subnormFract_T_2 = {31'h0, activated_data_e_act_raw_fractIn_1} << activated_data_e_act_raw_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_raw_subnormFract_T_3 = _activated_data_e_act_raw_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_raw_subnormFract_1 = {_activated_data_e_act_raw_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_raw_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_raw_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_raw_adjustedExp_T_6 = activated_data_e_act_raw_isZeroExpIn_1 ? _activated_data_e_act_raw_adjustedExp_T_5 : {1'h0, activated_data_e_act_raw_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_raw_adjustedExp_T_7 = activated_data_e_act_raw_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_raw_adjustedExp_T_8 = {6'h20, _activated_data_e_act_raw_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_raw_adjustedExp_T_9 = {1'h0, _activated_data_e_act_raw_adjustedExp_T_6} + {2'h0, _activated_data_e_act_raw_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_raw_adjustedExp_1 = _activated_data_e_act_raw_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_raw_out_sExp_T_2 = activated_data_e_act_raw_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_raw_isZero_1 = activated_data_e_act_raw_isZeroExpIn_1 & activated_data_e_act_raw_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_raw_1_isZero = activated_data_e_act_raw_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_raw_isSpecial_T_1 = activated_data_e_act_raw_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_raw_isSpecial_1 = &_activated_data_e_act_raw_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_raw_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_raw_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire [9:0] _activated_data_e_act_raw_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_raw_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_raw_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_raw_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_raw_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_raw_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_raw_out_isNaN_T_2 = ~activated_data_e_act_raw_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_raw_out_isNaN_T_3 = activated_data_e_act_raw_isSpecial_1 & _activated_data_e_act_raw_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_raw_1_isNaN = _activated_data_e_act_raw_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_raw_out_isInf_T_1 = activated_data_e_act_raw_isSpecial_1 & activated_data_e_act_raw_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_raw_1_isInf = _activated_data_e_act_raw_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_raw_out_sExp_T_3 = {1'h0, _activated_data_e_act_raw_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_raw_1_sExp = _activated_data_e_act_raw_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_raw_out_sig_T_4 = ~activated_data_e_act_raw_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_raw_out_sig_T_5 = {1'h0, _activated_data_e_act_raw_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_raw_out_sig_T_6 = activated_data_e_act_raw_isZeroExpIn_1 ? activated_data_e_act_raw_subnormFract_1 : activated_data_e_act_raw_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_raw_out_sig_T_7 = {_activated_data_e_act_raw_out_sig_T_5, _activated_data_e_act_raw_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_raw_1_sig = _activated_data_e_act_raw_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [31:0] _activated_data_e_act_result_bits_T_9; // @[Arithmetic.scala:514:27] wire [31:0] activated_data_e_act_result_5_bits; // @[Arithmetic.scala:513:26] wire _activated_data_e_act_result_bits_T_7 = ~activated_data_e_act_raw_1_isZero; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_result_bits_T_8 = _activated_data_e_act_result_bits_T_7 & activated_data_e_act_raw_1_sign; // @[rawFloatFromFN.scala:63:19] assign _activated_data_e_act_result_bits_T_9 = _activated_data_e_act_result_bits_T_8 ? 32'h0 : io_in_bits_acc_read_resp_data_1_0_bits_0; // @[Arithmetic.scala:514:{27,40}] assign activated_data_e_act_result_5_bits = _activated_data_e_act_result_bits_T_9; // @[Arithmetic.scala:513:26, :514:27] wire activated_data_e_act_self_rec_rawIn_5_sign = activated_data_e_act_self_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_5 = activated_data_e_act_self_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_5 = activated_data_e_act_self_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_220 = activated_data_e_act_self_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_221 = activated_data_e_act_self_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_222 = activated_data_e_act_self_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_223 = activated_data_e_act_self_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_224 = activated_data_e_act_self_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_225 = activated_data_e_act_self_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_226 = activated_data_e_act_self_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_227 = activated_data_e_act_self_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_228 = activated_data_e_act_self_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_229 = activated_data_e_act_self_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_230 = activated_data_e_act_self_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_231 = activated_data_e_act_self_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_232 = activated_data_e_act_self_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_233 = activated_data_e_act_self_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_234 = activated_data_e_act_self_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_235 = activated_data_e_act_self_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_236 = activated_data_e_act_self_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_237 = activated_data_e_act_self_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_238 = activated_data_e_act_self_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_239 = activated_data_e_act_self_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_240 = activated_data_e_act_self_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_241 = activated_data_e_act_self_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_242 = activated_data_e_act_self_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_243 = _activated_data_e_act_self_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_244 = _activated_data_e_act_self_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_245 = _activated_data_e_act_self_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_246 = _activated_data_e_act_self_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_247 = _activated_data_e_act_self_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_248 = _activated_data_e_act_self_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_249 = _activated_data_e_act_self_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_250 = _activated_data_e_act_self_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_251 = _activated_data_e_act_self_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_252 = _activated_data_e_act_self_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_253 = _activated_data_e_act_self_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_254 = _activated_data_e_act_self_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_255 = _activated_data_e_act_self_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_256 = _activated_data_e_act_self_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_257 = _activated_data_e_act_self_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_258 = _activated_data_e_act_self_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_259 = _activated_data_e_act_self_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_260 = _activated_data_e_act_self_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_261 = _activated_data_e_act_self_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_262 = _activated_data_e_act_self_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_263 = _activated_data_e_act_self_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_5 = _activated_data_e_act_self_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_5} << activated_data_e_act_self_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_11 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_5 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_26 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_27 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_5 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_10 = activated_data_e_act_self_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_5 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_5 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_5_isZero = activated_data_e_act_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_5 = activated_data_e_act_self_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_5 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_42 = activated_data_e_act_self_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_11 = activated_data_e_act_self_rec_rawIn_isSpecial_5 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_5_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_5 = activated_data_e_act_self_rec_rawIn_isSpecial_5 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_5_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_5_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_20 = ~activated_data_e_act_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_22 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_5 ? activated_data_e_act_self_rec_rawIn_subnormFract_5 : activated_data_e_act_self_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_23 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_21, _activated_data_e_act_self_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_5_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_40 = activated_data_e_act_self_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_41 = activated_data_e_act_self_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_43 = {_activated_data_e_act_self_rec_T_41[2:1], _activated_data_e_act_self_rec_T_41[0] | _activated_data_e_act_self_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_44 = {activated_data_e_act_self_rec_rawIn_5_sign, _activated_data_e_act_self_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_45 = activated_data_e_act_self_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_46 = {_activated_data_e_act_self_rec_T_44, _activated_data_e_act_self_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_47 = activated_data_e_act_self_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_5 = {_activated_data_e_act_self_rec_T_46, _activated_data_e_act_self_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_10; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_6_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_4 = _activated_data_e_act_muladder_4_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_4 = activated_data_e_act_result_bits_rawIn_exp_4[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_4 = _activated_data_e_act_result_bits_rawIn_isZero_T_4 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_4_isZero = activated_data_e_act_result_bits_rawIn_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_4 = activated_data_e_act_result_bits_rawIn_exp_4[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_4 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_4; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_14; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_4; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_4; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_19; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_4_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_4_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_4_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_4_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_4_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_8 = activated_data_e_act_result_bits_rawIn_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_12 = activated_data_e_act_result_bits_rawIn_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_9 = activated_data_e_act_result_bits_rawIn_isSpecial_4 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_8; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_4_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_13 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_12; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_14 = activated_data_e_act_result_bits_rawIn_isSpecial_4 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_13; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_4_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_14; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_4 = _activated_data_e_act_muladder_4_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_4_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_4; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_4 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_4}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_4_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_4; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_16 = ~activated_data_e_act_result_bits_rawIn_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_16}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_18 = _activated_data_e_act_muladder_4_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_19 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_17, _activated_data_e_act_result_bits_rawIn_out_sig_T_18}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_4_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_19; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_4 = $signed(activated_data_e_act_result_bits_rawIn_4_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_8 = activated_data_e_act_result_bits_rawIn_4_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_9 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_8}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_4 = _activated_data_e_act_result_bits_denormShiftDist_T_9[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_8 = activated_data_e_act_result_bits_rawIn_4_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_9 = _activated_data_e_act_result_bits_denormFract_T_8 >> activated_data_e_act_result_bits_denormShiftDist_4; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_4 = _activated_data_e_act_result_bits_denormFract_T_9[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_24 = activated_data_e_act_result_bits_rawIn_4_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_25 = {1'h0, _activated_data_e_act_result_bits_expOut_T_24} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_26 = _activated_data_e_act_result_bits_expOut_T_25[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_27 = activated_data_e_act_result_bits_isSubnormal_4 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_26; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_28 = activated_data_e_act_result_bits_rawIn_4_isNaN | activated_data_e_act_result_bits_rawIn_4_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_29 = {8{_activated_data_e_act_result_bits_expOut_T_28}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_4 = _activated_data_e_act_result_bits_expOut_T_27 | _activated_data_e_act_result_bits_expOut_T_29; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_8 = activated_data_e_act_result_bits_rawIn_4_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_9 = activated_data_e_act_result_bits_rawIn_4_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_8; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_4 = activated_data_e_act_result_bits_isSubnormal_4 ? activated_data_e_act_result_bits_denormFract_4 : _activated_data_e_act_result_bits_fractOut_T_9; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_4 = {activated_data_e_act_result_bits_rawIn_4_sign, activated_data_e_act_result_bits_expOut_4}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_10 = {activated_data_e_act_result_bits_hi_4, activated_data_e_act_result_bits_fractOut_4}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_6_bits = _activated_data_e_act_result_bits_T_10; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_sign_t_rec_rawIn_2_sign = activated_data_e_act_q_sign_t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_sign_t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_88 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_89 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_90 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_91 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_92 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_93 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_94 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_95 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_96 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_97 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_98 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_99 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_100 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_101 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_102 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_103 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_104 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_105 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_106 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_107 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_108 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_109 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_110 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_t_rec_rawIn_normDist_2 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2} << activated_data_e_act_q_sign_t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_sign_t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_sign_t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_sign_t_rec_rawIn_isZero_2 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_sign_t_rec_rawIn_2_isZero = activated_data_e_act_q_sign_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_t_rec_T_18 = activated_data_e_act_q_sign_t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_sign_t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_sign_t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_sign_t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_sign_t_rec_rawIn_2_isNaN = _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_2 & activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_sign_t_rec_rawIn_2_isInf = _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_sign_t_rec_rawIn_2_sExp = _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_sign_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_2 : activated_data_e_act_q_sign_t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_sign_t_rec_rawIn_2_sig = _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_16 = activated_data_e_act_q_sign_t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_17 = activated_data_e_act_q_sign_t_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_sign_t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_19 = {_activated_data_e_act_q_sign_t_rec_T_17[2:1], _activated_data_e_act_q_sign_t_rec_T_17[0] | _activated_data_e_act_q_sign_t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_sign_t_rec_T_20 = {activated_data_e_act_q_sign_t_rec_rawIn_2_sign, _activated_data_e_act_q_sign_t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_sign_t_rec_T_21 = activated_data_e_act_q_sign_t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_sign_t_rec_T_22 = {_activated_data_e_act_q_sign_t_rec_T_20, _activated_data_e_act_q_sign_t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_sign_t_rec_T_23 = activated_data_e_act_q_sign_t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_sign_t_rec_2 = {_activated_data_e_act_q_sign_t_rec_T_22, _activated_data_e_act_q_sign_t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] activated_data_e_act_q_sign_1_bits = {_activated_data_e_act_q_sign_comparator_1_io_gt, 31'h3F800000}; // @[Arithmetic.scala:475:32] wire activated_data_e_act_q_abs_t_rec_rawIn_2_sign = activated_data_e_act_q_abs_t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_abs_t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_88 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_89 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_90 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_91 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_92 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_93 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_94 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_95 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_96 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_97 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_98 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_99 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_100 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_101 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_102 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_103 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_104 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_105 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_106 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_107 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_108 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_109 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_110 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_t_rec_rawIn_normDist_2 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2} << activated_data_e_act_q_abs_t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_abs_t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_abs_t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_abs_t_rec_rawIn_isZero_2 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_abs_t_rec_rawIn_2_isZero = activated_data_e_act_q_abs_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_t_rec_T_18 = activated_data_e_act_q_abs_t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_abs_t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_abs_t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_abs_t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_abs_t_rec_rawIn_2_isNaN = _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_2 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_abs_t_rec_rawIn_2_isInf = _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_abs_t_rec_rawIn_2_sExp = _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_2 : activated_data_e_act_q_abs_t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_abs_t_rec_rawIn_2_sig = _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_16 = activated_data_e_act_q_abs_t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_17 = activated_data_e_act_q_abs_t_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_abs_t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_19 = {_activated_data_e_act_q_abs_t_rec_T_17[2:1], _activated_data_e_act_q_abs_t_rec_T_17[0] | _activated_data_e_act_q_abs_t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_abs_t_rec_T_20 = {activated_data_e_act_q_abs_t_rec_rawIn_2_sign, _activated_data_e_act_q_abs_t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_abs_t_rec_T_21 = activated_data_e_act_q_abs_t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_abs_t_rec_T_22 = {_activated_data_e_act_q_abs_t_rec_T_20, _activated_data_e_act_q_abs_t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_abs_t_rec_T_23 = activated_data_e_act_q_abs_t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_abs_t_rec_2 = {_activated_data_e_act_q_abs_t_rec_T_22, _activated_data_e_act_q_abs_t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _activated_data_e_act_q_abs_neg_t_T_4 = ~activated_data_e_act_q_abs_t_sgn_1; // @[Arithmetic.scala:432:27, :433:25] wire [30:0] _activated_data_e_act_q_abs_neg_t_T_5 = io_in_bits_acc_read_resp_data_1_0_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [31:0] _activated_data_e_act_q_abs_neg_t_T_6 = {_activated_data_e_act_q_abs_neg_t_T_4, _activated_data_e_act_q_abs_neg_t_T_5}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_abs_neg_t_WIRE_1 = _activated_data_e_act_q_abs_neg_t_T_6; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_abs_neg_t_T_7; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_abs_neg_t_1_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_abs_neg_t_T_7 = _activated_data_e_act_q_abs_neg_t_WIRE_1; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_abs_neg_t_1_bits = _activated_data_e_act_q_abs_neg_t_T_7; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_abs_t_rec_rawIn_sign_3 = activated_data_e_act_q_abs_neg_t_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_rec_rawIn_3_sign = activated_data_e_act_q_abs_t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_abs_t_rec_rawIn_expIn_3 = activated_data_e_act_q_abs_neg_t_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3 = activated_data_e_act_q_abs_neg_t_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_abs_t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_132 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_133 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_134 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_135 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_136 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_137 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_138 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_139 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_140 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_141 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_142 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_143 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_144 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_145 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_146 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_147 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_148 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_149 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_150 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_151 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_152 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_153 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_154 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_t_rec_rawIn_normDist_3 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3} << activated_data_e_act_q_abs_t_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_abs_t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_abs_t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_abs_t_rec_rawIn_isZero_3 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_abs_t_rec_rawIn_3_isZero = activated_data_e_act_q_abs_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_t_rec_T_26 = activated_data_e_act_q_abs_t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_abs_t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_abs_t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_abs_t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_abs_t_rec_rawIn_3_isNaN = _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_3 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_abs_t_rec_rawIn_3_isInf = _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_abs_t_rec_rawIn_3_sExp = _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_3 : activated_data_e_act_q_abs_t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_abs_t_rec_rawIn_3_sig = _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_24 = activated_data_e_act_q_abs_t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_25 = activated_data_e_act_q_abs_t_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_abs_t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_27 = {_activated_data_e_act_q_abs_t_rec_T_25[2:1], _activated_data_e_act_q_abs_t_rec_T_25[0] | _activated_data_e_act_q_abs_t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_abs_t_rec_T_28 = {activated_data_e_act_q_abs_t_rec_rawIn_3_sign, _activated_data_e_act_q_abs_t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_abs_t_rec_T_29 = activated_data_e_act_q_abs_t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_abs_t_rec_T_30 = {_activated_data_e_act_q_abs_t_rec_T_28, _activated_data_e_act_q_abs_t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_abs_t_rec_T_31 = activated_data_e_act_q_abs_t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_abs_t_rec_3 = {_activated_data_e_act_q_abs_t_rec_T_30, _activated_data_e_act_q_abs_t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_abs_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_abs_result_1_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_abs_result_bits_rawIn_exp_1 = _activated_data_e_act_q_abs_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_abs_result_bits_rawIn_isZero_T_1 = activated_data_e_act_q_abs_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_abs_result_bits_rawIn_isZero_1 = _activated_data_e_act_q_abs_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_abs_result_bits_rawIn_1_isZero = activated_data_e_act_q_abs_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_T_1 = activated_data_e_act_q_abs_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_1 = &_activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_abs_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_abs_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_abs_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_abs_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_abs_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_q_abs_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_3 = activated_data_e_act_q_abs_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_abs_result_bits_rawIn_1_isNaN = _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_5 = activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_abs_result_bits_rawIn_1_isInf = _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T_1 = _activated_data_e_act_q_abs_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_abs_result_bits_rawIn_1_sign = _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_q_abs_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_abs_result_bits_rawIn_1_sExp = _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_q_abs_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_6 = _activated_data_e_act_q_abs_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_5, _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_abs_result_bits_rawIn_1_sig = _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_abs_result_bits_isSubnormal_1 = $signed(activated_data_e_act_q_abs_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_2 = activated_data_e_act_q_abs_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_abs_result_bits_denormShiftDist_1 = _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_abs_result_bits_denormFract_T_2 = activated_data_e_act_q_abs_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_abs_result_bits_denormFract_T_3 = _activated_data_e_act_q_abs_result_bits_denormFract_T_2 >> activated_data_e_act_q_abs_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_abs_result_bits_denormFract_1 = _activated_data_e_act_q_abs_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_6 = activated_data_e_act_q_abs_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_abs_result_bits_expOut_T_7 = {1'h0, _activated_data_e_act_q_abs_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_8 = _activated_data_e_act_q_abs_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_9 = activated_data_e_act_q_abs_result_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_q_abs_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_abs_result_bits_expOut_T_10 = activated_data_e_act_q_abs_result_bits_rawIn_1_isNaN | activated_data_e_act_q_abs_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_11 = {8{_activated_data_e_act_q_abs_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_abs_result_bits_expOut_1 = _activated_data_e_act_q_abs_result_bits_expOut_T_9 | _activated_data_e_act_q_abs_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_abs_result_bits_fractOut_T_2 = activated_data_e_act_q_abs_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_abs_result_bits_fractOut_T_3 = activated_data_e_act_q_abs_result_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_q_abs_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_abs_result_bits_fractOut_1 = activated_data_e_act_q_abs_result_bits_isSubnormal_1 ? activated_data_e_act_q_abs_result_bits_denormFract_1 : _activated_data_e_act_q_abs_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_abs_result_bits_hi_1 = {activated_data_e_act_q_abs_result_bits_rawIn_1_sign, activated_data_e_act_q_abs_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_abs_result_bits_T_1 = {activated_data_e_act_q_abs_result_bits_hi_1, activated_data_e_act_q_abs_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_abs_result_1_bits = _activated_data_e_act_q_abs_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_abs_1_bits = _activated_data_e_act_q_abs_comparator_1_io_gt ? activated_data_e_act_q_abs_result_1_bits : io_in_bits_acc_read_resp_data_1_0_bits_0; // @[Arithmetic.scala:426:26, :475:32] wire _activated_data_e_act_q_clipped_neg_t_T_8 = ~activated_data_e_act_q_clipped_t_sgn_2; // @[Arithmetic.scala:432:27, :433:25] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_10 = {_activated_data_e_act_q_clipped_neg_t_T_8, _activated_data_e_act_q_clipped_neg_t_T_9}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_WIRE_2 = _activated_data_e_act_q_clipped_neg_t_T_10; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_11; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_clipped_neg_t_2_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_clipped_neg_t_T_11 = _activated_data_e_act_q_clipped_neg_t_WIRE_2; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_clipped_neg_t_2_bits = _activated_data_e_act_q_clipped_neg_t_T_11; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_3 = activated_data_e_act_q_clipped_neg_t_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_3_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_3 = activated_data_e_act_q_clipped_neg_t_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3 = activated_data_e_act_q_clipped_neg_t_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_132 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_133 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_134 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_135 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_136 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_137 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_138 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_139 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_140 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_141 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_142 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_143 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_144 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_145 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_146 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_147 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_148 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_149 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_150 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_151 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_152 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_153 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_154 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_3 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_3 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_3_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_26 = activated_data_e_act_q_clipped_t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_3_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_3 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_3_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_3_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_3 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_3_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_24 = activated_data_e_act_q_clipped_t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_25 = activated_data_e_act_q_clipped_t_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_27 = {_activated_data_e_act_q_clipped_t_rec_T_25[2:1], _activated_data_e_act_q_clipped_t_rec_T_25[0] | _activated_data_e_act_q_clipped_t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_28 = {activated_data_e_act_q_clipped_t_rec_rawIn_3_sign, _activated_data_e_act_q_clipped_t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_29 = activated_data_e_act_q_clipped_t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_30 = {_activated_data_e_act_q_clipped_t_rec_T_28, _activated_data_e_act_q_clipped_t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_31 = activated_data_e_act_q_clipped_t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_3 = {_activated_data_e_act_q_clipped_t_rec_T_30, _activated_data_e_act_q_clipped_t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_clipped_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_result_2_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_clipped_result_bits_rawIn_exp_2 = _activated_data_e_act_q_clipped_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_2 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isZero_2 = _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_clipped_result_bits_rawIn_2_isZero = activated_data_e_act_q_clipped_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_2 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_2 = &_activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_clipped_result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_clipped_result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_clipped_result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_6 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_clipped_result_bits_rawIn_2_isNaN = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_8 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_clipped_result_bits_rawIn_2_isInf = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_2 = _activated_data_e_act_q_clipped_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_clipped_result_bits_rawIn_2_sign = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_q_clipped_result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_clipped_result_bits_rawIn_2_sExp = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_q_clipped_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_10 = _activated_data_e_act_q_clipped_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_9, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_clipped_result_bits_rawIn_2_sig = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_clipped_result_bits_isSubnormal_2 = $signed(activated_data_e_act_q_clipped_result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_4 = activated_data_e_act_q_clipped_result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_clipped_result_bits_denormShiftDist_2 = _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_4 = activated_data_e_act_q_clipped_result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_5 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_4 >> activated_data_e_act_q_clipped_result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_clipped_result_bits_denormFract_2 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_12 = activated_data_e_act_q_clipped_result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_13 = {1'h0, _activated_data_e_act_q_clipped_result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_14 = _activated_data_e_act_q_clipped_result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_15 = activated_data_e_act_q_clipped_result_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_q_clipped_result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_clipped_result_bits_expOut_T_16 = activated_data_e_act_q_clipped_result_bits_rawIn_2_isNaN | activated_data_e_act_q_clipped_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_17 = {8{_activated_data_e_act_q_clipped_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_clipped_result_bits_expOut_2 = _activated_data_e_act_q_clipped_result_bits_expOut_T_15 | _activated_data_e_act_q_clipped_result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_4 = activated_data_e_act_q_clipped_result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_5 = activated_data_e_act_q_clipped_result_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_clipped_result_bits_fractOut_2 = activated_data_e_act_q_clipped_result_bits_isSubnormal_2 ? activated_data_e_act_q_clipped_result_bits_denormFract_2 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_clipped_result_bits_hi_2 = {activated_data_e_act_q_clipped_result_bits_rawIn_2_sign, activated_data_e_act_q_clipped_result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_clipped_result_bits_T_2 = {activated_data_e_act_q_clipped_result_bits_hi_2, activated_data_e_act_q_clipped_result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_clipped_result_2_bits = _activated_data_e_act_q_clipped_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_4 = activated_data_e_act_q_clipped_result_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_4_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_4 = activated_data_e_act_q_clipped_result_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4 = activated_data_e_act_q_clipped_result_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_176 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_177 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_178 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_179 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_180 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_181 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_182 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_183 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_184 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_185 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_186 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_187 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_188 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_189 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_190 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_191 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_192 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_193 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_194 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_195 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_196 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_197 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_198 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_199 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_200 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_201 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_202 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_203 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_204 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_205 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_206 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_207 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_208 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_209 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_210 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_211 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_212 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_213 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_214 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_215 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_216 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_217 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_218 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_219 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_4 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_4 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_4 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_8 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_4 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_4_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_4 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_4 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_34 = activated_data_e_act_q_clipped_t_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_4 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_4_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_4 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_4 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_4_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_4_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_18 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_4 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_17, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_4_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_32 = activated_data_e_act_q_clipped_t_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_33 = activated_data_e_act_q_clipped_t_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_35 = {_activated_data_e_act_q_clipped_t_rec_T_33[2:1], _activated_data_e_act_q_clipped_t_rec_T_33[0] | _activated_data_e_act_q_clipped_t_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_36 = {activated_data_e_act_q_clipped_t_rec_rawIn_4_sign, _activated_data_e_act_q_clipped_t_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_37 = activated_data_e_act_q_clipped_t_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_38 = {_activated_data_e_act_q_clipped_t_rec_T_36, _activated_data_e_act_q_clipped_t_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_39 = activated_data_e_act_q_clipped_t_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_4 = {_activated_data_e_act_q_clipped_t_rec_T_38, _activated_data_e_act_q_clipped_t_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_4 = activated_data_e_act_q_abs_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_self_rec_rawIn_4_sign = activated_data_e_act_q_clipped_self_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_4 = activated_data_e_act_q_abs_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4 = activated_data_e_act_q_abs_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_q_clipped_self_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_176 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_177 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_178 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_179 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_180 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_181 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_182 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_183 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_184 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_185 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_186 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_187 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_188 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_189 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_190 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_191 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_192 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_193 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_194 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_195 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_196 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_197 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_198 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_199 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_200 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_201 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_202 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_203 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_204 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_205 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_206 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_207 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_208 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_209 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_210 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_211 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_212 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_213 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_214 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_215 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_216 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_217 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_218 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_219 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_4 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4} << activated_data_e_act_q_clipped_self_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_4 = {_activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_q_clipped_self_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_q_clipped_self_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_4 = _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_8 = activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_4 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_4_isZero = activated_data_e_act_q_clipped_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_4 = activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_4 = &_activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_T_34 = activated_data_e_act_q_clipped_self_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_self_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_4 & _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_self_rec_rawIn_4_isNaN = _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_4 = activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_4 & activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_self_rec_rawIn_4_isInf = _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_self_rec_rawIn_4_sExp = _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_q_clipped_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_18 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_4 : activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_17, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_self_rec_rawIn_4_sig = _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_32 = activated_data_e_act_q_clipped_self_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_33 = activated_data_e_act_q_clipped_self_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_q_clipped_self_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_35 = {_activated_data_e_act_q_clipped_self_rec_T_33[2:1], _activated_data_e_act_q_clipped_self_rec_T_33[0] | _activated_data_e_act_q_clipped_self_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_36 = {activated_data_e_act_q_clipped_self_rec_rawIn_4_sign, _activated_data_e_act_q_clipped_self_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_37 = activated_data_e_act_q_clipped_self_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_38 = {_activated_data_e_act_q_clipped_self_rec_T_36, _activated_data_e_act_q_clipped_self_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_39 = activated_data_e_act_q_clipped_self_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_self_rec_4 = {_activated_data_e_act_q_clipped_self_rec_T_38, _activated_data_e_act_q_clipped_self_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _activated_data_e_act_q_clipped_neg_t_T_12 = ~activated_data_e_act_q_clipped_t_sgn_3; // @[Arithmetic.scala:432:27, :433:25] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_14 = {_activated_data_e_act_q_clipped_neg_t_T_12, _activated_data_e_act_q_clipped_neg_t_T_13}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_WIRE_3 = _activated_data_e_act_q_clipped_neg_t_T_14; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_15; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_clipped_neg_t_3_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_clipped_neg_t_T_15 = _activated_data_e_act_q_clipped_neg_t_WIRE_3; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_clipped_neg_t_3_bits = _activated_data_e_act_q_clipped_neg_t_T_15; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_5 = activated_data_e_act_q_clipped_neg_t_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_5_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_5 = activated_data_e_act_q_clipped_neg_t_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5 = activated_data_e_act_q_clipped_neg_t_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_5 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_5 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_220 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_221 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_222 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_223 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_224 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_225 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_226 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_227 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_228 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_229 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_230 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_231 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_232 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_233 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_234 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_235 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_236 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_237 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_238 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_239 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_240 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_241 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_242 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_243 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_244 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_245 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_246 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_247 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_248 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_249 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_250 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_251 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_252 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_253 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_254 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_255 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_256 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_257 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_258 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_259 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_260 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_261 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_262 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_263 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_5 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_11 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_5 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_26 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_27 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_5 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_10 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_5 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_5 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_5_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_5 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_5 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_42 = activated_data_e_act_q_clipped_t_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_11 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_5 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_5_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_5 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_5 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_5_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_5_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_20 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_22 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_5 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_5 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_23 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_21, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_5_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_40 = activated_data_e_act_q_clipped_t_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_41 = activated_data_e_act_q_clipped_t_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_43 = {_activated_data_e_act_q_clipped_t_rec_T_41[2:1], _activated_data_e_act_q_clipped_t_rec_T_41[0] | _activated_data_e_act_q_clipped_t_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_44 = {activated_data_e_act_q_clipped_t_rec_rawIn_5_sign, _activated_data_e_act_q_clipped_t_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_45 = activated_data_e_act_q_clipped_t_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_46 = {_activated_data_e_act_q_clipped_t_rec_T_44, _activated_data_e_act_q_clipped_t_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_47 = activated_data_e_act_q_clipped_t_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_5 = {_activated_data_e_act_q_clipped_t_rec_T_46, _activated_data_e_act_q_clipped_t_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_clipped_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_result_3_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_clipped_result_bits_rawIn_exp_3 = _activated_data_e_act_q_clipped_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_3 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isZero_3 = _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_clipped_result_bits_rawIn_3_isZero = activated_data_e_act_q_clipped_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_3 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_3 = &_activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_clipped_result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_clipped_result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_clipped_result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_9 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_clipped_result_bits_rawIn_3_isNaN = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_11 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_clipped_result_bits_rawIn_3_isInf = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_3 = _activated_data_e_act_q_clipped_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_clipped_result_bits_rawIn_3_sign = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_q_clipped_result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_clipped_result_bits_rawIn_3_sExp = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_q_clipped_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_14 = _activated_data_e_act_q_clipped_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_13, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_clipped_result_bits_rawIn_3_sig = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_clipped_result_bits_isSubnormal_3 = $signed(activated_data_e_act_q_clipped_result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_6 = activated_data_e_act_q_clipped_result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_clipped_result_bits_denormShiftDist_3 = _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_6 = activated_data_e_act_q_clipped_result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_7 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_6 >> activated_data_e_act_q_clipped_result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_clipped_result_bits_denormFract_3 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_18 = activated_data_e_act_q_clipped_result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_19 = {1'h0, _activated_data_e_act_q_clipped_result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_20 = _activated_data_e_act_q_clipped_result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_21 = activated_data_e_act_q_clipped_result_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_q_clipped_result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_clipped_result_bits_expOut_T_22 = activated_data_e_act_q_clipped_result_bits_rawIn_3_isNaN | activated_data_e_act_q_clipped_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_23 = {8{_activated_data_e_act_q_clipped_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_clipped_result_bits_expOut_3 = _activated_data_e_act_q_clipped_result_bits_expOut_T_21 | _activated_data_e_act_q_clipped_result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_6 = activated_data_e_act_q_clipped_result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_7 = activated_data_e_act_q_clipped_result_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_clipped_result_bits_fractOut_3 = activated_data_e_act_q_clipped_result_bits_isSubnormal_3 ? activated_data_e_act_q_clipped_result_bits_denormFract_3 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_clipped_result_bits_hi_3 = {activated_data_e_act_q_clipped_result_bits_rawIn_3_sign, activated_data_e_act_q_clipped_result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_clipped_result_bits_T_3 = {activated_data_e_act_q_clipped_result_bits_hi_3, activated_data_e_act_q_clipped_result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_clipped_result_3_bits = _activated_data_e_act_q_clipped_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_1_bits = _activated_data_e_act_q_clipped_comparator_1_io_gt ? activated_data_e_act_q_clipped_result_3_bits : activated_data_e_act_q_abs_1_bits; // @[Arithmetic.scala:426:26, :475:32] wire activated_data_e_act_q_poly_t_rec_rawIn_2_sign = activated_data_e_act_q_poly_t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_poly_t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_88 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_89 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_90 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_91 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_92 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_93 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_94 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_95 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_96 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_97 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_98 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_99 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_100 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_101 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_102 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_103 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_104 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_105 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_106 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_107 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_108 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_109 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_110 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_t_rec_rawIn_normDist_2 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2} << activated_data_e_act_q_poly_t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_poly_t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_poly_t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_t_rec_rawIn_isZero_2 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_t_rec_rawIn_2_isZero = activated_data_e_act_q_poly_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_t_rec_T_18 = activated_data_e_act_q_poly_t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_t_rec_rawIn_2_isNaN = _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_2 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_t_rec_rawIn_2_isInf = _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_t_rec_rawIn_2_sExp = _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_2 : activated_data_e_act_q_poly_t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_t_rec_rawIn_2_sig = _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_16 = activated_data_e_act_q_poly_t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_17 = activated_data_e_act_q_poly_t_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_poly_t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_19 = {_activated_data_e_act_q_poly_t_rec_T_17[2:1], _activated_data_e_act_q_poly_t_rec_T_17[0] | _activated_data_e_act_q_poly_t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_t_rec_T_20 = {activated_data_e_act_q_poly_t_rec_rawIn_2_sign, _activated_data_e_act_q_poly_t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_t_rec_T_21 = activated_data_e_act_q_poly_t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_t_rec_T_22 = {_activated_data_e_act_q_poly_t_rec_T_20, _activated_data_e_act_q_poly_t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_t_rec_T_23 = activated_data_e_act_q_poly_t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_t_rec_2 = {_activated_data_e_act_q_poly_t_rec_T_22, _activated_data_e_act_q_poly_t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_4 = activated_data_e_act_q_clipped_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_5 = activated_data_e_act_q_clipped_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_4_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_4 = activated_data_e_act_q_clipped_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_5 = activated_data_e_act_q_clipped_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4 = activated_data_e_act_q_clipped_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5 = activated_data_e_act_q_clipped_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_176 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_177 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_178 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_179 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_180 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_181 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_182 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_183 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_184 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_185 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_186 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_187 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_188 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_189 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_190 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_191 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_192 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_193 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_194 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_195 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_196 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_197 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_198 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_199 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_200 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_201 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_202 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_203 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_204 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_205 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_206 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_207 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_208 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_209 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_210 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_211 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_212 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_213 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_214 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_215 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_216 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_217 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_218 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_219 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_4 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_4 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_4 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_8 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_4 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_4_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_4 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_4 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_34 = activated_data_e_act_q_poly_self_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_4 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_4_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_4 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_4 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_4_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_4_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_18 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_4 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_17, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_4_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_32 = activated_data_e_act_q_poly_self_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_33 = activated_data_e_act_q_poly_self_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_35 = {_activated_data_e_act_q_poly_self_rec_T_33[2:1], _activated_data_e_act_q_poly_self_rec_T_33[0] | _activated_data_e_act_q_poly_self_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_36 = {activated_data_e_act_q_poly_self_rec_rawIn_4_sign, _activated_data_e_act_q_poly_self_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_37 = activated_data_e_act_q_poly_self_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_38 = {_activated_data_e_act_q_poly_self_rec_T_36, _activated_data_e_act_q_poly_self_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_39 = activated_data_e_act_q_poly_self_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_4 = {_activated_data_e_act_q_poly_self_rec_T_38, _activated_data_e_act_q_poly_self_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_result_2_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_3 = _activated_data_e_act_q_poly_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_3 = activated_data_e_act_q_poly_result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_3 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_3_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_q_poly_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_9 = activated_data_e_act_q_poly_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_3_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_11 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_3_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_3 = _activated_data_e_act_q_poly_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_3_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_3_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_14 = _activated_data_e_act_q_poly_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_3_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_3 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_6 = activated_data_e_act_q_poly_result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_3 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_6 = activated_data_e_act_q_poly_result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_7 = _activated_data_e_act_q_poly_result_bits_denormFract_T_6 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_3 = _activated_data_e_act_q_poly_result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_18 = activated_data_e_act_q_poly_result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_19 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_20 = _activated_data_e_act_q_poly_result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_21 = activated_data_e_act_q_poly_result_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_22 = activated_data_e_act_q_poly_result_bits_rawIn_3_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_23 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_3 = _activated_data_e_act_q_poly_result_bits_expOut_T_21 | _activated_data_e_act_q_poly_result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_6 = activated_data_e_act_q_poly_result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_7 = activated_data_e_act_q_poly_result_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_3 = activated_data_e_act_q_poly_result_bits_isSubnormal_3 ? activated_data_e_act_q_poly_result_bits_denormFract_3 : _activated_data_e_act_q_poly_result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_3 = {activated_data_e_act_q_poly_result_bits_rawIn_3_sign, activated_data_e_act_q_poly_result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_3 = {activated_data_e_act_q_poly_result_bits_hi_3, activated_data_e_act_q_poly_result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_result_2_bits = _activated_data_e_act_q_poly_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_t_rec_rawIn_3_sign = activated_data_e_act_q_poly_t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_poly_t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_132 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_133 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_134 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_135 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_136 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_137 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_138 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_139 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_140 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_141 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_142 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_143 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_144 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_145 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_146 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_147 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_148 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_149 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_150 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_151 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_152 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_153 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_154 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_t_rec_rawIn_normDist_3 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3} << activated_data_e_act_q_poly_t_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_poly_t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_poly_t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_t_rec_rawIn_isZero_3 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_t_rec_rawIn_3_isZero = activated_data_e_act_q_poly_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_t_rec_T_26 = activated_data_e_act_q_poly_t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_t_rec_rawIn_3_isNaN = _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_3 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_t_rec_rawIn_3_isInf = _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_t_rec_rawIn_3_sExp = _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_3 : activated_data_e_act_q_poly_t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_t_rec_rawIn_3_sig = _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_24 = activated_data_e_act_q_poly_t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_25 = activated_data_e_act_q_poly_t_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_poly_t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_27 = {_activated_data_e_act_q_poly_t_rec_T_25[2:1], _activated_data_e_act_q_poly_t_rec_T_25[0] | _activated_data_e_act_q_poly_t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_t_rec_T_28 = {activated_data_e_act_q_poly_t_rec_rawIn_3_sign, _activated_data_e_act_q_poly_t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_t_rec_T_29 = activated_data_e_act_q_poly_t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_t_rec_T_30 = {_activated_data_e_act_q_poly_t_rec_T_28, _activated_data_e_act_q_poly_t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_t_rec_T_31 = activated_data_e_act_q_poly_t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_t_rec_3 = {_activated_data_e_act_q_poly_t_rec_T_30, _activated_data_e_act_q_poly_t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_5_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_5 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_5 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_220 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_221 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_222 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_223 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_224 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_225 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_226 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_227 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_228 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_229 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_230 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_231 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_232 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_233 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_234 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_235 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_236 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_237 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_238 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_239 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_240 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_241 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_242 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_243 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_244 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_245 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_246 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_247 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_248 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_249 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_250 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_251 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_252 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_253 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_254 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_255 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_256 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_257 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_258 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_259 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_260 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_261 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_262 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_263 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_5 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_11 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_5 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_26 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_27 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_5 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_10 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_5 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_5 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_5_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_5 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_5 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_42 = activated_data_e_act_q_poly_self_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_11 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_5 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_5_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_5 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_5 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_5_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_5_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_20 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_22 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_5 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_5 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_23 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_21, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_5_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_40 = activated_data_e_act_q_poly_self_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_41 = activated_data_e_act_q_poly_self_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_43 = {_activated_data_e_act_q_poly_self_rec_T_41[2:1], _activated_data_e_act_q_poly_self_rec_T_41[0] | _activated_data_e_act_q_poly_self_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_44 = {activated_data_e_act_q_poly_self_rec_rawIn_5_sign, _activated_data_e_act_q_poly_self_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_45 = activated_data_e_act_q_poly_self_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_46 = {_activated_data_e_act_q_poly_self_rec_T_44, _activated_data_e_act_q_poly_self_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_47 = activated_data_e_act_q_poly_self_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_5 = {_activated_data_e_act_q_poly_self_rec_T_46, _activated_data_e_act_q_poly_self_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_4; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_result_3_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_4 = _activated_data_e_act_q_poly_muladder_4_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_4 = activated_data_e_act_q_poly_result_bits_rawIn_exp_4[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_4 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_4 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_4_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_4 = activated_data_e_act_q_poly_result_bits_rawIn_exp_4[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_4 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_4; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_14; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_4; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_4; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_19; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_4_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_4_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_4_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_4_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_4_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_8 = activated_data_e_act_q_poly_result_bits_rawIn_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_12 = activated_data_e_act_q_poly_result_bits_rawIn_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_9 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_4 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_8; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_4_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_13 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_12; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_14 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_4 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_13; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_4_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_14; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_4 = _activated_data_e_act_q_poly_muladder_4_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_4_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_4; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_4 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_4}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_4_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_4; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_16 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_16}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_18 = _activated_data_e_act_q_poly_muladder_4_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_19 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_17, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_18}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_4_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_19; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_4 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_4_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_8 = activated_data_e_act_q_poly_result_bits_rawIn_4_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_9 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_8}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_4 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_9[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_8 = activated_data_e_act_q_poly_result_bits_rawIn_4_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_9 = _activated_data_e_act_q_poly_result_bits_denormFract_T_8 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_4; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_4 = _activated_data_e_act_q_poly_result_bits_denormFract_T_9[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_24 = activated_data_e_act_q_poly_result_bits_rawIn_4_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_25 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_24} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_26 = _activated_data_e_act_q_poly_result_bits_expOut_T_25[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_27 = activated_data_e_act_q_poly_result_bits_isSubnormal_4 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_26; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_28 = activated_data_e_act_q_poly_result_bits_rawIn_4_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_4_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_29 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_28}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_4 = _activated_data_e_act_q_poly_result_bits_expOut_T_27 | _activated_data_e_act_q_poly_result_bits_expOut_T_29; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_8 = activated_data_e_act_q_poly_result_bits_rawIn_4_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_9 = activated_data_e_act_q_poly_result_bits_rawIn_4_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_8; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_4 = activated_data_e_act_q_poly_result_bits_isSubnormal_4 ? activated_data_e_act_q_poly_result_bits_denormFract_4 : _activated_data_e_act_q_poly_result_bits_fractOut_T_9; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_4 = {activated_data_e_act_q_poly_result_bits_rawIn_4_sign, activated_data_e_act_q_poly_result_bits_expOut_4}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_4 = {activated_data_e_act_q_poly_result_bits_hi_4, activated_data_e_act_q_poly_result_bits_fractOut_4}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_result_3_bits = _activated_data_e_act_q_poly_result_bits_T_4; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_m1_rec_rawIn_sign_1 = activated_data_e_act_q_poly_result_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_m1_rec_rawIn_1_sign = activated_data_e_act_q_poly_m1_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_m1_rec_rawIn_expIn_1 = activated_data_e_act_q_poly_result_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1 = activated_data_e_act_q_poly_result_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_poly_m1_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_44 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_45 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_46 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_47 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_48 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_49 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_50 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_51 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_52 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_53 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_54 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_55 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_56 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_57 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_58 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_59 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_60 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_61 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_62 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_63 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_64 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_65 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_66 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_m1_rec_rawIn_normDist_1 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1} << activated_data_e_act_q_poly_m1_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_poly_m1_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_poly_m1_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZero_1 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_m1_rec_rawIn_1_isZero = activated_data_e_act_q_poly_m1_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_m1_rec_T_10 = activated_data_e_act_q_poly_m1_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_m1_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_m1_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_m1_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_m1_rec_rawIn_1_isNaN = _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_1 & activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_m1_rec_rawIn_1_isInf = _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_m1_rec_rawIn_1_sExp = _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_m1_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_1 : activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_m1_rec_rawIn_1_sig = _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_8 = activated_data_e_act_q_poly_m1_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_9 = activated_data_e_act_q_poly_m1_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_poly_m1_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_11 = {_activated_data_e_act_q_poly_m1_rec_T_9[2:1], _activated_data_e_act_q_poly_m1_rec_T_9[0] | _activated_data_e_act_q_poly_m1_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_m1_rec_T_12 = {activated_data_e_act_q_poly_m1_rec_rawIn_1_sign, _activated_data_e_act_q_poly_m1_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_m1_rec_T_13 = activated_data_e_act_q_poly_m1_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_m1_rec_T_14 = {_activated_data_e_act_q_poly_m1_rec_T_12, _activated_data_e_act_q_poly_m1_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_m1_rec_T_15 = activated_data_e_act_q_poly_m1_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_m1_rec_1 = {_activated_data_e_act_q_poly_m1_rec_T_14, _activated_data_e_act_q_poly_m1_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_m2_rec_rawIn_sign_1 = activated_data_e_act_q_poly_result_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_m2_rec_rawIn_1_sign = activated_data_e_act_q_poly_m2_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_m2_rec_rawIn_expIn_1 = activated_data_e_act_q_poly_result_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1 = activated_data_e_act_q_poly_result_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_poly_m2_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_44 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_45 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_46 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_47 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_48 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_49 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_50 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_51 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_52 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_53 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_54 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_55 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_56 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_57 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_58 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_59 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_60 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_61 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_62 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_63 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_64 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_65 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_66 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_m2_rec_rawIn_normDist_1 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1} << activated_data_e_act_q_poly_m2_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_poly_m2_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_poly_m2_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZero_1 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_m2_rec_rawIn_1_isZero = activated_data_e_act_q_poly_m2_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_m2_rec_T_10 = activated_data_e_act_q_poly_m2_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_m2_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_m2_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_m2_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_m2_rec_rawIn_1_isNaN = _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_1 & activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_m2_rec_rawIn_1_isInf = _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_m2_rec_rawIn_1_sExp = _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_m2_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_1 : activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_m2_rec_rawIn_1_sig = _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_8 = activated_data_e_act_q_poly_m2_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_9 = activated_data_e_act_q_poly_m2_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_poly_m2_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_11 = {_activated_data_e_act_q_poly_m2_rec_T_9[2:1], _activated_data_e_act_q_poly_m2_rec_T_9[0] | _activated_data_e_act_q_poly_m2_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_m2_rec_T_12 = {activated_data_e_act_q_poly_m2_rec_rawIn_1_sign, _activated_data_e_act_q_poly_m2_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_m2_rec_T_13 = activated_data_e_act_q_poly_m2_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_m2_rec_T_14 = {_activated_data_e_act_q_poly_m2_rec_T_12, _activated_data_e_act_q_poly_m2_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_m2_rec_T_15 = activated_data_e_act_q_poly_m2_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_m2_rec_1 = {_activated_data_e_act_q_poly_m2_rec_T_14, _activated_data_e_act_q_poly_m2_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_6_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_264 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_265 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_266 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_267 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_268 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_269 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_270 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_271 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_272 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_273 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_274 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_275 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_276 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_277 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_278 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_279 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_280 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_281 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_282 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_283 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_284 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_285 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_286 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_287 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_288 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_289 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_290 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_291 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_292 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_293 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_294 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_295 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_296 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_297 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_298 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_299 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_300 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_301 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_302 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_303 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_304 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_305 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_306 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_307 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_6 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_6 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_6 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_12 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_6 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_6_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_6 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_6 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_50 = activated_data_e_act_q_poly_self_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_6 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_6_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_6 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_6 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_6_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_6_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_26 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_6 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_25, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_6_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_48 = activated_data_e_act_q_poly_self_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_49 = activated_data_e_act_q_poly_self_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_51 = {_activated_data_e_act_q_poly_self_rec_T_49[2:1], _activated_data_e_act_q_poly_self_rec_T_49[0] | _activated_data_e_act_q_poly_self_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_52 = {activated_data_e_act_q_poly_self_rec_rawIn_6_sign, _activated_data_e_act_q_poly_self_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_53 = activated_data_e_act_q_poly_self_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_54 = {_activated_data_e_act_q_poly_self_rec_T_52, _activated_data_e_act_q_poly_self_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_55 = activated_data_e_act_q_poly_self_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_6 = {_activated_data_e_act_q_poly_self_rec_T_54, _activated_data_e_act_q_poly_self_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_out_1_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_q_poly_out_bits_rawIn_exp_1 = _activated_data_e_act_q_poly_muladder_5_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_out_bits_rawIn_isZero_T_1 = activated_data_e_act_q_poly_out_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_out_bits_rawIn_isZero_1 = _activated_data_e_act_q_poly_out_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_out_bits_rawIn_1_isZero = activated_data_e_act_q_poly_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_out_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_out_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_out_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_out_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_out_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_q_poly_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_out_bits_rawIn_1_isNaN = _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_5 = activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_out_bits_rawIn_1_isInf = _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T_1 = _activated_data_e_act_q_poly_muladder_5_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_out_bits_rawIn_1_sign = _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_q_poly_out_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_out_bits_rawIn_1_sExp = _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_6 = _activated_data_e_act_q_poly_muladder_5_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_out_bits_rawIn_1_sig = _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_out_bits_isSubnormal_1 = $signed(activated_data_e_act_q_poly_out_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_2 = activated_data_e_act_q_poly_out_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_out_bits_denormShiftDist_1 = _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_out_bits_denormFract_T_2 = activated_data_e_act_q_poly_out_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_out_bits_denormFract_T_3 = _activated_data_e_act_q_poly_out_bits_denormFract_T_2 >> activated_data_e_act_q_poly_out_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_out_bits_denormFract_1 = _activated_data_e_act_q_poly_out_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_6 = activated_data_e_act_q_poly_out_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_out_bits_expOut_T_7 = {1'h0, _activated_data_e_act_q_poly_out_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_8 = _activated_data_e_act_q_poly_out_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_9 = activated_data_e_act_q_poly_out_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_q_poly_out_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_out_bits_expOut_T_10 = activated_data_e_act_q_poly_out_bits_rawIn_1_isNaN | activated_data_e_act_q_poly_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_11 = {8{_activated_data_e_act_q_poly_out_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_out_bits_expOut_1 = _activated_data_e_act_q_poly_out_bits_expOut_T_9 | _activated_data_e_act_q_poly_out_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_out_bits_fractOut_T_2 = activated_data_e_act_q_poly_out_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_out_bits_fractOut_T_3 = activated_data_e_act_q_poly_out_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_q_poly_out_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_out_bits_fractOut_1 = activated_data_e_act_q_poly_out_bits_isSubnormal_1 ? activated_data_e_act_q_poly_out_bits_denormFract_1 : _activated_data_e_act_q_poly_out_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_out_bits_hi_1 = {activated_data_e_act_q_poly_out_bits_rawIn_1_sign, activated_data_e_act_q_poly_out_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_out_bits_T_1 = {activated_data_e_act_q_poly_out_bits_hi_1, activated_data_e_act_q_poly_out_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_out_1_bits = _activated_data_e_act_q_poly_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_7 = activated_data_e_act_q_poly_out_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_7_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_7 = activated_data_e_act_q_poly_out_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7 = activated_data_e_act_q_poly_out_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_7 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_7 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_308 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_309 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_310 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_311 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_312 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_313 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_314 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_315 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_316 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_317 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_318 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_319 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_320 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_321 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_322 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_323 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_324 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_325 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_326 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_327 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_328 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_329 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_330 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_331 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_332 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_333 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_334 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_335 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_336 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_337 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_338 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_339 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_340 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_341 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_342 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_343 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_344 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_345 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_346 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_347 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_348 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_349 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_350 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_351 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_7 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_15 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_7 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_36 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_37 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_7 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_14 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_7 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_7 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_7_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_7 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_7 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_58 = activated_data_e_act_q_poly_self_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_15 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_7 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_7_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_7 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_7 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_7_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_7_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_28 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_30 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_7 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_7 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_31 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_29, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_7_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_56 = activated_data_e_act_q_poly_self_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_57 = activated_data_e_act_q_poly_self_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_59 = {_activated_data_e_act_q_poly_self_rec_T_57[2:1], _activated_data_e_act_q_poly_self_rec_T_57[0] | _activated_data_e_act_q_poly_self_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_60 = {activated_data_e_act_q_poly_self_rec_rawIn_7_sign, _activated_data_e_act_q_poly_self_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_61 = activated_data_e_act_q_poly_self_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_62 = {_activated_data_e_act_q_poly_self_rec_T_60, _activated_data_e_act_q_poly_self_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_63 = activated_data_e_act_q_poly_self_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_7 = {_activated_data_e_act_q_poly_self_rec_T_62, _activated_data_e_act_q_poly_self_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_5; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_1_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_5 = _activated_data_e_act_q_poly_resizer_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_5 = activated_data_e_act_q_poly_result_bits_rawIn_exp_5[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_5 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_5 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_5_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_5 = activated_data_e_act_q_poly_result_bits_rawIn_exp_5[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_5 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_5; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_17; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_5; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_5; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_23; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_5_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_5_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_5_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_5_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_5_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_10 = activated_data_e_act_q_poly_result_bits_rawIn_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_15 = activated_data_e_act_q_poly_result_bits_rawIn_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_11 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_5 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_10; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_5_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_16 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_15; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_17 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_5 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_16; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_5_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_17; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_5 = _activated_data_e_act_q_poly_resizer_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_5_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_5; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_5 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_5}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_5_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_5; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_20 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_20}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_22 = _activated_data_e_act_q_poly_resizer_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_23 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_21, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_22}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_5_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_23; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_5 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_5_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_10 = activated_data_e_act_q_poly_result_bits_rawIn_5_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_11 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_10}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_5 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_11[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_10 = activated_data_e_act_q_poly_result_bits_rawIn_5_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_11 = _activated_data_e_act_q_poly_result_bits_denormFract_T_10 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_5; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_5 = _activated_data_e_act_q_poly_result_bits_denormFract_T_11[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_30 = activated_data_e_act_q_poly_result_bits_rawIn_5_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_31 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_30} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_32 = _activated_data_e_act_q_poly_result_bits_expOut_T_31[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_33 = activated_data_e_act_q_poly_result_bits_isSubnormal_5 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_32; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_34 = activated_data_e_act_q_poly_result_bits_rawIn_5_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_5_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_35 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_34}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_5 = _activated_data_e_act_q_poly_result_bits_expOut_T_33 | _activated_data_e_act_q_poly_result_bits_expOut_T_35; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_10 = activated_data_e_act_q_poly_result_bits_rawIn_5_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_11 = activated_data_e_act_q_poly_result_bits_rawIn_5_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_10; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_5 = activated_data_e_act_q_poly_result_bits_isSubnormal_5 ? activated_data_e_act_q_poly_result_bits_denormFract_5 : _activated_data_e_act_q_poly_result_bits_fractOut_T_11; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_5 = {activated_data_e_act_q_poly_result_bits_rawIn_5_sign, activated_data_e_act_q_poly_result_bits_expOut_5}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_5 = {activated_data_e_act_q_poly_result_bits_hi_5, activated_data_e_act_q_poly_result_bits_fractOut_5}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_1_bits = _activated_data_e_act_q_poly_result_bits_T_5; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_erf_t_rec_rawIn_sign_1 = activated_data_e_act_q_poly_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_t_rec_rawIn_1_sign = activated_data_e_act_q_erf_t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_t_rec_rawIn_expIn_1 = activated_data_e_act_q_poly_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1 = activated_data_e_act_q_poly_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_erf_t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_44 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_45 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_46 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_47 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_48 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_49 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_50 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_51 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_52 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_53 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_54 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_55 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_56 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_57 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_58 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_59 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_60 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_61 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_62 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_63 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_64 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_65 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_66 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_t_rec_rawIn_normDist_1 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1} << activated_data_e_act_q_erf_t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_erf_t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_erf_t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_t_rec_rawIn_isZero_1 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_t_rec_rawIn_1_isZero = activated_data_e_act_q_erf_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_t_rec_T_10 = activated_data_e_act_q_erf_t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_t_rec_rawIn_1_isNaN = _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_1 & activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_t_rec_rawIn_1_isInf = _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_t_rec_rawIn_1_sExp = _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_erf_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_1 : activated_data_e_act_q_erf_t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_t_rec_rawIn_1_sig = _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_8 = activated_data_e_act_q_erf_t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_9 = activated_data_e_act_q_erf_t_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_erf_t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_11 = {_activated_data_e_act_q_erf_t_rec_T_9[2:1], _activated_data_e_act_q_erf_t_rec_T_9[0] | _activated_data_e_act_q_erf_t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_t_rec_T_12 = {activated_data_e_act_q_erf_t_rec_rawIn_1_sign, _activated_data_e_act_q_erf_t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_t_rec_T_13 = activated_data_e_act_q_erf_t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_t_rec_T_14 = {_activated_data_e_act_q_erf_t_rec_T_12, _activated_data_e_act_q_erf_t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_t_rec_T_15 = activated_data_e_act_q_erf_t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_t_rec_1 = {_activated_data_e_act_q_erf_t_rec_T_14, _activated_data_e_act_q_erf_t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_erf_self_rec_rawIn_sign_2 = activated_data_e_act_q_sign_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_self_rec_rawIn_2_sign = activated_data_e_act_q_erf_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_self_rec_rawIn_expIn_2 = activated_data_e_act_q_sign_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2 = activated_data_e_act_q_sign_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_erf_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_88 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_89 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_90 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_91 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_92 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_93 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_94 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_95 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_96 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_97 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_98 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_99 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_100 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_101 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_102 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_103 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_104 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_105 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_106 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_107 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_108 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_109 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_110 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_self_rec_rawIn_normDist_2 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2} << activated_data_e_act_q_erf_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_erf_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_erf_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_self_rec_rawIn_isZero_2 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_self_rec_rawIn_2_isZero = activated_data_e_act_q_erf_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_self_rec_T_18 = activated_data_e_act_q_erf_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_self_rec_rawIn_2_isNaN = _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_2 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_self_rec_rawIn_2_isInf = _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_self_rec_rawIn_2_sExp = _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_2 : activated_data_e_act_q_erf_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_self_rec_rawIn_2_sig = _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_16 = activated_data_e_act_q_erf_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_17 = activated_data_e_act_q_erf_self_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_erf_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_19 = {_activated_data_e_act_q_erf_self_rec_T_17[2:1], _activated_data_e_act_q_erf_self_rec_T_17[0] | _activated_data_e_act_q_erf_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_self_rec_T_20 = {activated_data_e_act_q_erf_self_rec_rawIn_2_sign, _activated_data_e_act_q_erf_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_self_rec_T_21 = activated_data_e_act_q_erf_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_self_rec_T_22 = {_activated_data_e_act_q_erf_self_rec_T_20, _activated_data_e_act_q_erf_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_self_rec_T_23 = activated_data_e_act_q_erf_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_self_rec_2 = {_activated_data_e_act_q_erf_self_rec_T_22, _activated_data_e_act_q_erf_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_erf_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_erf_out_1_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_q_erf_out_bits_rawIn_exp_1 = _activated_data_e_act_q_erf_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_erf_out_bits_rawIn_isZero_T_1 = activated_data_e_act_q_erf_out_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_erf_out_bits_rawIn_isZero_1 = _activated_data_e_act_q_erf_out_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_erf_out_bits_rawIn_1_isZero = activated_data_e_act_q_erf_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_T_1 = activated_data_e_act_q_erf_out_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_1 = &_activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_erf_out_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_out_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_erf_out_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_erf_out_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_q_erf_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_3 = activated_data_e_act_q_erf_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_erf_out_bits_rawIn_1_isNaN = _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_5 = activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_erf_out_bits_rawIn_1_isInf = _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T_1 = _activated_data_e_act_q_erf_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_erf_out_bits_rawIn_1_sign = _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_q_erf_out_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_erf_out_bits_rawIn_1_sExp = _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_q_erf_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_6 = _activated_data_e_act_q_erf_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_5, _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_erf_out_bits_rawIn_1_sig = _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_erf_out_bits_isSubnormal_1 = $signed(activated_data_e_act_q_erf_out_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_2 = activated_data_e_act_q_erf_out_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_erf_out_bits_denormShiftDist_1 = _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_erf_out_bits_denormFract_T_2 = activated_data_e_act_q_erf_out_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_erf_out_bits_denormFract_T_3 = _activated_data_e_act_q_erf_out_bits_denormFract_T_2 >> activated_data_e_act_q_erf_out_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_erf_out_bits_denormFract_1 = _activated_data_e_act_q_erf_out_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_6 = activated_data_e_act_q_erf_out_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_erf_out_bits_expOut_T_7 = {1'h0, _activated_data_e_act_q_erf_out_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_8 = _activated_data_e_act_q_erf_out_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_9 = activated_data_e_act_q_erf_out_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_q_erf_out_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_erf_out_bits_expOut_T_10 = activated_data_e_act_q_erf_out_bits_rawIn_1_isNaN | activated_data_e_act_q_erf_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_11 = {8{_activated_data_e_act_q_erf_out_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_erf_out_bits_expOut_1 = _activated_data_e_act_q_erf_out_bits_expOut_T_9 | _activated_data_e_act_q_erf_out_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_erf_out_bits_fractOut_T_2 = activated_data_e_act_q_erf_out_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_erf_out_bits_fractOut_T_3 = activated_data_e_act_q_erf_out_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_q_erf_out_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_erf_out_bits_fractOut_1 = activated_data_e_act_q_erf_out_bits_isSubnormal_1 ? activated_data_e_act_q_erf_out_bits_denormFract_1 : _activated_data_e_act_q_erf_out_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_erf_out_bits_hi_1 = {activated_data_e_act_q_erf_out_bits_rawIn_1_sign, activated_data_e_act_q_erf_out_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_erf_out_bits_T_1 = {activated_data_e_act_q_erf_out_bits_hi_1, activated_data_e_act_q_erf_out_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_erf_out_1_bits = _activated_data_e_act_q_erf_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_erf_self_rec_rawIn_sign_3 = activated_data_e_act_q_erf_out_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_self_rec_rawIn_3_sign = activated_data_e_act_q_erf_self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_self_rec_rawIn_expIn_3 = activated_data_e_act_q_erf_out_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3 = activated_data_e_act_q_erf_out_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_erf_self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_132 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_133 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_134 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_135 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_136 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_137 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_138 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_139 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_140 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_141 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_142 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_143 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_144 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_145 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_146 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_147 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_148 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_149 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_150 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_151 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_152 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_153 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_154 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_self_rec_rawIn_normDist_3 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3} << activated_data_e_act_q_erf_self_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_erf_self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_erf_self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_self_rec_rawIn_isZero_3 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_self_rec_rawIn_3_isZero = activated_data_e_act_q_erf_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_self_rec_T_26 = activated_data_e_act_q_erf_self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_self_rec_rawIn_3_isNaN = _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_3 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_self_rec_rawIn_3_isInf = _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_self_rec_rawIn_3_sExp = _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_3 : activated_data_e_act_q_erf_self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_self_rec_rawIn_3_sig = _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_24 = activated_data_e_act_q_erf_self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_25 = activated_data_e_act_q_erf_self_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_erf_self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_27 = {_activated_data_e_act_q_erf_self_rec_T_25[2:1], _activated_data_e_act_q_erf_self_rec_T_25[0] | _activated_data_e_act_q_erf_self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_self_rec_T_28 = {activated_data_e_act_q_erf_self_rec_rawIn_3_sign, _activated_data_e_act_q_erf_self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_self_rec_T_29 = activated_data_e_act_q_erf_self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_self_rec_T_30 = {_activated_data_e_act_q_erf_self_rec_T_28, _activated_data_e_act_q_erf_self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_self_rec_T_31 = activated_data_e_act_q_erf_self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_self_rec_3 = {_activated_data_e_act_q_erf_self_rec_T_30, _activated_data_e_act_q_erf_self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_erf_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_erf_1_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_erf_result_bits_rawIn_exp_1 = _activated_data_e_act_q_erf_resizer_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_erf_result_bits_rawIn_isZero_T_1 = activated_data_e_act_q_erf_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_erf_result_bits_rawIn_isZero_1 = _activated_data_e_act_q_erf_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_erf_result_bits_rawIn_1_isZero = activated_data_e_act_q_erf_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_T_1 = activated_data_e_act_q_erf_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_1 = &_activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_erf_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_erf_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_erf_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_q_erf_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_3 = activated_data_e_act_q_erf_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_erf_result_bits_rawIn_1_isNaN = _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_5 = activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_erf_result_bits_rawIn_1_isInf = _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T_1 = _activated_data_e_act_q_erf_resizer_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_erf_result_bits_rawIn_1_sign = _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_q_erf_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_erf_result_bits_rawIn_1_sExp = _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_q_erf_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_6 = _activated_data_e_act_q_erf_resizer_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_5, _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_erf_result_bits_rawIn_1_sig = _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_erf_result_bits_isSubnormal_1 = $signed(activated_data_e_act_q_erf_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_2 = activated_data_e_act_q_erf_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_erf_result_bits_denormShiftDist_1 = _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_erf_result_bits_denormFract_T_2 = activated_data_e_act_q_erf_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_erf_result_bits_denormFract_T_3 = _activated_data_e_act_q_erf_result_bits_denormFract_T_2 >> activated_data_e_act_q_erf_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_erf_result_bits_denormFract_1 = _activated_data_e_act_q_erf_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_6 = activated_data_e_act_q_erf_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_erf_result_bits_expOut_T_7 = {1'h0, _activated_data_e_act_q_erf_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_8 = _activated_data_e_act_q_erf_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_9 = activated_data_e_act_q_erf_result_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_q_erf_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_erf_result_bits_expOut_T_10 = activated_data_e_act_q_erf_result_bits_rawIn_1_isNaN | activated_data_e_act_q_erf_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_11 = {8{_activated_data_e_act_q_erf_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_erf_result_bits_expOut_1 = _activated_data_e_act_q_erf_result_bits_expOut_T_9 | _activated_data_e_act_q_erf_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_erf_result_bits_fractOut_T_2 = activated_data_e_act_q_erf_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_erf_result_bits_fractOut_T_3 = activated_data_e_act_q_erf_result_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_q_erf_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_erf_result_bits_fractOut_1 = activated_data_e_act_q_erf_result_bits_isSubnormal_1 ? activated_data_e_act_q_erf_result_bits_denormFract_1 : _activated_data_e_act_q_erf_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_erf_result_bits_hi_1 = {activated_data_e_act_q_erf_result_bits_rawIn_1_sign, activated_data_e_act_q_erf_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_erf_result_bits_T_1 = {activated_data_e_act_q_erf_result_bits_hi_1, activated_data_e_act_q_erf_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_erf_1_bits = _activated_data_e_act_q_erf_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_t_rec_rawIn_5_sign = activated_data_e_act_t_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_5 = activated_data_e_act_t_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_5 = activated_data_e_act_t_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_t_rec_rawIn_normDist_T_220 = activated_data_e_act_t_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_221 = activated_data_e_act_t_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_222 = activated_data_e_act_t_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_223 = activated_data_e_act_t_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_224 = activated_data_e_act_t_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_225 = activated_data_e_act_t_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_226 = activated_data_e_act_t_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_227 = activated_data_e_act_t_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_228 = activated_data_e_act_t_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_229 = activated_data_e_act_t_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_230 = activated_data_e_act_t_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_231 = activated_data_e_act_t_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_232 = activated_data_e_act_t_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_233 = activated_data_e_act_t_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_234 = activated_data_e_act_t_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_235 = activated_data_e_act_t_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_236 = activated_data_e_act_t_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_237 = activated_data_e_act_t_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_238 = activated_data_e_act_t_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_239 = activated_data_e_act_t_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_240 = activated_data_e_act_t_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_241 = activated_data_e_act_t_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_242 = activated_data_e_act_t_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_243 = _activated_data_e_act_t_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_244 = _activated_data_e_act_t_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_act_t_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_245 = _activated_data_e_act_t_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_act_t_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_246 = _activated_data_e_act_t_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_act_t_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_247 = _activated_data_e_act_t_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_act_t_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_248 = _activated_data_e_act_t_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_act_t_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_249 = _activated_data_e_act_t_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_act_t_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_250 = _activated_data_e_act_t_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_act_t_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_251 = _activated_data_e_act_t_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_act_t_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_252 = _activated_data_e_act_t_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_act_t_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_253 = _activated_data_e_act_t_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_act_t_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_254 = _activated_data_e_act_t_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_act_t_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_255 = _activated_data_e_act_t_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_act_t_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_256 = _activated_data_e_act_t_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_act_t_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_257 = _activated_data_e_act_t_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_act_t_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_258 = _activated_data_e_act_t_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_act_t_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_259 = _activated_data_e_act_t_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_act_t_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_260 = _activated_data_e_act_t_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_act_t_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_261 = _activated_data_e_act_t_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_act_t_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_262 = _activated_data_e_act_t_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_act_t_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_263 = _activated_data_e_act_t_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_act_t_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_5 = _activated_data_e_act_t_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_act_t_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_act_t_rec_rawIn_fractIn_5} << activated_data_e_act_t_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_11 = _activated_data_e_act_t_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_5 = {_activated_data_e_act_t_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_act_t_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_26 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_act_t_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_act_t_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_27 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_5 = _activated_data_e_act_t_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_10 = activated_data_e_act_t_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_t_rec_rawIn_isZero_5 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_5 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_t_rec_rawIn_5_isZero = activated_data_e_act_t_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_5 = activated_data_e_act_t_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_t_rec_rawIn_isSpecial_5 = &_activated_data_e_act_t_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_T_42 = activated_data_e_act_t_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_t_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_t_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_t_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_act_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_t_rec_rawIn_out_isNaN_T_11 = activated_data_e_act_t_rec_rawIn_isSpecial_5 & _activated_data_e_act_t_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_t_rec_rawIn_5_isNaN = _activated_data_e_act_t_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_t_rec_rawIn_out_isInf_T_5 = activated_data_e_act_t_rec_rawIn_isSpecial_5 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_t_rec_rawIn_5_isInf = _activated_data_e_act_t_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_t_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_t_rec_rawIn_5_sExp = _activated_data_e_act_t_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_20 = ~activated_data_e_act_t_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_22 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_5 ? activated_data_e_act_t_rec_rawIn_subnormFract_5 : activated_data_e_act_t_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_t_rec_rawIn_out_sig_T_23 = {_activated_data_e_act_t_rec_rawIn_out_sig_T_21, _activated_data_e_act_t_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_t_rec_rawIn_5_sig = _activated_data_e_act_t_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_t_rec_T_40 = activated_data_e_act_t_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_41 = activated_data_e_act_t_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_act_t_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_t_rec_T_43 = {_activated_data_e_act_t_rec_T_41[2:1], _activated_data_e_act_t_rec_T_41[0] | _activated_data_e_act_t_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_t_rec_T_44 = {activated_data_e_act_t_rec_rawIn_5_sign, _activated_data_e_act_t_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_t_rec_T_45 = activated_data_e_act_t_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_t_rec_T_46 = {_activated_data_e_act_t_rec_T_44, _activated_data_e_act_t_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_t_rec_T_47 = activated_data_e_act_t_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_t_rec_5 = {_activated_data_e_act_t_rec_T_46, _activated_data_e_act_t_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_self_rec_rawIn_sign_6 = activated_data_e_act_q_erf_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_6_sign = activated_data_e_act_self_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_6 = activated_data_e_act_q_erf_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_6 = activated_data_e_act_q_erf_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_self_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_self_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_264 = activated_data_e_act_self_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_265 = activated_data_e_act_self_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_266 = activated_data_e_act_self_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_267 = activated_data_e_act_self_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_268 = activated_data_e_act_self_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_269 = activated_data_e_act_self_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_270 = activated_data_e_act_self_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_271 = activated_data_e_act_self_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_272 = activated_data_e_act_self_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_273 = activated_data_e_act_self_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_274 = activated_data_e_act_self_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_275 = activated_data_e_act_self_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_276 = activated_data_e_act_self_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_277 = activated_data_e_act_self_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_278 = activated_data_e_act_self_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_279 = activated_data_e_act_self_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_280 = activated_data_e_act_self_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_281 = activated_data_e_act_self_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_282 = activated_data_e_act_self_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_283 = activated_data_e_act_self_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_284 = activated_data_e_act_self_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_285 = activated_data_e_act_self_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_286 = activated_data_e_act_self_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_287 = _activated_data_e_act_self_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_288 = _activated_data_e_act_self_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_289 = _activated_data_e_act_self_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_290 = _activated_data_e_act_self_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_291 = _activated_data_e_act_self_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_292 = _activated_data_e_act_self_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_293 = _activated_data_e_act_self_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_294 = _activated_data_e_act_self_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_295 = _activated_data_e_act_self_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_296 = _activated_data_e_act_self_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_297 = _activated_data_e_act_self_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_298 = _activated_data_e_act_self_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_299 = _activated_data_e_act_self_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_300 = _activated_data_e_act_self_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_301 = _activated_data_e_act_self_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_302 = _activated_data_e_act_self_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_303 = _activated_data_e_act_self_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_304 = _activated_data_e_act_self_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_305 = _activated_data_e_act_self_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_306 = _activated_data_e_act_self_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_307 = _activated_data_e_act_self_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_6 = _activated_data_e_act_self_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_6} << activated_data_e_act_self_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_6 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_6 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_12 = activated_data_e_act_self_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_6 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_6_isZero = activated_data_e_act_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_6 = activated_data_e_act_self_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_6 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_50 = activated_data_e_act_self_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_self_rec_rawIn_isSpecial_6 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_6_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_6 = activated_data_e_act_self_rec_rawIn_isSpecial_6 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_6_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_6_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_26 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_self_rec_rawIn_subnormFract_6 : activated_data_e_act_self_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_25, _activated_data_e_act_self_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_6_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_48 = activated_data_e_act_self_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_49 = activated_data_e_act_self_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_51 = {_activated_data_e_act_self_rec_T_49[2:1], _activated_data_e_act_self_rec_T_49[0] | _activated_data_e_act_self_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_52 = {activated_data_e_act_self_rec_rawIn_6_sign, _activated_data_e_act_self_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_53 = activated_data_e_act_self_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_54 = {_activated_data_e_act_self_rec_T_52, _activated_data_e_act_self_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_55 = activated_data_e_act_self_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_6 = {_activated_data_e_act_self_rec_T_54, _activated_data_e_act_self_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_11; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_7_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_5 = _activated_data_e_act_muladder_5_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_5 = activated_data_e_act_result_bits_rawIn_exp_5[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_5 = _activated_data_e_act_result_bits_rawIn_isZero_T_5 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_5_isZero = activated_data_e_act_result_bits_rawIn_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_5 = activated_data_e_act_result_bits_rawIn_exp_5[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_5 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_5; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_17; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_5; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_5; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_23; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_5_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_5_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_5_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_5_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_5_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_10 = activated_data_e_act_result_bits_rawIn_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_15 = activated_data_e_act_result_bits_rawIn_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_11 = activated_data_e_act_result_bits_rawIn_isSpecial_5 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_10; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_5_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_16 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_15; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_17 = activated_data_e_act_result_bits_rawIn_isSpecial_5 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_16; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_5_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_17; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_5 = _activated_data_e_act_muladder_5_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_5_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_5; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_5 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_5}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_5_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_5; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_20 = ~activated_data_e_act_result_bits_rawIn_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_20}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_22 = _activated_data_e_act_muladder_5_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_23 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_21, _activated_data_e_act_result_bits_rawIn_out_sig_T_22}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_5_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_23; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_5 = $signed(activated_data_e_act_result_bits_rawIn_5_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_10 = activated_data_e_act_result_bits_rawIn_5_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_11 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_10}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_5 = _activated_data_e_act_result_bits_denormShiftDist_T_11[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_10 = activated_data_e_act_result_bits_rawIn_5_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_11 = _activated_data_e_act_result_bits_denormFract_T_10 >> activated_data_e_act_result_bits_denormShiftDist_5; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_5 = _activated_data_e_act_result_bits_denormFract_T_11[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_30 = activated_data_e_act_result_bits_rawIn_5_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_31 = {1'h0, _activated_data_e_act_result_bits_expOut_T_30} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_32 = _activated_data_e_act_result_bits_expOut_T_31[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_33 = activated_data_e_act_result_bits_isSubnormal_5 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_32; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_34 = activated_data_e_act_result_bits_rawIn_5_isNaN | activated_data_e_act_result_bits_rawIn_5_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_35 = {8{_activated_data_e_act_result_bits_expOut_T_34}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_5 = _activated_data_e_act_result_bits_expOut_T_33 | _activated_data_e_act_result_bits_expOut_T_35; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_10 = activated_data_e_act_result_bits_rawIn_5_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_11 = activated_data_e_act_result_bits_rawIn_5_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_10; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_5 = activated_data_e_act_result_bits_isSubnormal_5 ? activated_data_e_act_result_bits_denormFract_5 : _activated_data_e_act_result_bits_fractOut_T_11; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_5 = {activated_data_e_act_result_bits_rawIn_5_sign, activated_data_e_act_result_bits_expOut_5}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_11 = {activated_data_e_act_result_bits_hi_5, activated_data_e_act_result_bits_fractOut_5}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_7_bits = _activated_data_e_act_result_bits_T_11; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_t_rec_rawIn_sign_6 = activated_data_e_act_result_7_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_6_sign = activated_data_e_act_t_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_6 = activated_data_e_act_result_7_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_6 = activated_data_e_act_result_7_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_t_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_t_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_t_rec_rawIn_normDist_T_264 = activated_data_e_act_t_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_265 = activated_data_e_act_t_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_266 = activated_data_e_act_t_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_267 = activated_data_e_act_t_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_268 = activated_data_e_act_t_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_269 = activated_data_e_act_t_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_270 = activated_data_e_act_t_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_271 = activated_data_e_act_t_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_272 = activated_data_e_act_t_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_273 = activated_data_e_act_t_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_274 = activated_data_e_act_t_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_275 = activated_data_e_act_t_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_276 = activated_data_e_act_t_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_277 = activated_data_e_act_t_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_278 = activated_data_e_act_t_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_279 = activated_data_e_act_t_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_280 = activated_data_e_act_t_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_281 = activated_data_e_act_t_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_282 = activated_data_e_act_t_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_283 = activated_data_e_act_t_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_284 = activated_data_e_act_t_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_285 = activated_data_e_act_t_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_286 = activated_data_e_act_t_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_287 = _activated_data_e_act_t_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_288 = _activated_data_e_act_t_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_t_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_289 = _activated_data_e_act_t_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_t_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_290 = _activated_data_e_act_t_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_t_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_291 = _activated_data_e_act_t_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_t_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_292 = _activated_data_e_act_t_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_t_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_293 = _activated_data_e_act_t_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_t_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_294 = _activated_data_e_act_t_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_t_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_295 = _activated_data_e_act_t_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_t_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_296 = _activated_data_e_act_t_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_t_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_297 = _activated_data_e_act_t_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_t_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_298 = _activated_data_e_act_t_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_t_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_299 = _activated_data_e_act_t_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_t_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_300 = _activated_data_e_act_t_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_t_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_301 = _activated_data_e_act_t_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_t_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_302 = _activated_data_e_act_t_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_t_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_303 = _activated_data_e_act_t_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_t_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_304 = _activated_data_e_act_t_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_t_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_305 = _activated_data_e_act_t_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_t_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_306 = _activated_data_e_act_t_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_t_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_307 = _activated_data_e_act_t_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_t_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_6 = _activated_data_e_act_t_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_t_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_t_rec_rawIn_fractIn_6} << activated_data_e_act_t_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_t_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_6 = {_activated_data_e_act_t_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_t_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_t_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_t_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_6 = _activated_data_e_act_t_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_12 = activated_data_e_act_t_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_t_rec_rawIn_isZero_6 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_t_rec_rawIn_6_isZero = activated_data_e_act_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_6 = activated_data_e_act_t_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_t_rec_rawIn_isSpecial_6 = &_activated_data_e_act_t_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_T_50 = activated_data_e_act_t_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_t_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_t_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_t_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_t_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_t_rec_rawIn_isSpecial_6 & _activated_data_e_act_t_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_t_rec_rawIn_6_isNaN = _activated_data_e_act_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_t_rec_rawIn_out_isInf_T_6 = activated_data_e_act_t_rec_rawIn_isSpecial_6 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_t_rec_rawIn_6_isInf = _activated_data_e_act_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_t_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_t_rec_rawIn_6_sExp = _activated_data_e_act_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_26 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_t_rec_rawIn_subnormFract_6 : activated_data_e_act_t_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_t_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_t_rec_rawIn_out_sig_T_25, _activated_data_e_act_t_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_t_rec_rawIn_6_sig = _activated_data_e_act_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_t_rec_T_48 = activated_data_e_act_t_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_49 = activated_data_e_act_t_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_t_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_t_rec_T_51 = {_activated_data_e_act_t_rec_T_49[2:1], _activated_data_e_act_t_rec_T_49[0] | _activated_data_e_act_t_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_t_rec_T_52 = {activated_data_e_act_t_rec_rawIn_6_sign, _activated_data_e_act_t_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_t_rec_T_53 = activated_data_e_act_t_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_t_rec_T_54 = {_activated_data_e_act_t_rec_T_52, _activated_data_e_act_t_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_t_rec_T_55 = activated_data_e_act_t_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_t_rec_6 = {_activated_data_e_act_t_rec_T_54, _activated_data_e_act_t_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_self_rec_rawIn_7_sign = activated_data_e_act_self_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_7 = activated_data_e_act_self_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_7 = activated_data_e_act_self_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_308 = activated_data_e_act_self_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_309 = activated_data_e_act_self_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_310 = activated_data_e_act_self_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_311 = activated_data_e_act_self_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_312 = activated_data_e_act_self_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_313 = activated_data_e_act_self_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_314 = activated_data_e_act_self_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_315 = activated_data_e_act_self_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_316 = activated_data_e_act_self_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_317 = activated_data_e_act_self_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_318 = activated_data_e_act_self_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_319 = activated_data_e_act_self_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_320 = activated_data_e_act_self_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_321 = activated_data_e_act_self_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_322 = activated_data_e_act_self_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_323 = activated_data_e_act_self_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_324 = activated_data_e_act_self_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_325 = activated_data_e_act_self_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_326 = activated_data_e_act_self_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_327 = activated_data_e_act_self_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_328 = activated_data_e_act_self_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_329 = activated_data_e_act_self_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_330 = activated_data_e_act_self_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_331 = _activated_data_e_act_self_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_332 = _activated_data_e_act_self_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_333 = _activated_data_e_act_self_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_334 = _activated_data_e_act_self_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_335 = _activated_data_e_act_self_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_336 = _activated_data_e_act_self_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_337 = _activated_data_e_act_self_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_338 = _activated_data_e_act_self_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_339 = _activated_data_e_act_self_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_340 = _activated_data_e_act_self_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_341 = _activated_data_e_act_self_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_342 = _activated_data_e_act_self_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_343 = _activated_data_e_act_self_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_344 = _activated_data_e_act_self_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_345 = _activated_data_e_act_self_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_346 = _activated_data_e_act_self_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_347 = _activated_data_e_act_self_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_348 = _activated_data_e_act_self_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_349 = _activated_data_e_act_self_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_350 = _activated_data_e_act_self_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_351 = _activated_data_e_act_self_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_7 = _activated_data_e_act_self_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_7} << activated_data_e_act_self_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_15 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_7 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_36 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_37 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_7 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_14 = activated_data_e_act_self_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_7 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_7 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_7_isZero = activated_data_e_act_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_7 = activated_data_e_act_self_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_7 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_58 = activated_data_e_act_self_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_15 = activated_data_e_act_self_rec_rawIn_isSpecial_7 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_7_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_7 = activated_data_e_act_self_rec_rawIn_isSpecial_7 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_7_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_7_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_28 = ~activated_data_e_act_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_30 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_7 ? activated_data_e_act_self_rec_rawIn_subnormFract_7 : activated_data_e_act_self_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_31 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_29, _activated_data_e_act_self_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_7_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_56 = activated_data_e_act_self_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_57 = activated_data_e_act_self_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_59 = {_activated_data_e_act_self_rec_T_57[2:1], _activated_data_e_act_self_rec_T_57[0] | _activated_data_e_act_self_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_60 = {activated_data_e_act_self_rec_rawIn_7_sign, _activated_data_e_act_self_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_61 = activated_data_e_act_self_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_62 = {_activated_data_e_act_self_rec_T_60, _activated_data_e_act_self_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_63 = activated_data_e_act_self_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_7 = {_activated_data_e_act_self_rec_T_62, _activated_data_e_act_self_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_out_1_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_out_bits_rawIn_exp_1 = _activated_data_e_act_muladder_6_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_out_bits_rawIn_isZero_T_1 = activated_data_e_act_out_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_out_bits_rawIn_isZero_1 = _activated_data_e_act_out_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_out_bits_rawIn_1_isZero = activated_data_e_act_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_out_bits_rawIn_isSpecial_T_1 = activated_data_e_act_out_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_out_bits_rawIn_isSpecial_1 = &_activated_data_e_act_out_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_out_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_out_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_out_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_out_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_out_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_3 = activated_data_e_act_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_out_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_out_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_out_bits_rawIn_1_isNaN = _activated_data_e_act_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_out_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_out_bits_rawIn_out_isInf_T_5 = activated_data_e_act_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_out_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_out_bits_rawIn_1_isInf = _activated_data_e_act_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_out_bits_rawIn_out_sign_T_1 = _activated_data_e_act_muladder_6_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_out_bits_rawIn_1_sign = _activated_data_e_act_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_out_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_out_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_out_bits_rawIn_1_sExp = _activated_data_e_act_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_out_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_out_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_6 = _activated_data_e_act_muladder_6_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_out_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_out_bits_rawIn_out_sig_T_5, _activated_data_e_act_out_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_out_bits_rawIn_1_sig = _activated_data_e_act_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_out_bits_isSubnormal_1 = $signed(activated_data_e_act_out_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_out_bits_denormShiftDist_T_2 = activated_data_e_act_out_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_out_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_out_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_out_bits_denormShiftDist_1 = _activated_data_e_act_out_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_out_bits_denormFract_T_2 = activated_data_e_act_out_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_out_bits_denormFract_T_3 = _activated_data_e_act_out_bits_denormFract_T_2 >> activated_data_e_act_out_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_out_bits_denormFract_1 = _activated_data_e_act_out_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_out_bits_expOut_T_6 = activated_data_e_act_out_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_out_bits_expOut_T_7 = {1'h0, _activated_data_e_act_out_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_out_bits_expOut_T_8 = _activated_data_e_act_out_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_out_bits_expOut_T_9 = activated_data_e_act_out_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_out_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_out_bits_expOut_T_10 = activated_data_e_act_out_bits_rawIn_1_isNaN | activated_data_e_act_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_out_bits_expOut_T_11 = {8{_activated_data_e_act_out_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_out_bits_expOut_1 = _activated_data_e_act_out_bits_expOut_T_9 | _activated_data_e_act_out_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_out_bits_fractOut_T_2 = activated_data_e_act_out_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_out_bits_fractOut_T_3 = activated_data_e_act_out_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_out_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_out_bits_fractOut_1 = activated_data_e_act_out_bits_isSubnormal_1 ? activated_data_e_act_out_bits_denormFract_1 : _activated_data_e_act_out_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_out_bits_hi_1 = {activated_data_e_act_out_bits_rawIn_1_sign, activated_data_e_act_out_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_out_bits_T_1 = {activated_data_e_act_out_bits_hi_1, activated_data_e_act_out_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_out_1_bits = _activated_data_e_act_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_self_rec_rawIn_sign_8 = activated_data_e_act_out_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_8_sign = activated_data_e_act_self_rec_rawIn_sign_8; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_8 = activated_data_e_act_out_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_8 = activated_data_e_act_out_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_8 = activated_data_e_act_self_rec_rawIn_expIn_8 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_8 = activated_data_e_act_self_rec_rawIn_fractIn_8 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_352 = activated_data_e_act_self_rec_rawIn_fractIn_8[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_353 = activated_data_e_act_self_rec_rawIn_fractIn_8[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_354 = activated_data_e_act_self_rec_rawIn_fractIn_8[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_355 = activated_data_e_act_self_rec_rawIn_fractIn_8[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_356 = activated_data_e_act_self_rec_rawIn_fractIn_8[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_357 = activated_data_e_act_self_rec_rawIn_fractIn_8[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_358 = activated_data_e_act_self_rec_rawIn_fractIn_8[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_359 = activated_data_e_act_self_rec_rawIn_fractIn_8[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_360 = activated_data_e_act_self_rec_rawIn_fractIn_8[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_361 = activated_data_e_act_self_rec_rawIn_fractIn_8[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_362 = activated_data_e_act_self_rec_rawIn_fractIn_8[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_363 = activated_data_e_act_self_rec_rawIn_fractIn_8[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_364 = activated_data_e_act_self_rec_rawIn_fractIn_8[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_365 = activated_data_e_act_self_rec_rawIn_fractIn_8[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_366 = activated_data_e_act_self_rec_rawIn_fractIn_8[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_367 = activated_data_e_act_self_rec_rawIn_fractIn_8[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_368 = activated_data_e_act_self_rec_rawIn_fractIn_8[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_369 = activated_data_e_act_self_rec_rawIn_fractIn_8[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_370 = activated_data_e_act_self_rec_rawIn_fractIn_8[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_371 = activated_data_e_act_self_rec_rawIn_fractIn_8[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_372 = activated_data_e_act_self_rec_rawIn_fractIn_8[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_373 = activated_data_e_act_self_rec_rawIn_fractIn_8[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_374 = activated_data_e_act_self_rec_rawIn_fractIn_8[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_375 = _activated_data_e_act_self_rec_rawIn_normDist_T_353 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_376 = _activated_data_e_act_self_rec_rawIn_normDist_T_354 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_375; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_377 = _activated_data_e_act_self_rec_rawIn_normDist_T_355 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_376; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_378 = _activated_data_e_act_self_rec_rawIn_normDist_T_356 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_377; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_379 = _activated_data_e_act_self_rec_rawIn_normDist_T_357 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_378; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_380 = _activated_data_e_act_self_rec_rawIn_normDist_T_358 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_379; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_381 = _activated_data_e_act_self_rec_rawIn_normDist_T_359 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_380; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_382 = _activated_data_e_act_self_rec_rawIn_normDist_T_360 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_381; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_383 = _activated_data_e_act_self_rec_rawIn_normDist_T_361 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_382; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_384 = _activated_data_e_act_self_rec_rawIn_normDist_T_362 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_383; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_385 = _activated_data_e_act_self_rec_rawIn_normDist_T_363 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_384; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_386 = _activated_data_e_act_self_rec_rawIn_normDist_T_364 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_385; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_387 = _activated_data_e_act_self_rec_rawIn_normDist_T_365 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_386; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_388 = _activated_data_e_act_self_rec_rawIn_normDist_T_366 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_387; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_389 = _activated_data_e_act_self_rec_rawIn_normDist_T_367 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_388; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_390 = _activated_data_e_act_self_rec_rawIn_normDist_T_368 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_389; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_391 = _activated_data_e_act_self_rec_rawIn_normDist_T_369 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_390; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_392 = _activated_data_e_act_self_rec_rawIn_normDist_T_370 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_391; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_393 = _activated_data_e_act_self_rec_rawIn_normDist_T_371 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_392; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_394 = _activated_data_e_act_self_rec_rawIn_normDist_T_372 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_393; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_395 = _activated_data_e_act_self_rec_rawIn_normDist_T_373 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_394; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_8 = _activated_data_e_act_self_rec_rawIn_normDist_T_374 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_395; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_16 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_8} << activated_data_e_act_self_rec_rawIn_normDist_8; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_17 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_16[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_8 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_17, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_40 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_8}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_41 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_8 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_40 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_8}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_42 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_8 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_43 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_42}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_44 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_41} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_43}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_8 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_44[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_16 = activated_data_e_act_self_rec_rawIn_adjustedExp_8; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_8 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_8 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_8_isZero = activated_data_e_act_self_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_8 = activated_data_e_act_self_rec_rawIn_adjustedExp_8[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_8 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_8; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_66 = activated_data_e_act_self_rec_rawIn_8_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_8_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_8_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_8_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_16 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_17 = activated_data_e_act_self_rec_rawIn_isSpecial_8 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_16; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_8_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_8 = activated_data_e_act_self_rec_rawIn_isSpecial_8 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_8_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_17 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_16}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_8_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_32 = ~activated_data_e_act_self_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_33 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_32}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_34 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_8 ? activated_data_e_act_self_rec_rawIn_subnormFract_8 : activated_data_e_act_self_rec_rawIn_fractIn_8; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_35 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_33, _activated_data_e_act_self_rec_rawIn_out_sig_T_34}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_8_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_64 = activated_data_e_act_self_rec_rawIn_8_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_65 = activated_data_e_act_self_rec_rawIn_8_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_64; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_67 = {_activated_data_e_act_self_rec_T_65[2:1], _activated_data_e_act_self_rec_T_65[0] | _activated_data_e_act_self_rec_T_66}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_68 = {activated_data_e_act_self_rec_rawIn_8_sign, _activated_data_e_act_self_rec_T_67}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_69 = activated_data_e_act_self_rec_rawIn_8_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_70 = {_activated_data_e_act_self_rec_T_68, _activated_data_e_act_self_rec_T_69}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_71 = activated_data_e_act_self_rec_rawIn_8_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_8 = {_activated_data_e_act_self_rec_T_70, _activated_data_e_act_self_rec_T_71}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_12; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_8_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_6 = _activated_data_e_act_resizer_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_6 = activated_data_e_act_result_bits_rawIn_exp_6[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_6 = _activated_data_e_act_result_bits_rawIn_isZero_T_6 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_6_isZero = activated_data_e_act_result_bits_rawIn_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_6 = activated_data_e_act_result_bits_rawIn_exp_6[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_6 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_6; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_20; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_6; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_6; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_27; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_6_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_6_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_6_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_6_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_6_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_12 = activated_data_e_act_result_bits_rawIn_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_18 = activated_data_e_act_result_bits_rawIn_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_13 = activated_data_e_act_result_bits_rawIn_isSpecial_6 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_12; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_6_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_19 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_18; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_20 = activated_data_e_act_result_bits_rawIn_isSpecial_6 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_19; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_6_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_20; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_6 = _activated_data_e_act_resizer_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_6_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_6; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_6 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_6}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_6_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_6; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_24 = ~activated_data_e_act_result_bits_rawIn_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_24}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_26 = _activated_data_e_act_resizer_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_27 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_25, _activated_data_e_act_result_bits_rawIn_out_sig_T_26}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_6_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_27; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_6 = $signed(activated_data_e_act_result_bits_rawIn_6_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_12 = activated_data_e_act_result_bits_rawIn_6_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_13 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_12}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_6 = _activated_data_e_act_result_bits_denormShiftDist_T_13[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_12 = activated_data_e_act_result_bits_rawIn_6_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_13 = _activated_data_e_act_result_bits_denormFract_T_12 >> activated_data_e_act_result_bits_denormShiftDist_6; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_6 = _activated_data_e_act_result_bits_denormFract_T_13[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_36 = activated_data_e_act_result_bits_rawIn_6_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_37 = {1'h0, _activated_data_e_act_result_bits_expOut_T_36} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_38 = _activated_data_e_act_result_bits_expOut_T_37[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_39 = activated_data_e_act_result_bits_isSubnormal_6 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_38; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_40 = activated_data_e_act_result_bits_rawIn_6_isNaN | activated_data_e_act_result_bits_rawIn_6_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_41 = {8{_activated_data_e_act_result_bits_expOut_T_40}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_6 = _activated_data_e_act_result_bits_expOut_T_39 | _activated_data_e_act_result_bits_expOut_T_41; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_12 = activated_data_e_act_result_bits_rawIn_6_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_13 = activated_data_e_act_result_bits_rawIn_6_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_12; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_6 = activated_data_e_act_result_bits_isSubnormal_6 ? activated_data_e_act_result_bits_denormFract_6 : _activated_data_e_act_result_bits_fractOut_T_13; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_6 = {activated_data_e_act_result_bits_rawIn_6_sign, activated_data_e_act_result_bits_expOut_6}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_12 = {activated_data_e_act_result_bits_hi_6, activated_data_e_act_result_bits_fractOut_6}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_8_bits = _activated_data_e_act_result_bits_T_12; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_self_rec_rawIn_9_sign = activated_data_e_act_self_rec_rawIn_sign_9; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_9 = activated_data_e_act_self_rec_rawIn_expIn_9 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_9 = activated_data_e_act_self_rec_rawIn_fractIn_9 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_396 = activated_data_e_act_self_rec_rawIn_fractIn_9[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_397 = activated_data_e_act_self_rec_rawIn_fractIn_9[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_398 = activated_data_e_act_self_rec_rawIn_fractIn_9[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_399 = activated_data_e_act_self_rec_rawIn_fractIn_9[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_400 = activated_data_e_act_self_rec_rawIn_fractIn_9[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_401 = activated_data_e_act_self_rec_rawIn_fractIn_9[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_402 = activated_data_e_act_self_rec_rawIn_fractIn_9[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_403 = activated_data_e_act_self_rec_rawIn_fractIn_9[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_404 = activated_data_e_act_self_rec_rawIn_fractIn_9[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_405 = activated_data_e_act_self_rec_rawIn_fractIn_9[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_406 = activated_data_e_act_self_rec_rawIn_fractIn_9[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_407 = activated_data_e_act_self_rec_rawIn_fractIn_9[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_408 = activated_data_e_act_self_rec_rawIn_fractIn_9[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_409 = activated_data_e_act_self_rec_rawIn_fractIn_9[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_410 = activated_data_e_act_self_rec_rawIn_fractIn_9[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_411 = activated_data_e_act_self_rec_rawIn_fractIn_9[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_412 = activated_data_e_act_self_rec_rawIn_fractIn_9[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_413 = activated_data_e_act_self_rec_rawIn_fractIn_9[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_414 = activated_data_e_act_self_rec_rawIn_fractIn_9[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_415 = activated_data_e_act_self_rec_rawIn_fractIn_9[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_416 = activated_data_e_act_self_rec_rawIn_fractIn_9[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_417 = activated_data_e_act_self_rec_rawIn_fractIn_9[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_418 = activated_data_e_act_self_rec_rawIn_fractIn_9[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_419 = _activated_data_e_act_self_rec_rawIn_normDist_T_397 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_420 = _activated_data_e_act_self_rec_rawIn_normDist_T_398 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_419; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_421 = _activated_data_e_act_self_rec_rawIn_normDist_T_399 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_420; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_422 = _activated_data_e_act_self_rec_rawIn_normDist_T_400 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_421; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_423 = _activated_data_e_act_self_rec_rawIn_normDist_T_401 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_422; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_424 = _activated_data_e_act_self_rec_rawIn_normDist_T_402 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_423; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_425 = _activated_data_e_act_self_rec_rawIn_normDist_T_403 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_424; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_426 = _activated_data_e_act_self_rec_rawIn_normDist_T_404 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_425; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_427 = _activated_data_e_act_self_rec_rawIn_normDist_T_405 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_426; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_428 = _activated_data_e_act_self_rec_rawIn_normDist_T_406 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_427; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_429 = _activated_data_e_act_self_rec_rawIn_normDist_T_407 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_428; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_430 = _activated_data_e_act_self_rec_rawIn_normDist_T_408 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_429; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_431 = _activated_data_e_act_self_rec_rawIn_normDist_T_409 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_430; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_432 = _activated_data_e_act_self_rec_rawIn_normDist_T_410 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_431; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_433 = _activated_data_e_act_self_rec_rawIn_normDist_T_411 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_432; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_434 = _activated_data_e_act_self_rec_rawIn_normDist_T_412 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_433; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_435 = _activated_data_e_act_self_rec_rawIn_normDist_T_413 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_434; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_436 = _activated_data_e_act_self_rec_rawIn_normDist_T_414 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_435; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_437 = _activated_data_e_act_self_rec_rawIn_normDist_T_415 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_436; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_438 = _activated_data_e_act_self_rec_rawIn_normDist_T_416 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_437; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_439 = _activated_data_e_act_self_rec_rawIn_normDist_T_417 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_438; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_9 = _activated_data_e_act_self_rec_rawIn_normDist_T_418 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_439; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_18 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_9} << activated_data_e_act_self_rec_rawIn_normDist_9; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_19 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_18[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_9 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_19, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_45 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_9}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_46 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_9 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_45 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_9}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_47 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_9 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_48 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_47}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_49 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_46} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_48}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_9 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_49[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_18 = activated_data_e_act_self_rec_rawIn_adjustedExp_9; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_9 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_9 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_9_isZero = activated_data_e_act_self_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_9 = activated_data_e_act_self_rec_rawIn_adjustedExp_9[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_9 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_9; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_74 = activated_data_e_act_self_rec_rawIn_9_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_9_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_9_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_9_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_18 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_19 = activated_data_e_act_self_rec_rawIn_isSpecial_9 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_18; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_9_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_9 = activated_data_e_act_self_rec_rawIn_isSpecial_9 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_9_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_19 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_18}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_9_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_36 = ~activated_data_e_act_self_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_37 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_36}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_38 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_9 ? activated_data_e_act_self_rec_rawIn_subnormFract_9 : activated_data_e_act_self_rec_rawIn_fractIn_9; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_39 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_37, _activated_data_e_act_self_rec_rawIn_out_sig_T_38}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_9_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_72 = activated_data_e_act_self_rec_rawIn_9_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_73 = activated_data_e_act_self_rec_rawIn_9_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_72; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_75 = {_activated_data_e_act_self_rec_T_73[2:1], _activated_data_e_act_self_rec_T_73[0] | _activated_data_e_act_self_rec_T_74}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_76 = {activated_data_e_act_self_rec_rawIn_9_sign, _activated_data_e_act_self_rec_T_75}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_77 = activated_data_e_act_self_rec_rawIn_9_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_78 = {_activated_data_e_act_self_rec_T_76, _activated_data_e_act_self_rec_T_77}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_79 = activated_data_e_act_self_rec_rawIn_9_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_9 = {_activated_data_e_act_self_rec_T_78, _activated_data_e_act_self_rec_T_79}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_13; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_9_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_7 = _activated_data_e_act_muladder_7_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_7 = activated_data_e_act_result_bits_rawIn_exp_7[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_7 = _activated_data_e_act_result_bits_rawIn_isZero_T_7 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_7_isZero = activated_data_e_act_result_bits_rawIn_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_7 = activated_data_e_act_result_bits_rawIn_exp_7[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_7 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_7; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_23; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_7; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_7; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_31; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_7_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_7_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_7_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_7_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_7_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_14 = activated_data_e_act_result_bits_rawIn_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_21 = activated_data_e_act_result_bits_rawIn_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_15 = activated_data_e_act_result_bits_rawIn_isSpecial_7 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_14; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_7_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_22 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_21; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_23 = activated_data_e_act_result_bits_rawIn_isSpecial_7 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_22; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_7_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_23; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_7 = _activated_data_e_act_muladder_7_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_7_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_7; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_7 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_7}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_7_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_7; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_28 = ~activated_data_e_act_result_bits_rawIn_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_28}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_30 = _activated_data_e_act_muladder_7_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_31 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_29, _activated_data_e_act_result_bits_rawIn_out_sig_T_30}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_7_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_31; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_7 = $signed(activated_data_e_act_result_bits_rawIn_7_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_14 = activated_data_e_act_result_bits_rawIn_7_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_15 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_14}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_7 = _activated_data_e_act_result_bits_denormShiftDist_T_15[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_14 = activated_data_e_act_result_bits_rawIn_7_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_15 = _activated_data_e_act_result_bits_denormFract_T_14 >> activated_data_e_act_result_bits_denormShiftDist_7; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_7 = _activated_data_e_act_result_bits_denormFract_T_15[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_42 = activated_data_e_act_result_bits_rawIn_7_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_43 = {1'h0, _activated_data_e_act_result_bits_expOut_T_42} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_44 = _activated_data_e_act_result_bits_expOut_T_43[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_45 = activated_data_e_act_result_bits_isSubnormal_7 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_44; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_46 = activated_data_e_act_result_bits_rawIn_7_isNaN | activated_data_e_act_result_bits_rawIn_7_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_47 = {8{_activated_data_e_act_result_bits_expOut_T_46}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_7 = _activated_data_e_act_result_bits_expOut_T_45 | _activated_data_e_act_result_bits_expOut_T_47; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_14 = activated_data_e_act_result_bits_rawIn_7_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_15 = activated_data_e_act_result_bits_rawIn_7_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_14; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_7 = activated_data_e_act_result_bits_isSubnormal_7 ? activated_data_e_act_result_bits_denormFract_7 : _activated_data_e_act_result_bits_fractOut_T_15; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_7 = {activated_data_e_act_result_bits_rawIn_7_sign, activated_data_e_act_result_bits_expOut_7}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_13 = {activated_data_e_act_result_bits_hi_7, activated_data_e_act_result_bits_fractOut_7}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_9_bits = _activated_data_e_act_result_bits_T_13; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_neg_q_iexp_t_sgn_1 = activated_data_e_act_result_9_bits[31]; // @[Arithmetic.scala:426:26, :432:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_sign_2 = activated_data_e_act_result_9_bits[31]; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_neg_q_iexp_neg_t_T_4 = ~activated_data_e_act_neg_q_iexp_t_sgn_1; // @[Arithmetic.scala:432:27, :433:25] wire [30:0] _activated_data_e_act_neg_q_iexp_neg_t_T_5 = activated_data_e_act_result_9_bits[30:0]; // @[Arithmetic.scala:426:26, :433:39] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_T_6 = {_activated_data_e_act_neg_q_iexp_neg_t_T_4, _activated_data_e_act_neg_q_iexp_neg_t_T_5}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_WIRE_1 = _activated_data_e_act_neg_q_iexp_neg_t_T_6; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_T_7; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_neg_q_iexp_neg_t_1_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_neg_q_iexp_neg_t_T_7 = _activated_data_e_act_neg_q_iexp_neg_t_WIRE_1; // @[Arithmetic.scala:433:65] assign activated_data_e_act_neg_q_iexp_neg_t_1_bits = _activated_data_e_act_neg_q_iexp_neg_t_T_7; // @[Arithmetic.scala:433:65] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_sign_1 = activated_data_e_act_neg_q_iexp_neg_t_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_sign = activated_data_e_act_neg_q_iexp_t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn_1 = activated_data_e_act_neg_q_iexp_neg_t_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1 = activated_data_e_act_neg_q_iexp_neg_t_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_44 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_45 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_46 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_47 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_48 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_49 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_50 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_51 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_52 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_53 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_54 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_55 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_56 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_57 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_58 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_59 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_60 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_61 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_62 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_63 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_64 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_65 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_66 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_67 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_68 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_69 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_70 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_71 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_72 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_73 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_74 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_75 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_76 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_77 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_78 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_79 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_80 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_81 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_82 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_83 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_84 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_85 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_86 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_87 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_1 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1} << activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_1 = {_activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_1 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_2 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_1 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_isZero = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_T_1 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_1 = &_activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_neg_q_iexp_t_rec_T_10 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_1 & _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_isNaN = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T_1 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_1 & activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_isInf = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_sExp = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_6 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_1 : activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_5, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_sig = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_8 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_9 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_neg_q_iexp_t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_11 = {_activated_data_e_act_neg_q_iexp_t_rec_T_9[2:1], _activated_data_e_act_neg_q_iexp_t_rec_T_9[0] | _activated_data_e_act_neg_q_iexp_t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_neg_q_iexp_t_rec_T_12 = {activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_sign, _activated_data_e_act_neg_q_iexp_t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_neg_q_iexp_t_rec_T_13 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_T_14 = {_activated_data_e_act_neg_q_iexp_t_rec_T_12, _activated_data_e_act_neg_q_iexp_t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_neg_q_iexp_t_rec_T_15 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_neg_q_iexp_t_rec_1 = {_activated_data_e_act_neg_q_iexp_t_rec_T_14, _activated_data_e_act_neg_q_iexp_t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_neg_q_iexp_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_neg_q_iexp_1_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_1 = _activated_data_e_act_neg_q_iexp_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_T_1 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_1 = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_isZero = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_T_1 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_1 = &_activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_3 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_isNaN = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_5 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_isInf = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T_1 = _activated_data_e_act_neg_q_iexp_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sign = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sExp = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_6 = _activated_data_e_act_neg_q_iexp_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_5, _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sig = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_neg_q_iexp_result_bits_isSubnormal_1 = $signed(activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_2 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_1 = _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_2 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_3 = _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_2 >> activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_neg_q_iexp_result_bits_denormFract_1 = _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_6 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_7 = {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_8 = _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_9 = activated_data_e_act_neg_q_iexp_result_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_10 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_isNaN | activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_11 = {8{_activated_data_e_act_neg_q_iexp_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_neg_q_iexp_result_bits_expOut_1 = _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_9 | _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_2 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_3 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_neg_q_iexp_result_bits_fractOut_1 = activated_data_e_act_neg_q_iexp_result_bits_isSubnormal_1 ? activated_data_e_act_neg_q_iexp_result_bits_denormFract_1 : _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_neg_q_iexp_result_bits_hi_1 = {activated_data_e_act_neg_q_iexp_result_bits_rawIn_1_sign, activated_data_e_act_neg_q_iexp_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_neg_q_iexp_result_bits_T_1 = {activated_data_e_act_neg_q_iexp_result_bits_hi_1, activated_data_e_act_neg_q_iexp_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_neg_q_iexp_1_bits = _activated_data_e_act_neg_q_iexp_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_z_iexp_t_rec_rawIn_1_sign = activated_data_e_act_z_iexp_t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_z_iexp_t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_44 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_45 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_46 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_47 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_48 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_49 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_50 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_51 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_52 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_53 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_54 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_55 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_56 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_57 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_58 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_59 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_60 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_61 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_62 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_63 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_64 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_65 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_66 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_67 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_68 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_69 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_70 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_71 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_72 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_73 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_74 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_75 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_76 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_77 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_78 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_79 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_80 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_81 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_82 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_83 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_84 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_85 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_86 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_87 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_z_iexp_t_rec_rawIn_normDist_1 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1} << activated_data_e_act_z_iexp_t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_1 = {_activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_z_iexp_t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_z_iexp_t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_1 = _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_2 = activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZero_1 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_z_iexp_t_rec_rawIn_1_isZero = activated_data_e_act_z_iexp_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_T_1 = activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_1 = &_activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_z_iexp_t_rec_T_10 = activated_data_e_act_z_iexp_t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_z_iexp_t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_z_iexp_t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_z_iexp_t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_1 & _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_z_iexp_t_rec_rawIn_1_isNaN = _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T_1 = activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_1 & activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_z_iexp_t_rec_rawIn_1_isInf = _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_z_iexp_t_rec_rawIn_1_sExp = _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_z_iexp_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_6 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_1 : activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_5, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_z_iexp_t_rec_rawIn_1_sig = _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_8 = activated_data_e_act_z_iexp_t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_9 = activated_data_e_act_z_iexp_t_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_z_iexp_t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_11 = {_activated_data_e_act_z_iexp_t_rec_T_9[2:1], _activated_data_e_act_z_iexp_t_rec_T_9[0] | _activated_data_e_act_z_iexp_t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_z_iexp_t_rec_T_12 = {activated_data_e_act_z_iexp_t_rec_rawIn_1_sign, _activated_data_e_act_z_iexp_t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_z_iexp_t_rec_T_13 = activated_data_e_act_z_iexp_t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_z_iexp_t_rec_T_14 = {_activated_data_e_act_z_iexp_t_rec_T_12, _activated_data_e_act_z_iexp_t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_z_iexp_t_rec_T_15 = activated_data_e_act_z_iexp_t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_z_iexp_t_rec_1 = {_activated_data_e_act_z_iexp_t_rec_T_14, _activated_data_e_act_z_iexp_t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_z_iexp_self_rec_rawIn_sign_1 = activated_data_e_act_neg_q_iexp_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_z_iexp_self_rec_rawIn_1_sign = activated_data_e_act_z_iexp_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_z_iexp_self_rec_rawIn_expIn_1 = activated_data_e_act_neg_q_iexp_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1 = activated_data_e_act_neg_q_iexp_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_z_iexp_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_44 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_45 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_46 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_47 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_48 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_49 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_50 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_51 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_52 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_53 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_54 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_55 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_56 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_57 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_58 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_59 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_60 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_61 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_62 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_63 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_64 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_65 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_66 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_67 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_68 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_69 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_70 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_71 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_72 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_73 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_74 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_75 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_76 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_77 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_78 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_79 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_80 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_81 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_82 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_83 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_84 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_85 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_86 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_87 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_z_iexp_self_rec_rawIn_normDist_1 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1} << activated_data_e_act_z_iexp_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_1 = {_activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_z_iexp_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_z_iexp_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_1 = _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_2 = activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZero_1 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_z_iexp_self_rec_rawIn_1_isZero = activated_data_e_act_z_iexp_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_T_1 = activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_1 = &_activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_z_iexp_self_rec_T_10 = activated_data_e_act_z_iexp_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_z_iexp_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_z_iexp_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_z_iexp_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_1 & _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_z_iexp_self_rec_rawIn_1_isNaN = _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T_1 = activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_1 & activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_z_iexp_self_rec_rawIn_1_isInf = _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_z_iexp_self_rec_rawIn_1_sExp = _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_z_iexp_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_6 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_1 : activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_5, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_z_iexp_self_rec_rawIn_1_sig = _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_8 = activated_data_e_act_z_iexp_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_9 = activated_data_e_act_z_iexp_self_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_z_iexp_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_11 = {_activated_data_e_act_z_iexp_self_rec_T_9[2:1], _activated_data_e_act_z_iexp_self_rec_T_9[0] | _activated_data_e_act_z_iexp_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_z_iexp_self_rec_T_12 = {activated_data_e_act_z_iexp_self_rec_rawIn_1_sign, _activated_data_e_act_z_iexp_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_z_iexp_self_rec_T_13 = activated_data_e_act_z_iexp_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_z_iexp_self_rec_T_14 = {_activated_data_e_act_z_iexp_self_rec_T_12, _activated_data_e_act_z_iexp_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_z_iexp_self_rec_T_15 = activated_data_e_act_z_iexp_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_z_iexp_self_rec_1 = {_activated_data_e_act_z_iexp_self_rec_T_14, _activated_data_e_act_z_iexp_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_z_iexp_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_z_iexp_out_1_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_z_iexp_out_bits_rawIn_exp_1 = _activated_data_e_act_z_iexp_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_z_iexp_out_bits_rawIn_isZero_T_1 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_z_iexp_out_bits_rawIn_isZero_1 = _activated_data_e_act_z_iexp_out_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_z_iexp_out_bits_rawIn_1_isZero = activated_data_e_act_z_iexp_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_T_1 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_1 = &_activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_z_iexp_out_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_z_iexp_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_z_iexp_out_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_z_iexp_out_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_z_iexp_out_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_3 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_z_iexp_out_bits_rawIn_1_isNaN = _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_5 = activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_z_iexp_out_bits_rawIn_1_isInf = _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T_1 = _activated_data_e_act_z_iexp_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_z_iexp_out_bits_rawIn_1_sign = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_z_iexp_out_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_z_iexp_out_bits_rawIn_1_sExp = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_z_iexp_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_6 = _activated_data_e_act_z_iexp_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_5, _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_z_iexp_out_bits_rawIn_1_sig = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_z_iexp_out_bits_isSubnormal_1 = $signed(activated_data_e_act_z_iexp_out_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_2 = activated_data_e_act_z_iexp_out_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_z_iexp_out_bits_denormShiftDist_1 = _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_z_iexp_out_bits_denormFract_T_2 = activated_data_e_act_z_iexp_out_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_z_iexp_out_bits_denormFract_T_3 = _activated_data_e_act_z_iexp_out_bits_denormFract_T_2 >> activated_data_e_act_z_iexp_out_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_z_iexp_out_bits_denormFract_1 = _activated_data_e_act_z_iexp_out_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_6 = activated_data_e_act_z_iexp_out_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_7 = {1'h0, _activated_data_e_act_z_iexp_out_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_8 = _activated_data_e_act_z_iexp_out_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_9 = activated_data_e_act_z_iexp_out_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_z_iexp_out_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_z_iexp_out_bits_expOut_T_10 = activated_data_e_act_z_iexp_out_bits_rawIn_1_isNaN | activated_data_e_act_z_iexp_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_11 = {8{_activated_data_e_act_z_iexp_out_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_z_iexp_out_bits_expOut_1 = _activated_data_e_act_z_iexp_out_bits_expOut_T_9 | _activated_data_e_act_z_iexp_out_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_z_iexp_out_bits_fractOut_T_2 = activated_data_e_act_z_iexp_out_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_z_iexp_out_bits_fractOut_T_3 = activated_data_e_act_z_iexp_out_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_z_iexp_out_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_z_iexp_out_bits_fractOut_1 = activated_data_e_act_z_iexp_out_bits_isSubnormal_1 ? activated_data_e_act_z_iexp_out_bits_denormFract_1 : _activated_data_e_act_z_iexp_out_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_z_iexp_out_bits_hi_1 = {activated_data_e_act_z_iexp_out_bits_rawIn_1_sign, activated_data_e_act_z_iexp_out_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_z_iexp_out_bits_T_1 = {activated_data_e_act_z_iexp_out_bits_hi_1, activated_data_e_act_z_iexp_out_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_z_iexp_out_1_bits = _activated_data_e_act_z_iexp_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [15:0] _activated_data_e_act_z_iexp_T_2 = activated_data_e_act_z_iexp_out_1_bits[31:16]; // @[Arithmetic.scala:350:23] wire [31:0] _activated_data_e_act_z_iexp_T_3; // @[AccumulatorScale.scala:398:67] wire [31:0] activated_data_e_act_z_iexp_1_bits; // @[AccumulatorScale.scala:398:67] assign _activated_data_e_act_z_iexp_T_3 = _activated_data_e_act_z_iexp_WIRE_1; // @[AccumulatorScale.scala:398:67] assign _activated_data_e_act_z_iexp_WIRE_1 = {16'h0, _activated_data_e_act_z_iexp_T_2}; // @[AccumulatorScale.scala:398:{54,67}] assign activated_data_e_act_z_iexp_1_bits = _activated_data_e_act_z_iexp_T_3; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_43_bits; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_1_bits; // @[AccumulatorScale.scala:399:32] wire _activated_data_e_act_z_iexp_saturated_T_22 = activated_data_e_act_z_iexp_1_bits[5]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_23 = activated_data_e_act_z_iexp_1_bits[6]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_24 = activated_data_e_act_z_iexp_1_bits[7]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_25 = activated_data_e_act_z_iexp_1_bits[8]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_26 = activated_data_e_act_z_iexp_1_bits[9]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_27 = activated_data_e_act_z_iexp_1_bits[10]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_28 = activated_data_e_act_z_iexp_1_bits[11]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_29 = activated_data_e_act_z_iexp_1_bits[12]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_30 = activated_data_e_act_z_iexp_1_bits[13]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_31 = activated_data_e_act_z_iexp_1_bits[14]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_32 = activated_data_e_act_z_iexp_1_bits[15]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_33 = _activated_data_e_act_z_iexp_saturated_T_22 | _activated_data_e_act_z_iexp_saturated_T_23; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_34 = _activated_data_e_act_z_iexp_saturated_T_33 | _activated_data_e_act_z_iexp_saturated_T_24; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_35 = _activated_data_e_act_z_iexp_saturated_T_34 | _activated_data_e_act_z_iexp_saturated_T_25; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_36 = _activated_data_e_act_z_iexp_saturated_T_35 | _activated_data_e_act_z_iexp_saturated_T_26; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_37 = _activated_data_e_act_z_iexp_saturated_T_36 | _activated_data_e_act_z_iexp_saturated_T_27; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_38 = _activated_data_e_act_z_iexp_saturated_T_37 | _activated_data_e_act_z_iexp_saturated_T_28; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_39 = _activated_data_e_act_z_iexp_saturated_T_38 | _activated_data_e_act_z_iexp_saturated_T_29; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_40 = _activated_data_e_act_z_iexp_saturated_T_39 | _activated_data_e_act_z_iexp_saturated_T_30; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_41 = _activated_data_e_act_z_iexp_saturated_T_40 | _activated_data_e_act_z_iexp_saturated_T_31; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_42 = _activated_data_e_act_z_iexp_saturated_T_41 | _activated_data_e_act_z_iexp_saturated_T_32; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_43_bits = _activated_data_e_act_z_iexp_saturated_T_42 ? 32'h20 : activated_data_e_act_z_iexp_1_bits; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_1_bits = _activated_data_e_act_z_iexp_saturated_T_43_bits; // @[AccumulatorScale.scala:399:32, :400:28] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_sign_1 = activated_data_e_act_z_iexp_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_1_sign = activated_data_e_act_qp_iexp_m1_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn_1 = activated_data_e_act_z_iexp_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1 = activated_data_e_act_z_iexp_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_44 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_45 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_46 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_47 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_48 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_49 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_50 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_51 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_52 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_53 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_54 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_55 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_56 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_57 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_58 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_59 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_60 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_61 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_62 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_63 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_64 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_65 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_66 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_67 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_68 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_69 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_70 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_71 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_72 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_73 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_74 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_75 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_76 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_77 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_78 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_79 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_80 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_81 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_82 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_83 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_84 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_85 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_86 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_87 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_1 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1} << activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_1 = {_activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_1 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_2 = activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_1 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_1_isZero = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_T_1 = activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_1 = &_activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_m1_rec_T_10 = activated_data_e_act_qp_iexp_m1_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_1 & _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_1_isNaN = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T_1 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_1 & activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_1_isInf = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_1_sExp = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_6 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_1 : activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_5, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_1_sig = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_8 = activated_data_e_act_qp_iexp_m1_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_9 = activated_data_e_act_qp_iexp_m1_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_m1_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_11 = {_activated_data_e_act_qp_iexp_m1_rec_T_9[2:1], _activated_data_e_act_qp_iexp_m1_rec_T_9[0] | _activated_data_e_act_qp_iexp_m1_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_m1_rec_T_12 = {activated_data_e_act_qp_iexp_m1_rec_rawIn_1_sign, _activated_data_e_act_qp_iexp_m1_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_m1_rec_T_13 = activated_data_e_act_qp_iexp_m1_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_T_14 = {_activated_data_e_act_qp_iexp_m1_rec_T_12, _activated_data_e_act_qp_iexp_m1_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_m1_rec_T_15 = activated_data_e_act_qp_iexp_m1_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_m1_rec_1 = {_activated_data_e_act_qp_iexp_m1_rec_T_14, _activated_data_e_act_qp_iexp_m1_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_1_sign = activated_data_e_act_qp_iexp_m2_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_44 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_45 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_46 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_47 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_48 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_49 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_50 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_51 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_52 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_53 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_54 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_55 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_56 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_57 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_58 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_59 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_60 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_61 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_62 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_63 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_64 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_65 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_66 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_67 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_68 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_69 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_70 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_71 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_72 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_73 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_74 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_75 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_76 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_77 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_78 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_79 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_80 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_81 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_82 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_83 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_84 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_85 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_86 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_87 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_1 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1} << activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_1 = {_activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_1 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_2 = activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_1 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_1_isZero = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_T_1 = activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_1 = &_activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_m2_rec_T_10 = activated_data_e_act_qp_iexp_m2_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_1 & _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_1_isNaN = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T_1 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_1 & activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_1_isInf = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_1_sExp = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_6 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_1 : activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_5, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_1_sig = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_8 = activated_data_e_act_qp_iexp_m2_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_9 = activated_data_e_act_qp_iexp_m2_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_m2_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_11 = {_activated_data_e_act_qp_iexp_m2_rec_T_9[2:1], _activated_data_e_act_qp_iexp_m2_rec_T_9[0] | _activated_data_e_act_qp_iexp_m2_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_m2_rec_T_12 = {activated_data_e_act_qp_iexp_m2_rec_rawIn_1_sign, _activated_data_e_act_qp_iexp_m2_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_m2_rec_T_13 = activated_data_e_act_qp_iexp_m2_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_T_14 = {_activated_data_e_act_qp_iexp_m2_rec_T_12, _activated_data_e_act_qp_iexp_m2_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_m2_rec_T_15 = activated_data_e_act_qp_iexp_m2_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_m2_rec_1 = {_activated_data_e_act_qp_iexp_m2_rec_T_14, _activated_data_e_act_qp_iexp_m2_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_qp_iexp_self_rec_rawIn_2_sign = activated_data_e_act_qp_iexp_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_2 = activated_data_e_act_result_9_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2 = activated_data_e_act_result_9_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_88 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_89 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_90 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_91 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_92 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_93 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_94 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_95 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_96 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_97 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_98 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_99 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_100 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_101 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_102 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_103 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_104 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_105 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_106 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_107 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_108 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_109 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_110 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_111 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_112 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_113 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_114 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_115 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_116 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_117 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_118 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_119 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_120 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_121 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_122 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_123 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_124 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_125 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_126 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_127 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_128 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_129 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_130 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_131 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_2 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2} << activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_2 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_2 = _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_4 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_2 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_2_isZero = activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_2 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_2 = &_activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_self_rec_T_18 = activated_data_e_act_qp_iexp_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_2 & _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_2_isNaN = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_2 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_2 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_self_rec_rawIn_2_isInf = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_2_sExp = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_10 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_2 : activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_9, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_2_sig = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_16 = activated_data_e_act_qp_iexp_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_17 = activated_data_e_act_qp_iexp_self_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_19 = {_activated_data_e_act_qp_iexp_self_rec_T_17[2:1], _activated_data_e_act_qp_iexp_self_rec_T_17[0] | _activated_data_e_act_qp_iexp_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_self_rec_T_20 = {activated_data_e_act_qp_iexp_self_rec_rawIn_2_sign, _activated_data_e_act_qp_iexp_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_self_rec_T_21 = activated_data_e_act_qp_iexp_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_T_22 = {_activated_data_e_act_qp_iexp_self_rec_T_20, _activated_data_e_act_qp_iexp_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_T_23 = activated_data_e_act_qp_iexp_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_self_rec_2 = {_activated_data_e_act_qp_iexp_self_rec_T_22, _activated_data_e_act_qp_iexp_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_qp_iexp_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_qp_iexp_out_1_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_qp_iexp_out_bits_rawIn_exp_1 = _activated_data_e_act_qp_iexp_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_T_1 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_1 = _activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_qp_iexp_out_bits_rawIn_1_isZero = activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_T_1 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_1 = &_activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_qp_iexp_out_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_out_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_qp_iexp_out_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_qp_iexp_out_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_3 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_1_isNaN = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_5 = activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_1_isInf = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T_1 = _activated_data_e_act_qp_iexp_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_qp_iexp_out_bits_rawIn_1_sign = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_qp_iexp_out_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_qp_iexp_out_bits_rawIn_1_sExp = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_6 = _activated_data_e_act_qp_iexp_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_5, _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_1_sig = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_qp_iexp_out_bits_isSubnormal_1 = $signed(activated_data_e_act_qp_iexp_out_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_2 = activated_data_e_act_qp_iexp_out_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_qp_iexp_out_bits_denormShiftDist_1 = _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_qp_iexp_out_bits_denormFract_T_2 = activated_data_e_act_qp_iexp_out_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_qp_iexp_out_bits_denormFract_T_3 = _activated_data_e_act_qp_iexp_out_bits_denormFract_T_2 >> activated_data_e_act_qp_iexp_out_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_qp_iexp_out_bits_denormFract_1 = _activated_data_e_act_qp_iexp_out_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_6 = activated_data_e_act_qp_iexp_out_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_7 = {1'h0, _activated_data_e_act_qp_iexp_out_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_8 = _activated_data_e_act_qp_iexp_out_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_9 = activated_data_e_act_qp_iexp_out_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_qp_iexp_out_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_qp_iexp_out_bits_expOut_T_10 = activated_data_e_act_qp_iexp_out_bits_rawIn_1_isNaN | activated_data_e_act_qp_iexp_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_11 = {8{_activated_data_e_act_qp_iexp_out_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_qp_iexp_out_bits_expOut_1 = _activated_data_e_act_qp_iexp_out_bits_expOut_T_9 | _activated_data_e_act_qp_iexp_out_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_fractOut_T_2 = activated_data_e_act_qp_iexp_out_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_fractOut_T_3 = activated_data_e_act_qp_iexp_out_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_qp_iexp_out_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_qp_iexp_out_bits_fractOut_1 = activated_data_e_act_qp_iexp_out_bits_isSubnormal_1 ? activated_data_e_act_qp_iexp_out_bits_denormFract_1 : _activated_data_e_act_qp_iexp_out_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_qp_iexp_out_bits_hi_1 = {activated_data_e_act_qp_iexp_out_bits_rawIn_1_sign, activated_data_e_act_qp_iexp_out_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_qp_iexp_out_bits_T_1 = {activated_data_e_act_qp_iexp_out_bits_hi_1, activated_data_e_act_qp_iexp_out_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_qp_iexp_out_1_bits = _activated_data_e_act_qp_iexp_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_qp_iexp_self_rec_rawIn_sign_3 = activated_data_e_act_qp_iexp_out_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_self_rec_rawIn_3_sign = activated_data_e_act_qp_iexp_self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_3 = activated_data_e_act_qp_iexp_out_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3 = activated_data_e_act_qp_iexp_out_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_132 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_133 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_134 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_135 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_136 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_137 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_138 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_139 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_140 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_141 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_142 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_143 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_144 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_145 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_146 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_147 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_148 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_149 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_150 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_151 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_152 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_153 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_154 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_155 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_156 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_157 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_158 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_159 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_160 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_161 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_162 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_163 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_164 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_165 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_166 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_167 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_168 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_169 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_170 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_171 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_172 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_173 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_174 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_175 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_3 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3} << activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_3 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_3 = _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_6 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_3 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_3_isZero = activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_3 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_3 = &_activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_self_rec_T_26 = activated_data_e_act_qp_iexp_self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_3 & _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_3_isNaN = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_3 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_3 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_self_rec_rawIn_3_isInf = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_3_sExp = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_14 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_3 : activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_13, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_3_sig = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_24 = activated_data_e_act_qp_iexp_self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_25 = activated_data_e_act_qp_iexp_self_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_27 = {_activated_data_e_act_qp_iexp_self_rec_T_25[2:1], _activated_data_e_act_qp_iexp_self_rec_T_25[0] | _activated_data_e_act_qp_iexp_self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_self_rec_T_28 = {activated_data_e_act_qp_iexp_self_rec_rawIn_3_sign, _activated_data_e_act_qp_iexp_self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_self_rec_T_29 = activated_data_e_act_qp_iexp_self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_T_30 = {_activated_data_e_act_qp_iexp_self_rec_T_28, _activated_data_e_act_qp_iexp_self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_T_31 = activated_data_e_act_qp_iexp_self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_self_rec_3 = {_activated_data_e_act_qp_iexp_self_rec_T_30, _activated_data_e_act_qp_iexp_self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_qp_iexp_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_qp_iexp_1_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_qp_iexp_result_bits_rawIn_exp_1 = _activated_data_e_act_qp_iexp_resizer_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_T_1 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_1 = _activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_qp_iexp_result_bits_rawIn_1_isZero = activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_T_1 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_1 = &_activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_qp_iexp_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_qp_iexp_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_qp_iexp_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_3 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_1_isNaN = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_5 = activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_1 & _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_1_isInf = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T_1 = _activated_data_e_act_qp_iexp_resizer_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_qp_iexp_result_bits_rawIn_1_sign = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_qp_iexp_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_qp_iexp_result_bits_rawIn_1_sExp = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_6 = _activated_data_e_act_qp_iexp_resizer_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_5, _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_1_sig = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_qp_iexp_result_bits_isSubnormal_1 = $signed(activated_data_e_act_qp_iexp_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_2 = activated_data_e_act_qp_iexp_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_qp_iexp_result_bits_denormShiftDist_1 = _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_qp_iexp_result_bits_denormFract_T_2 = activated_data_e_act_qp_iexp_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_qp_iexp_result_bits_denormFract_T_3 = _activated_data_e_act_qp_iexp_result_bits_denormFract_T_2 >> activated_data_e_act_qp_iexp_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_qp_iexp_result_bits_denormFract_1 = _activated_data_e_act_qp_iexp_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_6 = activated_data_e_act_qp_iexp_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_7 = {1'h0, _activated_data_e_act_qp_iexp_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_8 = _activated_data_e_act_qp_iexp_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_9 = activated_data_e_act_qp_iexp_result_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_qp_iexp_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_qp_iexp_result_bits_expOut_T_10 = activated_data_e_act_qp_iexp_result_bits_rawIn_1_isNaN | activated_data_e_act_qp_iexp_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_11 = {8{_activated_data_e_act_qp_iexp_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_qp_iexp_result_bits_expOut_1 = _activated_data_e_act_qp_iexp_result_bits_expOut_T_9 | _activated_data_e_act_qp_iexp_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_fractOut_T_2 = activated_data_e_act_qp_iexp_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_fractOut_T_3 = activated_data_e_act_qp_iexp_result_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_qp_iexp_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_qp_iexp_result_bits_fractOut_1 = activated_data_e_act_qp_iexp_result_bits_isSubnormal_1 ? activated_data_e_act_qp_iexp_result_bits_denormFract_1 : _activated_data_e_act_qp_iexp_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_qp_iexp_result_bits_hi_1 = {activated_data_e_act_qp_iexp_result_bits_rawIn_1_sign, activated_data_e_act_qp_iexp_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_qp_iexp_result_bits_T_1 = {activated_data_e_act_qp_iexp_result_bits_hi_1, activated_data_e_act_qp_iexp_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_qp_iexp_1_bits = _activated_data_e_act_qp_iexp_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_sign = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_88 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_89 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_90 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_91 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_92 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_93 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_94 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_95 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_96 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_97 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_98 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_99 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_100 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_101 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_102 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_103 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_104 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_105 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_106 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_107 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_108 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_109 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_110 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_2 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2} << activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_2 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_isZero = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_t_rec_T_18 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_isNaN = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_2 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_isInf = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_sExp = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_2 : activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_sig = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_16 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_17 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_19 = {_activated_data_e_act_q_poly_iexp_t_rec_T_17[2:1], _activated_data_e_act_q_poly_iexp_t_rec_T_17[0] | _activated_data_e_act_q_poly_iexp_t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_t_rec_T_20 = {activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_sign, _activated_data_e_act_q_poly_iexp_t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_t_rec_T_21 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_T_22 = {_activated_data_e_act_q_poly_iexp_t_rec_T_20, _activated_data_e_act_q_poly_iexp_t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_T_23 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_t_rec_2 = {_activated_data_e_act_q_poly_iexp_t_rec_T_22, _activated_data_e_act_q_poly_iexp_t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_4 = activated_data_e_act_qp_iexp_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_5 = activated_data_e_act_qp_iexp_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_4 = activated_data_e_act_qp_iexp_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_5 = activated_data_e_act_qp_iexp_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4 = activated_data_e_act_qp_iexp_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5 = activated_data_e_act_qp_iexp_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_176 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_177 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_178 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_179 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_180 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_181 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_182 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_183 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_184 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_185 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_186 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_187 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_188 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_189 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_190 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_191 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_192 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_193 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_194 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_195 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_196 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_197 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_198 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_199 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_200 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_201 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_202 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_203 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_204 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_205 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_206 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_207 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_208 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_209 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_210 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_211 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_212 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_213 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_214 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_215 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_216 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_217 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_218 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_219 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_4 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_4 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_4 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_8 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_4 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_4 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_4 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_34 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_4 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_4 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_4 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_18 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_4 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_17, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_32 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_33 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_35 = {_activated_data_e_act_q_poly_iexp_self_rec_T_33[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_33[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_36 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_37 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_38 = {_activated_data_e_act_q_poly_iexp_self_rec_T_36, _activated_data_e_act_q_poly_iexp_self_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_39 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_4 = {_activated_data_e_act_q_poly_iexp_self_rec_T_38, _activated_data_e_act_q_poly_iexp_self_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_result_2_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_3 = _activated_data_e_act_q_poly_iexp_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_3 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_3 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_9 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_11 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_3 = _activated_data_e_act_q_poly_iexp_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_14 = _activated_data_e_act_q_poly_iexp_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_3 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_6 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_3 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_6 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_7 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_6 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_3 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_18 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_19 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_20 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_21 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_22 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_23 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_3 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_21 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_6 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_7 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_3 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_3 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_3 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_3 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_3_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_3 = {activated_data_e_act_q_poly_iexp_result_bits_hi_3, activated_data_e_act_q_poly_iexp_result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_result_2_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_sign = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_132 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_133 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_134 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_135 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_136 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_137 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_138 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_139 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_140 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_141 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_142 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_143 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_144 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_145 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_146 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_147 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_148 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_149 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_150 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_151 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_152 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_153 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_154 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_3 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3} << activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_3 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_isZero = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_t_rec_T_26 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_isNaN = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_3 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_isInf = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_sExp = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_3 : activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_sig = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_24 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_25 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_27 = {_activated_data_e_act_q_poly_iexp_t_rec_T_25[2:1], _activated_data_e_act_q_poly_iexp_t_rec_T_25[0] | _activated_data_e_act_q_poly_iexp_t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_t_rec_T_28 = {activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_sign, _activated_data_e_act_q_poly_iexp_t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_t_rec_T_29 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_T_30 = {_activated_data_e_act_q_poly_iexp_t_rec_T_28, _activated_data_e_act_q_poly_iexp_t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_T_31 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_t_rec_3 = {_activated_data_e_act_q_poly_iexp_t_rec_T_30, _activated_data_e_act_q_poly_iexp_t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_5 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_5 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_220 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_221 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_222 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_223 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_224 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_225 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_226 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_227 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_228 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_229 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_230 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_231 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_232 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_233 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_234 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_235 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_236 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_237 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_238 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_239 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_240 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_241 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_242 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_243 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_244 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_245 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_246 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_247 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_248 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_249 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_250 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_251 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_252 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_253 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_254 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_255 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_256 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_257 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_258 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_259 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_260 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_261 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_262 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_263 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_5 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_11 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_5 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_26 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_27 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_5 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_10 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_5 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_5 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_5 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_5 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_42 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_11 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_5 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_5 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_5 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_20 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_22 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_5 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_5 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_23 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_21, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_40 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_41 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_43 = {_activated_data_e_act_q_poly_iexp_self_rec_T_41[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_41[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_44 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_45 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_46 = {_activated_data_e_act_q_poly_iexp_self_rec_T_44, _activated_data_e_act_q_poly_iexp_self_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_47 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_5 = {_activated_data_e_act_q_poly_iexp_self_rec_T_46, _activated_data_e_act_q_poly_iexp_self_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_4; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_result_3_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_4 = _activated_data_e_act_q_poly_iexp_muladder_4_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_4 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_4[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_4 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_4 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_4 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_4[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_4 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_4; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_14; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_4; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_4; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_19; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_8 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_12 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_9 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_4 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_8; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_13 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_12; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_14 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_4 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_13; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_14; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_4 = _activated_data_e_act_q_poly_iexp_muladder_4_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_4; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_4 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_4}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_4; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_16 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_16}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_18 = _activated_data_e_act_q_poly_iexp_muladder_4_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_19 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_17, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_18}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_19; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_4 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_8 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_9 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_8}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_4 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_9[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_8 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_9 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_8 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_4; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_4 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_9[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_24 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_25 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_24} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_26 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_25[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_27 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_4 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_26; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_28 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_29 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_28}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_4 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_27 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_29; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_8 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_9 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_8; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_4 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_4 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_4 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_9; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_4 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_4_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_4}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_4 = {activated_data_e_act_q_poly_iexp_result_bits_hi_4, activated_data_e_act_q_poly_iexp_result_bits_fractOut_4}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_result_3_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_4; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sign_1 = activated_data_e_act_q_poly_iexp_result_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_sign = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn_1 = activated_data_e_act_q_poly_iexp_result_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1 = activated_data_e_act_q_poly_iexp_result_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_44 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_45 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_46 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_47 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_48 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_49 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_50 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_51 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_52 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_53 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_54 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_55 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_56 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_57 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_58 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_59 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_60 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_61 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_62 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_63 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_64 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_65 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_66 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_1 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1} << activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_1 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_isZero = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_m1_rec_T_10 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_isNaN = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_1 & activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_isInf = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_sExp = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_1 : activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_sig = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_8 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_9 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_m1_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_11 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_9[2:1], _activated_data_e_act_q_poly_iexp_m1_rec_T_9[0] | _activated_data_e_act_q_poly_iexp_m1_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_12 = {activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_sign, _activated_data_e_act_q_poly_iexp_m1_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_13 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_14 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_12, _activated_data_e_act_q_poly_iexp_m1_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_15 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_m1_rec_1 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_14, _activated_data_e_act_q_poly_iexp_m1_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sign_1 = activated_data_e_act_q_poly_iexp_result_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_sign = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn_1 = activated_data_e_act_q_poly_iexp_result_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1 = activated_data_e_act_q_poly_iexp_result_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_1 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_1 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_44 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_45 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_46 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_47 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_48 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_49 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_50 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_51 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_52 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_53 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_54 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_55 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_56 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_57 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_58 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_59 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_60 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_61 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_62 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_63 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_64 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_65 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_66 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_67 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_68 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_69 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_70 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_71 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_72 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_73 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_74 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_75 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_76 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_77 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_78 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_79 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_80 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_81 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_82 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_83 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_84 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_85 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_86 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_87 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_1 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1} << activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_3 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_1 = {_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_6 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_7 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_1 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_2 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_1 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_1 & activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_isZero = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_m2_rec_T_10 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_isNaN = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T_1 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_1 & activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_isInf = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_sExp = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_6 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_1 ? activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_1 : activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_sig = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_8 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_9 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_m2_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_11 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_9[2:1], _activated_data_e_act_q_poly_iexp_m2_rec_T_9[0] | _activated_data_e_act_q_poly_iexp_m2_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_12 = {activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_sign, _activated_data_e_act_q_poly_iexp_m2_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_13 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_14 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_12, _activated_data_e_act_q_poly_iexp_m2_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_15 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_m2_rec_1 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_14, _activated_data_e_act_q_poly_iexp_m2_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_264 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_265 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_266 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_267 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_268 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_269 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_270 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_271 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_272 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_273 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_274 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_275 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_276 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_277 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_278 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_279 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_280 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_281 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_282 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_283 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_284 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_285 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_286 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_287 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_288 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_289 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_290 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_291 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_292 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_293 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_294 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_295 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_296 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_297 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_298 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_299 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_300 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_301 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_302 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_303 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_304 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_305 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_306 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_307 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_6 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_6 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_6 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_12 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_6 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_6 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_6 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_50 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_6 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_6 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_6 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_26 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_6 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_25, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_48 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_49 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_51 = {_activated_data_e_act_q_poly_iexp_self_rec_T_49[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_49[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_52 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_53 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_54 = {_activated_data_e_act_q_poly_iexp_self_rec_T_52, _activated_data_e_act_q_poly_iexp_self_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_55 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_6 = {_activated_data_e_act_q_poly_iexp_self_rec_T_54, _activated_data_e_act_q_poly_iexp_self_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_out_1_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_1 = _activated_data_e_act_q_poly_iexp_muladder_5_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_T_1 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_1 = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_isZero = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_T_1 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_1 = &_activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_2 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_3 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_isNaN = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_5 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_1 & _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_isInf = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T_1 = _activated_data_e_act_q_poly_iexp_muladder_5_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sign = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sExp = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_4 = ~activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_6 = _activated_data_e_act_q_poly_iexp_muladder_5_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_7 = {_activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_5, _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sig = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_out_bits_isSubnormal_1 = $signed(activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_2 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_1 = _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_2 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_3 = _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_2 >> activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_out_bits_denormFract_1 = _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_6 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_7 = {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_8 = _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_9 = activated_data_e_act_q_poly_iexp_out_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_10 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_isNaN | activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_11 = {8{_activated_data_e_act_q_poly_iexp_out_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_out_bits_expOut_1 = _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_9 | _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_2 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_3 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_out_bits_fractOut_1 = activated_data_e_act_q_poly_iexp_out_bits_isSubnormal_1 ? activated_data_e_act_q_poly_iexp_out_bits_denormFract_1 : _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_out_bits_hi_1 = {activated_data_e_act_q_poly_iexp_out_bits_rawIn_1_sign, activated_data_e_act_q_poly_iexp_out_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_out_bits_T_1 = {activated_data_e_act_q_poly_iexp_out_bits_hi_1, activated_data_e_act_q_poly_iexp_out_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_out_1_bits = _activated_data_e_act_q_poly_iexp_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_7 = activated_data_e_act_q_poly_iexp_out_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_7 = activated_data_e_act_q_poly_iexp_out_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7 = activated_data_e_act_q_poly_iexp_out_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_7 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_7 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_308 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_309 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_310 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_311 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_312 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_313 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_314 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_315 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_316 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_317 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_318 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_319 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_320 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_321 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_322 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_323 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_324 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_325 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_326 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_327 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_328 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_329 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_330 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_331 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_332 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_333 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_334 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_335 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_336 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_337 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_338 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_339 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_340 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_341 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_342 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_343 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_344 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_345 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_346 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_347 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_348 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_349 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_350 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_351 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_7 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_15 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_7 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_36 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_37 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_7 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_14 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_7 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_7 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_7 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_7 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_58 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_15 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_7 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_7 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_7 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_28 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_30 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_7 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_7 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_31 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_29, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_56 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_57 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_59 = {_activated_data_e_act_q_poly_iexp_self_rec_T_57[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_57[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_60 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_61 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_62 = {_activated_data_e_act_q_poly_iexp_self_rec_T_60, _activated_data_e_act_q_poly_iexp_self_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_63 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_7 = {_activated_data_e_act_q_poly_iexp_self_rec_T_62, _activated_data_e_act_q_poly_iexp_self_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_5; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_1_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_5 = _activated_data_e_act_q_poly_iexp_resizer_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_5 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_5[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_5 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_5 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_5 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_5[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_5 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_5; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_17; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_5; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_5; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_23; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_10 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_15 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_11 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_5 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_10; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_16 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_15; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_17 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_5 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_16; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_17; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_5 = _activated_data_e_act_q_poly_iexp_resizer_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_5; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_5 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_5}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_5; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_20 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_20}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_22 = _activated_data_e_act_q_poly_iexp_resizer_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_23 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_21, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_22}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_23; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_5 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_10 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_11 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_10}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_5 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_11[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_10 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_11 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_10 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_5; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_5 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_11[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_30 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_31 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_30} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_32 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_31[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_33 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_5 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_32; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_34 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_35 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_34}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_5 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_33 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_35; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_10 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_11 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_10; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_5 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_5 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_5 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_11; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_5 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_5_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_5}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_5 = {activated_data_e_act_q_poly_iexp_result_bits_hi_5, activated_data_e_act_q_poly_iexp_result_bits_fractOut_5}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_1_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_5; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_T_27 = activated_data_e_act_q_poly_iexp_1_bits >> activated_data_e_act_z_iexp_saturated_1_bits; // @[Arithmetic.scala:491:26] wire [31:0] _activated_data_e_act_WIRE_3 = _activated_data_e_act_T_27; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_T_28; // @[AccumulatorScale.scala:405:65] assign _activated_data_e_act_T_28 = _activated_data_e_act_WIRE_3; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_WIRE_2_bits = _activated_data_e_act_T_28; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_30_bits = _activated_data_e_act_T_29_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_31_bits = _activated_data_e_act_T_30_bits; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_1_bits = _activated_data_e_act_T_17 ? activated_data_e_act_result_5_bits : _activated_data_e_act_T_31_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_18_bits = _activated_data_e_scaled_T_17_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_7 = _activated_data_e_scaled_T_18_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_19; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_19 = _activated_data_e_scaled_WIRE_7; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_6_bits = _activated_data_e_scaled_T_19; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_t_rec_rawIn_sign_1 = _activated_data_e_scaled_WIRE_6_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_t_rec_rawIn_1_sign = activated_data_e_scaled_t_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_t_rec_rawIn_expIn_1 = _activated_data_e_scaled_WIRE_6_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_t_rec_rawIn_fractIn_1 = _activated_data_e_scaled_WIRE_6_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_1 = activated_data_e_scaled_t_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_1 = activated_data_e_scaled_t_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_44 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_45 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_46 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_47 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_48 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_49 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_50 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_51 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_52 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_53 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_54 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_55 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_56 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_57 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_58 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_59 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_60 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_61 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_62 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_63 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_64 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_65 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_66 = activated_data_e_scaled_t_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_67 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_68 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_69 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_70 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_71 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_72 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_73 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_scaled_t_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_74 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_scaled_t_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_75 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_scaled_t_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_76 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_scaled_t_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_77 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_scaled_t_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_78 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_scaled_t_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_79 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_80 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_81 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_82 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_83 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_84 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_85 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_86 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_87 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_t_rec_rawIn_normDist_1 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_t_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_scaled_t_rec_rawIn_fractIn_1} << activated_data_e_scaled_t_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_t_rec_rawIn_subnormFract_T_3 = _activated_data_e_scaled_t_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_t_rec_rawIn_subnormFract_1 = {_activated_data_e_scaled_t_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_scaled_t_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_6 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_scaled_t_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_7 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_scaled_t_rec_rawIn_adjustedExp_1 = _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_2 = activated_data_e_scaled_t_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_t_rec_rawIn_isZero_1 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_1 & activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_t_rec_rawIn_1_isZero = activated_data_e_scaled_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_isSpecial_T_1 = activated_data_e_scaled_t_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_t_rec_rawIn_isSpecial_1 = &_activated_data_e_scaled_t_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_t_rec_T_10 = activated_data_e_scaled_t_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_t_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_t_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_t_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_3 = activated_data_e_scaled_t_rec_rawIn_isSpecial_1 & _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_t_rec_rawIn_1_isNaN = _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_t_rec_rawIn_out_isInf_T_1 = activated_data_e_scaled_t_rec_rawIn_isSpecial_1 & activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_t_rec_rawIn_1_isInf = _activated_data_e_scaled_t_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_t_rec_rawIn_1_sExp = _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_t_rec_rawIn_out_sig_T_4 = ~activated_data_e_scaled_t_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_6 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_1 ? activated_data_e_scaled_t_rec_rawIn_subnormFract_1 : activated_data_e_scaled_t_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_t_rec_rawIn_out_sig_T_7 = {_activated_data_e_scaled_t_rec_rawIn_out_sig_T_5, _activated_data_e_scaled_t_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_t_rec_rawIn_1_sig = _activated_data_e_scaled_t_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_t_rec_T_8 = activated_data_e_scaled_t_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_t_rec_T_9 = activated_data_e_scaled_t_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_scaled_t_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_t_rec_T_11 = {_activated_data_e_scaled_t_rec_T_9[2:1], _activated_data_e_scaled_t_rec_T_9[0] | _activated_data_e_scaled_t_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_t_rec_T_12 = {activated_data_e_scaled_t_rec_rawIn_1_sign, _activated_data_e_scaled_t_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_t_rec_T_13 = activated_data_e_scaled_t_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_t_rec_T_14 = {_activated_data_e_scaled_t_rec_T_12, _activated_data_e_scaled_t_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_t_rec_T_15 = activated_data_e_scaled_t_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_t_rec_1 = {_activated_data_e_scaled_t_rec_T_14, _activated_data_e_scaled_t_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_scaled_self_rec_rawIn_sign_1 = activated_data_e_act_1_bits[31]; // @[Mux.scala:126:16] wire activated_data_e_scaled_self_rec_rawIn_1_sign = activated_data_e_scaled_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_self_rec_rawIn_expIn_1 = activated_data_e_act_1_bits[30:23]; // @[Mux.scala:126:16] wire [22:0] activated_data_e_scaled_self_rec_rawIn_fractIn_1 = activated_data_e_act_1_bits[22:0]; // @[Mux.scala:126:16] wire activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_1 = activated_data_e_scaled_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_1 = activated_data_e_scaled_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_44 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_45 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_46 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_47 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_48 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_49 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_50 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_51 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_52 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_53 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_54 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_55 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_56 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_57 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_58 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_59 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_60 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_61 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_62 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_63 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_64 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_65 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_66 = activated_data_e_scaled_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_67 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_68 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_69 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_70 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_71 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_72 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_73 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_scaled_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_74 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_scaled_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_75 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_scaled_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_76 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_scaled_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_77 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_scaled_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_78 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_scaled_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_79 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_80 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_81 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_82 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_83 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_84 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_85 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_86 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_87 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_self_rec_rawIn_normDist_1 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_self_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_scaled_self_rec_rawIn_fractIn_1} << activated_data_e_scaled_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_self_rec_rawIn_subnormFract_T_3 = _activated_data_e_scaled_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_self_rec_rawIn_subnormFract_1 = {_activated_data_e_scaled_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_scaled_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_6 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_scaled_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_7 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_scaled_self_rec_rawIn_adjustedExp_1 = _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_2 = activated_data_e_scaled_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_self_rec_rawIn_isZero_1 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_1 & activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_self_rec_rawIn_1_isZero = activated_data_e_scaled_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_isSpecial_T_1 = activated_data_e_scaled_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_self_rec_rawIn_isSpecial_1 = &_activated_data_e_scaled_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_self_rec_T_10 = activated_data_e_scaled_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_3 = activated_data_e_scaled_self_rec_rawIn_isSpecial_1 & _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_self_rec_rawIn_1_isNaN = _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_self_rec_rawIn_out_isInf_T_1 = activated_data_e_scaled_self_rec_rawIn_isSpecial_1 & activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_self_rec_rawIn_1_isInf = _activated_data_e_scaled_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_self_rec_rawIn_1_sExp = _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_self_rec_rawIn_out_sig_T_4 = ~activated_data_e_scaled_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_6 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_1 ? activated_data_e_scaled_self_rec_rawIn_subnormFract_1 : activated_data_e_scaled_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_self_rec_rawIn_out_sig_T_7 = {_activated_data_e_scaled_self_rec_rawIn_out_sig_T_5, _activated_data_e_scaled_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_self_rec_rawIn_1_sig = _activated_data_e_scaled_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_self_rec_T_8 = activated_data_e_scaled_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_self_rec_T_9 = activated_data_e_scaled_self_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_scaled_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_self_rec_T_11 = {_activated_data_e_scaled_self_rec_T_9[2:1], _activated_data_e_scaled_self_rec_T_9[0] | _activated_data_e_scaled_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_self_rec_T_12 = {activated_data_e_scaled_self_rec_rawIn_1_sign, _activated_data_e_scaled_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_self_rec_T_13 = activated_data_e_scaled_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_self_rec_T_14 = {_activated_data_e_scaled_self_rec_T_12, _activated_data_e_scaled_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_self_rec_T_15 = activated_data_e_scaled_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_self_rec_1 = {_activated_data_e_scaled_self_rec_T_14, _activated_data_e_scaled_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_scaled_1_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_scaled_out_bits_rawIn_exp_1 = _activated_data_e_scaled_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_out_bits_rawIn_isZero_T_1 = activated_data_e_scaled_out_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_out_bits_rawIn_isZero_1 = _activated_data_e_scaled_out_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_out_bits_rawIn_1_isZero = activated_data_e_scaled_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_out_bits_rawIn_isSpecial_T_1 = activated_data_e_scaled_out_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_out_bits_rawIn_isSpecial_1 = &_activated_data_e_scaled_out_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_out_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_out_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_out_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_out_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_2 = activated_data_e_scaled_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_3 = activated_data_e_scaled_out_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_3 = activated_data_e_scaled_out_bits_rawIn_isSpecial_1 & _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_out_bits_rawIn_1_isNaN = _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_scaled_out_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_5 = activated_data_e_scaled_out_bits_rawIn_isSpecial_1 & _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_out_bits_rawIn_1_isInf = _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_out_bits_rawIn_out_sign_T_1 = _activated_data_e_scaled_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_out_bits_rawIn_1_sign = _activated_data_e_scaled_out_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_out_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_scaled_out_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_out_bits_rawIn_1_sExp = _activated_data_e_scaled_out_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_out_bits_rawIn_out_sig_T_4 = ~activated_data_e_scaled_out_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_scaled_out_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_6 = _activated_data_e_scaled_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_out_bits_rawIn_out_sig_T_7 = {_activated_data_e_scaled_out_bits_rawIn_out_sig_T_5, _activated_data_e_scaled_out_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_out_bits_rawIn_1_sig = _activated_data_e_scaled_out_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_scaled_out_bits_isSubnormal_1 = $signed(activated_data_e_scaled_out_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_scaled_out_bits_denormShiftDist_T_2 = activated_data_e_scaled_out_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_scaled_out_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_scaled_out_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_scaled_out_bits_denormShiftDist_1 = _activated_data_e_scaled_out_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_scaled_out_bits_denormFract_T_2 = activated_data_e_scaled_out_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_scaled_out_bits_denormFract_T_3 = _activated_data_e_scaled_out_bits_denormFract_T_2 >> activated_data_e_scaled_out_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_scaled_out_bits_denormFract_1 = _activated_data_e_scaled_out_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_6 = activated_data_e_scaled_out_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_scaled_out_bits_expOut_T_7 = {1'h0, _activated_data_e_scaled_out_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_8 = _activated_data_e_scaled_out_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_9 = activated_data_e_scaled_out_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_scaled_out_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_scaled_out_bits_expOut_T_10 = activated_data_e_scaled_out_bits_rawIn_1_isNaN | activated_data_e_scaled_out_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_11 = {8{_activated_data_e_scaled_out_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_scaled_out_bits_expOut_1 = _activated_data_e_scaled_out_bits_expOut_T_9 | _activated_data_e_scaled_out_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_scaled_out_bits_fractOut_T_2 = activated_data_e_scaled_out_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_scaled_out_bits_fractOut_T_3 = activated_data_e_scaled_out_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_scaled_out_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_scaled_out_bits_fractOut_1 = activated_data_e_scaled_out_bits_isSubnormal_1 ? activated_data_e_scaled_out_bits_denormFract_1 : _activated_data_e_scaled_out_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_scaled_out_bits_hi_1 = {activated_data_e_scaled_out_bits_rawIn_1_sign, activated_data_e_scaled_out_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_scaled_out_bits_T_1 = {activated_data_e_scaled_out_bits_hi_1, activated_data_e_scaled_out_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_scaled_1_bits = _activated_data_e_scaled_out_bits_T_1; // @[fNFromRecFN.scala:66:12] wire activated_data_e_clipped_self_rec_rawIn_sign_1 = activated_data_e_scaled_1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_clipped_self_rec_rawIn_1_sign = activated_data_e_clipped_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_clipped_self_rec_rawIn_expIn_1 = activated_data_e_scaled_1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_clipped_self_rec_rawIn_fractIn_1 = activated_data_e_scaled_1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_1 = activated_data_e_clipped_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_1 = activated_data_e_clipped_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_44 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_45 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_46 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_47 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_48 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_49 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_50 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_51 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_52 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_53 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_54 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_55 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_56 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_57 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_58 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_59 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_60 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_61 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_62 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_63 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_64 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_65 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_66 = activated_data_e_clipped_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_67 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_68 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_69 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_70 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_71 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_72 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_73 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_clipped_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_74 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_clipped_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_75 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_clipped_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_76 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_clipped_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_77 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_clipped_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_78 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_clipped_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_79 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_80 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_81 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_82 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_83 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_84 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_85 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_86 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_87 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_clipped_self_rec_rawIn_normDist_1 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_clipped_self_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_clipped_self_rec_rawIn_fractIn_1} << activated_data_e_clipped_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_clipped_self_rec_rawIn_subnormFract_T_3 = _activated_data_e_clipped_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_clipped_self_rec_rawIn_subnormFract_1 = {_activated_data_e_clipped_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_clipped_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_6 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_clipped_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_7 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_clipped_self_rec_rawIn_adjustedExp_1 = _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_2 = activated_data_e_clipped_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_clipped_self_rec_rawIn_isZero_1 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_1 & activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_clipped_self_rec_rawIn_1_isZero = activated_data_e_clipped_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_isSpecial_T_1 = activated_data_e_clipped_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_clipped_self_rec_rawIn_isSpecial_1 = &_activated_data_e_clipped_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_clipped_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_clipped_self_rec_T_10 = activated_data_e_clipped_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_clipped_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_clipped_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_clipped_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_3 = activated_data_e_clipped_self_rec_rawIn_isSpecial_1 & _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_clipped_self_rec_rawIn_1_isNaN = _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_clipped_self_rec_rawIn_out_isInf_T_1 = activated_data_e_clipped_self_rec_rawIn_isSpecial_1 & activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_clipped_self_rec_rawIn_1_isInf = _activated_data_e_clipped_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_clipped_self_rec_rawIn_1_sExp = _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_clipped_self_rec_rawIn_out_sig_T_4 = ~activated_data_e_clipped_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_6 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_1 ? activated_data_e_clipped_self_rec_rawIn_subnormFract_1 : activated_data_e_clipped_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_clipped_self_rec_rawIn_out_sig_T_7 = {_activated_data_e_clipped_self_rec_rawIn_out_sig_T_5, _activated_data_e_clipped_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_clipped_self_rec_rawIn_1_sig = _activated_data_e_clipped_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_clipped_self_rec_T_8 = activated_data_e_clipped_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_clipped_self_rec_T_9 = activated_data_e_clipped_self_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_clipped_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_clipped_self_rec_T_11 = {_activated_data_e_clipped_self_rec_T_9[2:1], _activated_data_e_clipped_self_rec_T_9[0] | _activated_data_e_clipped_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_clipped_self_rec_T_12 = {activated_data_e_clipped_self_rec_rawIn_1_sign, _activated_data_e_clipped_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_clipped_self_rec_T_13 = activated_data_e_clipped_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_clipped_self_rec_T_14 = {_activated_data_e_clipped_self_rec_T_12, _activated_data_e_clipped_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_clipped_self_rec_T_15 = activated_data_e_clipped_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_clipped_self_rec_1 = {_activated_data_e_clipped_self_rec_T_14, _activated_data_e_clipped_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_clipped_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_clipped_1_bits; // @[Arithmetic.scala:505:26] wire [31:0] _activated_data_WIRE_1_0_bits = activated_data_e_clipped_1_bits; // @[Arithmetic.scala:505:26] wire [8:0] activated_data_e_clipped_result_bits_rawIn_exp_1 = _activated_data_e_clipped_resizer_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_clipped_result_bits_rawIn_isZero_T_1 = activated_data_e_clipped_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_clipped_result_bits_rawIn_isZero_1 = _activated_data_e_clipped_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_clipped_result_bits_rawIn_1_isZero = activated_data_e_clipped_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_clipped_result_bits_rawIn_isSpecial_T_1 = activated_data_e_clipped_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_clipped_result_bits_rawIn_isSpecial_1 = &_activated_data_e_clipped_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_clipped_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_clipped_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_clipped_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_clipped_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_clipped_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_clipped_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_clipped_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_2 = activated_data_e_clipped_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_3 = activated_data_e_clipped_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_3 = activated_data_e_clipped_result_bits_rawIn_isSpecial_1 & _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_clipped_result_bits_rawIn_1_isNaN = _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_4 = ~_activated_data_e_clipped_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_5 = activated_data_e_clipped_result_bits_rawIn_isSpecial_1 & _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_clipped_result_bits_rawIn_1_isInf = _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_clipped_result_bits_rawIn_out_sign_T_1 = _activated_data_e_clipped_resizer_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_clipped_result_bits_rawIn_1_sign = _activated_data_e_clipped_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_clipped_result_bits_rawIn_out_sExp_T_1 = {1'h0, activated_data_e_clipped_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_clipped_result_bits_rawIn_1_sExp = _activated_data_e_clipped_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_clipped_result_bits_rawIn_out_sig_T_4 = ~activated_data_e_clipped_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_clipped_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_6 = _activated_data_e_clipped_resizer_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_clipped_result_bits_rawIn_out_sig_T_7 = {_activated_data_e_clipped_result_bits_rawIn_out_sig_T_5, _activated_data_e_clipped_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_clipped_result_bits_rawIn_1_sig = _activated_data_e_clipped_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_clipped_result_bits_isSubnormal_1 = $signed(activated_data_e_clipped_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_clipped_result_bits_denormShiftDist_T_2 = activated_data_e_clipped_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_clipped_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _activated_data_e_clipped_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_clipped_result_bits_denormShiftDist_1 = _activated_data_e_clipped_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_clipped_result_bits_denormFract_T_2 = activated_data_e_clipped_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_clipped_result_bits_denormFract_T_3 = _activated_data_e_clipped_result_bits_denormFract_T_2 >> activated_data_e_clipped_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_clipped_result_bits_denormFract_1 = _activated_data_e_clipped_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_6 = activated_data_e_clipped_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_clipped_result_bits_expOut_T_7 = {1'h0, _activated_data_e_clipped_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_8 = _activated_data_e_clipped_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_9 = activated_data_e_clipped_result_bits_isSubnormal_1 ? 8'h0 : _activated_data_e_clipped_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_clipped_result_bits_expOut_T_10 = activated_data_e_clipped_result_bits_rawIn_1_isNaN | activated_data_e_clipped_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_11 = {8{_activated_data_e_clipped_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_clipped_result_bits_expOut_1 = _activated_data_e_clipped_result_bits_expOut_T_9 | _activated_data_e_clipped_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_clipped_result_bits_fractOut_T_2 = activated_data_e_clipped_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_clipped_result_bits_fractOut_T_3 = activated_data_e_clipped_result_bits_rawIn_1_isInf ? 23'h0 : _activated_data_e_clipped_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_clipped_result_bits_fractOut_1 = activated_data_e_clipped_result_bits_isSubnormal_1 ? activated_data_e_clipped_result_bits_denormFract_1 : _activated_data_e_clipped_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_clipped_result_bits_hi_1 = {activated_data_e_clipped_result_bits_rawIn_1_sign, activated_data_e_clipped_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_clipped_result_bits_T_1 = {activated_data_e_clipped_result_bits_hi_1, activated_data_e_clipped_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_clipped_1_bits = _activated_data_e_clipped_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_1_0_bits = _activated_data_WIRE_1_0_bits; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_33 = _activated_data_e_act_T_32; // @[AccumulatorScale.scala:118:{38,45}] wire activated_data_e_act_raw_sign_2 = io_in_bits_acc_read_resp_data_2_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_10 = io_in_bits_acc_read_resp_data_2_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_sign_t_rec_rawIn_sign_4 = io_in_bits_acc_read_resp_data_2_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_rec_rawIn_sign_4 = io_in_bits_acc_read_resp_data_2_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_sgn_2 = io_in_bits_acc_read_resp_data_2_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_12 = io_in_bits_acc_read_resp_data_2_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_14 = io_in_bits_acc_read_resp_data_2_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_raw_2_sign = activated_data_e_act_raw_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_raw_expIn_2 = io_in_bits_acc_read_resp_data_2_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_10 = io_in_bits_acc_read_resp_data_2_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_t_rec_rawIn_expIn_4 = io_in_bits_acc_read_resp_data_2_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_abs_t_rec_rawIn_expIn_4 = io_in_bits_acc_read_resp_data_2_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_12 = io_in_bits_acc_read_resp_data_2_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_14 = io_in_bits_acc_read_resp_data_2_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_raw_fractIn_2 = io_in_bits_acc_read_resp_data_2_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_10 = io_in_bits_acc_read_resp_data_2_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4 = io_in_bits_acc_read_resp_data_2_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4 = io_in_bits_acc_read_resp_data_2_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_12 = io_in_bits_acc_read_resp_data_2_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_14 = io_in_bits_acc_read_resp_data_2_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_raw_isZeroExpIn_2 = activated_data_e_act_raw_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_raw_isZeroFractIn_2 = activated_data_e_act_raw_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_raw_normDist_T_88 = activated_data_e_act_raw_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_89 = activated_data_e_act_raw_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_90 = activated_data_e_act_raw_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_91 = activated_data_e_act_raw_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_92 = activated_data_e_act_raw_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_93 = activated_data_e_act_raw_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_94 = activated_data_e_act_raw_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_95 = activated_data_e_act_raw_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_96 = activated_data_e_act_raw_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_97 = activated_data_e_act_raw_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_98 = activated_data_e_act_raw_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_99 = activated_data_e_act_raw_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_100 = activated_data_e_act_raw_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_101 = activated_data_e_act_raw_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_102 = activated_data_e_act_raw_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_103 = activated_data_e_act_raw_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_104 = activated_data_e_act_raw_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_105 = activated_data_e_act_raw_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_106 = activated_data_e_act_raw_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_107 = activated_data_e_act_raw_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_108 = activated_data_e_act_raw_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_109 = activated_data_e_act_raw_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_110 = activated_data_e_act_raw_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_raw_normDist_T_111 = _activated_data_e_act_raw_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_112 = _activated_data_e_act_raw_normDist_T_90 ? 5'h14 : _activated_data_e_act_raw_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_113 = _activated_data_e_act_raw_normDist_T_91 ? 5'h13 : _activated_data_e_act_raw_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_114 = _activated_data_e_act_raw_normDist_T_92 ? 5'h12 : _activated_data_e_act_raw_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_115 = _activated_data_e_act_raw_normDist_T_93 ? 5'h11 : _activated_data_e_act_raw_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_116 = _activated_data_e_act_raw_normDist_T_94 ? 5'h10 : _activated_data_e_act_raw_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_117 = _activated_data_e_act_raw_normDist_T_95 ? 5'hF : _activated_data_e_act_raw_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_118 = _activated_data_e_act_raw_normDist_T_96 ? 5'hE : _activated_data_e_act_raw_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_119 = _activated_data_e_act_raw_normDist_T_97 ? 5'hD : _activated_data_e_act_raw_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_120 = _activated_data_e_act_raw_normDist_T_98 ? 5'hC : _activated_data_e_act_raw_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_121 = _activated_data_e_act_raw_normDist_T_99 ? 5'hB : _activated_data_e_act_raw_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_122 = _activated_data_e_act_raw_normDist_T_100 ? 5'hA : _activated_data_e_act_raw_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_123 = _activated_data_e_act_raw_normDist_T_101 ? 5'h9 : _activated_data_e_act_raw_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_124 = _activated_data_e_act_raw_normDist_T_102 ? 5'h8 : _activated_data_e_act_raw_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_125 = _activated_data_e_act_raw_normDist_T_103 ? 5'h7 : _activated_data_e_act_raw_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_126 = _activated_data_e_act_raw_normDist_T_104 ? 5'h6 : _activated_data_e_act_raw_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_127 = _activated_data_e_act_raw_normDist_T_105 ? 5'h5 : _activated_data_e_act_raw_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_128 = _activated_data_e_act_raw_normDist_T_106 ? 5'h4 : _activated_data_e_act_raw_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_129 = _activated_data_e_act_raw_normDist_T_107 ? 5'h3 : _activated_data_e_act_raw_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_130 = _activated_data_e_act_raw_normDist_T_108 ? 5'h2 : _activated_data_e_act_raw_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_131 = _activated_data_e_act_raw_normDist_T_109 ? 5'h1 : _activated_data_e_act_raw_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_raw_normDist_2 = _activated_data_e_act_raw_normDist_T_110 ? 5'h0 : _activated_data_e_act_raw_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_raw_subnormFract_T_4 = {31'h0, activated_data_e_act_raw_fractIn_2} << activated_data_e_act_raw_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_raw_subnormFract_T_5 = _activated_data_e_act_raw_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_raw_subnormFract_2 = {_activated_data_e_act_raw_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_raw_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_raw_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_raw_adjustedExp_T_11 = activated_data_e_act_raw_isZeroExpIn_2 ? _activated_data_e_act_raw_adjustedExp_T_10 : {1'h0, activated_data_e_act_raw_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_raw_adjustedExp_T_12 = activated_data_e_act_raw_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_raw_adjustedExp_T_13 = {6'h20, _activated_data_e_act_raw_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_raw_adjustedExp_T_14 = {1'h0, _activated_data_e_act_raw_adjustedExp_T_11} + {2'h0, _activated_data_e_act_raw_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_raw_adjustedExp_2 = _activated_data_e_act_raw_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_raw_out_sExp_T_4 = activated_data_e_act_raw_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_raw_isZero_2 = activated_data_e_act_raw_isZeroExpIn_2 & activated_data_e_act_raw_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_raw_2_isZero = activated_data_e_act_raw_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_raw_isSpecial_T_2 = activated_data_e_act_raw_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_raw_isSpecial_2 = &_activated_data_e_act_raw_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_raw_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_raw_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire [9:0] _activated_data_e_act_raw_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_raw_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_raw_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_raw_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_raw_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_raw_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_raw_out_isNaN_T_4 = ~activated_data_e_act_raw_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_raw_out_isNaN_T_5 = activated_data_e_act_raw_isSpecial_2 & _activated_data_e_act_raw_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_raw_2_isNaN = _activated_data_e_act_raw_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_raw_out_isInf_T_2 = activated_data_e_act_raw_isSpecial_2 & activated_data_e_act_raw_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_raw_2_isInf = _activated_data_e_act_raw_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_raw_out_sExp_T_5 = {1'h0, _activated_data_e_act_raw_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_raw_2_sExp = _activated_data_e_act_raw_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_raw_out_sig_T_8 = ~activated_data_e_act_raw_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_raw_out_sig_T_9 = {1'h0, _activated_data_e_act_raw_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_raw_out_sig_T_10 = activated_data_e_act_raw_isZeroExpIn_2 ? activated_data_e_act_raw_subnormFract_2 : activated_data_e_act_raw_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_raw_out_sig_T_11 = {_activated_data_e_act_raw_out_sig_T_9, _activated_data_e_act_raw_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_raw_2_sig = _activated_data_e_act_raw_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [31:0] _activated_data_e_act_result_bits_T_16; // @[Arithmetic.scala:514:27] wire [31:0] activated_data_e_act_result_10_bits; // @[Arithmetic.scala:513:26] wire _activated_data_e_act_result_bits_T_14 = ~activated_data_e_act_raw_2_isZero; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_result_bits_T_15 = _activated_data_e_act_result_bits_T_14 & activated_data_e_act_raw_2_sign; // @[rawFloatFromFN.scala:63:19] assign _activated_data_e_act_result_bits_T_16 = _activated_data_e_act_result_bits_T_15 ? 32'h0 : io_in_bits_acc_read_resp_data_2_0_bits_0; // @[Arithmetic.scala:514:{27,40}] assign activated_data_e_act_result_10_bits = _activated_data_e_act_result_bits_T_16; // @[Arithmetic.scala:513:26, :514:27] wire activated_data_e_act_self_rec_rawIn_10_sign = activated_data_e_act_self_rec_rawIn_sign_10; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_10 = activated_data_e_act_self_rec_rawIn_expIn_10 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_10 = activated_data_e_act_self_rec_rawIn_fractIn_10 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_440 = activated_data_e_act_self_rec_rawIn_fractIn_10[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_441 = activated_data_e_act_self_rec_rawIn_fractIn_10[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_442 = activated_data_e_act_self_rec_rawIn_fractIn_10[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_443 = activated_data_e_act_self_rec_rawIn_fractIn_10[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_444 = activated_data_e_act_self_rec_rawIn_fractIn_10[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_445 = activated_data_e_act_self_rec_rawIn_fractIn_10[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_446 = activated_data_e_act_self_rec_rawIn_fractIn_10[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_447 = activated_data_e_act_self_rec_rawIn_fractIn_10[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_448 = activated_data_e_act_self_rec_rawIn_fractIn_10[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_449 = activated_data_e_act_self_rec_rawIn_fractIn_10[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_450 = activated_data_e_act_self_rec_rawIn_fractIn_10[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_451 = activated_data_e_act_self_rec_rawIn_fractIn_10[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_452 = activated_data_e_act_self_rec_rawIn_fractIn_10[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_453 = activated_data_e_act_self_rec_rawIn_fractIn_10[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_454 = activated_data_e_act_self_rec_rawIn_fractIn_10[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_455 = activated_data_e_act_self_rec_rawIn_fractIn_10[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_456 = activated_data_e_act_self_rec_rawIn_fractIn_10[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_457 = activated_data_e_act_self_rec_rawIn_fractIn_10[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_458 = activated_data_e_act_self_rec_rawIn_fractIn_10[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_459 = activated_data_e_act_self_rec_rawIn_fractIn_10[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_460 = activated_data_e_act_self_rec_rawIn_fractIn_10[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_461 = activated_data_e_act_self_rec_rawIn_fractIn_10[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_462 = activated_data_e_act_self_rec_rawIn_fractIn_10[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_463 = _activated_data_e_act_self_rec_rawIn_normDist_T_441 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_464 = _activated_data_e_act_self_rec_rawIn_normDist_T_442 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_463; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_465 = _activated_data_e_act_self_rec_rawIn_normDist_T_443 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_464; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_466 = _activated_data_e_act_self_rec_rawIn_normDist_T_444 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_465; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_467 = _activated_data_e_act_self_rec_rawIn_normDist_T_445 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_466; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_468 = _activated_data_e_act_self_rec_rawIn_normDist_T_446 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_467; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_469 = _activated_data_e_act_self_rec_rawIn_normDist_T_447 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_468; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_470 = _activated_data_e_act_self_rec_rawIn_normDist_T_448 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_469; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_471 = _activated_data_e_act_self_rec_rawIn_normDist_T_449 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_470; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_472 = _activated_data_e_act_self_rec_rawIn_normDist_T_450 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_471; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_473 = _activated_data_e_act_self_rec_rawIn_normDist_T_451 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_472; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_474 = _activated_data_e_act_self_rec_rawIn_normDist_T_452 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_473; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_475 = _activated_data_e_act_self_rec_rawIn_normDist_T_453 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_474; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_476 = _activated_data_e_act_self_rec_rawIn_normDist_T_454 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_475; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_477 = _activated_data_e_act_self_rec_rawIn_normDist_T_455 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_476; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_478 = _activated_data_e_act_self_rec_rawIn_normDist_T_456 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_477; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_479 = _activated_data_e_act_self_rec_rawIn_normDist_T_457 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_478; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_480 = _activated_data_e_act_self_rec_rawIn_normDist_T_458 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_479; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_481 = _activated_data_e_act_self_rec_rawIn_normDist_T_459 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_480; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_482 = _activated_data_e_act_self_rec_rawIn_normDist_T_460 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_481; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_483 = _activated_data_e_act_self_rec_rawIn_normDist_T_461 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_482; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_10 = _activated_data_e_act_self_rec_rawIn_normDist_T_462 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_483; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_20 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_10} << activated_data_e_act_self_rec_rawIn_normDist_10; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_21 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_20[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_10 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_21, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_50 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_10}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_51 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_10 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_50 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_10}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_52 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_10 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_53 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_52}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_54 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_51} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_53}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_10 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_54[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_20 = activated_data_e_act_self_rec_rawIn_adjustedExp_10; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_10 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_10 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_10_isZero = activated_data_e_act_self_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_10 = activated_data_e_act_self_rec_rawIn_adjustedExp_10[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_10 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_10; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_82 = activated_data_e_act_self_rec_rawIn_10_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_10_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_10_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_10_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_20 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_21 = activated_data_e_act_self_rec_rawIn_isSpecial_10 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_20; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_10_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_10 = activated_data_e_act_self_rec_rawIn_isSpecial_10 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_10_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_21 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_20}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_10_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_40 = ~activated_data_e_act_self_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_40}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_42 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_10 ? activated_data_e_act_self_rec_rawIn_subnormFract_10 : activated_data_e_act_self_rec_rawIn_fractIn_10; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_43 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_41, _activated_data_e_act_self_rec_rawIn_out_sig_T_42}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_10_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_80 = activated_data_e_act_self_rec_rawIn_10_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_81 = activated_data_e_act_self_rec_rawIn_10_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_80; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_83 = {_activated_data_e_act_self_rec_T_81[2:1], _activated_data_e_act_self_rec_T_81[0] | _activated_data_e_act_self_rec_T_82}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_84 = {activated_data_e_act_self_rec_rawIn_10_sign, _activated_data_e_act_self_rec_T_83}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_85 = activated_data_e_act_self_rec_rawIn_10_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_86 = {_activated_data_e_act_self_rec_T_84, _activated_data_e_act_self_rec_T_85}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_87 = activated_data_e_act_self_rec_rawIn_10_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_10 = {_activated_data_e_act_self_rec_T_86, _activated_data_e_act_self_rec_T_87}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_17; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_11_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_8 = _activated_data_e_act_muladder_8_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_8 = activated_data_e_act_result_bits_rawIn_exp_8[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_8 = _activated_data_e_act_result_bits_rawIn_isZero_T_8 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_8_isZero = activated_data_e_act_result_bits_rawIn_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_8 = activated_data_e_act_result_bits_rawIn_exp_8[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_8 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_8; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_26; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_8; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_8; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_35; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_8_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_8_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_8_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_8_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_8_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_16 = activated_data_e_act_result_bits_rawIn_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_24 = activated_data_e_act_result_bits_rawIn_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_17 = activated_data_e_act_result_bits_rawIn_isSpecial_8 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_16; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_8_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_25 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_24; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_26 = activated_data_e_act_result_bits_rawIn_isSpecial_8 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_25; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_8_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_26; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_8 = _activated_data_e_act_muladder_8_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_8_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_8; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_8 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_8}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_8_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_8; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_32 = ~activated_data_e_act_result_bits_rawIn_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_33 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_32}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_34 = _activated_data_e_act_muladder_8_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_35 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_33, _activated_data_e_act_result_bits_rawIn_out_sig_T_34}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_8_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_35; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_8 = $signed(activated_data_e_act_result_bits_rawIn_8_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_16 = activated_data_e_act_result_bits_rawIn_8_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_17 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_16}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_8 = _activated_data_e_act_result_bits_denormShiftDist_T_17[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_16 = activated_data_e_act_result_bits_rawIn_8_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_17 = _activated_data_e_act_result_bits_denormFract_T_16 >> activated_data_e_act_result_bits_denormShiftDist_8; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_8 = _activated_data_e_act_result_bits_denormFract_T_17[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_48 = activated_data_e_act_result_bits_rawIn_8_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_49 = {1'h0, _activated_data_e_act_result_bits_expOut_T_48} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_50 = _activated_data_e_act_result_bits_expOut_T_49[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_51 = activated_data_e_act_result_bits_isSubnormal_8 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_50; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_52 = activated_data_e_act_result_bits_rawIn_8_isNaN | activated_data_e_act_result_bits_rawIn_8_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_53 = {8{_activated_data_e_act_result_bits_expOut_T_52}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_8 = _activated_data_e_act_result_bits_expOut_T_51 | _activated_data_e_act_result_bits_expOut_T_53; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_16 = activated_data_e_act_result_bits_rawIn_8_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_17 = activated_data_e_act_result_bits_rawIn_8_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_16; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_8 = activated_data_e_act_result_bits_isSubnormal_8 ? activated_data_e_act_result_bits_denormFract_8 : _activated_data_e_act_result_bits_fractOut_T_17; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_8 = {activated_data_e_act_result_bits_rawIn_8_sign, activated_data_e_act_result_bits_expOut_8}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_17 = {activated_data_e_act_result_bits_hi_8, activated_data_e_act_result_bits_fractOut_8}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_11_bits = _activated_data_e_act_result_bits_T_17; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_sign_t_rec_rawIn_4_sign = activated_data_e_act_q_sign_t_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_q_sign_t_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_176 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_177 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_178 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_179 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_180 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_181 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_182 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_183 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_184 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_185 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_186 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_187 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_188 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_189 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_190 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_191 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_192 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_193 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_194 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_195 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_196 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_197 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_198 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_199 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_200 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_201 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_202 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_203 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_204 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_205 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_206 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_207 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_208 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_209 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_210 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_211 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_212 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_213 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_214 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_215 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_216 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_217 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_218 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_219 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_t_rec_rawIn_normDist_4 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4} << activated_data_e_act_q_sign_t_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_4 = {_activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_q_sign_t_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_q_sign_t_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_4 = _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_8 = activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_sign_t_rec_rawIn_isZero_4 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_sign_t_rec_rawIn_4_isZero = activated_data_e_act_q_sign_t_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T_4 = activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_4 = &_activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_t_rec_T_34 = activated_data_e_act_q_sign_t_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_sign_t_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_sign_t_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_sign_t_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_4 & _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_sign_t_rec_rawIn_4_isNaN = _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_4 = activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_4 & activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_sign_t_rec_rawIn_4_isInf = _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_sign_t_rec_rawIn_4_sExp = _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_q_sign_t_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_18 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_4 : activated_data_e_act_q_sign_t_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_17, _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_sign_t_rec_rawIn_4_sig = _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_32 = activated_data_e_act_q_sign_t_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_33 = activated_data_e_act_q_sign_t_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_q_sign_t_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_35 = {_activated_data_e_act_q_sign_t_rec_T_33[2:1], _activated_data_e_act_q_sign_t_rec_T_33[0] | _activated_data_e_act_q_sign_t_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_sign_t_rec_T_36 = {activated_data_e_act_q_sign_t_rec_rawIn_4_sign, _activated_data_e_act_q_sign_t_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_sign_t_rec_T_37 = activated_data_e_act_q_sign_t_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_sign_t_rec_T_38 = {_activated_data_e_act_q_sign_t_rec_T_36, _activated_data_e_act_q_sign_t_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_sign_t_rec_T_39 = activated_data_e_act_q_sign_t_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_sign_t_rec_4 = {_activated_data_e_act_q_sign_t_rec_T_38, _activated_data_e_act_q_sign_t_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] activated_data_e_act_q_sign_2_bits = {_activated_data_e_act_q_sign_comparator_2_io_gt, 31'h3F800000}; // @[Arithmetic.scala:475:32] wire activated_data_e_act_q_abs_t_rec_rawIn_4_sign = activated_data_e_act_q_abs_t_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_q_abs_t_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_176 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_177 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_178 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_179 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_180 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_181 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_182 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_183 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_184 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_185 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_186 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_187 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_188 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_189 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_190 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_191 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_192 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_193 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_194 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_195 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_196 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_197 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_198 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_199 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_200 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_201 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_202 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_203 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_204 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_205 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_206 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_207 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_208 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_209 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_210 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_211 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_212 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_213 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_214 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_215 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_216 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_217 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_218 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_219 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_t_rec_rawIn_normDist_4 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4} << activated_data_e_act_q_abs_t_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_4 = {_activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_q_abs_t_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_q_abs_t_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_4 = _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_8 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_abs_t_rec_rawIn_isZero_4 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_abs_t_rec_rawIn_4_isZero = activated_data_e_act_q_abs_t_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_4 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_4 = &_activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_t_rec_T_34 = activated_data_e_act_q_abs_t_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_abs_t_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_abs_t_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_abs_t_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_4 & _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_abs_t_rec_rawIn_4_isNaN = _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_4 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_4 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_abs_t_rec_rawIn_4_isInf = _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_abs_t_rec_rawIn_4_sExp = _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_18 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_4 : activated_data_e_act_q_abs_t_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_17, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_abs_t_rec_rawIn_4_sig = _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_32 = activated_data_e_act_q_abs_t_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_33 = activated_data_e_act_q_abs_t_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_q_abs_t_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_35 = {_activated_data_e_act_q_abs_t_rec_T_33[2:1], _activated_data_e_act_q_abs_t_rec_T_33[0] | _activated_data_e_act_q_abs_t_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_abs_t_rec_T_36 = {activated_data_e_act_q_abs_t_rec_rawIn_4_sign, _activated_data_e_act_q_abs_t_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_abs_t_rec_T_37 = activated_data_e_act_q_abs_t_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_abs_t_rec_T_38 = {_activated_data_e_act_q_abs_t_rec_T_36, _activated_data_e_act_q_abs_t_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_abs_t_rec_T_39 = activated_data_e_act_q_abs_t_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_abs_t_rec_4 = {_activated_data_e_act_q_abs_t_rec_T_38, _activated_data_e_act_q_abs_t_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _activated_data_e_act_q_abs_neg_t_T_8 = ~activated_data_e_act_q_abs_t_sgn_2; // @[Arithmetic.scala:432:27, :433:25] wire [30:0] _activated_data_e_act_q_abs_neg_t_T_9 = io_in_bits_acc_read_resp_data_2_0_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [31:0] _activated_data_e_act_q_abs_neg_t_T_10 = {_activated_data_e_act_q_abs_neg_t_T_8, _activated_data_e_act_q_abs_neg_t_T_9}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_abs_neg_t_WIRE_2 = _activated_data_e_act_q_abs_neg_t_T_10; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_abs_neg_t_T_11; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_abs_neg_t_2_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_abs_neg_t_T_11 = _activated_data_e_act_q_abs_neg_t_WIRE_2; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_abs_neg_t_2_bits = _activated_data_e_act_q_abs_neg_t_T_11; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_abs_t_rec_rawIn_sign_5 = activated_data_e_act_q_abs_neg_t_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_rec_rawIn_5_sign = activated_data_e_act_q_abs_t_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_abs_t_rec_rawIn_expIn_5 = activated_data_e_act_q_abs_neg_t_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5 = activated_data_e_act_q_abs_neg_t_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_5 = activated_data_e_act_q_abs_t_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_5 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_220 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_221 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_222 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_223 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_224 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_225 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_226 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_227 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_228 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_229 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_230 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_231 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_232 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_233 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_234 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_235 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_236 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_237 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_238 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_239 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_240 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_241 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_242 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_243 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_244 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_245 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_246 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_247 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_248 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_249 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_250 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_251 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_252 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_253 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_254 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_255 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_256 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_257 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_258 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_259 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_260 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_261 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_262 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_263 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_t_rec_rawIn_normDist_5 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5} << activated_data_e_act_q_abs_t_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_11 = _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_5 = {_activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_act_q_abs_t_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_26 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_act_q_abs_t_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_27 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_5 = _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_10 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_abs_t_rec_rawIn_isZero_5 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_5 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_abs_t_rec_rawIn_5_isZero = activated_data_e_act_q_abs_t_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_5 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_5 = &_activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_t_rec_T_42 = activated_data_e_act_q_abs_t_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_abs_t_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_abs_t_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_abs_t_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_11 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_5 & _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_abs_t_rec_rawIn_5_isNaN = _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_5 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_5 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_abs_t_rec_rawIn_5_isInf = _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_abs_t_rec_rawIn_5_sExp = _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_20 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_22 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_5 ? activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_5 : activated_data_e_act_q_abs_t_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_23 = {_activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_21, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_abs_t_rec_rawIn_5_sig = _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_40 = activated_data_e_act_q_abs_t_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_41 = activated_data_e_act_q_abs_t_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_act_q_abs_t_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_43 = {_activated_data_e_act_q_abs_t_rec_T_41[2:1], _activated_data_e_act_q_abs_t_rec_T_41[0] | _activated_data_e_act_q_abs_t_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_abs_t_rec_T_44 = {activated_data_e_act_q_abs_t_rec_rawIn_5_sign, _activated_data_e_act_q_abs_t_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_abs_t_rec_T_45 = activated_data_e_act_q_abs_t_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_abs_t_rec_T_46 = {_activated_data_e_act_q_abs_t_rec_T_44, _activated_data_e_act_q_abs_t_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_abs_t_rec_T_47 = activated_data_e_act_q_abs_t_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_abs_t_rec_5 = {_activated_data_e_act_q_abs_t_rec_T_46, _activated_data_e_act_q_abs_t_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_abs_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_abs_result_2_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_abs_result_bits_rawIn_exp_2 = _activated_data_e_act_q_abs_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_abs_result_bits_rawIn_isZero_T_2 = activated_data_e_act_q_abs_result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_abs_result_bits_rawIn_isZero_2 = _activated_data_e_act_q_abs_result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_abs_result_bits_rawIn_2_isZero = activated_data_e_act_q_abs_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_T_2 = activated_data_e_act_q_abs_result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_2 = &_activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_abs_result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_abs_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_abs_result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_abs_result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_abs_result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_q_abs_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_6 = activated_data_e_act_q_abs_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_abs_result_bits_rawIn_2_isNaN = _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_8 = activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_abs_result_bits_rawIn_2_isInf = _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T_2 = _activated_data_e_act_q_abs_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_abs_result_bits_rawIn_2_sign = _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_q_abs_result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_abs_result_bits_rawIn_2_sExp = _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_q_abs_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_10 = _activated_data_e_act_q_abs_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_9, _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_abs_result_bits_rawIn_2_sig = _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_abs_result_bits_isSubnormal_2 = $signed(activated_data_e_act_q_abs_result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_4 = activated_data_e_act_q_abs_result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_abs_result_bits_denormShiftDist_2 = _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_abs_result_bits_denormFract_T_4 = activated_data_e_act_q_abs_result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_abs_result_bits_denormFract_T_5 = _activated_data_e_act_q_abs_result_bits_denormFract_T_4 >> activated_data_e_act_q_abs_result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_abs_result_bits_denormFract_2 = _activated_data_e_act_q_abs_result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_12 = activated_data_e_act_q_abs_result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_abs_result_bits_expOut_T_13 = {1'h0, _activated_data_e_act_q_abs_result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_14 = _activated_data_e_act_q_abs_result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_15 = activated_data_e_act_q_abs_result_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_q_abs_result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_abs_result_bits_expOut_T_16 = activated_data_e_act_q_abs_result_bits_rawIn_2_isNaN | activated_data_e_act_q_abs_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_17 = {8{_activated_data_e_act_q_abs_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_abs_result_bits_expOut_2 = _activated_data_e_act_q_abs_result_bits_expOut_T_15 | _activated_data_e_act_q_abs_result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_abs_result_bits_fractOut_T_4 = activated_data_e_act_q_abs_result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_abs_result_bits_fractOut_T_5 = activated_data_e_act_q_abs_result_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_q_abs_result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_abs_result_bits_fractOut_2 = activated_data_e_act_q_abs_result_bits_isSubnormal_2 ? activated_data_e_act_q_abs_result_bits_denormFract_2 : _activated_data_e_act_q_abs_result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_abs_result_bits_hi_2 = {activated_data_e_act_q_abs_result_bits_rawIn_2_sign, activated_data_e_act_q_abs_result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_abs_result_bits_T_2 = {activated_data_e_act_q_abs_result_bits_hi_2, activated_data_e_act_q_abs_result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_abs_result_2_bits = _activated_data_e_act_q_abs_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_abs_2_bits = _activated_data_e_act_q_abs_comparator_2_io_gt ? activated_data_e_act_q_abs_result_2_bits : io_in_bits_acc_read_resp_data_2_0_bits_0; // @[Arithmetic.scala:426:26, :475:32] wire _activated_data_e_act_q_clipped_neg_t_T_16 = ~activated_data_e_act_q_clipped_t_sgn_4; // @[Arithmetic.scala:432:27, :433:25] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_18 = {_activated_data_e_act_q_clipped_neg_t_T_16, _activated_data_e_act_q_clipped_neg_t_T_17}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_WIRE_4 = _activated_data_e_act_q_clipped_neg_t_T_18; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_19; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_clipped_neg_t_4_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_clipped_neg_t_T_19 = _activated_data_e_act_q_clipped_neg_t_WIRE_4; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_clipped_neg_t_4_bits = _activated_data_e_act_q_clipped_neg_t_T_19; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_6 = activated_data_e_act_q_clipped_neg_t_4_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_6_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_6 = activated_data_e_act_q_clipped_neg_t_4_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6 = activated_data_e_act_q_clipped_neg_t_4_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_264 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_265 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_266 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_267 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_268 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_269 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_270 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_271 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_272 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_273 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_274 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_275 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_276 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_277 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_278 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_279 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_280 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_281 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_282 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_283 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_284 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_285 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_286 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_287 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_288 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_289 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_290 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_291 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_292 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_293 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_294 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_295 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_296 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_297 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_298 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_299 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_300 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_301 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_302 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_303 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_304 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_305 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_306 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_307 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_6 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_6 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_6 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_12 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_6 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_6_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_6 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_6 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_50 = activated_data_e_act_q_clipped_t_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_6 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_6_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_6 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_6 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_6_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_6_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_26 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_6 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_25, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_6_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_48 = activated_data_e_act_q_clipped_t_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_49 = activated_data_e_act_q_clipped_t_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_51 = {_activated_data_e_act_q_clipped_t_rec_T_49[2:1], _activated_data_e_act_q_clipped_t_rec_T_49[0] | _activated_data_e_act_q_clipped_t_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_52 = {activated_data_e_act_q_clipped_t_rec_rawIn_6_sign, _activated_data_e_act_q_clipped_t_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_53 = activated_data_e_act_q_clipped_t_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_54 = {_activated_data_e_act_q_clipped_t_rec_T_52, _activated_data_e_act_q_clipped_t_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_55 = activated_data_e_act_q_clipped_t_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_6 = {_activated_data_e_act_q_clipped_t_rec_T_54, _activated_data_e_act_q_clipped_t_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_clipped_result_bits_T_4; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_result_4_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_clipped_result_bits_rawIn_exp_4 = _activated_data_e_act_q_clipped_muladder_4_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_4 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_4[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isZero_4 = _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_4 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_clipped_result_bits_rawIn_4_isZero = activated_data_e_act_q_clipped_result_bits_rawIn_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_4 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_4[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_4 = &_activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_4; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_14; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_4; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_4; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_19; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_clipped_result_bits_rawIn_4_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_4_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_4_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_clipped_result_bits_rawIn_4_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_clipped_result_bits_rawIn_4_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_8 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_12 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_9 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_4 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_8; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_clipped_result_bits_rawIn_4_isNaN = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_13 = ~_activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_12; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_14 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_4 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_13; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_clipped_result_bits_rawIn_4_isInf = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_14; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_4 = _activated_data_e_act_q_clipped_muladder_4_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_clipped_result_bits_rawIn_4_sign = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_4; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_4 = {1'h0, activated_data_e_act_q_clipped_result_bits_rawIn_exp_4}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_clipped_result_bits_rawIn_4_sExp = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_4; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_16 = ~activated_data_e_act_q_clipped_result_bits_rawIn_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_16}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_18 = _activated_data_e_act_q_clipped_muladder_4_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_19 = {_activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_17, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_18}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_clipped_result_bits_rawIn_4_sig = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_19; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_clipped_result_bits_isSubnormal_4 = $signed(activated_data_e_act_q_clipped_result_bits_rawIn_4_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_8 = activated_data_e_act_q_clipped_result_bits_rawIn_4_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_9 = 6'h1 - {1'h0, _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_8}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_clipped_result_bits_denormShiftDist_4 = _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_9[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_8 = activated_data_e_act_q_clipped_result_bits_rawIn_4_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_9 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_8 >> activated_data_e_act_q_clipped_result_bits_denormShiftDist_4; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_clipped_result_bits_denormFract_4 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_9[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_24 = activated_data_e_act_q_clipped_result_bits_rawIn_4_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_25 = {1'h0, _activated_data_e_act_q_clipped_result_bits_expOut_T_24} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_26 = _activated_data_e_act_q_clipped_result_bits_expOut_T_25[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_27 = activated_data_e_act_q_clipped_result_bits_isSubnormal_4 ? 8'h0 : _activated_data_e_act_q_clipped_result_bits_expOut_T_26; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_clipped_result_bits_expOut_T_28 = activated_data_e_act_q_clipped_result_bits_rawIn_4_isNaN | activated_data_e_act_q_clipped_result_bits_rawIn_4_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_29 = {8{_activated_data_e_act_q_clipped_result_bits_expOut_T_28}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_clipped_result_bits_expOut_4 = _activated_data_e_act_q_clipped_result_bits_expOut_T_27 | _activated_data_e_act_q_clipped_result_bits_expOut_T_29; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_8 = activated_data_e_act_q_clipped_result_bits_rawIn_4_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_9 = activated_data_e_act_q_clipped_result_bits_rawIn_4_isInf ? 23'h0 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_8; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_clipped_result_bits_fractOut_4 = activated_data_e_act_q_clipped_result_bits_isSubnormal_4 ? activated_data_e_act_q_clipped_result_bits_denormFract_4 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_9; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_clipped_result_bits_hi_4 = {activated_data_e_act_q_clipped_result_bits_rawIn_4_sign, activated_data_e_act_q_clipped_result_bits_expOut_4}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_clipped_result_bits_T_4 = {activated_data_e_act_q_clipped_result_bits_hi_4, activated_data_e_act_q_clipped_result_bits_fractOut_4}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_clipped_result_4_bits = _activated_data_e_act_q_clipped_result_bits_T_4; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_7 = activated_data_e_act_q_clipped_result_4_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_7_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_7 = activated_data_e_act_q_clipped_result_4_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7 = activated_data_e_act_q_clipped_result_4_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_7 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_7 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_308 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_309 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_310 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_311 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_312 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_313 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_314 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_315 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_316 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_317 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_318 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_319 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_320 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_321 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_322 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_323 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_324 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_325 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_326 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_327 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_328 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_329 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_330 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_331 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_332 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_333 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_334 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_335 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_336 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_337 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_338 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_339 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_340 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_341 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_342 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_343 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_344 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_345 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_346 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_347 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_348 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_349 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_350 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_351 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_7 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_15 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_7 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_36 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_37 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_7 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_14 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_7 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_7 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_7_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_7 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_7 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_58 = activated_data_e_act_q_clipped_t_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_15 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_7 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_7_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_7 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_7 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_7_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_7_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_28 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_30 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_7 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_7 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_31 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_29, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_7_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_56 = activated_data_e_act_q_clipped_t_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_57 = activated_data_e_act_q_clipped_t_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_59 = {_activated_data_e_act_q_clipped_t_rec_T_57[2:1], _activated_data_e_act_q_clipped_t_rec_T_57[0] | _activated_data_e_act_q_clipped_t_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_60 = {activated_data_e_act_q_clipped_t_rec_rawIn_7_sign, _activated_data_e_act_q_clipped_t_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_61 = activated_data_e_act_q_clipped_t_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_62 = {_activated_data_e_act_q_clipped_t_rec_T_60, _activated_data_e_act_q_clipped_t_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_63 = activated_data_e_act_q_clipped_t_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_7 = {_activated_data_e_act_q_clipped_t_rec_T_62, _activated_data_e_act_q_clipped_t_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_7 = activated_data_e_act_q_abs_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_self_rec_rawIn_7_sign = activated_data_e_act_q_clipped_self_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_7 = activated_data_e_act_q_abs_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7 = activated_data_e_act_q_abs_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_7 = activated_data_e_act_q_clipped_self_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_7 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_308 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_309 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_310 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_311 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_312 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_313 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_314 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_315 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_316 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_317 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_318 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_319 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_320 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_321 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_322 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_323 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_324 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_325 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_326 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_327 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_328 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_329 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_330 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_331 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_332 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_333 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_334 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_335 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_336 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_337 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_338 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_339 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_340 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_341 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_342 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_343 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_344 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_345 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_346 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_347 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_348 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_349 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_350 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_351 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_7 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7} << activated_data_e_act_q_clipped_self_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_15 = _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_7 = {_activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_act_q_clipped_self_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_36 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_act_q_clipped_self_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_37 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_7 = _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_14 = activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_7 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_7 & activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_7_isZero = activated_data_e_act_q_clipped_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_7 = activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_7 = &_activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_T_58 = activated_data_e_act_q_clipped_self_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_self_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_15 = activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_7 & _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_self_rec_rawIn_7_isNaN = _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_7 = activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_7 & activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_self_rec_rawIn_7_isInf = _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_self_rec_rawIn_7_sExp = _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_28 = ~activated_data_e_act_q_clipped_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_30 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_7 ? activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_7 : activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_31 = {_activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_29, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_self_rec_rawIn_7_sig = _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_56 = activated_data_e_act_q_clipped_self_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_57 = activated_data_e_act_q_clipped_self_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_act_q_clipped_self_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_59 = {_activated_data_e_act_q_clipped_self_rec_T_57[2:1], _activated_data_e_act_q_clipped_self_rec_T_57[0] | _activated_data_e_act_q_clipped_self_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_60 = {activated_data_e_act_q_clipped_self_rec_rawIn_7_sign, _activated_data_e_act_q_clipped_self_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_61 = activated_data_e_act_q_clipped_self_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_62 = {_activated_data_e_act_q_clipped_self_rec_T_60, _activated_data_e_act_q_clipped_self_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_63 = activated_data_e_act_q_clipped_self_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_self_rec_7 = {_activated_data_e_act_q_clipped_self_rec_T_62, _activated_data_e_act_q_clipped_self_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _activated_data_e_act_q_clipped_neg_t_T_20 = ~activated_data_e_act_q_clipped_t_sgn_5; // @[Arithmetic.scala:432:27, :433:25] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_22 = {_activated_data_e_act_q_clipped_neg_t_T_20, _activated_data_e_act_q_clipped_neg_t_T_21}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_WIRE_5 = _activated_data_e_act_q_clipped_neg_t_T_22; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_23; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_clipped_neg_t_5_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_clipped_neg_t_T_23 = _activated_data_e_act_q_clipped_neg_t_WIRE_5; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_clipped_neg_t_5_bits = _activated_data_e_act_q_clipped_neg_t_T_23; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_8 = activated_data_e_act_q_clipped_neg_t_5_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_8_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_8; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_8 = activated_data_e_act_q_clipped_neg_t_5_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8 = activated_data_e_act_q_clipped_neg_t_5_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_8 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_8 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_8 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_352 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_353 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_354 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_355 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_356 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_357 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_358 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_359 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_360 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_361 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_362 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_363 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_364 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_365 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_366 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_367 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_368 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_369 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_370 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_371 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_372 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_373 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_374 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_375 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_353 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_376 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_354 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_375; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_377 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_355 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_376; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_378 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_356 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_377; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_379 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_357 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_378; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_380 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_358 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_379; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_381 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_359 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_380; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_382 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_360 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_381; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_383 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_361 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_382; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_384 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_362 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_383; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_385 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_363 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_384; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_386 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_364 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_385; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_387 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_365 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_386; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_388 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_366 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_387; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_389 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_367 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_388; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_390 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_368 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_389; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_391 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_369 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_390; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_392 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_370 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_391; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_393 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_371 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_392; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_394 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_372 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_393; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_395 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_373 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_394; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_8 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_374 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_395; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_16 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_8; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_17 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_16[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_8 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_17, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_40 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_8}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_41 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_8 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_40 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_8}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_42 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_8 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_43 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_42}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_44 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_41} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_43}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_8 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_44[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_16 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_8; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_8 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_8 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_8_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_8 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_8[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_8 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_8; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_66 = activated_data_e_act_q_clipped_t_rec_rawIn_8_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_8_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_8_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_8_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_16 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_17 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_8 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_16; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_8_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_8 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_8 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_8_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_17 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_16}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_8_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_32 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_33 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_32}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_34 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_8 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_8 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_8; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_35 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_33, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_34}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_8_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_64 = activated_data_e_act_q_clipped_t_rec_rawIn_8_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_65 = activated_data_e_act_q_clipped_t_rec_rawIn_8_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_64; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_67 = {_activated_data_e_act_q_clipped_t_rec_T_65[2:1], _activated_data_e_act_q_clipped_t_rec_T_65[0] | _activated_data_e_act_q_clipped_t_rec_T_66}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_68 = {activated_data_e_act_q_clipped_t_rec_rawIn_8_sign, _activated_data_e_act_q_clipped_t_rec_T_67}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_69 = activated_data_e_act_q_clipped_t_rec_rawIn_8_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_70 = {_activated_data_e_act_q_clipped_t_rec_T_68, _activated_data_e_act_q_clipped_t_rec_T_69}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_71 = activated_data_e_act_q_clipped_t_rec_rawIn_8_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_8 = {_activated_data_e_act_q_clipped_t_rec_T_70, _activated_data_e_act_q_clipped_t_rec_T_71}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_clipped_result_bits_T_5; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_result_5_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_clipped_result_bits_rawIn_exp_5 = _activated_data_e_act_q_clipped_muladder_5_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_5 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_5[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isZero_5 = _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_5 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_clipped_result_bits_rawIn_5_isZero = activated_data_e_act_q_clipped_result_bits_rawIn_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_5 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_5[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_5 = &_activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_5; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_17; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_5; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_5; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_23; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_clipped_result_bits_rawIn_5_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_5_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_5_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_clipped_result_bits_rawIn_5_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_clipped_result_bits_rawIn_5_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_10 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_15 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_11 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_5 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_10; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_clipped_result_bits_rawIn_5_isNaN = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_16 = ~_activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_15; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_17 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_5 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_16; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_clipped_result_bits_rawIn_5_isInf = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_17; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_5 = _activated_data_e_act_q_clipped_muladder_5_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_clipped_result_bits_rawIn_5_sign = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_5; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_5 = {1'h0, activated_data_e_act_q_clipped_result_bits_rawIn_exp_5}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_clipped_result_bits_rawIn_5_sExp = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_5; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_20 = ~activated_data_e_act_q_clipped_result_bits_rawIn_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_20}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_22 = _activated_data_e_act_q_clipped_muladder_5_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_23 = {_activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_21, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_22}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_clipped_result_bits_rawIn_5_sig = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_23; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_clipped_result_bits_isSubnormal_5 = $signed(activated_data_e_act_q_clipped_result_bits_rawIn_5_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_10 = activated_data_e_act_q_clipped_result_bits_rawIn_5_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_11 = 6'h1 - {1'h0, _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_10}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_clipped_result_bits_denormShiftDist_5 = _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_11[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_10 = activated_data_e_act_q_clipped_result_bits_rawIn_5_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_11 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_10 >> activated_data_e_act_q_clipped_result_bits_denormShiftDist_5; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_clipped_result_bits_denormFract_5 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_11[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_30 = activated_data_e_act_q_clipped_result_bits_rawIn_5_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_31 = {1'h0, _activated_data_e_act_q_clipped_result_bits_expOut_T_30} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_32 = _activated_data_e_act_q_clipped_result_bits_expOut_T_31[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_33 = activated_data_e_act_q_clipped_result_bits_isSubnormal_5 ? 8'h0 : _activated_data_e_act_q_clipped_result_bits_expOut_T_32; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_clipped_result_bits_expOut_T_34 = activated_data_e_act_q_clipped_result_bits_rawIn_5_isNaN | activated_data_e_act_q_clipped_result_bits_rawIn_5_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_35 = {8{_activated_data_e_act_q_clipped_result_bits_expOut_T_34}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_clipped_result_bits_expOut_5 = _activated_data_e_act_q_clipped_result_bits_expOut_T_33 | _activated_data_e_act_q_clipped_result_bits_expOut_T_35; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_10 = activated_data_e_act_q_clipped_result_bits_rawIn_5_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_11 = activated_data_e_act_q_clipped_result_bits_rawIn_5_isInf ? 23'h0 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_10; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_clipped_result_bits_fractOut_5 = activated_data_e_act_q_clipped_result_bits_isSubnormal_5 ? activated_data_e_act_q_clipped_result_bits_denormFract_5 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_11; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_clipped_result_bits_hi_5 = {activated_data_e_act_q_clipped_result_bits_rawIn_5_sign, activated_data_e_act_q_clipped_result_bits_expOut_5}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_clipped_result_bits_T_5 = {activated_data_e_act_q_clipped_result_bits_hi_5, activated_data_e_act_q_clipped_result_bits_fractOut_5}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_clipped_result_5_bits = _activated_data_e_act_q_clipped_result_bits_T_5; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_2_bits = _activated_data_e_act_q_clipped_comparator_2_io_gt ? activated_data_e_act_q_clipped_result_5_bits : activated_data_e_act_q_abs_2_bits; // @[Arithmetic.scala:426:26, :475:32] wire activated_data_e_act_q_poly_t_rec_rawIn_4_sign = activated_data_e_act_q_poly_t_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_q_poly_t_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_176 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_177 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_178 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_179 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_180 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_181 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_182 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_183 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_184 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_185 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_186 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_187 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_188 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_189 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_190 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_191 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_192 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_193 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_194 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_195 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_196 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_197 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_198 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_199 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_200 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_201 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_202 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_203 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_204 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_205 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_206 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_207 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_208 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_209 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_210 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_211 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_212 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_213 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_214 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_215 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_216 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_217 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_218 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_219 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_t_rec_rawIn_normDist_4 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4} << activated_data_e_act_q_poly_t_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_4 = {_activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_q_poly_t_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_q_poly_t_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_4 = _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_8 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_t_rec_rawIn_isZero_4 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_t_rec_rawIn_4_isZero = activated_data_e_act_q_poly_t_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_4 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_4 = &_activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_t_rec_T_34 = activated_data_e_act_q_poly_t_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_t_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_t_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_t_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_4 & _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_t_rec_rawIn_4_isNaN = _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_4 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_4 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_t_rec_rawIn_4_isInf = _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_t_rec_rawIn_4_sExp = _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_18 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_4 : activated_data_e_act_q_poly_t_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_17, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_t_rec_rawIn_4_sig = _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_32 = activated_data_e_act_q_poly_t_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_33 = activated_data_e_act_q_poly_t_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_q_poly_t_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_35 = {_activated_data_e_act_q_poly_t_rec_T_33[2:1], _activated_data_e_act_q_poly_t_rec_T_33[0] | _activated_data_e_act_q_poly_t_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_t_rec_T_36 = {activated_data_e_act_q_poly_t_rec_rawIn_4_sign, _activated_data_e_act_q_poly_t_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_t_rec_T_37 = activated_data_e_act_q_poly_t_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_t_rec_T_38 = {_activated_data_e_act_q_poly_t_rec_T_36, _activated_data_e_act_q_poly_t_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_t_rec_T_39 = activated_data_e_act_q_poly_t_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_t_rec_4 = {_activated_data_e_act_q_poly_t_rec_T_38, _activated_data_e_act_q_poly_t_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_8 = activated_data_e_act_q_clipped_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_9 = activated_data_e_act_q_clipped_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_8_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_8; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_8 = activated_data_e_act_q_clipped_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_9 = activated_data_e_act_q_clipped_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8 = activated_data_e_act_q_clipped_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9 = activated_data_e_act_q_clipped_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_8 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_8 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_8 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_352 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_353 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_354 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_355 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_356 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_357 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_358 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_359 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_360 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_361 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_362 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_363 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_364 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_365 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_366 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_367 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_368 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_369 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_370 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_371 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_372 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_373 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_374 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_375 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_353 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_376 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_354 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_375; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_377 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_355 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_376; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_378 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_356 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_377; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_379 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_357 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_378; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_380 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_358 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_379; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_381 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_359 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_380; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_382 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_360 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_381; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_383 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_361 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_382; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_384 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_362 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_383; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_385 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_363 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_384; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_386 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_364 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_385; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_387 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_365 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_386; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_388 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_366 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_387; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_389 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_367 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_388; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_390 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_368 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_389; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_391 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_369 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_390; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_392 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_370 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_391; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_393 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_371 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_392; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_394 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_372 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_393; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_395 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_373 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_394; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_8 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_374 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_395; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_16 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_8; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_17 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_16[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_8 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_17, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_40 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_8}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_41 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_8 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_40 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_8}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_42 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_8 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_43 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_42}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_44 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_41} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_43}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_8 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_44[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_16 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_8; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_8 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_8 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_8_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_8 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_8[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_8 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_8; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_66 = activated_data_e_act_q_poly_self_rec_rawIn_8_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_8_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_8_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_8_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_16 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_17 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_8 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_16; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_8_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_8 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_8 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_8_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_17 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_16}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_8_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_32 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_33 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_32}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_34 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_8 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_8 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_8; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_35 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_33, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_34}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_8_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_64 = activated_data_e_act_q_poly_self_rec_rawIn_8_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_65 = activated_data_e_act_q_poly_self_rec_rawIn_8_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_64; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_67 = {_activated_data_e_act_q_poly_self_rec_T_65[2:1], _activated_data_e_act_q_poly_self_rec_T_65[0] | _activated_data_e_act_q_poly_self_rec_T_66}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_68 = {activated_data_e_act_q_poly_self_rec_rawIn_8_sign, _activated_data_e_act_q_poly_self_rec_T_67}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_69 = activated_data_e_act_q_poly_self_rec_rawIn_8_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_70 = {_activated_data_e_act_q_poly_self_rec_T_68, _activated_data_e_act_q_poly_self_rec_T_69}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_71 = activated_data_e_act_q_poly_self_rec_rawIn_8_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_8 = {_activated_data_e_act_q_poly_self_rec_T_70, _activated_data_e_act_q_poly_self_rec_T_71}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_6; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_result_4_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_6 = _activated_data_e_act_q_poly_muladder_6_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_6 = activated_data_e_act_q_poly_result_bits_rawIn_exp_6[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_6 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_6 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_6_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_6 = activated_data_e_act_q_poly_result_bits_rawIn_exp_6[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_6 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_6; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_20; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_6; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_6; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_27; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_6_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_6_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_6_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_6_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_6_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_12 = activated_data_e_act_q_poly_result_bits_rawIn_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_18 = activated_data_e_act_q_poly_result_bits_rawIn_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_13 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_6 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_12; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_6_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_19 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_18; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_20 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_6 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_19; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_6_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_20; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_6 = _activated_data_e_act_q_poly_muladder_6_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_6_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_6; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_6 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_6}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_6_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_6; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_24 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_24}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_26 = _activated_data_e_act_q_poly_muladder_6_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_27 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_25, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_26}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_6_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_27; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_6 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_6_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_12 = activated_data_e_act_q_poly_result_bits_rawIn_6_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_13 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_12}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_6 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_13[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_12 = activated_data_e_act_q_poly_result_bits_rawIn_6_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_13 = _activated_data_e_act_q_poly_result_bits_denormFract_T_12 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_6; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_6 = _activated_data_e_act_q_poly_result_bits_denormFract_T_13[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_36 = activated_data_e_act_q_poly_result_bits_rawIn_6_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_37 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_36} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_38 = _activated_data_e_act_q_poly_result_bits_expOut_T_37[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_39 = activated_data_e_act_q_poly_result_bits_isSubnormal_6 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_38; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_40 = activated_data_e_act_q_poly_result_bits_rawIn_6_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_6_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_41 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_40}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_6 = _activated_data_e_act_q_poly_result_bits_expOut_T_39 | _activated_data_e_act_q_poly_result_bits_expOut_T_41; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_12 = activated_data_e_act_q_poly_result_bits_rawIn_6_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_13 = activated_data_e_act_q_poly_result_bits_rawIn_6_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_12; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_6 = activated_data_e_act_q_poly_result_bits_isSubnormal_6 ? activated_data_e_act_q_poly_result_bits_denormFract_6 : _activated_data_e_act_q_poly_result_bits_fractOut_T_13; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_6 = {activated_data_e_act_q_poly_result_bits_rawIn_6_sign, activated_data_e_act_q_poly_result_bits_expOut_6}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_6 = {activated_data_e_act_q_poly_result_bits_hi_6, activated_data_e_act_q_poly_result_bits_fractOut_6}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_result_4_bits = _activated_data_e_act_q_poly_result_bits_T_6; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_t_rec_rawIn_5_sign = activated_data_e_act_q_poly_t_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_5 = activated_data_e_act_q_poly_t_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_5 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_220 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_221 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_222 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_223 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_224 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_225 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_226 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_227 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_228 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_229 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_230 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_231 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_232 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_233 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_234 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_235 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_236 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_237 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_238 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_239 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_240 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_241 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_242 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_243 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_244 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_245 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_246 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_247 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_248 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_249 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_250 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_251 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_252 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_253 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_254 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_255 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_256 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_257 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_258 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_259 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_260 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_261 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_262 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_263 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_t_rec_rawIn_normDist_5 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5} << activated_data_e_act_q_poly_t_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_11 = _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_5 = {_activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_act_q_poly_t_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_26 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_act_q_poly_t_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_27 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_5 = _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_10 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_t_rec_rawIn_isZero_5 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_5 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_t_rec_rawIn_5_isZero = activated_data_e_act_q_poly_t_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_5 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_5 = &_activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_t_rec_T_42 = activated_data_e_act_q_poly_t_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_t_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_t_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_t_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_11 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_5 & _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_t_rec_rawIn_5_isNaN = _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_5 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_5 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_t_rec_rawIn_5_isInf = _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_t_rec_rawIn_5_sExp = _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_20 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_22 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_5 ? activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_5 : activated_data_e_act_q_poly_t_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_23 = {_activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_21, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_t_rec_rawIn_5_sig = _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_40 = activated_data_e_act_q_poly_t_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_41 = activated_data_e_act_q_poly_t_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_act_q_poly_t_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_43 = {_activated_data_e_act_q_poly_t_rec_T_41[2:1], _activated_data_e_act_q_poly_t_rec_T_41[0] | _activated_data_e_act_q_poly_t_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_t_rec_T_44 = {activated_data_e_act_q_poly_t_rec_rawIn_5_sign, _activated_data_e_act_q_poly_t_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_t_rec_T_45 = activated_data_e_act_q_poly_t_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_t_rec_T_46 = {_activated_data_e_act_q_poly_t_rec_T_44, _activated_data_e_act_q_poly_t_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_t_rec_T_47 = activated_data_e_act_q_poly_t_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_t_rec_5 = {_activated_data_e_act_q_poly_t_rec_T_46, _activated_data_e_act_q_poly_t_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_9_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_9; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_9 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_9 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_9 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_396 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_397 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_398 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_399 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_400 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_401 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_402 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_403 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_404 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_405 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_406 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_407 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_408 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_409 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_410 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_411 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_412 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_413 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_414 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_415 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_416 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_417 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_418 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_419 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_397 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_420 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_398 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_419; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_421 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_399 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_420; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_422 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_400 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_421; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_423 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_401 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_422; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_424 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_402 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_423; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_425 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_403 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_424; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_426 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_404 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_425; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_427 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_405 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_426; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_428 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_406 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_427; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_429 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_407 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_428; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_430 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_408 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_429; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_431 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_409 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_430; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_432 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_410 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_431; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_433 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_411 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_432; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_434 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_412 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_433; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_435 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_413 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_434; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_436 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_414 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_435; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_437 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_415 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_436; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_438 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_416 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_437; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_439 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_417 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_438; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_9 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_418 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_439; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_18 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_9; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_19 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_18[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_9 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_19, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_45 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_9}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_46 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_9 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_45 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_9}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_47 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_9 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_48 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_47}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_49 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_46} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_48}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_9 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_49[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_18 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_9; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_9 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_9 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_9_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_9 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_9[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_9 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_9; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_74 = activated_data_e_act_q_poly_self_rec_rawIn_9_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_9_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_9_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_9_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_18 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_19 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_9 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_18; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_9_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_9 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_9 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_9_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_19 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_18}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_9_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_36 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_37 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_36}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_38 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_9 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_9 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_9; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_39 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_37, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_38}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_9_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_72 = activated_data_e_act_q_poly_self_rec_rawIn_9_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_73 = activated_data_e_act_q_poly_self_rec_rawIn_9_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_72; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_75 = {_activated_data_e_act_q_poly_self_rec_T_73[2:1], _activated_data_e_act_q_poly_self_rec_T_73[0] | _activated_data_e_act_q_poly_self_rec_T_74}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_76 = {activated_data_e_act_q_poly_self_rec_rawIn_9_sign, _activated_data_e_act_q_poly_self_rec_T_75}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_77 = activated_data_e_act_q_poly_self_rec_rawIn_9_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_78 = {_activated_data_e_act_q_poly_self_rec_T_76, _activated_data_e_act_q_poly_self_rec_T_77}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_79 = activated_data_e_act_q_poly_self_rec_rawIn_9_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_9 = {_activated_data_e_act_q_poly_self_rec_T_78, _activated_data_e_act_q_poly_self_rec_T_79}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_7; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_result_5_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_7 = _activated_data_e_act_q_poly_muladder_7_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_7 = activated_data_e_act_q_poly_result_bits_rawIn_exp_7[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_7 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_7 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_7_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_7 = activated_data_e_act_q_poly_result_bits_rawIn_exp_7[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_7 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_7; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_23; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_7; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_7; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_31; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_7_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_7_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_7_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_7_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_7_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_14 = activated_data_e_act_q_poly_result_bits_rawIn_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_21 = activated_data_e_act_q_poly_result_bits_rawIn_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_15 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_7 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_14; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_7_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_22 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_21; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_23 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_7 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_22; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_7_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_23; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_7 = _activated_data_e_act_q_poly_muladder_7_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_7_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_7; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_7 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_7}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_7_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_7; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_28 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_28}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_30 = _activated_data_e_act_q_poly_muladder_7_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_31 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_29, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_30}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_7_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_31; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_7 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_7_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_14 = activated_data_e_act_q_poly_result_bits_rawIn_7_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_15 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_14}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_7 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_15[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_14 = activated_data_e_act_q_poly_result_bits_rawIn_7_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_15 = _activated_data_e_act_q_poly_result_bits_denormFract_T_14 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_7; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_7 = _activated_data_e_act_q_poly_result_bits_denormFract_T_15[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_42 = activated_data_e_act_q_poly_result_bits_rawIn_7_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_43 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_42} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_44 = _activated_data_e_act_q_poly_result_bits_expOut_T_43[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_45 = activated_data_e_act_q_poly_result_bits_isSubnormal_7 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_44; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_46 = activated_data_e_act_q_poly_result_bits_rawIn_7_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_7_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_47 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_46}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_7 = _activated_data_e_act_q_poly_result_bits_expOut_T_45 | _activated_data_e_act_q_poly_result_bits_expOut_T_47; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_14 = activated_data_e_act_q_poly_result_bits_rawIn_7_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_15 = activated_data_e_act_q_poly_result_bits_rawIn_7_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_14; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_7 = activated_data_e_act_q_poly_result_bits_isSubnormal_7 ? activated_data_e_act_q_poly_result_bits_denormFract_7 : _activated_data_e_act_q_poly_result_bits_fractOut_T_15; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_7 = {activated_data_e_act_q_poly_result_bits_rawIn_7_sign, activated_data_e_act_q_poly_result_bits_expOut_7}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_7 = {activated_data_e_act_q_poly_result_bits_hi_7, activated_data_e_act_q_poly_result_bits_fractOut_7}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_result_5_bits = _activated_data_e_act_q_poly_result_bits_T_7; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_m1_rec_rawIn_sign_2 = activated_data_e_act_q_poly_result_4_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_m1_rec_rawIn_2_sign = activated_data_e_act_q_poly_m1_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_m1_rec_rawIn_expIn_2 = activated_data_e_act_q_poly_result_4_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2 = activated_data_e_act_q_poly_result_4_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_poly_m1_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_88 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_89 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_90 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_91 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_92 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_93 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_94 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_95 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_96 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_97 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_98 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_99 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_100 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_101 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_102 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_103 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_104 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_105 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_106 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_107 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_108 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_109 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_110 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_m1_rec_rawIn_normDist_2 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2} << activated_data_e_act_q_poly_m1_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_poly_m1_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_poly_m1_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZero_2 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_m1_rec_rawIn_2_isZero = activated_data_e_act_q_poly_m1_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_m1_rec_T_18 = activated_data_e_act_q_poly_m1_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_m1_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_m1_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_m1_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_m1_rec_rawIn_2_isNaN = _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_2 & activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_m1_rec_rawIn_2_isInf = _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_m1_rec_rawIn_2_sExp = _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_m1_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_2 : activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_m1_rec_rawIn_2_sig = _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_16 = activated_data_e_act_q_poly_m1_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_17 = activated_data_e_act_q_poly_m1_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_poly_m1_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_19 = {_activated_data_e_act_q_poly_m1_rec_T_17[2:1], _activated_data_e_act_q_poly_m1_rec_T_17[0] | _activated_data_e_act_q_poly_m1_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_m1_rec_T_20 = {activated_data_e_act_q_poly_m1_rec_rawIn_2_sign, _activated_data_e_act_q_poly_m1_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_m1_rec_T_21 = activated_data_e_act_q_poly_m1_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_m1_rec_T_22 = {_activated_data_e_act_q_poly_m1_rec_T_20, _activated_data_e_act_q_poly_m1_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_m1_rec_T_23 = activated_data_e_act_q_poly_m1_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_m1_rec_2 = {_activated_data_e_act_q_poly_m1_rec_T_22, _activated_data_e_act_q_poly_m1_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_m2_rec_rawIn_sign_2 = activated_data_e_act_q_poly_result_5_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_m2_rec_rawIn_2_sign = activated_data_e_act_q_poly_m2_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_m2_rec_rawIn_expIn_2 = activated_data_e_act_q_poly_result_5_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2 = activated_data_e_act_q_poly_result_5_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_poly_m2_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_88 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_89 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_90 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_91 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_92 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_93 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_94 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_95 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_96 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_97 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_98 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_99 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_100 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_101 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_102 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_103 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_104 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_105 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_106 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_107 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_108 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_109 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_110 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_m2_rec_rawIn_normDist_2 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2} << activated_data_e_act_q_poly_m2_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_poly_m2_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_poly_m2_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZero_2 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_m2_rec_rawIn_2_isZero = activated_data_e_act_q_poly_m2_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_m2_rec_T_18 = activated_data_e_act_q_poly_m2_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_m2_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_m2_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_m2_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_m2_rec_rawIn_2_isNaN = _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_2 & activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_m2_rec_rawIn_2_isInf = _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_m2_rec_rawIn_2_sExp = _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_m2_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_2 : activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_m2_rec_rawIn_2_sig = _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_16 = activated_data_e_act_q_poly_m2_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_17 = activated_data_e_act_q_poly_m2_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_poly_m2_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_19 = {_activated_data_e_act_q_poly_m2_rec_T_17[2:1], _activated_data_e_act_q_poly_m2_rec_T_17[0] | _activated_data_e_act_q_poly_m2_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_m2_rec_T_20 = {activated_data_e_act_q_poly_m2_rec_rawIn_2_sign, _activated_data_e_act_q_poly_m2_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_m2_rec_T_21 = activated_data_e_act_q_poly_m2_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_m2_rec_T_22 = {_activated_data_e_act_q_poly_m2_rec_T_20, _activated_data_e_act_q_poly_m2_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_m2_rec_T_23 = activated_data_e_act_q_poly_m2_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_m2_rec_2 = {_activated_data_e_act_q_poly_m2_rec_T_22, _activated_data_e_act_q_poly_m2_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_10_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_10; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_10 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_10 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_10 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_440 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_441 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_442 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_443 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_444 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_445 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_446 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_447 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_448 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_449 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_450 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_451 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_452 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_453 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_454 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_455 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_456 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_457 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_458 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_459 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_460 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_461 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_462 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_463 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_441 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_464 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_442 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_463; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_465 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_443 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_464; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_466 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_444 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_465; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_467 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_445 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_466; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_468 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_446 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_467; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_469 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_447 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_468; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_470 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_448 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_469; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_471 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_449 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_470; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_472 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_450 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_471; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_473 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_451 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_472; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_474 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_452 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_473; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_475 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_453 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_474; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_476 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_454 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_475; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_477 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_455 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_476; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_478 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_456 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_477; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_479 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_457 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_478; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_480 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_458 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_479; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_481 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_459 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_480; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_482 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_460 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_481; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_483 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_461 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_482; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_10 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_462 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_483; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_20 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_10; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_21 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_20[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_10 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_21, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_50 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_10}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_51 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_10 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_50 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_10}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_52 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_10 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_53 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_52}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_54 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_51} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_53}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_10 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_54[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_20 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_10; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_10 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_10 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_10_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_10 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_10[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_10 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_10; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_82 = activated_data_e_act_q_poly_self_rec_rawIn_10_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_10_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_10_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_10_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_20 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_21 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_10 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_20; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_10_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_10 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_10 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_10_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_21 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_20}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_10_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_40 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_40}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_42 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_10 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_10 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_10; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_43 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_41, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_42}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_10_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_80 = activated_data_e_act_q_poly_self_rec_rawIn_10_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_81 = activated_data_e_act_q_poly_self_rec_rawIn_10_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_80; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_83 = {_activated_data_e_act_q_poly_self_rec_T_81[2:1], _activated_data_e_act_q_poly_self_rec_T_81[0] | _activated_data_e_act_q_poly_self_rec_T_82}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_84 = {activated_data_e_act_q_poly_self_rec_rawIn_10_sign, _activated_data_e_act_q_poly_self_rec_T_83}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_85 = activated_data_e_act_q_poly_self_rec_rawIn_10_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_86 = {_activated_data_e_act_q_poly_self_rec_T_84, _activated_data_e_act_q_poly_self_rec_T_85}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_87 = activated_data_e_act_q_poly_self_rec_rawIn_10_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_10 = {_activated_data_e_act_q_poly_self_rec_T_86, _activated_data_e_act_q_poly_self_rec_T_87}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_out_2_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_q_poly_out_bits_rawIn_exp_2 = _activated_data_e_act_q_poly_muladder_8_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_out_bits_rawIn_isZero_T_2 = activated_data_e_act_q_poly_out_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_out_bits_rawIn_isZero_2 = _activated_data_e_act_q_poly_out_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_out_bits_rawIn_2_isZero = activated_data_e_act_q_poly_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_out_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_out_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_out_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_out_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_out_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_q_poly_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_6 = activated_data_e_act_q_poly_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_out_bits_rawIn_2_isNaN = _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_8 = activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_out_bits_rawIn_2_isInf = _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T_2 = _activated_data_e_act_q_poly_muladder_8_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_out_bits_rawIn_2_sign = _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_q_poly_out_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_out_bits_rawIn_2_sExp = _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_10 = _activated_data_e_act_q_poly_muladder_8_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_out_bits_rawIn_2_sig = _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_out_bits_isSubnormal_2 = $signed(activated_data_e_act_q_poly_out_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_4 = activated_data_e_act_q_poly_out_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_out_bits_denormShiftDist_2 = _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_out_bits_denormFract_T_4 = activated_data_e_act_q_poly_out_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_out_bits_denormFract_T_5 = _activated_data_e_act_q_poly_out_bits_denormFract_T_4 >> activated_data_e_act_q_poly_out_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_out_bits_denormFract_2 = _activated_data_e_act_q_poly_out_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_12 = activated_data_e_act_q_poly_out_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_out_bits_expOut_T_13 = {1'h0, _activated_data_e_act_q_poly_out_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_14 = _activated_data_e_act_q_poly_out_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_15 = activated_data_e_act_q_poly_out_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_q_poly_out_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_out_bits_expOut_T_16 = activated_data_e_act_q_poly_out_bits_rawIn_2_isNaN | activated_data_e_act_q_poly_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_17 = {8{_activated_data_e_act_q_poly_out_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_out_bits_expOut_2 = _activated_data_e_act_q_poly_out_bits_expOut_T_15 | _activated_data_e_act_q_poly_out_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_out_bits_fractOut_T_4 = activated_data_e_act_q_poly_out_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_out_bits_fractOut_T_5 = activated_data_e_act_q_poly_out_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_q_poly_out_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_out_bits_fractOut_2 = activated_data_e_act_q_poly_out_bits_isSubnormal_2 ? activated_data_e_act_q_poly_out_bits_denormFract_2 : _activated_data_e_act_q_poly_out_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_out_bits_hi_2 = {activated_data_e_act_q_poly_out_bits_rawIn_2_sign, activated_data_e_act_q_poly_out_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_out_bits_T_2 = {activated_data_e_act_q_poly_out_bits_hi_2, activated_data_e_act_q_poly_out_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_out_2_bits = _activated_data_e_act_q_poly_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_11 = activated_data_e_act_q_poly_out_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_11_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_11; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_11 = activated_data_e_act_q_poly_out_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11 = activated_data_e_act_q_poly_out_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_11 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_11 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_11 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_484 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_485 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_486 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_487 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_488 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_489 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_490 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_491 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_492 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_493 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_494 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_495 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_496 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_497 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_498 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_499 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_500 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_501 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_502 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_503 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_504 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_505 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_506 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_507 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_485 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_508 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_486 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_507; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_509 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_487 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_508; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_510 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_488 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_509; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_511 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_489 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_510; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_512 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_490 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_511; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_513 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_491 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_512; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_514 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_492 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_513; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_515 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_493 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_514; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_516 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_494 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_515; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_517 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_495 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_516; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_518 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_496 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_517; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_519 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_497 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_518; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_520 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_498 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_519; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_521 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_499 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_520; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_522 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_500 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_521; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_523 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_501 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_522; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_524 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_502 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_523; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_525 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_503 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_524; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_526 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_504 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_525; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_527 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_505 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_526; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_11 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_506 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_527; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_22 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_11; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_23 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_22[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_11 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_23, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_55 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_11}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_56 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_11 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_55 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_11}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_57 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_11 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_58 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_57}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_59 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_56} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_58}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_11 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_59[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_22 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_11; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_11 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_11 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_11_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_11 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_11[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_11 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_11; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_90 = activated_data_e_act_q_poly_self_rec_rawIn_11_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_11_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_11_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_11_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_22 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_23 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_11 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_22; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_11_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_11 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_11 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_11_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_23 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_22}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_11_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_44 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_45 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_44}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_46 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_11 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_11 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_11; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_47 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_45, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_46}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_11_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_88 = activated_data_e_act_q_poly_self_rec_rawIn_11_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_89 = activated_data_e_act_q_poly_self_rec_rawIn_11_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_88; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_91 = {_activated_data_e_act_q_poly_self_rec_T_89[2:1], _activated_data_e_act_q_poly_self_rec_T_89[0] | _activated_data_e_act_q_poly_self_rec_T_90}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_92 = {activated_data_e_act_q_poly_self_rec_rawIn_11_sign, _activated_data_e_act_q_poly_self_rec_T_91}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_93 = activated_data_e_act_q_poly_self_rec_rawIn_11_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_94 = {_activated_data_e_act_q_poly_self_rec_T_92, _activated_data_e_act_q_poly_self_rec_T_93}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_95 = activated_data_e_act_q_poly_self_rec_rawIn_11_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_11 = {_activated_data_e_act_q_poly_self_rec_T_94, _activated_data_e_act_q_poly_self_rec_T_95}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_8; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_2_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_8 = _activated_data_e_act_q_poly_resizer_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_8 = activated_data_e_act_q_poly_result_bits_rawIn_exp_8[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_8 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_8 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_8_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_8 = activated_data_e_act_q_poly_result_bits_rawIn_exp_8[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_8 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_8; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_26; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_8; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_8; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_35; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_8_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_8_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_8_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_8_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_8_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_16 = activated_data_e_act_q_poly_result_bits_rawIn_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_24 = activated_data_e_act_q_poly_result_bits_rawIn_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_17 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_8 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_16; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_8_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_25 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_24; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_26 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_8 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_25; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_8_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_26; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_8 = _activated_data_e_act_q_poly_resizer_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_8_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_8; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_8 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_8}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_8_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_8; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_32 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_33 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_32}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_34 = _activated_data_e_act_q_poly_resizer_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_35 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_33, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_34}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_8_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_35; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_8 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_8_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_16 = activated_data_e_act_q_poly_result_bits_rawIn_8_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_17 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_16}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_8 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_17[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_16 = activated_data_e_act_q_poly_result_bits_rawIn_8_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_17 = _activated_data_e_act_q_poly_result_bits_denormFract_T_16 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_8; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_8 = _activated_data_e_act_q_poly_result_bits_denormFract_T_17[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_48 = activated_data_e_act_q_poly_result_bits_rawIn_8_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_49 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_48} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_50 = _activated_data_e_act_q_poly_result_bits_expOut_T_49[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_51 = activated_data_e_act_q_poly_result_bits_isSubnormal_8 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_50; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_52 = activated_data_e_act_q_poly_result_bits_rawIn_8_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_8_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_53 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_52}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_8 = _activated_data_e_act_q_poly_result_bits_expOut_T_51 | _activated_data_e_act_q_poly_result_bits_expOut_T_53; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_16 = activated_data_e_act_q_poly_result_bits_rawIn_8_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_17 = activated_data_e_act_q_poly_result_bits_rawIn_8_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_16; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_8 = activated_data_e_act_q_poly_result_bits_isSubnormal_8 ? activated_data_e_act_q_poly_result_bits_denormFract_8 : _activated_data_e_act_q_poly_result_bits_fractOut_T_17; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_8 = {activated_data_e_act_q_poly_result_bits_rawIn_8_sign, activated_data_e_act_q_poly_result_bits_expOut_8}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_8 = {activated_data_e_act_q_poly_result_bits_hi_8, activated_data_e_act_q_poly_result_bits_fractOut_8}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_2_bits = _activated_data_e_act_q_poly_result_bits_T_8; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_erf_t_rec_rawIn_sign_2 = activated_data_e_act_q_poly_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_t_rec_rawIn_2_sign = activated_data_e_act_q_erf_t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_t_rec_rawIn_expIn_2 = activated_data_e_act_q_poly_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2 = activated_data_e_act_q_poly_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_erf_t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_88 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_89 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_90 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_91 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_92 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_93 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_94 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_95 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_96 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_97 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_98 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_99 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_100 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_101 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_102 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_103 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_104 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_105 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_106 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_107 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_108 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_109 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_110 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_t_rec_rawIn_normDist_2 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2} << activated_data_e_act_q_erf_t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_erf_t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_erf_t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_t_rec_rawIn_isZero_2 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_t_rec_rawIn_2_isZero = activated_data_e_act_q_erf_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_t_rec_T_18 = activated_data_e_act_q_erf_t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_t_rec_rawIn_2_isNaN = _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_2 & activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_t_rec_rawIn_2_isInf = _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_t_rec_rawIn_2_sExp = _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_erf_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_2 : activated_data_e_act_q_erf_t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_t_rec_rawIn_2_sig = _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_16 = activated_data_e_act_q_erf_t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_17 = activated_data_e_act_q_erf_t_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_erf_t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_19 = {_activated_data_e_act_q_erf_t_rec_T_17[2:1], _activated_data_e_act_q_erf_t_rec_T_17[0] | _activated_data_e_act_q_erf_t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_t_rec_T_20 = {activated_data_e_act_q_erf_t_rec_rawIn_2_sign, _activated_data_e_act_q_erf_t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_t_rec_T_21 = activated_data_e_act_q_erf_t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_t_rec_T_22 = {_activated_data_e_act_q_erf_t_rec_T_20, _activated_data_e_act_q_erf_t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_t_rec_T_23 = activated_data_e_act_q_erf_t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_t_rec_2 = {_activated_data_e_act_q_erf_t_rec_T_22, _activated_data_e_act_q_erf_t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_erf_self_rec_rawIn_sign_4 = activated_data_e_act_q_sign_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_self_rec_rawIn_4_sign = activated_data_e_act_q_erf_self_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_self_rec_rawIn_expIn_4 = activated_data_e_act_q_sign_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4 = activated_data_e_act_q_sign_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_q_erf_self_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_176 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_177 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_178 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_179 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_180 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_181 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_182 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_183 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_184 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_185 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_186 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_187 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_188 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_189 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_190 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_191 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_192 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_193 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_194 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_195 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_196 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_197 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_198 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_199 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_200 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_201 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_202 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_203 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_204 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_205 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_206 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_207 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_208 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_209 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_210 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_211 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_212 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_213 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_214 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_215 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_216 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_217 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_218 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_219 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_self_rec_rawIn_normDist_4 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4} << activated_data_e_act_q_erf_self_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_4 = {_activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_q_erf_self_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_q_erf_self_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_4 = _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_8 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_self_rec_rawIn_isZero_4 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_self_rec_rawIn_4_isZero = activated_data_e_act_q_erf_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_4 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_4 = &_activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_self_rec_T_34 = activated_data_e_act_q_erf_self_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_self_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_self_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_self_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_4 & _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_self_rec_rawIn_4_isNaN = _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_4 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_4 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_self_rec_rawIn_4_isInf = _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_self_rec_rawIn_4_sExp = _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_18 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_4 : activated_data_e_act_q_erf_self_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_17, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_self_rec_rawIn_4_sig = _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_32 = activated_data_e_act_q_erf_self_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_33 = activated_data_e_act_q_erf_self_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_q_erf_self_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_35 = {_activated_data_e_act_q_erf_self_rec_T_33[2:1], _activated_data_e_act_q_erf_self_rec_T_33[0] | _activated_data_e_act_q_erf_self_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_self_rec_T_36 = {activated_data_e_act_q_erf_self_rec_rawIn_4_sign, _activated_data_e_act_q_erf_self_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_self_rec_T_37 = activated_data_e_act_q_erf_self_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_self_rec_T_38 = {_activated_data_e_act_q_erf_self_rec_T_36, _activated_data_e_act_q_erf_self_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_self_rec_T_39 = activated_data_e_act_q_erf_self_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_self_rec_4 = {_activated_data_e_act_q_erf_self_rec_T_38, _activated_data_e_act_q_erf_self_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_erf_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_erf_out_2_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_q_erf_out_bits_rawIn_exp_2 = _activated_data_e_act_q_erf_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_erf_out_bits_rawIn_isZero_T_2 = activated_data_e_act_q_erf_out_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_erf_out_bits_rawIn_isZero_2 = _activated_data_e_act_q_erf_out_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_erf_out_bits_rawIn_2_isZero = activated_data_e_act_q_erf_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_T_2 = activated_data_e_act_q_erf_out_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_2 = &_activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_erf_out_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_out_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_erf_out_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_erf_out_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_q_erf_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_6 = activated_data_e_act_q_erf_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_erf_out_bits_rawIn_2_isNaN = _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_8 = activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_erf_out_bits_rawIn_2_isInf = _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T_2 = _activated_data_e_act_q_erf_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_erf_out_bits_rawIn_2_sign = _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_q_erf_out_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_erf_out_bits_rawIn_2_sExp = _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_q_erf_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_10 = _activated_data_e_act_q_erf_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_9, _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_erf_out_bits_rawIn_2_sig = _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_erf_out_bits_isSubnormal_2 = $signed(activated_data_e_act_q_erf_out_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_4 = activated_data_e_act_q_erf_out_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_erf_out_bits_denormShiftDist_2 = _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_erf_out_bits_denormFract_T_4 = activated_data_e_act_q_erf_out_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_erf_out_bits_denormFract_T_5 = _activated_data_e_act_q_erf_out_bits_denormFract_T_4 >> activated_data_e_act_q_erf_out_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_erf_out_bits_denormFract_2 = _activated_data_e_act_q_erf_out_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_12 = activated_data_e_act_q_erf_out_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_erf_out_bits_expOut_T_13 = {1'h0, _activated_data_e_act_q_erf_out_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_14 = _activated_data_e_act_q_erf_out_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_15 = activated_data_e_act_q_erf_out_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_q_erf_out_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_erf_out_bits_expOut_T_16 = activated_data_e_act_q_erf_out_bits_rawIn_2_isNaN | activated_data_e_act_q_erf_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_17 = {8{_activated_data_e_act_q_erf_out_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_erf_out_bits_expOut_2 = _activated_data_e_act_q_erf_out_bits_expOut_T_15 | _activated_data_e_act_q_erf_out_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_erf_out_bits_fractOut_T_4 = activated_data_e_act_q_erf_out_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_erf_out_bits_fractOut_T_5 = activated_data_e_act_q_erf_out_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_q_erf_out_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_erf_out_bits_fractOut_2 = activated_data_e_act_q_erf_out_bits_isSubnormal_2 ? activated_data_e_act_q_erf_out_bits_denormFract_2 : _activated_data_e_act_q_erf_out_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_erf_out_bits_hi_2 = {activated_data_e_act_q_erf_out_bits_rawIn_2_sign, activated_data_e_act_q_erf_out_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_erf_out_bits_T_2 = {activated_data_e_act_q_erf_out_bits_hi_2, activated_data_e_act_q_erf_out_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_erf_out_2_bits = _activated_data_e_act_q_erf_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_erf_self_rec_rawIn_sign_5 = activated_data_e_act_q_erf_out_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_self_rec_rawIn_5_sign = activated_data_e_act_q_erf_self_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_self_rec_rawIn_expIn_5 = activated_data_e_act_q_erf_out_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5 = activated_data_e_act_q_erf_out_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_5 = activated_data_e_act_q_erf_self_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_5 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_220 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_221 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_222 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_223 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_224 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_225 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_226 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_227 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_228 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_229 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_230 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_231 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_232 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_233 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_234 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_235 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_236 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_237 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_238 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_239 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_240 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_241 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_242 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_243 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_244 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_245 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_246 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_247 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_248 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_249 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_250 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_251 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_252 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_253 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_254 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_255 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_256 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_257 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_258 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_259 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_260 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_261 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_262 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_263 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_self_rec_rawIn_normDist_5 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5} << activated_data_e_act_q_erf_self_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_11 = _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_5 = {_activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_act_q_erf_self_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_26 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_act_q_erf_self_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_27 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_5 = _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_10 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_self_rec_rawIn_isZero_5 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_5 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_self_rec_rawIn_5_isZero = activated_data_e_act_q_erf_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_5 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_5 = &_activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_self_rec_T_42 = activated_data_e_act_q_erf_self_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_self_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_self_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_self_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_11 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_5 & _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_self_rec_rawIn_5_isNaN = _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_5 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_5 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_self_rec_rawIn_5_isInf = _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_self_rec_rawIn_5_sExp = _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_20 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_22 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_5 ? activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_5 : activated_data_e_act_q_erf_self_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_23 = {_activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_21, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_self_rec_rawIn_5_sig = _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_40 = activated_data_e_act_q_erf_self_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_41 = activated_data_e_act_q_erf_self_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_act_q_erf_self_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_43 = {_activated_data_e_act_q_erf_self_rec_T_41[2:1], _activated_data_e_act_q_erf_self_rec_T_41[0] | _activated_data_e_act_q_erf_self_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_self_rec_T_44 = {activated_data_e_act_q_erf_self_rec_rawIn_5_sign, _activated_data_e_act_q_erf_self_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_self_rec_T_45 = activated_data_e_act_q_erf_self_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_self_rec_T_46 = {_activated_data_e_act_q_erf_self_rec_T_44, _activated_data_e_act_q_erf_self_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_self_rec_T_47 = activated_data_e_act_q_erf_self_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_self_rec_5 = {_activated_data_e_act_q_erf_self_rec_T_46, _activated_data_e_act_q_erf_self_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_erf_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_erf_2_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_erf_result_bits_rawIn_exp_2 = _activated_data_e_act_q_erf_resizer_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_erf_result_bits_rawIn_isZero_T_2 = activated_data_e_act_q_erf_result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_erf_result_bits_rawIn_isZero_2 = _activated_data_e_act_q_erf_result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_erf_result_bits_rawIn_2_isZero = activated_data_e_act_q_erf_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_T_2 = activated_data_e_act_q_erf_result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_2 = &_activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_erf_result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_erf_result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_erf_result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_q_erf_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_6 = activated_data_e_act_q_erf_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_erf_result_bits_rawIn_2_isNaN = _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_8 = activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_erf_result_bits_rawIn_2_isInf = _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T_2 = _activated_data_e_act_q_erf_resizer_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_erf_result_bits_rawIn_2_sign = _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_q_erf_result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_erf_result_bits_rawIn_2_sExp = _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_q_erf_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_10 = _activated_data_e_act_q_erf_resizer_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_9, _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_erf_result_bits_rawIn_2_sig = _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_erf_result_bits_isSubnormal_2 = $signed(activated_data_e_act_q_erf_result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_4 = activated_data_e_act_q_erf_result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_erf_result_bits_denormShiftDist_2 = _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_erf_result_bits_denormFract_T_4 = activated_data_e_act_q_erf_result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_erf_result_bits_denormFract_T_5 = _activated_data_e_act_q_erf_result_bits_denormFract_T_4 >> activated_data_e_act_q_erf_result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_erf_result_bits_denormFract_2 = _activated_data_e_act_q_erf_result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_12 = activated_data_e_act_q_erf_result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_erf_result_bits_expOut_T_13 = {1'h0, _activated_data_e_act_q_erf_result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_14 = _activated_data_e_act_q_erf_result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_15 = activated_data_e_act_q_erf_result_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_q_erf_result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_erf_result_bits_expOut_T_16 = activated_data_e_act_q_erf_result_bits_rawIn_2_isNaN | activated_data_e_act_q_erf_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_17 = {8{_activated_data_e_act_q_erf_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_erf_result_bits_expOut_2 = _activated_data_e_act_q_erf_result_bits_expOut_T_15 | _activated_data_e_act_q_erf_result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_erf_result_bits_fractOut_T_4 = activated_data_e_act_q_erf_result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_erf_result_bits_fractOut_T_5 = activated_data_e_act_q_erf_result_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_q_erf_result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_erf_result_bits_fractOut_2 = activated_data_e_act_q_erf_result_bits_isSubnormal_2 ? activated_data_e_act_q_erf_result_bits_denormFract_2 : _activated_data_e_act_q_erf_result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_erf_result_bits_hi_2 = {activated_data_e_act_q_erf_result_bits_rawIn_2_sign, activated_data_e_act_q_erf_result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_erf_result_bits_T_2 = {activated_data_e_act_q_erf_result_bits_hi_2, activated_data_e_act_q_erf_result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_erf_2_bits = _activated_data_e_act_q_erf_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_t_rec_rawIn_9_sign = activated_data_e_act_t_rec_rawIn_sign_9; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_9 = activated_data_e_act_t_rec_rawIn_expIn_9 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_9 = activated_data_e_act_t_rec_rawIn_fractIn_9 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_t_rec_rawIn_normDist_T_396 = activated_data_e_act_t_rec_rawIn_fractIn_9[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_397 = activated_data_e_act_t_rec_rawIn_fractIn_9[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_398 = activated_data_e_act_t_rec_rawIn_fractIn_9[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_399 = activated_data_e_act_t_rec_rawIn_fractIn_9[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_400 = activated_data_e_act_t_rec_rawIn_fractIn_9[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_401 = activated_data_e_act_t_rec_rawIn_fractIn_9[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_402 = activated_data_e_act_t_rec_rawIn_fractIn_9[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_403 = activated_data_e_act_t_rec_rawIn_fractIn_9[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_404 = activated_data_e_act_t_rec_rawIn_fractIn_9[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_405 = activated_data_e_act_t_rec_rawIn_fractIn_9[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_406 = activated_data_e_act_t_rec_rawIn_fractIn_9[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_407 = activated_data_e_act_t_rec_rawIn_fractIn_9[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_408 = activated_data_e_act_t_rec_rawIn_fractIn_9[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_409 = activated_data_e_act_t_rec_rawIn_fractIn_9[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_410 = activated_data_e_act_t_rec_rawIn_fractIn_9[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_411 = activated_data_e_act_t_rec_rawIn_fractIn_9[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_412 = activated_data_e_act_t_rec_rawIn_fractIn_9[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_413 = activated_data_e_act_t_rec_rawIn_fractIn_9[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_414 = activated_data_e_act_t_rec_rawIn_fractIn_9[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_415 = activated_data_e_act_t_rec_rawIn_fractIn_9[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_416 = activated_data_e_act_t_rec_rawIn_fractIn_9[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_417 = activated_data_e_act_t_rec_rawIn_fractIn_9[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_418 = activated_data_e_act_t_rec_rawIn_fractIn_9[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_419 = _activated_data_e_act_t_rec_rawIn_normDist_T_397 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_420 = _activated_data_e_act_t_rec_rawIn_normDist_T_398 ? 5'h14 : _activated_data_e_act_t_rec_rawIn_normDist_T_419; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_421 = _activated_data_e_act_t_rec_rawIn_normDist_T_399 ? 5'h13 : _activated_data_e_act_t_rec_rawIn_normDist_T_420; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_422 = _activated_data_e_act_t_rec_rawIn_normDist_T_400 ? 5'h12 : _activated_data_e_act_t_rec_rawIn_normDist_T_421; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_423 = _activated_data_e_act_t_rec_rawIn_normDist_T_401 ? 5'h11 : _activated_data_e_act_t_rec_rawIn_normDist_T_422; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_424 = _activated_data_e_act_t_rec_rawIn_normDist_T_402 ? 5'h10 : _activated_data_e_act_t_rec_rawIn_normDist_T_423; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_425 = _activated_data_e_act_t_rec_rawIn_normDist_T_403 ? 5'hF : _activated_data_e_act_t_rec_rawIn_normDist_T_424; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_426 = _activated_data_e_act_t_rec_rawIn_normDist_T_404 ? 5'hE : _activated_data_e_act_t_rec_rawIn_normDist_T_425; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_427 = _activated_data_e_act_t_rec_rawIn_normDist_T_405 ? 5'hD : _activated_data_e_act_t_rec_rawIn_normDist_T_426; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_428 = _activated_data_e_act_t_rec_rawIn_normDist_T_406 ? 5'hC : _activated_data_e_act_t_rec_rawIn_normDist_T_427; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_429 = _activated_data_e_act_t_rec_rawIn_normDist_T_407 ? 5'hB : _activated_data_e_act_t_rec_rawIn_normDist_T_428; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_430 = _activated_data_e_act_t_rec_rawIn_normDist_T_408 ? 5'hA : _activated_data_e_act_t_rec_rawIn_normDist_T_429; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_431 = _activated_data_e_act_t_rec_rawIn_normDist_T_409 ? 5'h9 : _activated_data_e_act_t_rec_rawIn_normDist_T_430; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_432 = _activated_data_e_act_t_rec_rawIn_normDist_T_410 ? 5'h8 : _activated_data_e_act_t_rec_rawIn_normDist_T_431; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_433 = _activated_data_e_act_t_rec_rawIn_normDist_T_411 ? 5'h7 : _activated_data_e_act_t_rec_rawIn_normDist_T_432; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_434 = _activated_data_e_act_t_rec_rawIn_normDist_T_412 ? 5'h6 : _activated_data_e_act_t_rec_rawIn_normDist_T_433; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_435 = _activated_data_e_act_t_rec_rawIn_normDist_T_413 ? 5'h5 : _activated_data_e_act_t_rec_rawIn_normDist_T_434; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_436 = _activated_data_e_act_t_rec_rawIn_normDist_T_414 ? 5'h4 : _activated_data_e_act_t_rec_rawIn_normDist_T_435; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_437 = _activated_data_e_act_t_rec_rawIn_normDist_T_415 ? 5'h3 : _activated_data_e_act_t_rec_rawIn_normDist_T_436; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_438 = _activated_data_e_act_t_rec_rawIn_normDist_T_416 ? 5'h2 : _activated_data_e_act_t_rec_rawIn_normDist_T_437; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_439 = _activated_data_e_act_t_rec_rawIn_normDist_T_417 ? 5'h1 : _activated_data_e_act_t_rec_rawIn_normDist_T_438; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_9 = _activated_data_e_act_t_rec_rawIn_normDist_T_418 ? 5'h0 : _activated_data_e_act_t_rec_rawIn_normDist_T_439; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_18 = {31'h0, activated_data_e_act_t_rec_rawIn_fractIn_9} << activated_data_e_act_t_rec_rawIn_normDist_9; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_19 = _activated_data_e_act_t_rec_rawIn_subnormFract_T_18[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_9 = {_activated_data_e_act_t_rec_rawIn_subnormFract_T_19, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_45 = {4'hF, ~activated_data_e_act_t_rec_rawIn_normDist_9}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_46 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_9 ? _activated_data_e_act_t_rec_rawIn_adjustedExp_T_45 : {1'h0, activated_data_e_act_t_rec_rawIn_expIn_9}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_47 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_9 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_48 = {6'h20, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_47}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_49 = {1'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_46} + {2'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_48}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_9 = _activated_data_e_act_t_rec_rawIn_adjustedExp_T_49[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_18 = activated_data_e_act_t_rec_rawIn_adjustedExp_9; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_t_rec_rawIn_isZero_9 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_9 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_t_rec_rawIn_9_isZero = activated_data_e_act_t_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_9 = activated_data_e_act_t_rec_rawIn_adjustedExp_9[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_t_rec_rawIn_isSpecial_9 = &_activated_data_e_act_t_rec_rawIn_isSpecial_T_9; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_T_74 = activated_data_e_act_t_rec_rawIn_9_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_t_rec_rawIn_9_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_t_rec_rawIn_9_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_t_rec_rawIn_9_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_18 = ~activated_data_e_act_t_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_t_rec_rawIn_out_isNaN_T_19 = activated_data_e_act_t_rec_rawIn_isSpecial_9 & _activated_data_e_act_t_rec_rawIn_out_isNaN_T_18; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_t_rec_rawIn_9_isNaN = _activated_data_e_act_t_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_t_rec_rawIn_out_isInf_T_9 = activated_data_e_act_t_rec_rawIn_isSpecial_9 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_t_rec_rawIn_9_isInf = _activated_data_e_act_t_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_t_rec_rawIn_out_sExp_T_19 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sExp_T_18}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_t_rec_rawIn_9_sExp = _activated_data_e_act_t_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_36 = ~activated_data_e_act_t_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_37 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sig_T_36}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_38 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_9 ? activated_data_e_act_t_rec_rawIn_subnormFract_9 : activated_data_e_act_t_rec_rawIn_fractIn_9; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_t_rec_rawIn_out_sig_T_39 = {_activated_data_e_act_t_rec_rawIn_out_sig_T_37, _activated_data_e_act_t_rec_rawIn_out_sig_T_38}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_t_rec_rawIn_9_sig = _activated_data_e_act_t_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_t_rec_T_72 = activated_data_e_act_t_rec_rawIn_9_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_73 = activated_data_e_act_t_rec_rawIn_9_isZero ? 3'h0 : _activated_data_e_act_t_rec_T_72; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_t_rec_T_75 = {_activated_data_e_act_t_rec_T_73[2:1], _activated_data_e_act_t_rec_T_73[0] | _activated_data_e_act_t_rec_T_74}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_t_rec_T_76 = {activated_data_e_act_t_rec_rawIn_9_sign, _activated_data_e_act_t_rec_T_75}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_t_rec_T_77 = activated_data_e_act_t_rec_rawIn_9_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_t_rec_T_78 = {_activated_data_e_act_t_rec_T_76, _activated_data_e_act_t_rec_T_77}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_t_rec_T_79 = activated_data_e_act_t_rec_rawIn_9_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_t_rec_9 = {_activated_data_e_act_t_rec_T_78, _activated_data_e_act_t_rec_T_79}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_self_rec_rawIn_sign_11 = activated_data_e_act_q_erf_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_11_sign = activated_data_e_act_self_rec_rawIn_sign_11; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_11 = activated_data_e_act_q_erf_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_11 = activated_data_e_act_q_erf_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_11 = activated_data_e_act_self_rec_rawIn_expIn_11 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_11 = activated_data_e_act_self_rec_rawIn_fractIn_11 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_484 = activated_data_e_act_self_rec_rawIn_fractIn_11[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_485 = activated_data_e_act_self_rec_rawIn_fractIn_11[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_486 = activated_data_e_act_self_rec_rawIn_fractIn_11[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_487 = activated_data_e_act_self_rec_rawIn_fractIn_11[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_488 = activated_data_e_act_self_rec_rawIn_fractIn_11[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_489 = activated_data_e_act_self_rec_rawIn_fractIn_11[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_490 = activated_data_e_act_self_rec_rawIn_fractIn_11[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_491 = activated_data_e_act_self_rec_rawIn_fractIn_11[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_492 = activated_data_e_act_self_rec_rawIn_fractIn_11[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_493 = activated_data_e_act_self_rec_rawIn_fractIn_11[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_494 = activated_data_e_act_self_rec_rawIn_fractIn_11[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_495 = activated_data_e_act_self_rec_rawIn_fractIn_11[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_496 = activated_data_e_act_self_rec_rawIn_fractIn_11[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_497 = activated_data_e_act_self_rec_rawIn_fractIn_11[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_498 = activated_data_e_act_self_rec_rawIn_fractIn_11[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_499 = activated_data_e_act_self_rec_rawIn_fractIn_11[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_500 = activated_data_e_act_self_rec_rawIn_fractIn_11[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_501 = activated_data_e_act_self_rec_rawIn_fractIn_11[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_502 = activated_data_e_act_self_rec_rawIn_fractIn_11[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_503 = activated_data_e_act_self_rec_rawIn_fractIn_11[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_504 = activated_data_e_act_self_rec_rawIn_fractIn_11[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_505 = activated_data_e_act_self_rec_rawIn_fractIn_11[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_506 = activated_data_e_act_self_rec_rawIn_fractIn_11[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_507 = _activated_data_e_act_self_rec_rawIn_normDist_T_485 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_508 = _activated_data_e_act_self_rec_rawIn_normDist_T_486 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_507; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_509 = _activated_data_e_act_self_rec_rawIn_normDist_T_487 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_508; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_510 = _activated_data_e_act_self_rec_rawIn_normDist_T_488 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_509; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_511 = _activated_data_e_act_self_rec_rawIn_normDist_T_489 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_510; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_512 = _activated_data_e_act_self_rec_rawIn_normDist_T_490 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_511; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_513 = _activated_data_e_act_self_rec_rawIn_normDist_T_491 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_512; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_514 = _activated_data_e_act_self_rec_rawIn_normDist_T_492 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_513; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_515 = _activated_data_e_act_self_rec_rawIn_normDist_T_493 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_514; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_516 = _activated_data_e_act_self_rec_rawIn_normDist_T_494 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_515; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_517 = _activated_data_e_act_self_rec_rawIn_normDist_T_495 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_516; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_518 = _activated_data_e_act_self_rec_rawIn_normDist_T_496 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_517; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_519 = _activated_data_e_act_self_rec_rawIn_normDist_T_497 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_518; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_520 = _activated_data_e_act_self_rec_rawIn_normDist_T_498 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_519; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_521 = _activated_data_e_act_self_rec_rawIn_normDist_T_499 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_520; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_522 = _activated_data_e_act_self_rec_rawIn_normDist_T_500 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_521; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_523 = _activated_data_e_act_self_rec_rawIn_normDist_T_501 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_522; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_524 = _activated_data_e_act_self_rec_rawIn_normDist_T_502 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_523; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_525 = _activated_data_e_act_self_rec_rawIn_normDist_T_503 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_524; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_526 = _activated_data_e_act_self_rec_rawIn_normDist_T_504 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_525; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_527 = _activated_data_e_act_self_rec_rawIn_normDist_T_505 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_526; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_11 = _activated_data_e_act_self_rec_rawIn_normDist_T_506 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_527; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_22 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_11} << activated_data_e_act_self_rec_rawIn_normDist_11; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_23 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_22[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_11 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_23, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_55 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_11}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_56 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_11 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_55 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_11}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_57 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_11 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_58 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_57}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_59 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_56} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_58}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_11 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_59[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_22 = activated_data_e_act_self_rec_rawIn_adjustedExp_11; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_11 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_11 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_11_isZero = activated_data_e_act_self_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_11 = activated_data_e_act_self_rec_rawIn_adjustedExp_11[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_11 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_11; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_90 = activated_data_e_act_self_rec_rawIn_11_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_11_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_11_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_11_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_22 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_23 = activated_data_e_act_self_rec_rawIn_isSpecial_11 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_22; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_11_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_11 = activated_data_e_act_self_rec_rawIn_isSpecial_11 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_11_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_23 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_22}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_11_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_44 = ~activated_data_e_act_self_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_45 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_44}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_46 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_11 ? activated_data_e_act_self_rec_rawIn_subnormFract_11 : activated_data_e_act_self_rec_rawIn_fractIn_11; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_47 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_45, _activated_data_e_act_self_rec_rawIn_out_sig_T_46}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_11_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_88 = activated_data_e_act_self_rec_rawIn_11_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_89 = activated_data_e_act_self_rec_rawIn_11_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_88; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_91 = {_activated_data_e_act_self_rec_T_89[2:1], _activated_data_e_act_self_rec_T_89[0] | _activated_data_e_act_self_rec_T_90}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_92 = {activated_data_e_act_self_rec_rawIn_11_sign, _activated_data_e_act_self_rec_T_91}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_93 = activated_data_e_act_self_rec_rawIn_11_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_94 = {_activated_data_e_act_self_rec_T_92, _activated_data_e_act_self_rec_T_93}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_95 = activated_data_e_act_self_rec_rawIn_11_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_11 = {_activated_data_e_act_self_rec_T_94, _activated_data_e_act_self_rec_T_95}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_18; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_12_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_9 = _activated_data_e_act_muladder_9_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_9 = activated_data_e_act_result_bits_rawIn_exp_9[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_9 = _activated_data_e_act_result_bits_rawIn_isZero_T_9 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_9_isZero = activated_data_e_act_result_bits_rawIn_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_9 = activated_data_e_act_result_bits_rawIn_exp_9[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_9 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_9; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_29; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_9; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_9; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_39; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_9_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_9_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_9_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_9_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_9_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_18 = activated_data_e_act_result_bits_rawIn_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_27 = activated_data_e_act_result_bits_rawIn_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_19 = activated_data_e_act_result_bits_rawIn_isSpecial_9 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_18; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_9_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_28 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_27; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_29 = activated_data_e_act_result_bits_rawIn_isSpecial_9 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_28; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_9_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_29; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_9 = _activated_data_e_act_muladder_9_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_9_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_9; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_9 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_9}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_9_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_9; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_36 = ~activated_data_e_act_result_bits_rawIn_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_37 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_36}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_38 = _activated_data_e_act_muladder_9_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_39 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_37, _activated_data_e_act_result_bits_rawIn_out_sig_T_38}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_9_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_39; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_9 = $signed(activated_data_e_act_result_bits_rawIn_9_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_18 = activated_data_e_act_result_bits_rawIn_9_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_19 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_18}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_9 = _activated_data_e_act_result_bits_denormShiftDist_T_19[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_18 = activated_data_e_act_result_bits_rawIn_9_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_19 = _activated_data_e_act_result_bits_denormFract_T_18 >> activated_data_e_act_result_bits_denormShiftDist_9; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_9 = _activated_data_e_act_result_bits_denormFract_T_19[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_54 = activated_data_e_act_result_bits_rawIn_9_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_55 = {1'h0, _activated_data_e_act_result_bits_expOut_T_54} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_56 = _activated_data_e_act_result_bits_expOut_T_55[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_57 = activated_data_e_act_result_bits_isSubnormal_9 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_56; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_58 = activated_data_e_act_result_bits_rawIn_9_isNaN | activated_data_e_act_result_bits_rawIn_9_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_59 = {8{_activated_data_e_act_result_bits_expOut_T_58}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_9 = _activated_data_e_act_result_bits_expOut_T_57 | _activated_data_e_act_result_bits_expOut_T_59; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_18 = activated_data_e_act_result_bits_rawIn_9_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_19 = activated_data_e_act_result_bits_rawIn_9_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_18; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_9 = activated_data_e_act_result_bits_isSubnormal_9 ? activated_data_e_act_result_bits_denormFract_9 : _activated_data_e_act_result_bits_fractOut_T_19; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_9 = {activated_data_e_act_result_bits_rawIn_9_sign, activated_data_e_act_result_bits_expOut_9}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_18 = {activated_data_e_act_result_bits_hi_9, activated_data_e_act_result_bits_fractOut_9}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_12_bits = _activated_data_e_act_result_bits_T_18; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_t_rec_rawIn_sign_10 = activated_data_e_act_result_12_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_10_sign = activated_data_e_act_t_rec_rawIn_sign_10; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_10 = activated_data_e_act_result_12_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_10 = activated_data_e_act_result_12_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_10 = activated_data_e_act_t_rec_rawIn_expIn_10 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_10 = activated_data_e_act_t_rec_rawIn_fractIn_10 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_t_rec_rawIn_normDist_T_440 = activated_data_e_act_t_rec_rawIn_fractIn_10[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_441 = activated_data_e_act_t_rec_rawIn_fractIn_10[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_442 = activated_data_e_act_t_rec_rawIn_fractIn_10[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_443 = activated_data_e_act_t_rec_rawIn_fractIn_10[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_444 = activated_data_e_act_t_rec_rawIn_fractIn_10[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_445 = activated_data_e_act_t_rec_rawIn_fractIn_10[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_446 = activated_data_e_act_t_rec_rawIn_fractIn_10[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_447 = activated_data_e_act_t_rec_rawIn_fractIn_10[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_448 = activated_data_e_act_t_rec_rawIn_fractIn_10[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_449 = activated_data_e_act_t_rec_rawIn_fractIn_10[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_450 = activated_data_e_act_t_rec_rawIn_fractIn_10[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_451 = activated_data_e_act_t_rec_rawIn_fractIn_10[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_452 = activated_data_e_act_t_rec_rawIn_fractIn_10[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_453 = activated_data_e_act_t_rec_rawIn_fractIn_10[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_454 = activated_data_e_act_t_rec_rawIn_fractIn_10[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_455 = activated_data_e_act_t_rec_rawIn_fractIn_10[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_456 = activated_data_e_act_t_rec_rawIn_fractIn_10[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_457 = activated_data_e_act_t_rec_rawIn_fractIn_10[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_458 = activated_data_e_act_t_rec_rawIn_fractIn_10[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_459 = activated_data_e_act_t_rec_rawIn_fractIn_10[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_460 = activated_data_e_act_t_rec_rawIn_fractIn_10[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_461 = activated_data_e_act_t_rec_rawIn_fractIn_10[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_462 = activated_data_e_act_t_rec_rawIn_fractIn_10[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_463 = _activated_data_e_act_t_rec_rawIn_normDist_T_441 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_464 = _activated_data_e_act_t_rec_rawIn_normDist_T_442 ? 5'h14 : _activated_data_e_act_t_rec_rawIn_normDist_T_463; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_465 = _activated_data_e_act_t_rec_rawIn_normDist_T_443 ? 5'h13 : _activated_data_e_act_t_rec_rawIn_normDist_T_464; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_466 = _activated_data_e_act_t_rec_rawIn_normDist_T_444 ? 5'h12 : _activated_data_e_act_t_rec_rawIn_normDist_T_465; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_467 = _activated_data_e_act_t_rec_rawIn_normDist_T_445 ? 5'h11 : _activated_data_e_act_t_rec_rawIn_normDist_T_466; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_468 = _activated_data_e_act_t_rec_rawIn_normDist_T_446 ? 5'h10 : _activated_data_e_act_t_rec_rawIn_normDist_T_467; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_469 = _activated_data_e_act_t_rec_rawIn_normDist_T_447 ? 5'hF : _activated_data_e_act_t_rec_rawIn_normDist_T_468; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_470 = _activated_data_e_act_t_rec_rawIn_normDist_T_448 ? 5'hE : _activated_data_e_act_t_rec_rawIn_normDist_T_469; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_471 = _activated_data_e_act_t_rec_rawIn_normDist_T_449 ? 5'hD : _activated_data_e_act_t_rec_rawIn_normDist_T_470; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_472 = _activated_data_e_act_t_rec_rawIn_normDist_T_450 ? 5'hC : _activated_data_e_act_t_rec_rawIn_normDist_T_471; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_473 = _activated_data_e_act_t_rec_rawIn_normDist_T_451 ? 5'hB : _activated_data_e_act_t_rec_rawIn_normDist_T_472; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_474 = _activated_data_e_act_t_rec_rawIn_normDist_T_452 ? 5'hA : _activated_data_e_act_t_rec_rawIn_normDist_T_473; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_475 = _activated_data_e_act_t_rec_rawIn_normDist_T_453 ? 5'h9 : _activated_data_e_act_t_rec_rawIn_normDist_T_474; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_476 = _activated_data_e_act_t_rec_rawIn_normDist_T_454 ? 5'h8 : _activated_data_e_act_t_rec_rawIn_normDist_T_475; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_477 = _activated_data_e_act_t_rec_rawIn_normDist_T_455 ? 5'h7 : _activated_data_e_act_t_rec_rawIn_normDist_T_476; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_478 = _activated_data_e_act_t_rec_rawIn_normDist_T_456 ? 5'h6 : _activated_data_e_act_t_rec_rawIn_normDist_T_477; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_479 = _activated_data_e_act_t_rec_rawIn_normDist_T_457 ? 5'h5 : _activated_data_e_act_t_rec_rawIn_normDist_T_478; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_480 = _activated_data_e_act_t_rec_rawIn_normDist_T_458 ? 5'h4 : _activated_data_e_act_t_rec_rawIn_normDist_T_479; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_481 = _activated_data_e_act_t_rec_rawIn_normDist_T_459 ? 5'h3 : _activated_data_e_act_t_rec_rawIn_normDist_T_480; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_482 = _activated_data_e_act_t_rec_rawIn_normDist_T_460 ? 5'h2 : _activated_data_e_act_t_rec_rawIn_normDist_T_481; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_483 = _activated_data_e_act_t_rec_rawIn_normDist_T_461 ? 5'h1 : _activated_data_e_act_t_rec_rawIn_normDist_T_482; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_10 = _activated_data_e_act_t_rec_rawIn_normDist_T_462 ? 5'h0 : _activated_data_e_act_t_rec_rawIn_normDist_T_483; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_20 = {31'h0, activated_data_e_act_t_rec_rawIn_fractIn_10} << activated_data_e_act_t_rec_rawIn_normDist_10; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_21 = _activated_data_e_act_t_rec_rawIn_subnormFract_T_20[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_10 = {_activated_data_e_act_t_rec_rawIn_subnormFract_T_21, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_50 = {4'hF, ~activated_data_e_act_t_rec_rawIn_normDist_10}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_51 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_10 ? _activated_data_e_act_t_rec_rawIn_adjustedExp_T_50 : {1'h0, activated_data_e_act_t_rec_rawIn_expIn_10}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_52 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_10 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_53 = {6'h20, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_52}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_54 = {1'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_51} + {2'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_53}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_10 = _activated_data_e_act_t_rec_rawIn_adjustedExp_T_54[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_20 = activated_data_e_act_t_rec_rawIn_adjustedExp_10; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_t_rec_rawIn_isZero_10 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_10 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_t_rec_rawIn_10_isZero = activated_data_e_act_t_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_10 = activated_data_e_act_t_rec_rawIn_adjustedExp_10[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_t_rec_rawIn_isSpecial_10 = &_activated_data_e_act_t_rec_rawIn_isSpecial_T_10; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_T_82 = activated_data_e_act_t_rec_rawIn_10_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_t_rec_rawIn_10_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_t_rec_rawIn_10_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_t_rec_rawIn_10_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_20 = ~activated_data_e_act_t_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_t_rec_rawIn_out_isNaN_T_21 = activated_data_e_act_t_rec_rawIn_isSpecial_10 & _activated_data_e_act_t_rec_rawIn_out_isNaN_T_20; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_t_rec_rawIn_10_isNaN = _activated_data_e_act_t_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_t_rec_rawIn_out_isInf_T_10 = activated_data_e_act_t_rec_rawIn_isSpecial_10 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_t_rec_rawIn_10_isInf = _activated_data_e_act_t_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_t_rec_rawIn_out_sExp_T_21 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sExp_T_20}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_t_rec_rawIn_10_sExp = _activated_data_e_act_t_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_40 = ~activated_data_e_act_t_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sig_T_40}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_42 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_10 ? activated_data_e_act_t_rec_rawIn_subnormFract_10 : activated_data_e_act_t_rec_rawIn_fractIn_10; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_t_rec_rawIn_out_sig_T_43 = {_activated_data_e_act_t_rec_rawIn_out_sig_T_41, _activated_data_e_act_t_rec_rawIn_out_sig_T_42}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_t_rec_rawIn_10_sig = _activated_data_e_act_t_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_t_rec_T_80 = activated_data_e_act_t_rec_rawIn_10_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_81 = activated_data_e_act_t_rec_rawIn_10_isZero ? 3'h0 : _activated_data_e_act_t_rec_T_80; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_t_rec_T_83 = {_activated_data_e_act_t_rec_T_81[2:1], _activated_data_e_act_t_rec_T_81[0] | _activated_data_e_act_t_rec_T_82}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_t_rec_T_84 = {activated_data_e_act_t_rec_rawIn_10_sign, _activated_data_e_act_t_rec_T_83}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_t_rec_T_85 = activated_data_e_act_t_rec_rawIn_10_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_t_rec_T_86 = {_activated_data_e_act_t_rec_T_84, _activated_data_e_act_t_rec_T_85}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_t_rec_T_87 = activated_data_e_act_t_rec_rawIn_10_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_t_rec_10 = {_activated_data_e_act_t_rec_T_86, _activated_data_e_act_t_rec_T_87}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_self_rec_rawIn_12_sign = activated_data_e_act_self_rec_rawIn_sign_12; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_12 = activated_data_e_act_self_rec_rawIn_expIn_12 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_12 = activated_data_e_act_self_rec_rawIn_fractIn_12 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_528 = activated_data_e_act_self_rec_rawIn_fractIn_12[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_529 = activated_data_e_act_self_rec_rawIn_fractIn_12[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_530 = activated_data_e_act_self_rec_rawIn_fractIn_12[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_531 = activated_data_e_act_self_rec_rawIn_fractIn_12[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_532 = activated_data_e_act_self_rec_rawIn_fractIn_12[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_533 = activated_data_e_act_self_rec_rawIn_fractIn_12[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_534 = activated_data_e_act_self_rec_rawIn_fractIn_12[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_535 = activated_data_e_act_self_rec_rawIn_fractIn_12[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_536 = activated_data_e_act_self_rec_rawIn_fractIn_12[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_537 = activated_data_e_act_self_rec_rawIn_fractIn_12[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_538 = activated_data_e_act_self_rec_rawIn_fractIn_12[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_539 = activated_data_e_act_self_rec_rawIn_fractIn_12[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_540 = activated_data_e_act_self_rec_rawIn_fractIn_12[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_541 = activated_data_e_act_self_rec_rawIn_fractIn_12[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_542 = activated_data_e_act_self_rec_rawIn_fractIn_12[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_543 = activated_data_e_act_self_rec_rawIn_fractIn_12[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_544 = activated_data_e_act_self_rec_rawIn_fractIn_12[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_545 = activated_data_e_act_self_rec_rawIn_fractIn_12[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_546 = activated_data_e_act_self_rec_rawIn_fractIn_12[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_547 = activated_data_e_act_self_rec_rawIn_fractIn_12[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_548 = activated_data_e_act_self_rec_rawIn_fractIn_12[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_549 = activated_data_e_act_self_rec_rawIn_fractIn_12[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_550 = activated_data_e_act_self_rec_rawIn_fractIn_12[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_551 = _activated_data_e_act_self_rec_rawIn_normDist_T_529 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_552 = _activated_data_e_act_self_rec_rawIn_normDist_T_530 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_551; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_553 = _activated_data_e_act_self_rec_rawIn_normDist_T_531 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_552; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_554 = _activated_data_e_act_self_rec_rawIn_normDist_T_532 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_553; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_555 = _activated_data_e_act_self_rec_rawIn_normDist_T_533 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_554; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_556 = _activated_data_e_act_self_rec_rawIn_normDist_T_534 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_555; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_557 = _activated_data_e_act_self_rec_rawIn_normDist_T_535 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_556; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_558 = _activated_data_e_act_self_rec_rawIn_normDist_T_536 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_557; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_559 = _activated_data_e_act_self_rec_rawIn_normDist_T_537 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_558; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_560 = _activated_data_e_act_self_rec_rawIn_normDist_T_538 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_559; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_561 = _activated_data_e_act_self_rec_rawIn_normDist_T_539 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_560; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_562 = _activated_data_e_act_self_rec_rawIn_normDist_T_540 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_561; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_563 = _activated_data_e_act_self_rec_rawIn_normDist_T_541 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_562; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_564 = _activated_data_e_act_self_rec_rawIn_normDist_T_542 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_563; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_565 = _activated_data_e_act_self_rec_rawIn_normDist_T_543 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_564; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_566 = _activated_data_e_act_self_rec_rawIn_normDist_T_544 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_565; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_567 = _activated_data_e_act_self_rec_rawIn_normDist_T_545 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_566; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_568 = _activated_data_e_act_self_rec_rawIn_normDist_T_546 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_567; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_569 = _activated_data_e_act_self_rec_rawIn_normDist_T_547 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_568; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_570 = _activated_data_e_act_self_rec_rawIn_normDist_T_548 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_569; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_571 = _activated_data_e_act_self_rec_rawIn_normDist_T_549 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_570; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_12 = _activated_data_e_act_self_rec_rawIn_normDist_T_550 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_571; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_24 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_12} << activated_data_e_act_self_rec_rawIn_normDist_12; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_25 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_24[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_12 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_25, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_60 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_12}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_61 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_12 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_60 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_12}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_62 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_12 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_63 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_62}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_64 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_61} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_63}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_12 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_64[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_24 = activated_data_e_act_self_rec_rawIn_adjustedExp_12; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_12 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_12 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_12_isZero = activated_data_e_act_self_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_12 = activated_data_e_act_self_rec_rawIn_adjustedExp_12[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_12 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_12; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_98 = activated_data_e_act_self_rec_rawIn_12_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_12_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_12_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_12_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_24 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_25 = activated_data_e_act_self_rec_rawIn_isSpecial_12 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_24; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_12_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_12 = activated_data_e_act_self_rec_rawIn_isSpecial_12 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_12_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_25 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_24}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_12_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_48 = ~activated_data_e_act_self_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_49 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_48}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_50 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_12 ? activated_data_e_act_self_rec_rawIn_subnormFract_12 : activated_data_e_act_self_rec_rawIn_fractIn_12; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_51 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_49, _activated_data_e_act_self_rec_rawIn_out_sig_T_50}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_12_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_96 = activated_data_e_act_self_rec_rawIn_12_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_97 = activated_data_e_act_self_rec_rawIn_12_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_96; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_99 = {_activated_data_e_act_self_rec_T_97[2:1], _activated_data_e_act_self_rec_T_97[0] | _activated_data_e_act_self_rec_T_98}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_100 = {activated_data_e_act_self_rec_rawIn_12_sign, _activated_data_e_act_self_rec_T_99}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_101 = activated_data_e_act_self_rec_rawIn_12_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_102 = {_activated_data_e_act_self_rec_T_100, _activated_data_e_act_self_rec_T_101}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_103 = activated_data_e_act_self_rec_rawIn_12_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_12 = {_activated_data_e_act_self_rec_T_102, _activated_data_e_act_self_rec_T_103}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_out_2_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_out_bits_rawIn_exp_2 = _activated_data_e_act_muladder_10_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_out_bits_rawIn_isZero_T_2 = activated_data_e_act_out_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_out_bits_rawIn_isZero_2 = _activated_data_e_act_out_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_out_bits_rawIn_2_isZero = activated_data_e_act_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_out_bits_rawIn_isSpecial_T_2 = activated_data_e_act_out_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_out_bits_rawIn_isSpecial_2 = &_activated_data_e_act_out_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_out_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_out_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_out_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_out_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_out_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_6 = activated_data_e_act_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_out_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_out_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_out_bits_rawIn_2_isNaN = _activated_data_e_act_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_out_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_out_bits_rawIn_out_isInf_T_8 = activated_data_e_act_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_out_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_out_bits_rawIn_2_isInf = _activated_data_e_act_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_out_bits_rawIn_out_sign_T_2 = _activated_data_e_act_muladder_10_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_out_bits_rawIn_2_sign = _activated_data_e_act_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_out_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_out_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_out_bits_rawIn_2_sExp = _activated_data_e_act_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_out_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_out_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_10 = _activated_data_e_act_muladder_10_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_out_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_out_bits_rawIn_out_sig_T_9, _activated_data_e_act_out_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_out_bits_rawIn_2_sig = _activated_data_e_act_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_out_bits_isSubnormal_2 = $signed(activated_data_e_act_out_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_out_bits_denormShiftDist_T_4 = activated_data_e_act_out_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_out_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_out_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_out_bits_denormShiftDist_2 = _activated_data_e_act_out_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_out_bits_denormFract_T_4 = activated_data_e_act_out_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_out_bits_denormFract_T_5 = _activated_data_e_act_out_bits_denormFract_T_4 >> activated_data_e_act_out_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_out_bits_denormFract_2 = _activated_data_e_act_out_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_out_bits_expOut_T_12 = activated_data_e_act_out_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_out_bits_expOut_T_13 = {1'h0, _activated_data_e_act_out_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_out_bits_expOut_T_14 = _activated_data_e_act_out_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_out_bits_expOut_T_15 = activated_data_e_act_out_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_out_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_out_bits_expOut_T_16 = activated_data_e_act_out_bits_rawIn_2_isNaN | activated_data_e_act_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_out_bits_expOut_T_17 = {8{_activated_data_e_act_out_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_out_bits_expOut_2 = _activated_data_e_act_out_bits_expOut_T_15 | _activated_data_e_act_out_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_out_bits_fractOut_T_4 = activated_data_e_act_out_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_out_bits_fractOut_T_5 = activated_data_e_act_out_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_out_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_out_bits_fractOut_2 = activated_data_e_act_out_bits_isSubnormal_2 ? activated_data_e_act_out_bits_denormFract_2 : _activated_data_e_act_out_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_out_bits_hi_2 = {activated_data_e_act_out_bits_rawIn_2_sign, activated_data_e_act_out_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_out_bits_T_2 = {activated_data_e_act_out_bits_hi_2, activated_data_e_act_out_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_out_2_bits = _activated_data_e_act_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_self_rec_rawIn_sign_13 = activated_data_e_act_out_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_13_sign = activated_data_e_act_self_rec_rawIn_sign_13; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_13 = activated_data_e_act_out_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_13 = activated_data_e_act_out_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_13 = activated_data_e_act_self_rec_rawIn_expIn_13 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_13 = activated_data_e_act_self_rec_rawIn_fractIn_13 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_572 = activated_data_e_act_self_rec_rawIn_fractIn_13[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_573 = activated_data_e_act_self_rec_rawIn_fractIn_13[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_574 = activated_data_e_act_self_rec_rawIn_fractIn_13[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_575 = activated_data_e_act_self_rec_rawIn_fractIn_13[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_576 = activated_data_e_act_self_rec_rawIn_fractIn_13[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_577 = activated_data_e_act_self_rec_rawIn_fractIn_13[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_578 = activated_data_e_act_self_rec_rawIn_fractIn_13[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_579 = activated_data_e_act_self_rec_rawIn_fractIn_13[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_580 = activated_data_e_act_self_rec_rawIn_fractIn_13[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_581 = activated_data_e_act_self_rec_rawIn_fractIn_13[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_582 = activated_data_e_act_self_rec_rawIn_fractIn_13[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_583 = activated_data_e_act_self_rec_rawIn_fractIn_13[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_584 = activated_data_e_act_self_rec_rawIn_fractIn_13[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_585 = activated_data_e_act_self_rec_rawIn_fractIn_13[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_586 = activated_data_e_act_self_rec_rawIn_fractIn_13[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_587 = activated_data_e_act_self_rec_rawIn_fractIn_13[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_588 = activated_data_e_act_self_rec_rawIn_fractIn_13[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_589 = activated_data_e_act_self_rec_rawIn_fractIn_13[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_590 = activated_data_e_act_self_rec_rawIn_fractIn_13[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_591 = activated_data_e_act_self_rec_rawIn_fractIn_13[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_592 = activated_data_e_act_self_rec_rawIn_fractIn_13[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_593 = activated_data_e_act_self_rec_rawIn_fractIn_13[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_594 = activated_data_e_act_self_rec_rawIn_fractIn_13[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_595 = _activated_data_e_act_self_rec_rawIn_normDist_T_573 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_596 = _activated_data_e_act_self_rec_rawIn_normDist_T_574 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_595; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_597 = _activated_data_e_act_self_rec_rawIn_normDist_T_575 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_596; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_598 = _activated_data_e_act_self_rec_rawIn_normDist_T_576 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_597; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_599 = _activated_data_e_act_self_rec_rawIn_normDist_T_577 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_598; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_600 = _activated_data_e_act_self_rec_rawIn_normDist_T_578 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_599; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_601 = _activated_data_e_act_self_rec_rawIn_normDist_T_579 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_600; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_602 = _activated_data_e_act_self_rec_rawIn_normDist_T_580 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_601; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_603 = _activated_data_e_act_self_rec_rawIn_normDist_T_581 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_602; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_604 = _activated_data_e_act_self_rec_rawIn_normDist_T_582 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_603; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_605 = _activated_data_e_act_self_rec_rawIn_normDist_T_583 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_604; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_606 = _activated_data_e_act_self_rec_rawIn_normDist_T_584 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_605; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_607 = _activated_data_e_act_self_rec_rawIn_normDist_T_585 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_606; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_608 = _activated_data_e_act_self_rec_rawIn_normDist_T_586 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_607; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_609 = _activated_data_e_act_self_rec_rawIn_normDist_T_587 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_608; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_610 = _activated_data_e_act_self_rec_rawIn_normDist_T_588 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_609; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_611 = _activated_data_e_act_self_rec_rawIn_normDist_T_589 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_610; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_612 = _activated_data_e_act_self_rec_rawIn_normDist_T_590 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_611; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_613 = _activated_data_e_act_self_rec_rawIn_normDist_T_591 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_612; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_614 = _activated_data_e_act_self_rec_rawIn_normDist_T_592 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_613; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_615 = _activated_data_e_act_self_rec_rawIn_normDist_T_593 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_614; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_13 = _activated_data_e_act_self_rec_rawIn_normDist_T_594 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_615; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_26 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_13} << activated_data_e_act_self_rec_rawIn_normDist_13; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_27 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_26[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_13 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_27, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_65 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_13}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_66 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_13 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_65 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_13}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_67 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_13 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_68 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_67}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_69 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_66} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_68}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_13 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_69[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_26 = activated_data_e_act_self_rec_rawIn_adjustedExp_13; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_13 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_13 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_13_isZero = activated_data_e_act_self_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_13 = activated_data_e_act_self_rec_rawIn_adjustedExp_13[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_13 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_13; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_106 = activated_data_e_act_self_rec_rawIn_13_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_13_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_13_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_13_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_26 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_27 = activated_data_e_act_self_rec_rawIn_isSpecial_13 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_26; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_13_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_13 = activated_data_e_act_self_rec_rawIn_isSpecial_13 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_13_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_27 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_26}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_13_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_52 = ~activated_data_e_act_self_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_53 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_52}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_54 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_13 ? activated_data_e_act_self_rec_rawIn_subnormFract_13 : activated_data_e_act_self_rec_rawIn_fractIn_13; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_55 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_53, _activated_data_e_act_self_rec_rawIn_out_sig_T_54}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_13_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_104 = activated_data_e_act_self_rec_rawIn_13_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_105 = activated_data_e_act_self_rec_rawIn_13_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_104; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_107 = {_activated_data_e_act_self_rec_T_105[2:1], _activated_data_e_act_self_rec_T_105[0] | _activated_data_e_act_self_rec_T_106}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_108 = {activated_data_e_act_self_rec_rawIn_13_sign, _activated_data_e_act_self_rec_T_107}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_109 = activated_data_e_act_self_rec_rawIn_13_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_110 = {_activated_data_e_act_self_rec_T_108, _activated_data_e_act_self_rec_T_109}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_111 = activated_data_e_act_self_rec_rawIn_13_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_13 = {_activated_data_e_act_self_rec_T_110, _activated_data_e_act_self_rec_T_111}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_19; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_13_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_10 = _activated_data_e_act_resizer_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_10 = activated_data_e_act_result_bits_rawIn_exp_10[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_10 = _activated_data_e_act_result_bits_rawIn_isZero_T_10 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_10_isZero = activated_data_e_act_result_bits_rawIn_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_10 = activated_data_e_act_result_bits_rawIn_exp_10[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_10 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_10; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_32; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_10; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_10; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_43; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_10_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_10_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_10_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_10_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_10_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_20 = activated_data_e_act_result_bits_rawIn_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_30 = activated_data_e_act_result_bits_rawIn_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_21 = activated_data_e_act_result_bits_rawIn_isSpecial_10 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_20; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_10_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_31 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_30; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_32 = activated_data_e_act_result_bits_rawIn_isSpecial_10 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_31; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_10_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_32; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_10 = _activated_data_e_act_resizer_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_10_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_10; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_10 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_10}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_10_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_10; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_40 = ~activated_data_e_act_result_bits_rawIn_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_40}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_42 = _activated_data_e_act_resizer_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_43 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_41, _activated_data_e_act_result_bits_rawIn_out_sig_T_42}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_10_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_43; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_10 = $signed(activated_data_e_act_result_bits_rawIn_10_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_20 = activated_data_e_act_result_bits_rawIn_10_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_21 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_20}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_10 = _activated_data_e_act_result_bits_denormShiftDist_T_21[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_20 = activated_data_e_act_result_bits_rawIn_10_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_21 = _activated_data_e_act_result_bits_denormFract_T_20 >> activated_data_e_act_result_bits_denormShiftDist_10; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_10 = _activated_data_e_act_result_bits_denormFract_T_21[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_60 = activated_data_e_act_result_bits_rawIn_10_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_61 = {1'h0, _activated_data_e_act_result_bits_expOut_T_60} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_62 = _activated_data_e_act_result_bits_expOut_T_61[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_63 = activated_data_e_act_result_bits_isSubnormal_10 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_62; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_64 = activated_data_e_act_result_bits_rawIn_10_isNaN | activated_data_e_act_result_bits_rawIn_10_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_65 = {8{_activated_data_e_act_result_bits_expOut_T_64}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_10 = _activated_data_e_act_result_bits_expOut_T_63 | _activated_data_e_act_result_bits_expOut_T_65; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_20 = activated_data_e_act_result_bits_rawIn_10_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_21 = activated_data_e_act_result_bits_rawIn_10_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_20; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_10 = activated_data_e_act_result_bits_isSubnormal_10 ? activated_data_e_act_result_bits_denormFract_10 : _activated_data_e_act_result_bits_fractOut_T_21; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_10 = {activated_data_e_act_result_bits_rawIn_10_sign, activated_data_e_act_result_bits_expOut_10}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_19 = {activated_data_e_act_result_bits_hi_10, activated_data_e_act_result_bits_fractOut_10}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_13_bits = _activated_data_e_act_result_bits_T_19; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_self_rec_rawIn_14_sign = activated_data_e_act_self_rec_rawIn_sign_14; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_14 = activated_data_e_act_self_rec_rawIn_expIn_14 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_14 = activated_data_e_act_self_rec_rawIn_fractIn_14 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_616 = activated_data_e_act_self_rec_rawIn_fractIn_14[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_617 = activated_data_e_act_self_rec_rawIn_fractIn_14[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_618 = activated_data_e_act_self_rec_rawIn_fractIn_14[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_619 = activated_data_e_act_self_rec_rawIn_fractIn_14[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_620 = activated_data_e_act_self_rec_rawIn_fractIn_14[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_621 = activated_data_e_act_self_rec_rawIn_fractIn_14[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_622 = activated_data_e_act_self_rec_rawIn_fractIn_14[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_623 = activated_data_e_act_self_rec_rawIn_fractIn_14[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_624 = activated_data_e_act_self_rec_rawIn_fractIn_14[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_625 = activated_data_e_act_self_rec_rawIn_fractIn_14[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_626 = activated_data_e_act_self_rec_rawIn_fractIn_14[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_627 = activated_data_e_act_self_rec_rawIn_fractIn_14[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_628 = activated_data_e_act_self_rec_rawIn_fractIn_14[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_629 = activated_data_e_act_self_rec_rawIn_fractIn_14[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_630 = activated_data_e_act_self_rec_rawIn_fractIn_14[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_631 = activated_data_e_act_self_rec_rawIn_fractIn_14[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_632 = activated_data_e_act_self_rec_rawIn_fractIn_14[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_633 = activated_data_e_act_self_rec_rawIn_fractIn_14[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_634 = activated_data_e_act_self_rec_rawIn_fractIn_14[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_635 = activated_data_e_act_self_rec_rawIn_fractIn_14[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_636 = activated_data_e_act_self_rec_rawIn_fractIn_14[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_637 = activated_data_e_act_self_rec_rawIn_fractIn_14[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_638 = activated_data_e_act_self_rec_rawIn_fractIn_14[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_639 = _activated_data_e_act_self_rec_rawIn_normDist_T_617 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_640 = _activated_data_e_act_self_rec_rawIn_normDist_T_618 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_639; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_641 = _activated_data_e_act_self_rec_rawIn_normDist_T_619 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_640; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_642 = _activated_data_e_act_self_rec_rawIn_normDist_T_620 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_641; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_643 = _activated_data_e_act_self_rec_rawIn_normDist_T_621 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_642; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_644 = _activated_data_e_act_self_rec_rawIn_normDist_T_622 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_643; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_645 = _activated_data_e_act_self_rec_rawIn_normDist_T_623 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_644; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_646 = _activated_data_e_act_self_rec_rawIn_normDist_T_624 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_645; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_647 = _activated_data_e_act_self_rec_rawIn_normDist_T_625 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_646; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_648 = _activated_data_e_act_self_rec_rawIn_normDist_T_626 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_647; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_649 = _activated_data_e_act_self_rec_rawIn_normDist_T_627 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_648; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_650 = _activated_data_e_act_self_rec_rawIn_normDist_T_628 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_649; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_651 = _activated_data_e_act_self_rec_rawIn_normDist_T_629 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_650; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_652 = _activated_data_e_act_self_rec_rawIn_normDist_T_630 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_651; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_653 = _activated_data_e_act_self_rec_rawIn_normDist_T_631 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_652; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_654 = _activated_data_e_act_self_rec_rawIn_normDist_T_632 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_653; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_655 = _activated_data_e_act_self_rec_rawIn_normDist_T_633 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_654; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_656 = _activated_data_e_act_self_rec_rawIn_normDist_T_634 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_655; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_657 = _activated_data_e_act_self_rec_rawIn_normDist_T_635 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_656; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_658 = _activated_data_e_act_self_rec_rawIn_normDist_T_636 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_657; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_659 = _activated_data_e_act_self_rec_rawIn_normDist_T_637 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_658; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_14 = _activated_data_e_act_self_rec_rawIn_normDist_T_638 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_659; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_28 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_14} << activated_data_e_act_self_rec_rawIn_normDist_14; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_29 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_28[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_14 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_29, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_70 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_14}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_71 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_14 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_70 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_14}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_72 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_14 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_73 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_72}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_74 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_71} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_73}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_14 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_74[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_28 = activated_data_e_act_self_rec_rawIn_adjustedExp_14; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_14 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_14 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_14_isZero = activated_data_e_act_self_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_14 = activated_data_e_act_self_rec_rawIn_adjustedExp_14[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_14 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_14; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_114 = activated_data_e_act_self_rec_rawIn_14_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_14_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_14_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_14_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_28 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_29 = activated_data_e_act_self_rec_rawIn_isSpecial_14 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_28; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_14_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_14 = activated_data_e_act_self_rec_rawIn_isSpecial_14 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_14_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_29 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_28}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_14_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_56 = ~activated_data_e_act_self_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_57 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_56}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_58 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_14 ? activated_data_e_act_self_rec_rawIn_subnormFract_14 : activated_data_e_act_self_rec_rawIn_fractIn_14; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_59 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_57, _activated_data_e_act_self_rec_rawIn_out_sig_T_58}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_14_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_112 = activated_data_e_act_self_rec_rawIn_14_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_113 = activated_data_e_act_self_rec_rawIn_14_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_112; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_115 = {_activated_data_e_act_self_rec_T_113[2:1], _activated_data_e_act_self_rec_T_113[0] | _activated_data_e_act_self_rec_T_114}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_116 = {activated_data_e_act_self_rec_rawIn_14_sign, _activated_data_e_act_self_rec_T_115}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_117 = activated_data_e_act_self_rec_rawIn_14_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_118 = {_activated_data_e_act_self_rec_T_116, _activated_data_e_act_self_rec_T_117}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_119 = activated_data_e_act_self_rec_rawIn_14_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_14 = {_activated_data_e_act_self_rec_T_118, _activated_data_e_act_self_rec_T_119}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_20; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_14_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_11 = _activated_data_e_act_muladder_11_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_11 = activated_data_e_act_result_bits_rawIn_exp_11[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_11 = _activated_data_e_act_result_bits_rawIn_isZero_T_11 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_11_isZero = activated_data_e_act_result_bits_rawIn_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_11 = activated_data_e_act_result_bits_rawIn_exp_11[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_11 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_11; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_35; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_11; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_11; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_47; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_11_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_11_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_11_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_11_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_11_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_22 = activated_data_e_act_result_bits_rawIn_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_33 = activated_data_e_act_result_bits_rawIn_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_23 = activated_data_e_act_result_bits_rawIn_isSpecial_11 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_22; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_11_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_34 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_33; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_35 = activated_data_e_act_result_bits_rawIn_isSpecial_11 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_34; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_11_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_35; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_11 = _activated_data_e_act_muladder_11_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_11_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_11; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_11 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_11}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_11_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_11; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_44 = ~activated_data_e_act_result_bits_rawIn_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_45 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_44}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_46 = _activated_data_e_act_muladder_11_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_47 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_45, _activated_data_e_act_result_bits_rawIn_out_sig_T_46}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_11_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_47; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_11 = $signed(activated_data_e_act_result_bits_rawIn_11_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_22 = activated_data_e_act_result_bits_rawIn_11_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_23 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_22}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_11 = _activated_data_e_act_result_bits_denormShiftDist_T_23[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_22 = activated_data_e_act_result_bits_rawIn_11_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_23 = _activated_data_e_act_result_bits_denormFract_T_22 >> activated_data_e_act_result_bits_denormShiftDist_11; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_11 = _activated_data_e_act_result_bits_denormFract_T_23[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_66 = activated_data_e_act_result_bits_rawIn_11_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_67 = {1'h0, _activated_data_e_act_result_bits_expOut_T_66} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_68 = _activated_data_e_act_result_bits_expOut_T_67[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_69 = activated_data_e_act_result_bits_isSubnormal_11 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_68; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_70 = activated_data_e_act_result_bits_rawIn_11_isNaN | activated_data_e_act_result_bits_rawIn_11_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_71 = {8{_activated_data_e_act_result_bits_expOut_T_70}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_11 = _activated_data_e_act_result_bits_expOut_T_69 | _activated_data_e_act_result_bits_expOut_T_71; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_22 = activated_data_e_act_result_bits_rawIn_11_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_23 = activated_data_e_act_result_bits_rawIn_11_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_22; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_11 = activated_data_e_act_result_bits_isSubnormal_11 ? activated_data_e_act_result_bits_denormFract_11 : _activated_data_e_act_result_bits_fractOut_T_23; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_11 = {activated_data_e_act_result_bits_rawIn_11_sign, activated_data_e_act_result_bits_expOut_11}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_20 = {activated_data_e_act_result_bits_hi_11, activated_data_e_act_result_bits_fractOut_11}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_14_bits = _activated_data_e_act_result_bits_T_20; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_neg_q_iexp_t_sgn_2 = activated_data_e_act_result_14_bits[31]; // @[Arithmetic.scala:426:26, :432:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_sign_4 = activated_data_e_act_result_14_bits[31]; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_neg_q_iexp_neg_t_T_8 = ~activated_data_e_act_neg_q_iexp_t_sgn_2; // @[Arithmetic.scala:432:27, :433:25] wire [30:0] _activated_data_e_act_neg_q_iexp_neg_t_T_9 = activated_data_e_act_result_14_bits[30:0]; // @[Arithmetic.scala:426:26, :433:39] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_T_10 = {_activated_data_e_act_neg_q_iexp_neg_t_T_8, _activated_data_e_act_neg_q_iexp_neg_t_T_9}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_WIRE_2 = _activated_data_e_act_neg_q_iexp_neg_t_T_10; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_T_11; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_neg_q_iexp_neg_t_2_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_neg_q_iexp_neg_t_T_11 = _activated_data_e_act_neg_q_iexp_neg_t_WIRE_2; // @[Arithmetic.scala:433:65] assign activated_data_e_act_neg_q_iexp_neg_t_2_bits = _activated_data_e_act_neg_q_iexp_neg_t_T_11; // @[Arithmetic.scala:433:65] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_sign_2 = activated_data_e_act_neg_q_iexp_neg_t_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_sign = activated_data_e_act_neg_q_iexp_t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn_2 = activated_data_e_act_neg_q_iexp_neg_t_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2 = activated_data_e_act_neg_q_iexp_neg_t_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_88 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_89 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_90 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_91 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_92 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_93 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_94 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_95 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_96 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_97 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_98 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_99 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_100 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_101 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_102 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_103 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_104 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_105 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_106 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_107 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_108 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_109 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_110 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_111 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_112 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_113 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_114 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_115 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_116 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_117 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_118 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_119 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_120 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_121 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_122 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_123 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_124 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_125 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_126 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_127 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_128 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_129 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_130 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_131 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_2 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2} << activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_2 = {_activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_2 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_4 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_2 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_isZero = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_T_2 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_2 = &_activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_neg_q_iexp_t_rec_T_18 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_2 & _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_isNaN = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T_2 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_2 & activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_isInf = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_sExp = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_10 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_2 : activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_9, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_sig = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_16 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_17 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_neg_q_iexp_t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_19 = {_activated_data_e_act_neg_q_iexp_t_rec_T_17[2:1], _activated_data_e_act_neg_q_iexp_t_rec_T_17[0] | _activated_data_e_act_neg_q_iexp_t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_neg_q_iexp_t_rec_T_20 = {activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_sign, _activated_data_e_act_neg_q_iexp_t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_neg_q_iexp_t_rec_T_21 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_T_22 = {_activated_data_e_act_neg_q_iexp_t_rec_T_20, _activated_data_e_act_neg_q_iexp_t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_neg_q_iexp_t_rec_T_23 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_neg_q_iexp_t_rec_2 = {_activated_data_e_act_neg_q_iexp_t_rec_T_22, _activated_data_e_act_neg_q_iexp_t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_neg_q_iexp_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_neg_q_iexp_2_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_2 = _activated_data_e_act_neg_q_iexp_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_T_2 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_2 = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_isZero = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_T_2 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_2 = &_activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_6 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_isNaN = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_8 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_isInf = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T_2 = _activated_data_e_act_neg_q_iexp_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sign = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sExp = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_10 = _activated_data_e_act_neg_q_iexp_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_9, _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sig = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_neg_q_iexp_result_bits_isSubnormal_2 = $signed(activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_4 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_2 = _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_4 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_5 = _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_4 >> activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_neg_q_iexp_result_bits_denormFract_2 = _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_12 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_13 = {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_14 = _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_15 = activated_data_e_act_neg_q_iexp_result_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_16 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_isNaN | activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_17 = {8{_activated_data_e_act_neg_q_iexp_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_neg_q_iexp_result_bits_expOut_2 = _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_15 | _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_4 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_5 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_neg_q_iexp_result_bits_fractOut_2 = activated_data_e_act_neg_q_iexp_result_bits_isSubnormal_2 ? activated_data_e_act_neg_q_iexp_result_bits_denormFract_2 : _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_neg_q_iexp_result_bits_hi_2 = {activated_data_e_act_neg_q_iexp_result_bits_rawIn_2_sign, activated_data_e_act_neg_q_iexp_result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_neg_q_iexp_result_bits_T_2 = {activated_data_e_act_neg_q_iexp_result_bits_hi_2, activated_data_e_act_neg_q_iexp_result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_neg_q_iexp_2_bits = _activated_data_e_act_neg_q_iexp_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_z_iexp_t_rec_rawIn_2_sign = activated_data_e_act_z_iexp_t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_z_iexp_t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_88 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_89 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_90 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_91 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_92 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_93 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_94 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_95 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_96 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_97 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_98 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_99 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_100 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_101 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_102 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_103 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_104 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_105 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_106 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_107 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_108 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_109 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_110 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_111 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_112 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_113 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_114 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_115 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_116 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_117 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_118 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_119 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_120 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_121 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_122 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_123 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_124 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_125 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_126 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_127 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_128 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_129 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_130 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_131 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_z_iexp_t_rec_rawIn_normDist_2 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2} << activated_data_e_act_z_iexp_t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_2 = {_activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_z_iexp_t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_z_iexp_t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_2 = _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_4 = activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZero_2 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_z_iexp_t_rec_rawIn_2_isZero = activated_data_e_act_z_iexp_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_T_2 = activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_2 = &_activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_z_iexp_t_rec_T_18 = activated_data_e_act_z_iexp_t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_z_iexp_t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_z_iexp_t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_z_iexp_t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_2 & _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_z_iexp_t_rec_rawIn_2_isNaN = _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T_2 = activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_2 & activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_z_iexp_t_rec_rawIn_2_isInf = _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_z_iexp_t_rec_rawIn_2_sExp = _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_z_iexp_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_10 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_2 : activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_9, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_z_iexp_t_rec_rawIn_2_sig = _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_16 = activated_data_e_act_z_iexp_t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_17 = activated_data_e_act_z_iexp_t_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_z_iexp_t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_19 = {_activated_data_e_act_z_iexp_t_rec_T_17[2:1], _activated_data_e_act_z_iexp_t_rec_T_17[0] | _activated_data_e_act_z_iexp_t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_z_iexp_t_rec_T_20 = {activated_data_e_act_z_iexp_t_rec_rawIn_2_sign, _activated_data_e_act_z_iexp_t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_z_iexp_t_rec_T_21 = activated_data_e_act_z_iexp_t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_z_iexp_t_rec_T_22 = {_activated_data_e_act_z_iexp_t_rec_T_20, _activated_data_e_act_z_iexp_t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_z_iexp_t_rec_T_23 = activated_data_e_act_z_iexp_t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_z_iexp_t_rec_2 = {_activated_data_e_act_z_iexp_t_rec_T_22, _activated_data_e_act_z_iexp_t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_z_iexp_self_rec_rawIn_sign_2 = activated_data_e_act_neg_q_iexp_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_z_iexp_self_rec_rawIn_2_sign = activated_data_e_act_z_iexp_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_z_iexp_self_rec_rawIn_expIn_2 = activated_data_e_act_neg_q_iexp_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2 = activated_data_e_act_neg_q_iexp_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_z_iexp_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_88 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_89 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_90 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_91 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_92 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_93 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_94 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_95 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_96 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_97 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_98 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_99 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_100 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_101 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_102 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_103 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_104 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_105 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_106 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_107 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_108 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_109 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_110 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_111 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_112 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_113 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_114 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_115 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_116 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_117 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_118 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_119 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_120 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_121 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_122 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_123 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_124 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_125 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_126 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_127 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_128 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_129 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_130 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_131 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_z_iexp_self_rec_rawIn_normDist_2 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2} << activated_data_e_act_z_iexp_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_2 = {_activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_z_iexp_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_z_iexp_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_2 = _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_4 = activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZero_2 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_z_iexp_self_rec_rawIn_2_isZero = activated_data_e_act_z_iexp_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_T_2 = activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_2 = &_activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_z_iexp_self_rec_T_18 = activated_data_e_act_z_iexp_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_z_iexp_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_z_iexp_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_z_iexp_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_2 & _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_z_iexp_self_rec_rawIn_2_isNaN = _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T_2 = activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_2 & activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_z_iexp_self_rec_rawIn_2_isInf = _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_z_iexp_self_rec_rawIn_2_sExp = _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_z_iexp_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_10 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_2 : activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_9, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_z_iexp_self_rec_rawIn_2_sig = _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_16 = activated_data_e_act_z_iexp_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_17 = activated_data_e_act_z_iexp_self_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_z_iexp_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_19 = {_activated_data_e_act_z_iexp_self_rec_T_17[2:1], _activated_data_e_act_z_iexp_self_rec_T_17[0] | _activated_data_e_act_z_iexp_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_z_iexp_self_rec_T_20 = {activated_data_e_act_z_iexp_self_rec_rawIn_2_sign, _activated_data_e_act_z_iexp_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_z_iexp_self_rec_T_21 = activated_data_e_act_z_iexp_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_z_iexp_self_rec_T_22 = {_activated_data_e_act_z_iexp_self_rec_T_20, _activated_data_e_act_z_iexp_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_z_iexp_self_rec_T_23 = activated_data_e_act_z_iexp_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_z_iexp_self_rec_2 = {_activated_data_e_act_z_iexp_self_rec_T_22, _activated_data_e_act_z_iexp_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_z_iexp_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_z_iexp_out_2_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_z_iexp_out_bits_rawIn_exp_2 = _activated_data_e_act_z_iexp_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_z_iexp_out_bits_rawIn_isZero_T_2 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_z_iexp_out_bits_rawIn_isZero_2 = _activated_data_e_act_z_iexp_out_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_z_iexp_out_bits_rawIn_2_isZero = activated_data_e_act_z_iexp_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_T_2 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_2 = &_activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_z_iexp_out_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_z_iexp_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_z_iexp_out_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_z_iexp_out_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_z_iexp_out_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_6 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_z_iexp_out_bits_rawIn_2_isNaN = _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_8 = activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_z_iexp_out_bits_rawIn_2_isInf = _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T_2 = _activated_data_e_act_z_iexp_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_z_iexp_out_bits_rawIn_2_sign = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_z_iexp_out_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_z_iexp_out_bits_rawIn_2_sExp = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_z_iexp_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_10 = _activated_data_e_act_z_iexp_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_9, _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_z_iexp_out_bits_rawIn_2_sig = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_z_iexp_out_bits_isSubnormal_2 = $signed(activated_data_e_act_z_iexp_out_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_4 = activated_data_e_act_z_iexp_out_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_z_iexp_out_bits_denormShiftDist_2 = _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_z_iexp_out_bits_denormFract_T_4 = activated_data_e_act_z_iexp_out_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_z_iexp_out_bits_denormFract_T_5 = _activated_data_e_act_z_iexp_out_bits_denormFract_T_4 >> activated_data_e_act_z_iexp_out_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_z_iexp_out_bits_denormFract_2 = _activated_data_e_act_z_iexp_out_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_12 = activated_data_e_act_z_iexp_out_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_13 = {1'h0, _activated_data_e_act_z_iexp_out_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_14 = _activated_data_e_act_z_iexp_out_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_15 = activated_data_e_act_z_iexp_out_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_z_iexp_out_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_z_iexp_out_bits_expOut_T_16 = activated_data_e_act_z_iexp_out_bits_rawIn_2_isNaN | activated_data_e_act_z_iexp_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_17 = {8{_activated_data_e_act_z_iexp_out_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_z_iexp_out_bits_expOut_2 = _activated_data_e_act_z_iexp_out_bits_expOut_T_15 | _activated_data_e_act_z_iexp_out_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_z_iexp_out_bits_fractOut_T_4 = activated_data_e_act_z_iexp_out_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_z_iexp_out_bits_fractOut_T_5 = activated_data_e_act_z_iexp_out_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_z_iexp_out_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_z_iexp_out_bits_fractOut_2 = activated_data_e_act_z_iexp_out_bits_isSubnormal_2 ? activated_data_e_act_z_iexp_out_bits_denormFract_2 : _activated_data_e_act_z_iexp_out_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_z_iexp_out_bits_hi_2 = {activated_data_e_act_z_iexp_out_bits_rawIn_2_sign, activated_data_e_act_z_iexp_out_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_z_iexp_out_bits_T_2 = {activated_data_e_act_z_iexp_out_bits_hi_2, activated_data_e_act_z_iexp_out_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_z_iexp_out_2_bits = _activated_data_e_act_z_iexp_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [15:0] _activated_data_e_act_z_iexp_T_4 = activated_data_e_act_z_iexp_out_2_bits[31:16]; // @[Arithmetic.scala:350:23] wire [31:0] _activated_data_e_act_z_iexp_T_5; // @[AccumulatorScale.scala:398:67] wire [31:0] activated_data_e_act_z_iexp_2_bits; // @[AccumulatorScale.scala:398:67] assign _activated_data_e_act_z_iexp_T_5 = _activated_data_e_act_z_iexp_WIRE_2; // @[AccumulatorScale.scala:398:67] assign _activated_data_e_act_z_iexp_WIRE_2 = {16'h0, _activated_data_e_act_z_iexp_T_4}; // @[AccumulatorScale.scala:398:{54,67}] assign activated_data_e_act_z_iexp_2_bits = _activated_data_e_act_z_iexp_T_5; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_65_bits; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_2_bits; // @[AccumulatorScale.scala:399:32] wire _activated_data_e_act_z_iexp_saturated_T_44 = activated_data_e_act_z_iexp_2_bits[5]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_45 = activated_data_e_act_z_iexp_2_bits[6]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_46 = activated_data_e_act_z_iexp_2_bits[7]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_47 = activated_data_e_act_z_iexp_2_bits[8]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_48 = activated_data_e_act_z_iexp_2_bits[9]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_49 = activated_data_e_act_z_iexp_2_bits[10]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_50 = activated_data_e_act_z_iexp_2_bits[11]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_51 = activated_data_e_act_z_iexp_2_bits[12]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_52 = activated_data_e_act_z_iexp_2_bits[13]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_53 = activated_data_e_act_z_iexp_2_bits[14]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_54 = activated_data_e_act_z_iexp_2_bits[15]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_55 = _activated_data_e_act_z_iexp_saturated_T_44 | _activated_data_e_act_z_iexp_saturated_T_45; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_56 = _activated_data_e_act_z_iexp_saturated_T_55 | _activated_data_e_act_z_iexp_saturated_T_46; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_57 = _activated_data_e_act_z_iexp_saturated_T_56 | _activated_data_e_act_z_iexp_saturated_T_47; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_58 = _activated_data_e_act_z_iexp_saturated_T_57 | _activated_data_e_act_z_iexp_saturated_T_48; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_59 = _activated_data_e_act_z_iexp_saturated_T_58 | _activated_data_e_act_z_iexp_saturated_T_49; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_60 = _activated_data_e_act_z_iexp_saturated_T_59 | _activated_data_e_act_z_iexp_saturated_T_50; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_61 = _activated_data_e_act_z_iexp_saturated_T_60 | _activated_data_e_act_z_iexp_saturated_T_51; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_62 = _activated_data_e_act_z_iexp_saturated_T_61 | _activated_data_e_act_z_iexp_saturated_T_52; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_63 = _activated_data_e_act_z_iexp_saturated_T_62 | _activated_data_e_act_z_iexp_saturated_T_53; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_64 = _activated_data_e_act_z_iexp_saturated_T_63 | _activated_data_e_act_z_iexp_saturated_T_54; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_65_bits = _activated_data_e_act_z_iexp_saturated_T_64 ? 32'h20 : activated_data_e_act_z_iexp_2_bits; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_2_bits = _activated_data_e_act_z_iexp_saturated_T_65_bits; // @[AccumulatorScale.scala:399:32, :400:28] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_sign_2 = activated_data_e_act_z_iexp_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_2_sign = activated_data_e_act_qp_iexp_m1_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn_2 = activated_data_e_act_z_iexp_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2 = activated_data_e_act_z_iexp_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_88 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_89 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_90 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_91 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_92 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_93 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_94 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_95 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_96 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_97 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_98 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_99 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_100 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_101 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_102 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_103 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_104 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_105 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_106 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_107 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_108 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_109 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_110 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_111 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_112 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_113 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_114 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_115 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_116 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_117 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_118 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_119 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_120 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_121 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_122 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_123 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_124 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_125 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_126 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_127 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_128 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_129 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_130 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_131 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_2 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2} << activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_2 = {_activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_2 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_4 = activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_2 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_2_isZero = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_T_2 = activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_2 = &_activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_m1_rec_T_18 = activated_data_e_act_qp_iexp_m1_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_2 & _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_2_isNaN = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T_2 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_2 & activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_2_isInf = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_2_sExp = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_10 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_2 : activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_9, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_2_sig = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_16 = activated_data_e_act_qp_iexp_m1_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_17 = activated_data_e_act_qp_iexp_m1_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_m1_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_19 = {_activated_data_e_act_qp_iexp_m1_rec_T_17[2:1], _activated_data_e_act_qp_iexp_m1_rec_T_17[0] | _activated_data_e_act_qp_iexp_m1_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_m1_rec_T_20 = {activated_data_e_act_qp_iexp_m1_rec_rawIn_2_sign, _activated_data_e_act_qp_iexp_m1_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_m1_rec_T_21 = activated_data_e_act_qp_iexp_m1_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_T_22 = {_activated_data_e_act_qp_iexp_m1_rec_T_20, _activated_data_e_act_qp_iexp_m1_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_m1_rec_T_23 = activated_data_e_act_qp_iexp_m1_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_m1_rec_2 = {_activated_data_e_act_qp_iexp_m1_rec_T_22, _activated_data_e_act_qp_iexp_m1_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_2_sign = activated_data_e_act_qp_iexp_m2_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_88 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_89 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_90 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_91 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_92 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_93 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_94 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_95 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_96 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_97 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_98 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_99 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_100 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_101 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_102 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_103 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_104 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_105 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_106 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_107 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_108 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_109 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_110 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_111 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_112 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_113 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_114 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_115 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_116 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_117 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_118 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_119 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_120 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_121 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_122 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_123 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_124 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_125 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_126 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_127 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_128 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_129 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_130 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_131 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_2 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2} << activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_2 = {_activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_2 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_4 = activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_2 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_2_isZero = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_T_2 = activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_2 = &_activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_m2_rec_T_18 = activated_data_e_act_qp_iexp_m2_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_2 & _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_2_isNaN = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T_2 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_2 & activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_2_isInf = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_2_sExp = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_10 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_2 : activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_9, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_2_sig = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_16 = activated_data_e_act_qp_iexp_m2_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_17 = activated_data_e_act_qp_iexp_m2_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_m2_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_19 = {_activated_data_e_act_qp_iexp_m2_rec_T_17[2:1], _activated_data_e_act_qp_iexp_m2_rec_T_17[0] | _activated_data_e_act_qp_iexp_m2_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_m2_rec_T_20 = {activated_data_e_act_qp_iexp_m2_rec_rawIn_2_sign, _activated_data_e_act_qp_iexp_m2_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_m2_rec_T_21 = activated_data_e_act_qp_iexp_m2_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_T_22 = {_activated_data_e_act_qp_iexp_m2_rec_T_20, _activated_data_e_act_qp_iexp_m2_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_m2_rec_T_23 = activated_data_e_act_qp_iexp_m2_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_m2_rec_2 = {_activated_data_e_act_qp_iexp_m2_rec_T_22, _activated_data_e_act_qp_iexp_m2_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_qp_iexp_self_rec_rawIn_4_sign = activated_data_e_act_qp_iexp_self_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_4 = activated_data_e_act_result_14_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4 = activated_data_e_act_result_14_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_176 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_177 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_178 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_179 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_180 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_181 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_182 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_183 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_184 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_185 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_186 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_187 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_188 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_189 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_190 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_191 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_192 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_193 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_194 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_195 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_196 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_197 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_198 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_199 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_200 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_201 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_202 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_203 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_204 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_205 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_206 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_207 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_208 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_209 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_210 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_211 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_212 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_213 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_214 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_215 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_216 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_217 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_218 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_219 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_4 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4} << activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_4 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_4 = _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_8 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_4 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_4_isZero = activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_4 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_4 = &_activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_self_rec_T_34 = activated_data_e_act_qp_iexp_self_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_self_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_self_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_4 & _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_4_isNaN = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_4 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_4 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_self_rec_rawIn_4_isInf = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_4_sExp = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_18 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_4 : activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_17, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_4_sig = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_32 = activated_data_e_act_qp_iexp_self_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_33 = activated_data_e_act_qp_iexp_self_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_self_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_35 = {_activated_data_e_act_qp_iexp_self_rec_T_33[2:1], _activated_data_e_act_qp_iexp_self_rec_T_33[0] | _activated_data_e_act_qp_iexp_self_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_self_rec_T_36 = {activated_data_e_act_qp_iexp_self_rec_rawIn_4_sign, _activated_data_e_act_qp_iexp_self_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_self_rec_T_37 = activated_data_e_act_qp_iexp_self_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_T_38 = {_activated_data_e_act_qp_iexp_self_rec_T_36, _activated_data_e_act_qp_iexp_self_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_T_39 = activated_data_e_act_qp_iexp_self_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_self_rec_4 = {_activated_data_e_act_qp_iexp_self_rec_T_38, _activated_data_e_act_qp_iexp_self_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_qp_iexp_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_qp_iexp_out_2_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_qp_iexp_out_bits_rawIn_exp_2 = _activated_data_e_act_qp_iexp_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_T_2 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_2 = _activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_qp_iexp_out_bits_rawIn_2_isZero = activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_T_2 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_2 = &_activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_qp_iexp_out_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_out_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_qp_iexp_out_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_qp_iexp_out_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_6 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_2_isNaN = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_8 = activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_2_isInf = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T_2 = _activated_data_e_act_qp_iexp_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_qp_iexp_out_bits_rawIn_2_sign = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_qp_iexp_out_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_qp_iexp_out_bits_rawIn_2_sExp = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_10 = _activated_data_e_act_qp_iexp_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_9, _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_2_sig = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_qp_iexp_out_bits_isSubnormal_2 = $signed(activated_data_e_act_qp_iexp_out_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_4 = activated_data_e_act_qp_iexp_out_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_qp_iexp_out_bits_denormShiftDist_2 = _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_qp_iexp_out_bits_denormFract_T_4 = activated_data_e_act_qp_iexp_out_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_qp_iexp_out_bits_denormFract_T_5 = _activated_data_e_act_qp_iexp_out_bits_denormFract_T_4 >> activated_data_e_act_qp_iexp_out_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_qp_iexp_out_bits_denormFract_2 = _activated_data_e_act_qp_iexp_out_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_12 = activated_data_e_act_qp_iexp_out_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_13 = {1'h0, _activated_data_e_act_qp_iexp_out_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_14 = _activated_data_e_act_qp_iexp_out_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_15 = activated_data_e_act_qp_iexp_out_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_qp_iexp_out_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_qp_iexp_out_bits_expOut_T_16 = activated_data_e_act_qp_iexp_out_bits_rawIn_2_isNaN | activated_data_e_act_qp_iexp_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_17 = {8{_activated_data_e_act_qp_iexp_out_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_qp_iexp_out_bits_expOut_2 = _activated_data_e_act_qp_iexp_out_bits_expOut_T_15 | _activated_data_e_act_qp_iexp_out_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_fractOut_T_4 = activated_data_e_act_qp_iexp_out_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_fractOut_T_5 = activated_data_e_act_qp_iexp_out_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_qp_iexp_out_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_qp_iexp_out_bits_fractOut_2 = activated_data_e_act_qp_iexp_out_bits_isSubnormal_2 ? activated_data_e_act_qp_iexp_out_bits_denormFract_2 : _activated_data_e_act_qp_iexp_out_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_qp_iexp_out_bits_hi_2 = {activated_data_e_act_qp_iexp_out_bits_rawIn_2_sign, activated_data_e_act_qp_iexp_out_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_qp_iexp_out_bits_T_2 = {activated_data_e_act_qp_iexp_out_bits_hi_2, activated_data_e_act_qp_iexp_out_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_qp_iexp_out_2_bits = _activated_data_e_act_qp_iexp_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_qp_iexp_self_rec_rawIn_sign_5 = activated_data_e_act_qp_iexp_out_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_self_rec_rawIn_5_sign = activated_data_e_act_qp_iexp_self_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_5 = activated_data_e_act_qp_iexp_out_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5 = activated_data_e_act_qp_iexp_out_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_5 = activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_5 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_220 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_221 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_222 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_223 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_224 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_225 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_226 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_227 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_228 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_229 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_230 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_231 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_232 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_233 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_234 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_235 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_236 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_237 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_238 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_239 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_240 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_241 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_242 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_243 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_244 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_245 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_246 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_247 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_248 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_249 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_250 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_251 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_252 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_253 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_254 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_255 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_256 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_257 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_258 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_259 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_260 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_261 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_262 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_263 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_5 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5} << activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_11 = _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_5 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_26 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_27 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_5 = _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_10 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_5 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_5 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_5_isZero = activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_5 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_5 = &_activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_self_rec_T_42 = activated_data_e_act_qp_iexp_self_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_self_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_self_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_11 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_5 & _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_5_isNaN = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_5 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_5 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_self_rec_rawIn_5_isInf = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_5_sExp = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_20 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_22 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_5 ? activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_5 : activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_23 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_21, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_5_sig = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_40 = activated_data_e_act_qp_iexp_self_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_41 = activated_data_e_act_qp_iexp_self_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_self_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_43 = {_activated_data_e_act_qp_iexp_self_rec_T_41[2:1], _activated_data_e_act_qp_iexp_self_rec_T_41[0] | _activated_data_e_act_qp_iexp_self_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_self_rec_T_44 = {activated_data_e_act_qp_iexp_self_rec_rawIn_5_sign, _activated_data_e_act_qp_iexp_self_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_self_rec_T_45 = activated_data_e_act_qp_iexp_self_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_T_46 = {_activated_data_e_act_qp_iexp_self_rec_T_44, _activated_data_e_act_qp_iexp_self_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_T_47 = activated_data_e_act_qp_iexp_self_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_self_rec_5 = {_activated_data_e_act_qp_iexp_self_rec_T_46, _activated_data_e_act_qp_iexp_self_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_qp_iexp_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_qp_iexp_2_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_qp_iexp_result_bits_rawIn_exp_2 = _activated_data_e_act_qp_iexp_resizer_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_T_2 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_2 = _activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_qp_iexp_result_bits_rawIn_2_isZero = activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_T_2 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_2 = &_activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_qp_iexp_result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_qp_iexp_result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_qp_iexp_result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_6 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_2_isNaN = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_8 = activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_2 & _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_2_isInf = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T_2 = _activated_data_e_act_qp_iexp_resizer_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_qp_iexp_result_bits_rawIn_2_sign = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_qp_iexp_result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_qp_iexp_result_bits_rawIn_2_sExp = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_10 = _activated_data_e_act_qp_iexp_resizer_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_9, _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_2_sig = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_qp_iexp_result_bits_isSubnormal_2 = $signed(activated_data_e_act_qp_iexp_result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_4 = activated_data_e_act_qp_iexp_result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_qp_iexp_result_bits_denormShiftDist_2 = _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_qp_iexp_result_bits_denormFract_T_4 = activated_data_e_act_qp_iexp_result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_qp_iexp_result_bits_denormFract_T_5 = _activated_data_e_act_qp_iexp_result_bits_denormFract_T_4 >> activated_data_e_act_qp_iexp_result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_qp_iexp_result_bits_denormFract_2 = _activated_data_e_act_qp_iexp_result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_12 = activated_data_e_act_qp_iexp_result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_13 = {1'h0, _activated_data_e_act_qp_iexp_result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_14 = _activated_data_e_act_qp_iexp_result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_15 = activated_data_e_act_qp_iexp_result_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_qp_iexp_result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_qp_iexp_result_bits_expOut_T_16 = activated_data_e_act_qp_iexp_result_bits_rawIn_2_isNaN | activated_data_e_act_qp_iexp_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_17 = {8{_activated_data_e_act_qp_iexp_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_qp_iexp_result_bits_expOut_2 = _activated_data_e_act_qp_iexp_result_bits_expOut_T_15 | _activated_data_e_act_qp_iexp_result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_fractOut_T_4 = activated_data_e_act_qp_iexp_result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_fractOut_T_5 = activated_data_e_act_qp_iexp_result_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_qp_iexp_result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_qp_iexp_result_bits_fractOut_2 = activated_data_e_act_qp_iexp_result_bits_isSubnormal_2 ? activated_data_e_act_qp_iexp_result_bits_denormFract_2 : _activated_data_e_act_qp_iexp_result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_qp_iexp_result_bits_hi_2 = {activated_data_e_act_qp_iexp_result_bits_rawIn_2_sign, activated_data_e_act_qp_iexp_result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_qp_iexp_result_bits_T_2 = {activated_data_e_act_qp_iexp_result_bits_hi_2, activated_data_e_act_qp_iexp_result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_qp_iexp_2_bits = _activated_data_e_act_qp_iexp_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_sign = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_4 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_4 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_176 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_177 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_178 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_179 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_180 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_181 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_182 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_183 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_184 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_185 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_186 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_187 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_188 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_189 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_190 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_191 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_192 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_193 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_194 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_195 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_196 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_197 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_198 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_199 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_200 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_201 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_202 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_203 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_204 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_205 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_206 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_207 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_208 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_209 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_210 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_211 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_212 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_213 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_214 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_215 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_216 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_217 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_218 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_219 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_4 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4} << activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_9 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_4 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_21 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_22 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_4 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_8 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_4 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_4 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_isZero = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_4 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_4 = &_activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_t_rec_T_34 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_9 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_4 & _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_isNaN = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_4 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_4 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_isInf = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_sExp = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_16 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_18 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_4 ? activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_4 : activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_19 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_17, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_sig = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_32 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_33 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_t_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_35 = {_activated_data_e_act_q_poly_iexp_t_rec_T_33[2:1], _activated_data_e_act_q_poly_iexp_t_rec_T_33[0] | _activated_data_e_act_q_poly_iexp_t_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_t_rec_T_36 = {activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_sign, _activated_data_e_act_q_poly_iexp_t_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_t_rec_T_37 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_T_38 = {_activated_data_e_act_q_poly_iexp_t_rec_T_36, _activated_data_e_act_q_poly_iexp_t_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_T_39 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_t_rec_4 = {_activated_data_e_act_q_poly_iexp_t_rec_T_38, _activated_data_e_act_q_poly_iexp_t_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_8 = activated_data_e_act_qp_iexp_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_9 = activated_data_e_act_qp_iexp_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_8; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_8 = activated_data_e_act_qp_iexp_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_9 = activated_data_e_act_qp_iexp_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8 = activated_data_e_act_qp_iexp_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9 = activated_data_e_act_qp_iexp_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_8 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_8 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_8 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_352 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_353 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_354 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_355 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_356 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_357 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_358 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_359 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_360 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_361 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_362 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_363 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_364 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_365 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_366 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_367 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_368 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_369 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_370 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_371 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_372 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_373 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_374 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_375 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_353 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_376 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_354 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_375; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_377 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_355 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_376; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_378 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_356 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_377; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_379 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_357 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_378; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_380 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_358 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_379; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_381 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_359 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_380; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_382 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_360 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_381; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_383 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_361 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_382; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_384 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_362 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_383; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_385 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_363 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_384; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_386 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_364 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_385; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_387 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_365 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_386; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_388 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_366 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_387; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_389 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_367 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_388; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_390 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_368 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_389; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_391 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_369 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_390; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_392 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_370 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_391; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_393 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_371 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_392; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_394 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_372 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_393; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_395 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_373 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_394; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_8 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_374 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_395; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_16 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_8; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_17 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_16[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_8 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_17, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_40 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_8}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_41 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_8 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_40 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_8}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_42 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_8 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_43 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_42}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_44 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_41} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_43}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_8 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_44[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_16 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_8; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_8 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_8 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_8 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_8[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_8 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_8; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_66 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_16 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_17 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_8 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_16; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_8 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_8 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_17 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_16}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_32 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_33 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_32}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_34 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_8 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_8 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_8; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_35 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_33, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_34}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_64 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_65 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_64; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_67 = {_activated_data_e_act_q_poly_iexp_self_rec_T_65[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_65[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_66}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_68 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_67}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_69 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_70 = {_activated_data_e_act_q_poly_iexp_self_rec_T_68, _activated_data_e_act_q_poly_iexp_self_rec_T_69}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_71 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_8_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_8 = {_activated_data_e_act_q_poly_iexp_self_rec_T_70, _activated_data_e_act_q_poly_iexp_self_rec_T_71}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_6; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_result_4_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_6 = _activated_data_e_act_q_poly_iexp_muladder_6_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_6 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_6[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_6 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_6 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_6 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_6[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_6 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_6; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_20; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_6; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_6; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_27; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_12 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_18 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_13 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_6 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_12; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_19 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_18; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_20 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_6 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_19; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_20; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_6 = _activated_data_e_act_q_poly_iexp_muladder_6_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_6; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_6 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_6}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_6; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_24 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_24}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_26 = _activated_data_e_act_q_poly_iexp_muladder_6_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_27 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_25, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_26}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_27; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_6 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_12 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_13 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_12}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_6 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_13[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_12 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_13 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_12 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_6; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_6 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_13[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_36 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_37 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_36} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_38 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_37[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_39 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_6 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_38; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_40 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_41 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_40}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_6 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_39 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_41; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_12 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_13 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_12; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_6 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_6 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_6 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_13; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_6 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_6_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_6}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_6 = {activated_data_e_act_q_poly_iexp_result_bits_hi_6, activated_data_e_act_q_poly_iexp_result_bits_fractOut_6}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_result_4_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_6; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_sign = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_5 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_5 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_220 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_221 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_222 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_223 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_224 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_225 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_226 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_227 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_228 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_229 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_230 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_231 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_232 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_233 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_234 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_235 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_236 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_237 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_238 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_239 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_240 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_241 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_242 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_243 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_244 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_245 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_246 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_247 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_248 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_249 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_250 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_251 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_252 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_253 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_254 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_255 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_256 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_257 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_258 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_259 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_260 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_261 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_262 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_263 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_5 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5} << activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_11 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_5 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_26 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_27 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_5 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_10 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_5 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_5 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_isZero = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_5 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_5 = &_activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_t_rec_T_42 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_11 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_5 & _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_isNaN = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_5 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_5 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_isInf = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_sExp = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_20 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_22 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_5 ? activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_5 : activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_23 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_21, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_sig = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_40 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_41 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_t_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_43 = {_activated_data_e_act_q_poly_iexp_t_rec_T_41[2:1], _activated_data_e_act_q_poly_iexp_t_rec_T_41[0] | _activated_data_e_act_q_poly_iexp_t_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_t_rec_T_44 = {activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_sign, _activated_data_e_act_q_poly_iexp_t_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_t_rec_T_45 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_T_46 = {_activated_data_e_act_q_poly_iexp_t_rec_T_44, _activated_data_e_act_q_poly_iexp_t_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_T_47 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_t_rec_5 = {_activated_data_e_act_q_poly_iexp_t_rec_T_46, _activated_data_e_act_q_poly_iexp_t_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_9; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_9 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_9 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_9 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_396 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_397 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_398 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_399 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_400 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_401 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_402 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_403 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_404 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_405 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_406 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_407 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_408 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_409 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_410 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_411 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_412 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_413 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_414 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_415 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_416 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_417 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_418 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_419 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_397 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_420 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_398 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_419; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_421 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_399 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_420; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_422 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_400 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_421; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_423 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_401 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_422; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_424 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_402 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_423; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_425 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_403 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_424; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_426 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_404 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_425; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_427 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_405 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_426; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_428 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_406 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_427; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_429 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_407 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_428; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_430 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_408 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_429; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_431 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_409 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_430; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_432 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_410 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_431; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_433 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_411 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_432; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_434 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_412 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_433; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_435 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_413 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_434; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_436 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_414 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_435; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_437 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_415 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_436; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_438 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_416 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_437; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_439 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_417 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_438; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_9 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_418 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_439; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_18 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_9; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_19 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_18[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_9 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_19, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_45 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_9}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_46 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_9 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_45 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_9}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_47 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_9 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_48 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_47}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_49 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_46} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_48}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_9 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_49[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_18 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_9; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_9 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_9 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_9 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_9[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_9 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_9; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_74 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_18 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_19 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_9 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_18; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_9 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_9 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_19 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_18}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_36 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_37 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_36}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_38 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_9 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_9 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_9; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_39 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_37, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_38}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_72 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_73 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_72; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_75 = {_activated_data_e_act_q_poly_iexp_self_rec_T_73[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_73[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_74}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_76 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_75}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_77 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_78 = {_activated_data_e_act_q_poly_iexp_self_rec_T_76, _activated_data_e_act_q_poly_iexp_self_rec_T_77}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_79 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_9_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_9 = {_activated_data_e_act_q_poly_iexp_self_rec_T_78, _activated_data_e_act_q_poly_iexp_self_rec_T_79}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_7; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_result_5_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_7 = _activated_data_e_act_q_poly_iexp_muladder_7_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_7 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_7[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_7 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_7 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_7 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_7[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_7 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_7; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_23; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_7; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_7; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_31; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_14 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_21 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_15 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_7 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_14; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_22 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_21; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_23 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_7 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_22; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_23; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_7 = _activated_data_e_act_q_poly_iexp_muladder_7_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_7; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_7 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_7}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_7; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_28 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_28}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_30 = _activated_data_e_act_q_poly_iexp_muladder_7_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_31 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_29, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_30}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_31; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_7 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_14 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_15 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_14}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_7 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_15[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_14 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_15 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_14 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_7; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_7 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_15[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_42 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_43 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_42} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_44 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_43[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_45 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_7 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_44; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_46 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_47 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_46}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_7 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_45 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_47; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_14 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_15 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_14; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_7 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_7 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_7 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_15; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_7 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_7_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_7}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_7 = {activated_data_e_act_q_poly_iexp_result_bits_hi_7, activated_data_e_act_q_poly_iexp_result_bits_fractOut_7}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_result_5_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_7; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sign_2 = activated_data_e_act_q_poly_iexp_result_4_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_sign = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn_2 = activated_data_e_act_q_poly_iexp_result_4_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2 = activated_data_e_act_q_poly_iexp_result_4_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_88 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_89 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_90 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_91 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_92 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_93 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_94 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_95 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_96 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_97 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_98 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_99 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_100 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_101 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_102 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_103 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_104 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_105 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_106 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_107 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_108 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_109 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_110 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_2 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2} << activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_2 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_isZero = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_m1_rec_T_18 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_isNaN = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_2 & activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_isInf = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_sExp = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_2 : activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_sig = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_16 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_17 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_m1_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_19 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_17[2:1], _activated_data_e_act_q_poly_iexp_m1_rec_T_17[0] | _activated_data_e_act_q_poly_iexp_m1_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_20 = {activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_sign, _activated_data_e_act_q_poly_iexp_m1_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_21 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_22 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_20, _activated_data_e_act_q_poly_iexp_m1_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_23 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_m1_rec_2 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_22, _activated_data_e_act_q_poly_iexp_m1_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sign_2 = activated_data_e_act_q_poly_iexp_result_5_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_sign = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn_2 = activated_data_e_act_q_poly_iexp_result_5_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2 = activated_data_e_act_q_poly_iexp_result_5_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_2 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_2 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_88 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_89 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_90 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_91 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_92 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_93 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_94 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_95 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_96 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_97 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_98 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_99 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_100 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_101 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_102 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_103 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_104 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_105 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_106 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_107 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_108 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_109 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_110 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_111 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_112 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_113 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_114 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_115 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_116 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_117 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_118 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_119 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_120 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_121 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_122 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_123 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_124 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_125 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_126 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_127 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_128 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_129 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_130 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_131 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_2 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2} << activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_5 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_2 = {_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_11 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_12 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_2 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_4 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_2 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_2 & activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_isZero = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_m2_rec_T_18 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_isNaN = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T_2 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_2 & activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_isInf = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_sExp = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_10 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_2 ? activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_2 : activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_sig = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_16 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_17 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_m2_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_19 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_17[2:1], _activated_data_e_act_q_poly_iexp_m2_rec_T_17[0] | _activated_data_e_act_q_poly_iexp_m2_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_20 = {activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_sign, _activated_data_e_act_q_poly_iexp_m2_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_21 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_22 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_20, _activated_data_e_act_q_poly_iexp_m2_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_23 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_m2_rec_2 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_22, _activated_data_e_act_q_poly_iexp_m2_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_10; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_10 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_10 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_10 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_440 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_441 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_442 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_443 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_444 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_445 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_446 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_447 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_448 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_449 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_450 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_451 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_452 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_453 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_454 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_455 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_456 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_457 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_458 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_459 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_460 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_461 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_462 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_463 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_441 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_464 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_442 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_463; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_465 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_443 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_464; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_466 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_444 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_465; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_467 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_445 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_466; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_468 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_446 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_467; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_469 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_447 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_468; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_470 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_448 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_469; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_471 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_449 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_470; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_472 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_450 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_471; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_473 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_451 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_472; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_474 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_452 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_473; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_475 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_453 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_474; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_476 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_454 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_475; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_477 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_455 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_476; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_478 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_456 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_477; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_479 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_457 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_478; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_480 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_458 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_479; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_481 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_459 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_480; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_482 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_460 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_481; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_483 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_461 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_482; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_10 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_462 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_483; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_20 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_10; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_21 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_20[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_10 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_21, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_50 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_10}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_51 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_10 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_50 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_10}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_52 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_10 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_53 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_52}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_54 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_51} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_53}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_10 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_54[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_20 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_10; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_10 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_10 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_10 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_10[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_10 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_10; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_82 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_20 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_21 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_10 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_20; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_10 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_10 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_21 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_20}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_40 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_40}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_42 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_10 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_10 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_10; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_43 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_41, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_42}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_80 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_81 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_80; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_83 = {_activated_data_e_act_q_poly_iexp_self_rec_T_81[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_81[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_82}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_84 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_83}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_85 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_86 = {_activated_data_e_act_q_poly_iexp_self_rec_T_84, _activated_data_e_act_q_poly_iexp_self_rec_T_85}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_87 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_10_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_10 = {_activated_data_e_act_q_poly_iexp_self_rec_T_86, _activated_data_e_act_q_poly_iexp_self_rec_T_87}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_out_2_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_2 = _activated_data_e_act_q_poly_iexp_muladder_8_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_T_2 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_2 = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_isZero = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_T_2 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_2 = &_activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_4 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_6 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_5 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_isNaN = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_8 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_2 & _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_isInf = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T_2 = _activated_data_e_act_q_poly_iexp_muladder_8_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sign = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sExp = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_8 = ~activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_10 = _activated_data_e_act_q_poly_iexp_muladder_8_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_11 = {_activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_9, _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sig = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_out_bits_isSubnormal_2 = $signed(activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_4 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_2 = _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_4 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_5 = _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_4 >> activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_out_bits_denormFract_2 = _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_12 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_13 = {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_14 = _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_15 = activated_data_e_act_q_poly_iexp_out_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_16 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_isNaN | activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_17 = {8{_activated_data_e_act_q_poly_iexp_out_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_out_bits_expOut_2 = _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_15 | _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_4 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_5 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_out_bits_fractOut_2 = activated_data_e_act_q_poly_iexp_out_bits_isSubnormal_2 ? activated_data_e_act_q_poly_iexp_out_bits_denormFract_2 : _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_out_bits_hi_2 = {activated_data_e_act_q_poly_iexp_out_bits_rawIn_2_sign, activated_data_e_act_q_poly_iexp_out_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_out_bits_T_2 = {activated_data_e_act_q_poly_iexp_out_bits_hi_2, activated_data_e_act_q_poly_iexp_out_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_out_2_bits = _activated_data_e_act_q_poly_iexp_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_11 = activated_data_e_act_q_poly_iexp_out_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_11; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_11 = activated_data_e_act_q_poly_iexp_out_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11 = activated_data_e_act_q_poly_iexp_out_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_11 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_11 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_11 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_484 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_485 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_486 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_487 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_488 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_489 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_490 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_491 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_492 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_493 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_494 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_495 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_496 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_497 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_498 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_499 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_500 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_501 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_502 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_503 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_504 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_505 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_506 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_507 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_485 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_508 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_486 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_507; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_509 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_487 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_508; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_510 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_488 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_509; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_511 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_489 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_510; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_512 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_490 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_511; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_513 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_491 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_512; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_514 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_492 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_513; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_515 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_493 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_514; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_516 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_494 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_515; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_517 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_495 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_516; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_518 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_496 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_517; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_519 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_497 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_518; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_520 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_498 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_519; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_521 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_499 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_520; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_522 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_500 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_521; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_523 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_501 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_522; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_524 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_502 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_523; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_525 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_503 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_524; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_526 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_504 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_525; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_527 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_505 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_526; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_11 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_506 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_527; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_22 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_11; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_23 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_22[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_11 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_23, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_55 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_11}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_56 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_11 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_55 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_11}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_57 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_11 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_58 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_57}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_59 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_56} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_58}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_11 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_59[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_22 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_11; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_11 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_11 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_11 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_11[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_11 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_11; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_90 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_22 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_23 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_11 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_22; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_11 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_11 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_23 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_22}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_44 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_45 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_44}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_46 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_11 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_11 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_11; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_47 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_45, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_46}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_88 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_89 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_88; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_91 = {_activated_data_e_act_q_poly_iexp_self_rec_T_89[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_89[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_90}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_92 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_91}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_93 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_94 = {_activated_data_e_act_q_poly_iexp_self_rec_T_92, _activated_data_e_act_q_poly_iexp_self_rec_T_93}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_95 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_11_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_11 = {_activated_data_e_act_q_poly_iexp_self_rec_T_94, _activated_data_e_act_q_poly_iexp_self_rec_T_95}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_8; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_2_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_8 = _activated_data_e_act_q_poly_iexp_resizer_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_8 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_8[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_8 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_8 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_8 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_8[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_8 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_8; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_26; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_8; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_8; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_35; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_16 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_24 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_17 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_8 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_16; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_25 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_24; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_26 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_8 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_25; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_26; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_8 = _activated_data_e_act_q_poly_iexp_resizer_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_8; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_8 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_8}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_8; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_32 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_33 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_32}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_34 = _activated_data_e_act_q_poly_iexp_resizer_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_35 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_33, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_34}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_35; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_8 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_16 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_17 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_16}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_8 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_17[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_16 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_17 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_16 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_8; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_8 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_17[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_48 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_49 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_48} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_50 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_49[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_51 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_8 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_50; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_52 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_53 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_52}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_8 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_51 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_53; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_16 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_17 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_16; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_8 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_8 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_8 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_17; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_8 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_8_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_8}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_8 = {activated_data_e_act_q_poly_iexp_result_bits_hi_8, activated_data_e_act_q_poly_iexp_result_bits_fractOut_8}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_2_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_8; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_T_43 = activated_data_e_act_q_poly_iexp_2_bits >> activated_data_e_act_z_iexp_saturated_2_bits; // @[Arithmetic.scala:491:26] wire [31:0] _activated_data_e_act_WIRE_5 = _activated_data_e_act_T_43; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_T_44; // @[AccumulatorScale.scala:405:65] assign _activated_data_e_act_T_44 = _activated_data_e_act_WIRE_5; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_WIRE_4_bits = _activated_data_e_act_T_44; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_46_bits = _activated_data_e_act_T_45_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_47_bits = _activated_data_e_act_T_46_bits; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_2_bits = _activated_data_e_act_T_33 ? activated_data_e_act_result_10_bits : _activated_data_e_act_T_47_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_28_bits = _activated_data_e_scaled_T_27_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_11 = _activated_data_e_scaled_T_28_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_29; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_29 = _activated_data_e_scaled_WIRE_11; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_10_bits = _activated_data_e_scaled_T_29; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_t_rec_rawIn_sign_2 = _activated_data_e_scaled_WIRE_10_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_t_rec_rawIn_2_sign = activated_data_e_scaled_t_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_t_rec_rawIn_expIn_2 = _activated_data_e_scaled_WIRE_10_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_t_rec_rawIn_fractIn_2 = _activated_data_e_scaled_WIRE_10_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_2 = activated_data_e_scaled_t_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_2 = activated_data_e_scaled_t_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_88 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_89 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_90 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_91 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_92 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_93 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_94 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_95 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_96 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_97 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_98 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_99 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_100 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_101 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_102 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_103 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_104 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_105 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_106 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_107 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_108 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_109 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_110 = activated_data_e_scaled_t_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_111 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_112 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_113 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_114 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_115 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_116 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_117 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_scaled_t_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_118 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_scaled_t_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_119 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_scaled_t_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_120 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_scaled_t_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_121 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_scaled_t_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_122 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_scaled_t_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_123 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_124 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_125 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_126 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_127 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_128 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_129 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_130 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_131 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_t_rec_rawIn_normDist_2 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_t_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_scaled_t_rec_rawIn_fractIn_2} << activated_data_e_scaled_t_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_t_rec_rawIn_subnormFract_T_5 = _activated_data_e_scaled_t_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_t_rec_rawIn_subnormFract_2 = {_activated_data_e_scaled_t_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_scaled_t_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_11 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_scaled_t_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_12 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_scaled_t_rec_rawIn_adjustedExp_2 = _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_4 = activated_data_e_scaled_t_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_t_rec_rawIn_isZero_2 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_2 & activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_t_rec_rawIn_2_isZero = activated_data_e_scaled_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_isSpecial_T_2 = activated_data_e_scaled_t_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_t_rec_rawIn_isSpecial_2 = &_activated_data_e_scaled_t_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_t_rec_T_18 = activated_data_e_scaled_t_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_t_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_t_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_t_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_5 = activated_data_e_scaled_t_rec_rawIn_isSpecial_2 & _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_t_rec_rawIn_2_isNaN = _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_t_rec_rawIn_out_isInf_T_2 = activated_data_e_scaled_t_rec_rawIn_isSpecial_2 & activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_t_rec_rawIn_2_isInf = _activated_data_e_scaled_t_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_t_rec_rawIn_2_sExp = _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_t_rec_rawIn_out_sig_T_8 = ~activated_data_e_scaled_t_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_10 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_2 ? activated_data_e_scaled_t_rec_rawIn_subnormFract_2 : activated_data_e_scaled_t_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_t_rec_rawIn_out_sig_T_11 = {_activated_data_e_scaled_t_rec_rawIn_out_sig_T_9, _activated_data_e_scaled_t_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_t_rec_rawIn_2_sig = _activated_data_e_scaled_t_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_t_rec_T_16 = activated_data_e_scaled_t_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_t_rec_T_17 = activated_data_e_scaled_t_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_scaled_t_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_t_rec_T_19 = {_activated_data_e_scaled_t_rec_T_17[2:1], _activated_data_e_scaled_t_rec_T_17[0] | _activated_data_e_scaled_t_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_t_rec_T_20 = {activated_data_e_scaled_t_rec_rawIn_2_sign, _activated_data_e_scaled_t_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_t_rec_T_21 = activated_data_e_scaled_t_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_t_rec_T_22 = {_activated_data_e_scaled_t_rec_T_20, _activated_data_e_scaled_t_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_t_rec_T_23 = activated_data_e_scaled_t_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_t_rec_2 = {_activated_data_e_scaled_t_rec_T_22, _activated_data_e_scaled_t_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_scaled_self_rec_rawIn_sign_2 = activated_data_e_act_2_bits[31]; // @[Mux.scala:126:16] wire activated_data_e_scaled_self_rec_rawIn_2_sign = activated_data_e_scaled_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_self_rec_rawIn_expIn_2 = activated_data_e_act_2_bits[30:23]; // @[Mux.scala:126:16] wire [22:0] activated_data_e_scaled_self_rec_rawIn_fractIn_2 = activated_data_e_act_2_bits[22:0]; // @[Mux.scala:126:16] wire activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_2 = activated_data_e_scaled_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_2 = activated_data_e_scaled_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_88 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_89 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_90 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_91 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_92 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_93 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_94 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_95 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_96 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_97 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_98 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_99 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_100 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_101 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_102 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_103 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_104 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_105 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_106 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_107 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_108 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_109 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_110 = activated_data_e_scaled_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_111 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_112 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_113 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_114 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_115 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_116 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_117 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_scaled_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_118 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_scaled_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_119 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_scaled_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_120 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_scaled_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_121 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_scaled_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_122 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_scaled_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_123 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_124 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_125 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_126 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_127 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_128 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_129 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_130 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_131 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_self_rec_rawIn_normDist_2 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_self_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_scaled_self_rec_rawIn_fractIn_2} << activated_data_e_scaled_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_self_rec_rawIn_subnormFract_T_5 = _activated_data_e_scaled_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_self_rec_rawIn_subnormFract_2 = {_activated_data_e_scaled_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_scaled_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_11 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_scaled_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_12 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_scaled_self_rec_rawIn_adjustedExp_2 = _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_4 = activated_data_e_scaled_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_self_rec_rawIn_isZero_2 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_2 & activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_self_rec_rawIn_2_isZero = activated_data_e_scaled_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_isSpecial_T_2 = activated_data_e_scaled_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_self_rec_rawIn_isSpecial_2 = &_activated_data_e_scaled_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_self_rec_T_18 = activated_data_e_scaled_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_5 = activated_data_e_scaled_self_rec_rawIn_isSpecial_2 & _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_self_rec_rawIn_2_isNaN = _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_self_rec_rawIn_out_isInf_T_2 = activated_data_e_scaled_self_rec_rawIn_isSpecial_2 & activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_self_rec_rawIn_2_isInf = _activated_data_e_scaled_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_self_rec_rawIn_2_sExp = _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_self_rec_rawIn_out_sig_T_8 = ~activated_data_e_scaled_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_10 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_2 ? activated_data_e_scaled_self_rec_rawIn_subnormFract_2 : activated_data_e_scaled_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_self_rec_rawIn_out_sig_T_11 = {_activated_data_e_scaled_self_rec_rawIn_out_sig_T_9, _activated_data_e_scaled_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_self_rec_rawIn_2_sig = _activated_data_e_scaled_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_self_rec_T_16 = activated_data_e_scaled_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_self_rec_T_17 = activated_data_e_scaled_self_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_scaled_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_self_rec_T_19 = {_activated_data_e_scaled_self_rec_T_17[2:1], _activated_data_e_scaled_self_rec_T_17[0] | _activated_data_e_scaled_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_self_rec_T_20 = {activated_data_e_scaled_self_rec_rawIn_2_sign, _activated_data_e_scaled_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_self_rec_T_21 = activated_data_e_scaled_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_self_rec_T_22 = {_activated_data_e_scaled_self_rec_T_20, _activated_data_e_scaled_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_self_rec_T_23 = activated_data_e_scaled_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_self_rec_2 = {_activated_data_e_scaled_self_rec_T_22, _activated_data_e_scaled_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_scaled_2_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_scaled_out_bits_rawIn_exp_2 = _activated_data_e_scaled_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_out_bits_rawIn_isZero_T_2 = activated_data_e_scaled_out_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_out_bits_rawIn_isZero_2 = _activated_data_e_scaled_out_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_out_bits_rawIn_2_isZero = activated_data_e_scaled_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_out_bits_rawIn_isSpecial_T_2 = activated_data_e_scaled_out_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_out_bits_rawIn_isSpecial_2 = &_activated_data_e_scaled_out_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_out_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_out_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_out_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_out_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_4 = activated_data_e_scaled_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_6 = activated_data_e_scaled_out_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_5 = activated_data_e_scaled_out_bits_rawIn_isSpecial_2 & _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_out_bits_rawIn_2_isNaN = _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_scaled_out_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_8 = activated_data_e_scaled_out_bits_rawIn_isSpecial_2 & _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_out_bits_rawIn_2_isInf = _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_out_bits_rawIn_out_sign_T_2 = _activated_data_e_scaled_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_out_bits_rawIn_2_sign = _activated_data_e_scaled_out_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_out_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_scaled_out_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_out_bits_rawIn_2_sExp = _activated_data_e_scaled_out_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_out_bits_rawIn_out_sig_T_8 = ~activated_data_e_scaled_out_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_scaled_out_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_10 = _activated_data_e_scaled_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_out_bits_rawIn_out_sig_T_11 = {_activated_data_e_scaled_out_bits_rawIn_out_sig_T_9, _activated_data_e_scaled_out_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_out_bits_rawIn_2_sig = _activated_data_e_scaled_out_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_scaled_out_bits_isSubnormal_2 = $signed(activated_data_e_scaled_out_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_scaled_out_bits_denormShiftDist_T_4 = activated_data_e_scaled_out_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_scaled_out_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_scaled_out_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_scaled_out_bits_denormShiftDist_2 = _activated_data_e_scaled_out_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_scaled_out_bits_denormFract_T_4 = activated_data_e_scaled_out_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_scaled_out_bits_denormFract_T_5 = _activated_data_e_scaled_out_bits_denormFract_T_4 >> activated_data_e_scaled_out_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_scaled_out_bits_denormFract_2 = _activated_data_e_scaled_out_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_12 = activated_data_e_scaled_out_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_scaled_out_bits_expOut_T_13 = {1'h0, _activated_data_e_scaled_out_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_14 = _activated_data_e_scaled_out_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_15 = activated_data_e_scaled_out_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_scaled_out_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_scaled_out_bits_expOut_T_16 = activated_data_e_scaled_out_bits_rawIn_2_isNaN | activated_data_e_scaled_out_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_17 = {8{_activated_data_e_scaled_out_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_scaled_out_bits_expOut_2 = _activated_data_e_scaled_out_bits_expOut_T_15 | _activated_data_e_scaled_out_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_scaled_out_bits_fractOut_T_4 = activated_data_e_scaled_out_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_scaled_out_bits_fractOut_T_5 = activated_data_e_scaled_out_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_scaled_out_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_scaled_out_bits_fractOut_2 = activated_data_e_scaled_out_bits_isSubnormal_2 ? activated_data_e_scaled_out_bits_denormFract_2 : _activated_data_e_scaled_out_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_scaled_out_bits_hi_2 = {activated_data_e_scaled_out_bits_rawIn_2_sign, activated_data_e_scaled_out_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_scaled_out_bits_T_2 = {activated_data_e_scaled_out_bits_hi_2, activated_data_e_scaled_out_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_scaled_2_bits = _activated_data_e_scaled_out_bits_T_2; // @[fNFromRecFN.scala:66:12] wire activated_data_e_clipped_self_rec_rawIn_sign_2 = activated_data_e_scaled_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_clipped_self_rec_rawIn_2_sign = activated_data_e_clipped_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_clipped_self_rec_rawIn_expIn_2 = activated_data_e_scaled_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_clipped_self_rec_rawIn_fractIn_2 = activated_data_e_scaled_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_2 = activated_data_e_clipped_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_2 = activated_data_e_clipped_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_88 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_89 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_90 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_91 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_92 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_93 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_94 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_95 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_96 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_97 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_98 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_99 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_100 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_101 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_102 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_103 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_104 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_105 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_106 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_107 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_108 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_109 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_110 = activated_data_e_clipped_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_111 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_112 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_113 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_114 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_115 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_116 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_117 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_clipped_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_118 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_clipped_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_119 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_clipped_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_120 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_clipped_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_121 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_clipped_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_122 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_clipped_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_123 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_124 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_125 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_126 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_127 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_128 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_129 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_130 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_131 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_clipped_self_rec_rawIn_normDist_2 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_clipped_self_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_clipped_self_rec_rawIn_fractIn_2} << activated_data_e_clipped_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_clipped_self_rec_rawIn_subnormFract_T_5 = _activated_data_e_clipped_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_clipped_self_rec_rawIn_subnormFract_2 = {_activated_data_e_clipped_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_clipped_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_11 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_clipped_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_12 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_clipped_self_rec_rawIn_adjustedExp_2 = _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_4 = activated_data_e_clipped_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_clipped_self_rec_rawIn_isZero_2 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_2 & activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_clipped_self_rec_rawIn_2_isZero = activated_data_e_clipped_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_isSpecial_T_2 = activated_data_e_clipped_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_clipped_self_rec_rawIn_isSpecial_2 = &_activated_data_e_clipped_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_clipped_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_clipped_self_rec_T_18 = activated_data_e_clipped_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_clipped_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_clipped_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_clipped_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_5 = activated_data_e_clipped_self_rec_rawIn_isSpecial_2 & _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_clipped_self_rec_rawIn_2_isNaN = _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_clipped_self_rec_rawIn_out_isInf_T_2 = activated_data_e_clipped_self_rec_rawIn_isSpecial_2 & activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_clipped_self_rec_rawIn_2_isInf = _activated_data_e_clipped_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_clipped_self_rec_rawIn_2_sExp = _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_clipped_self_rec_rawIn_out_sig_T_8 = ~activated_data_e_clipped_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_10 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_2 ? activated_data_e_clipped_self_rec_rawIn_subnormFract_2 : activated_data_e_clipped_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_clipped_self_rec_rawIn_out_sig_T_11 = {_activated_data_e_clipped_self_rec_rawIn_out_sig_T_9, _activated_data_e_clipped_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_clipped_self_rec_rawIn_2_sig = _activated_data_e_clipped_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_clipped_self_rec_T_16 = activated_data_e_clipped_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_clipped_self_rec_T_17 = activated_data_e_clipped_self_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_clipped_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_clipped_self_rec_T_19 = {_activated_data_e_clipped_self_rec_T_17[2:1], _activated_data_e_clipped_self_rec_T_17[0] | _activated_data_e_clipped_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_clipped_self_rec_T_20 = {activated_data_e_clipped_self_rec_rawIn_2_sign, _activated_data_e_clipped_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_clipped_self_rec_T_21 = activated_data_e_clipped_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_clipped_self_rec_T_22 = {_activated_data_e_clipped_self_rec_T_20, _activated_data_e_clipped_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_clipped_self_rec_T_23 = activated_data_e_clipped_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_clipped_self_rec_2 = {_activated_data_e_clipped_self_rec_T_22, _activated_data_e_clipped_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_clipped_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_clipped_2_bits; // @[Arithmetic.scala:505:26] wire [31:0] _activated_data_WIRE_2_0_bits = activated_data_e_clipped_2_bits; // @[Arithmetic.scala:505:26] wire [8:0] activated_data_e_clipped_result_bits_rawIn_exp_2 = _activated_data_e_clipped_resizer_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_clipped_result_bits_rawIn_isZero_T_2 = activated_data_e_clipped_result_bits_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_clipped_result_bits_rawIn_isZero_2 = _activated_data_e_clipped_result_bits_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_clipped_result_bits_rawIn_2_isZero = activated_data_e_clipped_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_clipped_result_bits_rawIn_isSpecial_T_2 = activated_data_e_clipped_result_bits_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_clipped_result_bits_rawIn_isSpecial_2 = &_activated_data_e_clipped_result_bits_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_clipped_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_clipped_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_clipped_result_bits_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_clipped_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_clipped_result_bits_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_clipped_result_bits_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_clipped_result_bits_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_4 = activated_data_e_clipped_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_6 = activated_data_e_clipped_result_bits_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_5 = activated_data_e_clipped_result_bits_rawIn_isSpecial_2 & _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_clipped_result_bits_rawIn_2_isNaN = _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_7 = ~_activated_data_e_clipped_result_bits_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_8 = activated_data_e_clipped_result_bits_rawIn_isSpecial_2 & _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_clipped_result_bits_rawIn_2_isInf = _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_clipped_result_bits_rawIn_out_sign_T_2 = _activated_data_e_clipped_resizer_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_clipped_result_bits_rawIn_2_sign = _activated_data_e_clipped_result_bits_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_clipped_result_bits_rawIn_out_sExp_T_2 = {1'h0, activated_data_e_clipped_result_bits_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_clipped_result_bits_rawIn_2_sExp = _activated_data_e_clipped_result_bits_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_clipped_result_bits_rawIn_out_sig_T_8 = ~activated_data_e_clipped_result_bits_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_clipped_result_bits_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_10 = _activated_data_e_clipped_resizer_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_clipped_result_bits_rawIn_out_sig_T_11 = {_activated_data_e_clipped_result_bits_rawIn_out_sig_T_9, _activated_data_e_clipped_result_bits_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_clipped_result_bits_rawIn_2_sig = _activated_data_e_clipped_result_bits_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_clipped_result_bits_isSubnormal_2 = $signed(activated_data_e_clipped_result_bits_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_clipped_result_bits_denormShiftDist_T_4 = activated_data_e_clipped_result_bits_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_clipped_result_bits_denormShiftDist_T_5 = 6'h1 - {1'h0, _activated_data_e_clipped_result_bits_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_clipped_result_bits_denormShiftDist_2 = _activated_data_e_clipped_result_bits_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_clipped_result_bits_denormFract_T_4 = activated_data_e_clipped_result_bits_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_clipped_result_bits_denormFract_T_5 = _activated_data_e_clipped_result_bits_denormFract_T_4 >> activated_data_e_clipped_result_bits_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_clipped_result_bits_denormFract_2 = _activated_data_e_clipped_result_bits_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_12 = activated_data_e_clipped_result_bits_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_clipped_result_bits_expOut_T_13 = {1'h0, _activated_data_e_clipped_result_bits_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_14 = _activated_data_e_clipped_result_bits_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_15 = activated_data_e_clipped_result_bits_isSubnormal_2 ? 8'h0 : _activated_data_e_clipped_result_bits_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_clipped_result_bits_expOut_T_16 = activated_data_e_clipped_result_bits_rawIn_2_isNaN | activated_data_e_clipped_result_bits_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_17 = {8{_activated_data_e_clipped_result_bits_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_clipped_result_bits_expOut_2 = _activated_data_e_clipped_result_bits_expOut_T_15 | _activated_data_e_clipped_result_bits_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_clipped_result_bits_fractOut_T_4 = activated_data_e_clipped_result_bits_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_clipped_result_bits_fractOut_T_5 = activated_data_e_clipped_result_bits_rawIn_2_isInf ? 23'h0 : _activated_data_e_clipped_result_bits_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_clipped_result_bits_fractOut_2 = activated_data_e_clipped_result_bits_isSubnormal_2 ? activated_data_e_clipped_result_bits_denormFract_2 : _activated_data_e_clipped_result_bits_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_clipped_result_bits_hi_2 = {activated_data_e_clipped_result_bits_rawIn_2_sign, activated_data_e_clipped_result_bits_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_clipped_result_bits_T_2 = {activated_data_e_clipped_result_bits_hi_2, activated_data_e_clipped_result_bits_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_clipped_2_bits = _activated_data_e_clipped_result_bits_T_2; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_2_0_bits = _activated_data_WIRE_2_0_bits; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_49 = _activated_data_e_act_T_48; // @[AccumulatorScale.scala:118:{38,45}] wire activated_data_e_act_raw_sign_3 = io_in_bits_acc_read_resp_data_3_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_15 = io_in_bits_acc_read_resp_data_3_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_sign_t_rec_rawIn_sign_6 = io_in_bits_acc_read_resp_data_3_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_rec_rawIn_sign_6 = io_in_bits_acc_read_resp_data_3_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_sgn_3 = io_in_bits_acc_read_resp_data_3_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_17 = io_in_bits_acc_read_resp_data_3_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_sign_19 = io_in_bits_acc_read_resp_data_3_0_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_raw_3_sign = activated_data_e_act_raw_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_raw_expIn_3 = io_in_bits_acc_read_resp_data_3_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_15 = io_in_bits_acc_read_resp_data_3_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_sign_t_rec_rawIn_expIn_6 = io_in_bits_acc_read_resp_data_3_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_abs_t_rec_rawIn_expIn_6 = io_in_bits_acc_read_resp_data_3_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_17 = io_in_bits_acc_read_resp_data_3_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_19 = io_in_bits_acc_read_resp_data_3_0_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_raw_fractIn_3 = io_in_bits_acc_read_resp_data_3_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_15 = io_in_bits_acc_read_resp_data_3_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6 = io_in_bits_acc_read_resp_data_3_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6 = io_in_bits_acc_read_resp_data_3_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_17 = io_in_bits_acc_read_resp_data_3_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_19 = io_in_bits_acc_read_resp_data_3_0_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_raw_isZeroExpIn_3 = activated_data_e_act_raw_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_raw_isZeroFractIn_3 = activated_data_e_act_raw_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_raw_normDist_T_132 = activated_data_e_act_raw_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_133 = activated_data_e_act_raw_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_134 = activated_data_e_act_raw_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_135 = activated_data_e_act_raw_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_136 = activated_data_e_act_raw_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_137 = activated_data_e_act_raw_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_138 = activated_data_e_act_raw_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_139 = activated_data_e_act_raw_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_140 = activated_data_e_act_raw_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_141 = activated_data_e_act_raw_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_142 = activated_data_e_act_raw_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_143 = activated_data_e_act_raw_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_144 = activated_data_e_act_raw_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_145 = activated_data_e_act_raw_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_146 = activated_data_e_act_raw_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_147 = activated_data_e_act_raw_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_148 = activated_data_e_act_raw_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_149 = activated_data_e_act_raw_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_150 = activated_data_e_act_raw_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_151 = activated_data_e_act_raw_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_152 = activated_data_e_act_raw_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_153 = activated_data_e_act_raw_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_raw_normDist_T_154 = activated_data_e_act_raw_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_raw_normDist_T_155 = _activated_data_e_act_raw_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_156 = _activated_data_e_act_raw_normDist_T_134 ? 5'h14 : _activated_data_e_act_raw_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_157 = _activated_data_e_act_raw_normDist_T_135 ? 5'h13 : _activated_data_e_act_raw_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_158 = _activated_data_e_act_raw_normDist_T_136 ? 5'h12 : _activated_data_e_act_raw_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_159 = _activated_data_e_act_raw_normDist_T_137 ? 5'h11 : _activated_data_e_act_raw_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_160 = _activated_data_e_act_raw_normDist_T_138 ? 5'h10 : _activated_data_e_act_raw_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_161 = _activated_data_e_act_raw_normDist_T_139 ? 5'hF : _activated_data_e_act_raw_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_162 = _activated_data_e_act_raw_normDist_T_140 ? 5'hE : _activated_data_e_act_raw_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_163 = _activated_data_e_act_raw_normDist_T_141 ? 5'hD : _activated_data_e_act_raw_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_164 = _activated_data_e_act_raw_normDist_T_142 ? 5'hC : _activated_data_e_act_raw_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_165 = _activated_data_e_act_raw_normDist_T_143 ? 5'hB : _activated_data_e_act_raw_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_166 = _activated_data_e_act_raw_normDist_T_144 ? 5'hA : _activated_data_e_act_raw_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_167 = _activated_data_e_act_raw_normDist_T_145 ? 5'h9 : _activated_data_e_act_raw_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_168 = _activated_data_e_act_raw_normDist_T_146 ? 5'h8 : _activated_data_e_act_raw_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_169 = _activated_data_e_act_raw_normDist_T_147 ? 5'h7 : _activated_data_e_act_raw_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_170 = _activated_data_e_act_raw_normDist_T_148 ? 5'h6 : _activated_data_e_act_raw_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_171 = _activated_data_e_act_raw_normDist_T_149 ? 5'h5 : _activated_data_e_act_raw_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_172 = _activated_data_e_act_raw_normDist_T_150 ? 5'h4 : _activated_data_e_act_raw_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_173 = _activated_data_e_act_raw_normDist_T_151 ? 5'h3 : _activated_data_e_act_raw_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_174 = _activated_data_e_act_raw_normDist_T_152 ? 5'h2 : _activated_data_e_act_raw_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_raw_normDist_T_175 = _activated_data_e_act_raw_normDist_T_153 ? 5'h1 : _activated_data_e_act_raw_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_raw_normDist_3 = _activated_data_e_act_raw_normDist_T_154 ? 5'h0 : _activated_data_e_act_raw_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_raw_subnormFract_T_6 = {31'h0, activated_data_e_act_raw_fractIn_3} << activated_data_e_act_raw_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_raw_subnormFract_T_7 = _activated_data_e_act_raw_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_raw_subnormFract_3 = {_activated_data_e_act_raw_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_raw_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_raw_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_raw_adjustedExp_T_16 = activated_data_e_act_raw_isZeroExpIn_3 ? _activated_data_e_act_raw_adjustedExp_T_15 : {1'h0, activated_data_e_act_raw_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_raw_adjustedExp_T_17 = activated_data_e_act_raw_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_raw_adjustedExp_T_18 = {6'h20, _activated_data_e_act_raw_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_raw_adjustedExp_T_19 = {1'h0, _activated_data_e_act_raw_adjustedExp_T_16} + {2'h0, _activated_data_e_act_raw_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_raw_adjustedExp_3 = _activated_data_e_act_raw_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_raw_out_sExp_T_6 = activated_data_e_act_raw_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_raw_isZero_3 = activated_data_e_act_raw_isZeroExpIn_3 & activated_data_e_act_raw_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_raw_3_isZero = activated_data_e_act_raw_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_raw_isSpecial_T_3 = activated_data_e_act_raw_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_raw_isSpecial_3 = &_activated_data_e_act_raw_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_raw_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_raw_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire [9:0] _activated_data_e_act_raw_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_raw_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_raw_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_act_raw_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_raw_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_raw_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_raw_out_isNaN_T_6 = ~activated_data_e_act_raw_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_raw_out_isNaN_T_7 = activated_data_e_act_raw_isSpecial_3 & _activated_data_e_act_raw_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_raw_3_isNaN = _activated_data_e_act_raw_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_raw_out_isInf_T_3 = activated_data_e_act_raw_isSpecial_3 & activated_data_e_act_raw_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_raw_3_isInf = _activated_data_e_act_raw_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_raw_out_sExp_T_7 = {1'h0, _activated_data_e_act_raw_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_raw_3_sExp = _activated_data_e_act_raw_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_raw_out_sig_T_12 = ~activated_data_e_act_raw_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_raw_out_sig_T_13 = {1'h0, _activated_data_e_act_raw_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_raw_out_sig_T_14 = activated_data_e_act_raw_isZeroExpIn_3 ? activated_data_e_act_raw_subnormFract_3 : activated_data_e_act_raw_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_raw_out_sig_T_15 = {_activated_data_e_act_raw_out_sig_T_13, _activated_data_e_act_raw_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_raw_3_sig = _activated_data_e_act_raw_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [31:0] _activated_data_e_act_result_bits_T_23; // @[Arithmetic.scala:514:27] wire [31:0] activated_data_e_act_result_15_bits; // @[Arithmetic.scala:513:26] wire _activated_data_e_act_result_bits_T_21 = ~activated_data_e_act_raw_3_isZero; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_result_bits_T_22 = _activated_data_e_act_result_bits_T_21 & activated_data_e_act_raw_3_sign; // @[rawFloatFromFN.scala:63:19] assign _activated_data_e_act_result_bits_T_23 = _activated_data_e_act_result_bits_T_22 ? 32'h0 : io_in_bits_acc_read_resp_data_3_0_bits_0; // @[Arithmetic.scala:514:{27,40}] assign activated_data_e_act_result_15_bits = _activated_data_e_act_result_bits_T_23; // @[Arithmetic.scala:513:26, :514:27] wire activated_data_e_act_self_rec_rawIn_15_sign = activated_data_e_act_self_rec_rawIn_sign_15; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_15 = activated_data_e_act_self_rec_rawIn_expIn_15 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_15 = activated_data_e_act_self_rec_rawIn_fractIn_15 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_660 = activated_data_e_act_self_rec_rawIn_fractIn_15[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_661 = activated_data_e_act_self_rec_rawIn_fractIn_15[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_662 = activated_data_e_act_self_rec_rawIn_fractIn_15[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_663 = activated_data_e_act_self_rec_rawIn_fractIn_15[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_664 = activated_data_e_act_self_rec_rawIn_fractIn_15[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_665 = activated_data_e_act_self_rec_rawIn_fractIn_15[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_666 = activated_data_e_act_self_rec_rawIn_fractIn_15[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_667 = activated_data_e_act_self_rec_rawIn_fractIn_15[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_668 = activated_data_e_act_self_rec_rawIn_fractIn_15[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_669 = activated_data_e_act_self_rec_rawIn_fractIn_15[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_670 = activated_data_e_act_self_rec_rawIn_fractIn_15[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_671 = activated_data_e_act_self_rec_rawIn_fractIn_15[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_672 = activated_data_e_act_self_rec_rawIn_fractIn_15[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_673 = activated_data_e_act_self_rec_rawIn_fractIn_15[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_674 = activated_data_e_act_self_rec_rawIn_fractIn_15[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_675 = activated_data_e_act_self_rec_rawIn_fractIn_15[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_676 = activated_data_e_act_self_rec_rawIn_fractIn_15[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_677 = activated_data_e_act_self_rec_rawIn_fractIn_15[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_678 = activated_data_e_act_self_rec_rawIn_fractIn_15[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_679 = activated_data_e_act_self_rec_rawIn_fractIn_15[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_680 = activated_data_e_act_self_rec_rawIn_fractIn_15[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_681 = activated_data_e_act_self_rec_rawIn_fractIn_15[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_682 = activated_data_e_act_self_rec_rawIn_fractIn_15[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_683 = _activated_data_e_act_self_rec_rawIn_normDist_T_661 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_684 = _activated_data_e_act_self_rec_rawIn_normDist_T_662 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_683; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_685 = _activated_data_e_act_self_rec_rawIn_normDist_T_663 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_684; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_686 = _activated_data_e_act_self_rec_rawIn_normDist_T_664 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_685; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_687 = _activated_data_e_act_self_rec_rawIn_normDist_T_665 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_686; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_688 = _activated_data_e_act_self_rec_rawIn_normDist_T_666 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_687; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_689 = _activated_data_e_act_self_rec_rawIn_normDist_T_667 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_688; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_690 = _activated_data_e_act_self_rec_rawIn_normDist_T_668 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_689; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_691 = _activated_data_e_act_self_rec_rawIn_normDist_T_669 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_690; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_692 = _activated_data_e_act_self_rec_rawIn_normDist_T_670 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_691; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_693 = _activated_data_e_act_self_rec_rawIn_normDist_T_671 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_692; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_694 = _activated_data_e_act_self_rec_rawIn_normDist_T_672 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_693; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_695 = _activated_data_e_act_self_rec_rawIn_normDist_T_673 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_694; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_696 = _activated_data_e_act_self_rec_rawIn_normDist_T_674 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_695; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_697 = _activated_data_e_act_self_rec_rawIn_normDist_T_675 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_696; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_698 = _activated_data_e_act_self_rec_rawIn_normDist_T_676 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_697; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_699 = _activated_data_e_act_self_rec_rawIn_normDist_T_677 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_698; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_700 = _activated_data_e_act_self_rec_rawIn_normDist_T_678 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_699; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_701 = _activated_data_e_act_self_rec_rawIn_normDist_T_679 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_700; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_702 = _activated_data_e_act_self_rec_rawIn_normDist_T_680 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_701; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_703 = _activated_data_e_act_self_rec_rawIn_normDist_T_681 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_702; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_15 = _activated_data_e_act_self_rec_rawIn_normDist_T_682 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_703; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_30 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_15} << activated_data_e_act_self_rec_rawIn_normDist_15; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_31 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_30[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_15 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_31, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_75 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_15}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_76 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_15 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_75 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_15}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_77 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_15 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_78 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_77}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_79 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_76} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_78}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_15 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_79[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_30 = activated_data_e_act_self_rec_rawIn_adjustedExp_15; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_15 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_15 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_15_isZero = activated_data_e_act_self_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_15 = activated_data_e_act_self_rec_rawIn_adjustedExp_15[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_15 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_15; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_122 = activated_data_e_act_self_rec_rawIn_15_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_15_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_15_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_15_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_30 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_31 = activated_data_e_act_self_rec_rawIn_isSpecial_15 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_30; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_15_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_15 = activated_data_e_act_self_rec_rawIn_isSpecial_15 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_15_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_31 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_30}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_15_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_60 = ~activated_data_e_act_self_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_61 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_60}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_62 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_15 ? activated_data_e_act_self_rec_rawIn_subnormFract_15 : activated_data_e_act_self_rec_rawIn_fractIn_15; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_63 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_61, _activated_data_e_act_self_rec_rawIn_out_sig_T_62}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_15_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_120 = activated_data_e_act_self_rec_rawIn_15_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_121 = activated_data_e_act_self_rec_rawIn_15_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_120; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_123 = {_activated_data_e_act_self_rec_T_121[2:1], _activated_data_e_act_self_rec_T_121[0] | _activated_data_e_act_self_rec_T_122}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_124 = {activated_data_e_act_self_rec_rawIn_15_sign, _activated_data_e_act_self_rec_T_123}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_125 = activated_data_e_act_self_rec_rawIn_15_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_126 = {_activated_data_e_act_self_rec_T_124, _activated_data_e_act_self_rec_T_125}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_127 = activated_data_e_act_self_rec_rawIn_15_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_15 = {_activated_data_e_act_self_rec_T_126, _activated_data_e_act_self_rec_T_127}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_24; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_16_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_12 = _activated_data_e_act_muladder_12_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_12 = activated_data_e_act_result_bits_rawIn_exp_12[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_12 = _activated_data_e_act_result_bits_rawIn_isZero_T_12 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_12_isZero = activated_data_e_act_result_bits_rawIn_isZero_12; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_12 = activated_data_e_act_result_bits_rawIn_exp_12[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_12 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_12; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_25; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_38; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_12; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_12; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_51; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_12_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_12_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_12_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_12_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_12_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_24 = activated_data_e_act_result_bits_rawIn_exp_12[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_36 = activated_data_e_act_result_bits_rawIn_exp_12[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_25 = activated_data_e_act_result_bits_rawIn_isSpecial_12 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_24; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_12_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_25; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_37 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_36; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_38 = activated_data_e_act_result_bits_rawIn_isSpecial_12 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_37; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_12_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_38; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_12 = _activated_data_e_act_muladder_12_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_12_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_12; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_12 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_12}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_12_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_12; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_48 = ~activated_data_e_act_result_bits_rawIn_isZero_12; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_49 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_48}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_50 = _activated_data_e_act_muladder_12_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_51 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_49, _activated_data_e_act_result_bits_rawIn_out_sig_T_50}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_12_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_51; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_12 = $signed(activated_data_e_act_result_bits_rawIn_12_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_24 = activated_data_e_act_result_bits_rawIn_12_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_25 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_24}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_12 = _activated_data_e_act_result_bits_denormShiftDist_T_25[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_24 = activated_data_e_act_result_bits_rawIn_12_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_25 = _activated_data_e_act_result_bits_denormFract_T_24 >> activated_data_e_act_result_bits_denormShiftDist_12; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_12 = _activated_data_e_act_result_bits_denormFract_T_25[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_72 = activated_data_e_act_result_bits_rawIn_12_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_73 = {1'h0, _activated_data_e_act_result_bits_expOut_T_72} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_74 = _activated_data_e_act_result_bits_expOut_T_73[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_75 = activated_data_e_act_result_bits_isSubnormal_12 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_74; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_76 = activated_data_e_act_result_bits_rawIn_12_isNaN | activated_data_e_act_result_bits_rawIn_12_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_77 = {8{_activated_data_e_act_result_bits_expOut_T_76}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_12 = _activated_data_e_act_result_bits_expOut_T_75 | _activated_data_e_act_result_bits_expOut_T_77; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_24 = activated_data_e_act_result_bits_rawIn_12_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_25 = activated_data_e_act_result_bits_rawIn_12_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_24; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_12 = activated_data_e_act_result_bits_isSubnormal_12 ? activated_data_e_act_result_bits_denormFract_12 : _activated_data_e_act_result_bits_fractOut_T_25; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_12 = {activated_data_e_act_result_bits_rawIn_12_sign, activated_data_e_act_result_bits_expOut_12}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_24 = {activated_data_e_act_result_bits_hi_12, activated_data_e_act_result_bits_fractOut_12}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_16_bits = _activated_data_e_act_result_bits_T_24; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_sign_t_rec_rawIn_6_sign = activated_data_e_act_q_sign_t_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_q_sign_t_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_264 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_265 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_266 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_267 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_268 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_269 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_270 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_271 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_272 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_273 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_274 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_275 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_276 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_277 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_278 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_279 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_280 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_281 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_282 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_283 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_284 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_285 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_286 = activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_287 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_288 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_289 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_290 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_291 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_292 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_293 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_294 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_295 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_296 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_297 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_298 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_299 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_300 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_301 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_302 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_303 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_304 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_305 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_306 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_307 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_sign_t_rec_rawIn_normDist_6 = _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_q_sign_t_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6} << activated_data_e_act_q_sign_t_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_6 = {_activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_q_sign_t_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_q_sign_t_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_6 = _activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_12 = activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_sign_t_rec_rawIn_isZero_6 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_sign_t_rec_rawIn_6_isZero = activated_data_e_act_q_sign_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T_6 = activated_data_e_act_q_sign_t_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_6 = &_activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_sign_t_rec_T_50 = activated_data_e_act_q_sign_t_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_sign_t_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_sign_t_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_sign_t_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_6 & _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_sign_t_rec_rawIn_6_isNaN = _activated_data_e_act_q_sign_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_6 = activated_data_e_act_q_sign_t_rec_rawIn_isSpecial_6 & activated_data_e_act_q_sign_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_sign_t_rec_rawIn_6_isInf = _activated_data_e_act_q_sign_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_sign_t_rec_rawIn_6_sExp = _activated_data_e_act_q_sign_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_q_sign_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_26 = activated_data_e_act_q_sign_t_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_q_sign_t_rec_rawIn_subnormFract_6 : activated_data_e_act_q_sign_t_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_25, _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_sign_t_rec_rawIn_6_sig = _activated_data_e_act_q_sign_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_48 = activated_data_e_act_q_sign_t_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_49 = activated_data_e_act_q_sign_t_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_q_sign_t_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_sign_t_rec_T_51 = {_activated_data_e_act_q_sign_t_rec_T_49[2:1], _activated_data_e_act_q_sign_t_rec_T_49[0] | _activated_data_e_act_q_sign_t_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_sign_t_rec_T_52 = {activated_data_e_act_q_sign_t_rec_rawIn_6_sign, _activated_data_e_act_q_sign_t_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_sign_t_rec_T_53 = activated_data_e_act_q_sign_t_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_sign_t_rec_T_54 = {_activated_data_e_act_q_sign_t_rec_T_52, _activated_data_e_act_q_sign_t_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_sign_t_rec_T_55 = activated_data_e_act_q_sign_t_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_sign_t_rec_6 = {_activated_data_e_act_q_sign_t_rec_T_54, _activated_data_e_act_q_sign_t_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] activated_data_e_act_q_sign_3_bits = {_activated_data_e_act_q_sign_comparator_3_io_gt, 31'h3F800000}; // @[Arithmetic.scala:475:32] wire activated_data_e_act_q_abs_t_rec_rawIn_6_sign = activated_data_e_act_q_abs_t_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_q_abs_t_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_264 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_265 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_266 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_267 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_268 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_269 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_270 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_271 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_272 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_273 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_274 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_275 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_276 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_277 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_278 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_279 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_280 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_281 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_282 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_283 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_284 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_285 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_286 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_287 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_288 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_289 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_290 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_291 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_292 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_293 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_294 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_295 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_296 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_297 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_298 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_299 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_300 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_301 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_302 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_303 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_304 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_305 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_306 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_307 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_t_rec_rawIn_normDist_6 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6} << activated_data_e_act_q_abs_t_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_6 = {_activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_q_abs_t_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_q_abs_t_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_6 = _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_12 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_abs_t_rec_rawIn_isZero_6 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_abs_t_rec_rawIn_6_isZero = activated_data_e_act_q_abs_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_6 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_6 = &_activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_t_rec_T_50 = activated_data_e_act_q_abs_t_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_abs_t_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_abs_t_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_abs_t_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_6 & _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_abs_t_rec_rawIn_6_isNaN = _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_6 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_6 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_abs_t_rec_rawIn_6_isInf = _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_abs_t_rec_rawIn_6_sExp = _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_26 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_6 : activated_data_e_act_q_abs_t_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_25, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_abs_t_rec_rawIn_6_sig = _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_48 = activated_data_e_act_q_abs_t_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_49 = activated_data_e_act_q_abs_t_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_q_abs_t_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_51 = {_activated_data_e_act_q_abs_t_rec_T_49[2:1], _activated_data_e_act_q_abs_t_rec_T_49[0] | _activated_data_e_act_q_abs_t_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_abs_t_rec_T_52 = {activated_data_e_act_q_abs_t_rec_rawIn_6_sign, _activated_data_e_act_q_abs_t_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_abs_t_rec_T_53 = activated_data_e_act_q_abs_t_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_abs_t_rec_T_54 = {_activated_data_e_act_q_abs_t_rec_T_52, _activated_data_e_act_q_abs_t_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_abs_t_rec_T_55 = activated_data_e_act_q_abs_t_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_abs_t_rec_6 = {_activated_data_e_act_q_abs_t_rec_T_54, _activated_data_e_act_q_abs_t_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _activated_data_e_act_q_abs_neg_t_T_12 = ~activated_data_e_act_q_abs_t_sgn_3; // @[Arithmetic.scala:432:27, :433:25] wire [30:0] _activated_data_e_act_q_abs_neg_t_T_13 = io_in_bits_acc_read_resp_data_3_0_bits_0[30:0]; // @[Arithmetic.scala:433:39] wire [31:0] _activated_data_e_act_q_abs_neg_t_T_14 = {_activated_data_e_act_q_abs_neg_t_T_12, _activated_data_e_act_q_abs_neg_t_T_13}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_abs_neg_t_WIRE_3 = _activated_data_e_act_q_abs_neg_t_T_14; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_abs_neg_t_T_15; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_abs_neg_t_3_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_abs_neg_t_T_15 = _activated_data_e_act_q_abs_neg_t_WIRE_3; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_abs_neg_t_3_bits = _activated_data_e_act_q_abs_neg_t_T_15; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_abs_t_rec_rawIn_sign_7 = activated_data_e_act_q_abs_neg_t_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_abs_t_rec_rawIn_7_sign = activated_data_e_act_q_abs_t_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_abs_t_rec_rawIn_expIn_7 = activated_data_e_act_q_abs_neg_t_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7 = activated_data_e_act_q_abs_neg_t_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_7 = activated_data_e_act_q_abs_t_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_7 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_308 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_309 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_310 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_311 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_312 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_313 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_314 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_315 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_316 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_317 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_318 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_319 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_320 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_321 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_322 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_323 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_324 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_325 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_326 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_327 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_328 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_329 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_330 = activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_331 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_332 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_333 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_334 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_335 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_336 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_337 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_338 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_339 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_340 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_341 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_342 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_343 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_344 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_345 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_346 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_347 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_348 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_349 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_350 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_351 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_abs_t_rec_rawIn_normDist_7 = _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_act_q_abs_t_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7} << activated_data_e_act_q_abs_t_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_15 = _activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_7 = {_activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_act_q_abs_t_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_36 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_act_q_abs_t_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_37 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_7 = _activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_14 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_abs_t_rec_rawIn_isZero_7 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_7 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_abs_t_rec_rawIn_7_isZero = activated_data_e_act_q_abs_t_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_7 = activated_data_e_act_q_abs_t_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_7 = &_activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_abs_t_rec_T_58 = activated_data_e_act_q_abs_t_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_abs_t_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_abs_t_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_abs_t_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_15 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_7 & _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_abs_t_rec_rawIn_7_isNaN = _activated_data_e_act_q_abs_t_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_7 = activated_data_e_act_q_abs_t_rec_rawIn_isSpecial_7 & activated_data_e_act_q_abs_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_abs_t_rec_rawIn_7_isInf = _activated_data_e_act_q_abs_t_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_abs_t_rec_rawIn_7_sExp = _activated_data_e_act_q_abs_t_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_28 = ~activated_data_e_act_q_abs_t_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_30 = activated_data_e_act_q_abs_t_rec_rawIn_isZeroExpIn_7 ? activated_data_e_act_q_abs_t_rec_rawIn_subnormFract_7 : activated_data_e_act_q_abs_t_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_31 = {_activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_29, _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_abs_t_rec_rawIn_7_sig = _activated_data_e_act_q_abs_t_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_56 = activated_data_e_act_q_abs_t_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_57 = activated_data_e_act_q_abs_t_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_act_q_abs_t_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_abs_t_rec_T_59 = {_activated_data_e_act_q_abs_t_rec_T_57[2:1], _activated_data_e_act_q_abs_t_rec_T_57[0] | _activated_data_e_act_q_abs_t_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_abs_t_rec_T_60 = {activated_data_e_act_q_abs_t_rec_rawIn_7_sign, _activated_data_e_act_q_abs_t_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_abs_t_rec_T_61 = activated_data_e_act_q_abs_t_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_abs_t_rec_T_62 = {_activated_data_e_act_q_abs_t_rec_T_60, _activated_data_e_act_q_abs_t_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_abs_t_rec_T_63 = activated_data_e_act_q_abs_t_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_abs_t_rec_7 = {_activated_data_e_act_q_abs_t_rec_T_62, _activated_data_e_act_q_abs_t_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_abs_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_abs_result_3_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_abs_result_bits_rawIn_exp_3 = _activated_data_e_act_q_abs_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_abs_result_bits_rawIn_isZero_T_3 = activated_data_e_act_q_abs_result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_abs_result_bits_rawIn_isZero_3 = _activated_data_e_act_q_abs_result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_abs_result_bits_rawIn_3_isZero = activated_data_e_act_q_abs_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_T_3 = activated_data_e_act_q_abs_result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_3 = &_activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_abs_result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_abs_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_abs_result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_abs_result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_abs_result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_q_abs_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_9 = activated_data_e_act_q_abs_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_abs_result_bits_rawIn_3_isNaN = _activated_data_e_act_q_abs_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_11 = activated_data_e_act_q_abs_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_abs_result_bits_rawIn_3_isInf = _activated_data_e_act_q_abs_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T_3 = _activated_data_e_act_q_abs_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_abs_result_bits_rawIn_3_sign = _activated_data_e_act_q_abs_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_q_abs_result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_abs_result_bits_rawIn_3_sExp = _activated_data_e_act_q_abs_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_q_abs_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_14 = _activated_data_e_act_q_abs_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_13, _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_abs_result_bits_rawIn_3_sig = _activated_data_e_act_q_abs_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_abs_result_bits_isSubnormal_3 = $signed(activated_data_e_act_q_abs_result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_6 = activated_data_e_act_q_abs_result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_abs_result_bits_denormShiftDist_3 = _activated_data_e_act_q_abs_result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_abs_result_bits_denormFract_T_6 = activated_data_e_act_q_abs_result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_abs_result_bits_denormFract_T_7 = _activated_data_e_act_q_abs_result_bits_denormFract_T_6 >> activated_data_e_act_q_abs_result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_abs_result_bits_denormFract_3 = _activated_data_e_act_q_abs_result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_18 = activated_data_e_act_q_abs_result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_abs_result_bits_expOut_T_19 = {1'h0, _activated_data_e_act_q_abs_result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_20 = _activated_data_e_act_q_abs_result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_21 = activated_data_e_act_q_abs_result_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_q_abs_result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_abs_result_bits_expOut_T_22 = activated_data_e_act_q_abs_result_bits_rawIn_3_isNaN | activated_data_e_act_q_abs_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_abs_result_bits_expOut_T_23 = {8{_activated_data_e_act_q_abs_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_abs_result_bits_expOut_3 = _activated_data_e_act_q_abs_result_bits_expOut_T_21 | _activated_data_e_act_q_abs_result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_abs_result_bits_fractOut_T_6 = activated_data_e_act_q_abs_result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_abs_result_bits_fractOut_T_7 = activated_data_e_act_q_abs_result_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_q_abs_result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_abs_result_bits_fractOut_3 = activated_data_e_act_q_abs_result_bits_isSubnormal_3 ? activated_data_e_act_q_abs_result_bits_denormFract_3 : _activated_data_e_act_q_abs_result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_abs_result_bits_hi_3 = {activated_data_e_act_q_abs_result_bits_rawIn_3_sign, activated_data_e_act_q_abs_result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_abs_result_bits_T_3 = {activated_data_e_act_q_abs_result_bits_hi_3, activated_data_e_act_q_abs_result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_abs_result_3_bits = _activated_data_e_act_q_abs_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_abs_3_bits = _activated_data_e_act_q_abs_comparator_3_io_gt ? activated_data_e_act_q_abs_result_3_bits : io_in_bits_acc_read_resp_data_3_0_bits_0; // @[Arithmetic.scala:426:26, :475:32] wire _activated_data_e_act_q_clipped_neg_t_T_24 = ~activated_data_e_act_q_clipped_t_sgn_6; // @[Arithmetic.scala:432:27, :433:25] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_26 = {_activated_data_e_act_q_clipped_neg_t_T_24, _activated_data_e_act_q_clipped_neg_t_T_25}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_WIRE_6 = _activated_data_e_act_q_clipped_neg_t_T_26; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_27; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_clipped_neg_t_6_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_clipped_neg_t_T_27 = _activated_data_e_act_q_clipped_neg_t_WIRE_6; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_clipped_neg_t_6_bits = _activated_data_e_act_q_clipped_neg_t_T_27; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_9 = activated_data_e_act_q_clipped_neg_t_6_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_9_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_9; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_9 = activated_data_e_act_q_clipped_neg_t_6_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9 = activated_data_e_act_q_clipped_neg_t_6_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_9 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_9 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_9 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_396 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_397 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_398 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_399 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_400 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_401 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_402 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_403 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_404 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_405 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_406 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_407 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_408 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_409 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_410 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_411 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_412 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_413 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_414 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_415 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_416 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_417 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_418 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_419 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_397 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_420 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_398 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_419; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_421 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_399 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_420; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_422 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_400 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_421; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_423 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_401 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_422; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_424 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_402 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_423; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_425 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_403 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_424; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_426 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_404 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_425; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_427 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_405 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_426; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_428 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_406 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_427; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_429 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_407 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_428; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_430 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_408 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_429; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_431 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_409 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_430; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_432 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_410 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_431; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_433 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_411 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_432; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_434 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_412 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_433; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_435 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_413 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_434; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_436 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_414 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_435; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_437 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_415 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_436; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_438 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_416 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_437; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_439 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_417 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_438; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_9 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_418 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_439; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_18 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_9; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_19 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_18[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_9 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_19, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_45 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_9}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_46 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_9 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_45 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_9}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_47 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_9 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_48 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_47}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_49 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_46} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_48}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_9 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_49[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_18 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_9; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_9 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_9 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_9_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_9 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_9[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_9 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_9; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_74 = activated_data_e_act_q_clipped_t_rec_rawIn_9_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_9_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_9_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_9_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_18 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_19 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_9 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_18; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_9_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_9 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_9 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_9_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_19 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_18}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_9_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_36 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_37 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_36}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_38 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_9 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_9 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_9; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_39 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_37, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_38}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_9_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_72 = activated_data_e_act_q_clipped_t_rec_rawIn_9_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_73 = activated_data_e_act_q_clipped_t_rec_rawIn_9_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_72; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_75 = {_activated_data_e_act_q_clipped_t_rec_T_73[2:1], _activated_data_e_act_q_clipped_t_rec_T_73[0] | _activated_data_e_act_q_clipped_t_rec_T_74}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_76 = {activated_data_e_act_q_clipped_t_rec_rawIn_9_sign, _activated_data_e_act_q_clipped_t_rec_T_75}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_77 = activated_data_e_act_q_clipped_t_rec_rawIn_9_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_78 = {_activated_data_e_act_q_clipped_t_rec_T_76, _activated_data_e_act_q_clipped_t_rec_T_77}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_79 = activated_data_e_act_q_clipped_t_rec_rawIn_9_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_9 = {_activated_data_e_act_q_clipped_t_rec_T_78, _activated_data_e_act_q_clipped_t_rec_T_79}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_clipped_result_bits_T_6; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_result_6_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_clipped_result_bits_rawIn_exp_6 = _activated_data_e_act_q_clipped_muladder_6_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_6 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_6[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isZero_6 = _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_6 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_clipped_result_bits_rawIn_6_isZero = activated_data_e_act_q_clipped_result_bits_rawIn_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_6 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_6[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_6 = &_activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_6; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_20; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_6; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_6; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_27; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_clipped_result_bits_rawIn_6_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_6_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_6_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_clipped_result_bits_rawIn_6_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_clipped_result_bits_rawIn_6_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_12 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_18 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_13 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_6 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_12; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_clipped_result_bits_rawIn_6_isNaN = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_19 = ~_activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_18; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_20 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_6 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_19; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_clipped_result_bits_rawIn_6_isInf = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_20; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_6 = _activated_data_e_act_q_clipped_muladder_6_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_clipped_result_bits_rawIn_6_sign = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_6; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_6 = {1'h0, activated_data_e_act_q_clipped_result_bits_rawIn_exp_6}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_clipped_result_bits_rawIn_6_sExp = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_6; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_24 = ~activated_data_e_act_q_clipped_result_bits_rawIn_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_24}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_26 = _activated_data_e_act_q_clipped_muladder_6_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_27 = {_activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_25, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_26}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_clipped_result_bits_rawIn_6_sig = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_27; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_clipped_result_bits_isSubnormal_6 = $signed(activated_data_e_act_q_clipped_result_bits_rawIn_6_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_12 = activated_data_e_act_q_clipped_result_bits_rawIn_6_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_13 = 6'h1 - {1'h0, _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_12}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_clipped_result_bits_denormShiftDist_6 = _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_13[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_12 = activated_data_e_act_q_clipped_result_bits_rawIn_6_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_13 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_12 >> activated_data_e_act_q_clipped_result_bits_denormShiftDist_6; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_clipped_result_bits_denormFract_6 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_13[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_36 = activated_data_e_act_q_clipped_result_bits_rawIn_6_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_37 = {1'h0, _activated_data_e_act_q_clipped_result_bits_expOut_T_36} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_38 = _activated_data_e_act_q_clipped_result_bits_expOut_T_37[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_39 = activated_data_e_act_q_clipped_result_bits_isSubnormal_6 ? 8'h0 : _activated_data_e_act_q_clipped_result_bits_expOut_T_38; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_clipped_result_bits_expOut_T_40 = activated_data_e_act_q_clipped_result_bits_rawIn_6_isNaN | activated_data_e_act_q_clipped_result_bits_rawIn_6_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_41 = {8{_activated_data_e_act_q_clipped_result_bits_expOut_T_40}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_clipped_result_bits_expOut_6 = _activated_data_e_act_q_clipped_result_bits_expOut_T_39 | _activated_data_e_act_q_clipped_result_bits_expOut_T_41; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_12 = activated_data_e_act_q_clipped_result_bits_rawIn_6_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_13 = activated_data_e_act_q_clipped_result_bits_rawIn_6_isInf ? 23'h0 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_12; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_clipped_result_bits_fractOut_6 = activated_data_e_act_q_clipped_result_bits_isSubnormal_6 ? activated_data_e_act_q_clipped_result_bits_denormFract_6 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_13; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_clipped_result_bits_hi_6 = {activated_data_e_act_q_clipped_result_bits_rawIn_6_sign, activated_data_e_act_q_clipped_result_bits_expOut_6}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_clipped_result_bits_T_6 = {activated_data_e_act_q_clipped_result_bits_hi_6, activated_data_e_act_q_clipped_result_bits_fractOut_6}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_clipped_result_6_bits = _activated_data_e_act_q_clipped_result_bits_T_6; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_10 = activated_data_e_act_q_clipped_result_6_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_10_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_10; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_10 = activated_data_e_act_q_clipped_result_6_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10 = activated_data_e_act_q_clipped_result_6_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_10 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_10 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_10 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_440 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_441 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_442 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_443 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_444 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_445 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_446 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_447 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_448 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_449 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_450 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_451 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_452 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_453 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_454 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_455 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_456 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_457 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_458 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_459 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_460 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_461 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_462 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_463 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_441 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_464 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_442 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_463; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_465 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_443 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_464; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_466 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_444 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_465; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_467 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_445 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_466; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_468 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_446 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_467; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_469 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_447 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_468; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_470 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_448 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_469; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_471 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_449 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_470; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_472 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_450 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_471; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_473 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_451 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_472; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_474 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_452 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_473; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_475 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_453 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_474; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_476 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_454 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_475; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_477 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_455 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_476; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_478 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_456 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_477; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_479 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_457 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_478; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_480 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_458 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_479; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_481 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_459 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_480; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_482 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_460 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_481; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_483 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_461 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_482; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_10 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_462 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_483; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_20 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_10; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_21 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_20[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_10 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_21, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_50 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_10}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_51 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_10 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_50 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_10}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_52 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_10 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_53 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_52}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_54 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_51} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_53}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_10 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_54[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_20 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_10; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_10 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_10 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_10_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_10 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_10[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_10 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_10; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_82 = activated_data_e_act_q_clipped_t_rec_rawIn_10_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_10_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_10_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_10_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_20 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_21 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_10 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_20; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_10_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_10 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_10 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_10_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_21 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_20}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_10_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_40 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_40}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_42 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_10 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_10 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_10; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_43 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_41, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_42}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_10_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_80 = activated_data_e_act_q_clipped_t_rec_rawIn_10_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_81 = activated_data_e_act_q_clipped_t_rec_rawIn_10_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_80; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_83 = {_activated_data_e_act_q_clipped_t_rec_T_81[2:1], _activated_data_e_act_q_clipped_t_rec_T_81[0] | _activated_data_e_act_q_clipped_t_rec_T_82}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_84 = {activated_data_e_act_q_clipped_t_rec_rawIn_10_sign, _activated_data_e_act_q_clipped_t_rec_T_83}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_85 = activated_data_e_act_q_clipped_t_rec_rawIn_10_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_86 = {_activated_data_e_act_q_clipped_t_rec_T_84, _activated_data_e_act_q_clipped_t_rec_T_85}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_87 = activated_data_e_act_q_clipped_t_rec_rawIn_10_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_10 = {_activated_data_e_act_q_clipped_t_rec_T_86, _activated_data_e_act_q_clipped_t_rec_T_87}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_clipped_self_rec_rawIn_sign_10 = activated_data_e_act_q_abs_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_self_rec_rawIn_10_sign = activated_data_e_act_q_clipped_self_rec_rawIn_sign_10; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_self_rec_rawIn_expIn_10 = activated_data_e_act_q_abs_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10 = activated_data_e_act_q_abs_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_10 = activated_data_e_act_q_clipped_self_rec_rawIn_expIn_10 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_10 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_440 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_441 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_442 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_443 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_444 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_445 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_446 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_447 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_448 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_449 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_450 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_451 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_452 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_453 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_454 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_455 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_456 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_457 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_458 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_459 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_460 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_461 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_462 = activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_463 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_441 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_464 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_442 ? 5'h14 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_463; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_465 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_443 ? 5'h13 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_464; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_466 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_444 ? 5'h12 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_465; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_467 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_445 ? 5'h11 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_466; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_468 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_446 ? 5'h10 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_467; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_469 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_447 ? 5'hF : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_468; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_470 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_448 ? 5'hE : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_469; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_471 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_449 ? 5'hD : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_470; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_472 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_450 ? 5'hC : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_471; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_473 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_451 ? 5'hB : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_472; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_474 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_452 ? 5'hA : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_473; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_475 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_453 ? 5'h9 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_474; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_476 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_454 ? 5'h8 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_475; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_477 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_455 ? 5'h7 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_476; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_478 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_456 ? 5'h6 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_477; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_479 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_457 ? 5'h5 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_478; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_480 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_458 ? 5'h4 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_479; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_481 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_459 ? 5'h3 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_480; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_482 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_460 ? 5'h2 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_481; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_483 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_461 ? 5'h1 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_482; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_self_rec_rawIn_normDist_10 = _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_462 ? 5'h0 : _activated_data_e_act_q_clipped_self_rec_rawIn_normDist_T_483; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_20 = {31'h0, activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10} << activated_data_e_act_q_clipped_self_rec_rawIn_normDist_10; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_21 = _activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_20[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_10 = {_activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_T_21, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_50 = {4'hF, ~activated_data_e_act_q_clipped_self_rec_rawIn_normDist_10}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_51 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_10 ? _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_50 : {1'h0, activated_data_e_act_q_clipped_self_rec_rawIn_expIn_10}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_52 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_10 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_53 = {6'h20, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_52}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_54 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_51} + {2'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_53}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_10 = _activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_T_54[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_20 = activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_10; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_self_rec_rawIn_isZero_10 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_10 & activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_self_rec_rawIn_10_isZero = activated_data_e_act_q_clipped_self_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_10 = activated_data_e_act_q_clipped_self_rec_rawIn_adjustedExp_10[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_10 = &_activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_T_10; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_self_rec_T_82 = activated_data_e_act_q_clipped_self_rec_rawIn_10_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_self_rec_rawIn_10_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_self_rec_rawIn_10_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_self_rec_rawIn_10_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_20 = ~activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_21 = activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_10 & _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_20; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_self_rec_rawIn_10_isNaN = _activated_data_e_act_q_clipped_self_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_10 = activated_data_e_act_q_clipped_self_rec_rawIn_isSpecial_10 & activated_data_e_act_q_clipped_self_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_self_rec_rawIn_10_isInf = _activated_data_e_act_q_clipped_self_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_21 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_20}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_self_rec_rawIn_10_sExp = _activated_data_e_act_q_clipped_self_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_40 = ~activated_data_e_act_q_clipped_self_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_40}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_42 = activated_data_e_act_q_clipped_self_rec_rawIn_isZeroExpIn_10 ? activated_data_e_act_q_clipped_self_rec_rawIn_subnormFract_10 : activated_data_e_act_q_clipped_self_rec_rawIn_fractIn_10; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_43 = {_activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_41, _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_42}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_self_rec_rawIn_10_sig = _activated_data_e_act_q_clipped_self_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_80 = activated_data_e_act_q_clipped_self_rec_rawIn_10_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_81 = activated_data_e_act_q_clipped_self_rec_rawIn_10_isZero ? 3'h0 : _activated_data_e_act_q_clipped_self_rec_T_80; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_self_rec_T_83 = {_activated_data_e_act_q_clipped_self_rec_T_81[2:1], _activated_data_e_act_q_clipped_self_rec_T_81[0] | _activated_data_e_act_q_clipped_self_rec_T_82}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_self_rec_T_84 = {activated_data_e_act_q_clipped_self_rec_rawIn_10_sign, _activated_data_e_act_q_clipped_self_rec_T_83}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_self_rec_T_85 = activated_data_e_act_q_clipped_self_rec_rawIn_10_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_self_rec_T_86 = {_activated_data_e_act_q_clipped_self_rec_T_84, _activated_data_e_act_q_clipped_self_rec_T_85}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_self_rec_T_87 = activated_data_e_act_q_clipped_self_rec_rawIn_10_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_self_rec_10 = {_activated_data_e_act_q_clipped_self_rec_T_86, _activated_data_e_act_q_clipped_self_rec_T_87}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _activated_data_e_act_q_clipped_neg_t_T_28 = ~activated_data_e_act_q_clipped_t_sgn_7; // @[Arithmetic.scala:432:27, :433:25] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_30 = {_activated_data_e_act_q_clipped_neg_t_T_28, _activated_data_e_act_q_clipped_neg_t_T_29}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_WIRE_7 = _activated_data_e_act_q_clipped_neg_t_T_30; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_q_clipped_neg_t_T_31; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_q_clipped_neg_t_7_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_q_clipped_neg_t_T_31 = _activated_data_e_act_q_clipped_neg_t_WIRE_7; // @[Arithmetic.scala:433:65] assign activated_data_e_act_q_clipped_neg_t_7_bits = _activated_data_e_act_q_clipped_neg_t_T_31; // @[Arithmetic.scala:433:65] wire activated_data_e_act_q_clipped_t_rec_rawIn_sign_11 = activated_data_e_act_q_clipped_neg_t_7_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_clipped_t_rec_rawIn_11_sign = activated_data_e_act_q_clipped_t_rec_rawIn_sign_11; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_clipped_t_rec_rawIn_expIn_11 = activated_data_e_act_q_clipped_neg_t_7_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11 = activated_data_e_act_q_clipped_neg_t_7_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_11 = activated_data_e_act_q_clipped_t_rec_rawIn_expIn_11 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_11 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_484 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_485 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_486 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_487 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_488 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_489 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_490 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_491 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_492 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_493 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_494 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_495 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_496 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_497 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_498 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_499 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_500 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_501 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_502 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_503 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_504 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_505 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_506 = activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_507 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_485 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_508 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_486 ? 5'h14 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_507; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_509 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_487 ? 5'h13 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_508; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_510 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_488 ? 5'h12 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_509; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_511 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_489 ? 5'h11 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_510; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_512 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_490 ? 5'h10 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_511; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_513 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_491 ? 5'hF : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_512; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_514 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_492 ? 5'hE : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_513; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_515 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_493 ? 5'hD : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_514; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_516 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_494 ? 5'hC : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_515; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_517 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_495 ? 5'hB : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_516; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_518 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_496 ? 5'hA : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_517; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_519 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_497 ? 5'h9 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_518; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_520 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_498 ? 5'h8 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_519; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_521 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_499 ? 5'h7 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_520; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_522 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_500 ? 5'h6 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_521; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_523 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_501 ? 5'h5 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_522; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_524 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_502 ? 5'h4 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_523; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_525 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_503 ? 5'h3 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_524; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_526 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_504 ? 5'h2 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_525; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_527 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_505 ? 5'h1 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_526; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_clipped_t_rec_rawIn_normDist_11 = _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_506 ? 5'h0 : _activated_data_e_act_q_clipped_t_rec_rawIn_normDist_T_527; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_22 = {31'h0, activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11} << activated_data_e_act_q_clipped_t_rec_rawIn_normDist_11; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_23 = _activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_22[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_11 = {_activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_T_23, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_55 = {4'hF, ~activated_data_e_act_q_clipped_t_rec_rawIn_normDist_11}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_56 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_11 ? _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_55 : {1'h0, activated_data_e_act_q_clipped_t_rec_rawIn_expIn_11}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_57 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_11 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_58 = {6'h20, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_57}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_59 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_56} + {2'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_58}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_11 = _activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_T_59[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_22 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_11; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_clipped_t_rec_rawIn_isZero_11 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_11 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_clipped_t_rec_rawIn_11_isZero = activated_data_e_act_q_clipped_t_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_11 = activated_data_e_act_q_clipped_t_rec_rawIn_adjustedExp_11[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_11 = &_activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_T_11; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_clipped_t_rec_T_90 = activated_data_e_act_q_clipped_t_rec_rawIn_11_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_clipped_t_rec_rawIn_11_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_clipped_t_rec_rawIn_11_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_clipped_t_rec_rawIn_11_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_22 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_23 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_11 & _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_22; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_clipped_t_rec_rawIn_11_isNaN = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_11 = activated_data_e_act_q_clipped_t_rec_rawIn_isSpecial_11 & activated_data_e_act_q_clipped_t_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_clipped_t_rec_rawIn_11_isInf = _activated_data_e_act_q_clipped_t_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_23 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_22}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_clipped_t_rec_rawIn_11_sExp = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_44 = ~activated_data_e_act_q_clipped_t_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_45 = {1'h0, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_44}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_46 = activated_data_e_act_q_clipped_t_rec_rawIn_isZeroExpIn_11 ? activated_data_e_act_q_clipped_t_rec_rawIn_subnormFract_11 : activated_data_e_act_q_clipped_t_rec_rawIn_fractIn_11; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_47 = {_activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_45, _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_46}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_clipped_t_rec_rawIn_11_sig = _activated_data_e_act_q_clipped_t_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_88 = activated_data_e_act_q_clipped_t_rec_rawIn_11_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_89 = activated_data_e_act_q_clipped_t_rec_rawIn_11_isZero ? 3'h0 : _activated_data_e_act_q_clipped_t_rec_T_88; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_clipped_t_rec_T_91 = {_activated_data_e_act_q_clipped_t_rec_T_89[2:1], _activated_data_e_act_q_clipped_t_rec_T_89[0] | _activated_data_e_act_q_clipped_t_rec_T_90}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_clipped_t_rec_T_92 = {activated_data_e_act_q_clipped_t_rec_rawIn_11_sign, _activated_data_e_act_q_clipped_t_rec_T_91}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_clipped_t_rec_T_93 = activated_data_e_act_q_clipped_t_rec_rawIn_11_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_clipped_t_rec_T_94 = {_activated_data_e_act_q_clipped_t_rec_T_92, _activated_data_e_act_q_clipped_t_rec_T_93}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_clipped_t_rec_T_95 = activated_data_e_act_q_clipped_t_rec_rawIn_11_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_clipped_t_rec_11 = {_activated_data_e_act_q_clipped_t_rec_T_94, _activated_data_e_act_q_clipped_t_rec_T_95}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_clipped_result_bits_T_7; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_result_7_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_clipped_result_bits_rawIn_exp_7 = _activated_data_e_act_q_clipped_muladder_7_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_7 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_7[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isZero_7 = _activated_data_e_act_q_clipped_result_bits_rawIn_isZero_T_7 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_clipped_result_bits_rawIn_7_isZero = activated_data_e_act_q_clipped_result_bits_rawIn_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_7 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_7[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_7 = &_activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_T_7; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_23; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_7; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_7; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_31; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_clipped_result_bits_rawIn_7_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_7_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_clipped_result_bits_rawIn_7_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_clipped_result_bits_rawIn_7_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_clipped_result_bits_rawIn_7_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_14 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_21 = activated_data_e_act_q_clipped_result_bits_rawIn_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_15 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_7 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_14; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_clipped_result_bits_rawIn_7_isNaN = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_22 = ~_activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_21; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_23 = activated_data_e_act_q_clipped_result_bits_rawIn_isSpecial_7 & _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_22; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_clipped_result_bits_rawIn_7_isInf = _activated_data_e_act_q_clipped_result_bits_rawIn_out_isInf_T_23; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_7 = _activated_data_e_act_q_clipped_muladder_7_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_clipped_result_bits_rawIn_7_sign = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sign_T_7; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_7 = {1'h0, activated_data_e_act_q_clipped_result_bits_rawIn_exp_7}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_clipped_result_bits_rawIn_7_sExp = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sExp_T_7; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_28 = ~activated_data_e_act_q_clipped_result_bits_rawIn_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_28}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_30 = _activated_data_e_act_q_clipped_muladder_7_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_31 = {_activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_29, _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_30}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_clipped_result_bits_rawIn_7_sig = _activated_data_e_act_q_clipped_result_bits_rawIn_out_sig_T_31; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_clipped_result_bits_isSubnormal_7 = $signed(activated_data_e_act_q_clipped_result_bits_rawIn_7_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_14 = activated_data_e_act_q_clipped_result_bits_rawIn_7_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_15 = 6'h1 - {1'h0, _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_14}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_clipped_result_bits_denormShiftDist_7 = _activated_data_e_act_q_clipped_result_bits_denormShiftDist_T_15[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_14 = activated_data_e_act_q_clipped_result_bits_rawIn_7_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_clipped_result_bits_denormFract_T_15 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_14 >> activated_data_e_act_q_clipped_result_bits_denormShiftDist_7; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_clipped_result_bits_denormFract_7 = _activated_data_e_act_q_clipped_result_bits_denormFract_T_15[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_42 = activated_data_e_act_q_clipped_result_bits_rawIn_7_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_43 = {1'h0, _activated_data_e_act_q_clipped_result_bits_expOut_T_42} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_44 = _activated_data_e_act_q_clipped_result_bits_expOut_T_43[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_45 = activated_data_e_act_q_clipped_result_bits_isSubnormal_7 ? 8'h0 : _activated_data_e_act_q_clipped_result_bits_expOut_T_44; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_clipped_result_bits_expOut_T_46 = activated_data_e_act_q_clipped_result_bits_rawIn_7_isNaN | activated_data_e_act_q_clipped_result_bits_rawIn_7_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_clipped_result_bits_expOut_T_47 = {8{_activated_data_e_act_q_clipped_result_bits_expOut_T_46}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_clipped_result_bits_expOut_7 = _activated_data_e_act_q_clipped_result_bits_expOut_T_45 | _activated_data_e_act_q_clipped_result_bits_expOut_T_47; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_14 = activated_data_e_act_q_clipped_result_bits_rawIn_7_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_clipped_result_bits_fractOut_T_15 = activated_data_e_act_q_clipped_result_bits_rawIn_7_isInf ? 23'h0 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_14; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_clipped_result_bits_fractOut_7 = activated_data_e_act_q_clipped_result_bits_isSubnormal_7 ? activated_data_e_act_q_clipped_result_bits_denormFract_7 : _activated_data_e_act_q_clipped_result_bits_fractOut_T_15; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_clipped_result_bits_hi_7 = {activated_data_e_act_q_clipped_result_bits_rawIn_7_sign, activated_data_e_act_q_clipped_result_bits_expOut_7}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_clipped_result_bits_T_7 = {activated_data_e_act_q_clipped_result_bits_hi_7, activated_data_e_act_q_clipped_result_bits_fractOut_7}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_clipped_result_7_bits = _activated_data_e_act_q_clipped_result_bits_T_7; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_clipped_3_bits = _activated_data_e_act_q_clipped_comparator_3_io_gt ? activated_data_e_act_q_clipped_result_7_bits : activated_data_e_act_q_abs_3_bits; // @[Arithmetic.scala:426:26, :475:32] wire activated_data_e_act_q_poly_t_rec_rawIn_6_sign = activated_data_e_act_q_poly_t_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_q_poly_t_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_264 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_265 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_266 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_267 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_268 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_269 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_270 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_271 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_272 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_273 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_274 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_275 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_276 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_277 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_278 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_279 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_280 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_281 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_282 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_283 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_284 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_285 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_286 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_287 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_288 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_289 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_290 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_291 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_292 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_293 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_294 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_295 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_296 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_297 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_298 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_299 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_300 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_301 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_302 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_303 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_304 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_305 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_306 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_307 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_t_rec_rawIn_normDist_6 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6} << activated_data_e_act_q_poly_t_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_6 = {_activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_q_poly_t_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_q_poly_t_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_6 = _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_12 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_t_rec_rawIn_isZero_6 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_t_rec_rawIn_6_isZero = activated_data_e_act_q_poly_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_6 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_6 = &_activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_t_rec_T_50 = activated_data_e_act_q_poly_t_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_t_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_t_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_t_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_6 & _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_t_rec_rawIn_6_isNaN = _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_6 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_6 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_t_rec_rawIn_6_isInf = _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_t_rec_rawIn_6_sExp = _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_26 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_6 : activated_data_e_act_q_poly_t_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_25, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_t_rec_rawIn_6_sig = _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_48 = activated_data_e_act_q_poly_t_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_49 = activated_data_e_act_q_poly_t_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_q_poly_t_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_51 = {_activated_data_e_act_q_poly_t_rec_T_49[2:1], _activated_data_e_act_q_poly_t_rec_T_49[0] | _activated_data_e_act_q_poly_t_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_t_rec_T_52 = {activated_data_e_act_q_poly_t_rec_rawIn_6_sign, _activated_data_e_act_q_poly_t_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_t_rec_T_53 = activated_data_e_act_q_poly_t_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_t_rec_T_54 = {_activated_data_e_act_q_poly_t_rec_T_52, _activated_data_e_act_q_poly_t_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_t_rec_T_55 = activated_data_e_act_q_poly_t_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_t_rec_6 = {_activated_data_e_act_q_poly_t_rec_T_54, _activated_data_e_act_q_poly_t_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_12 = activated_data_e_act_q_clipped_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_13 = activated_data_e_act_q_clipped_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_12_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_12; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_12 = activated_data_e_act_q_clipped_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_13 = activated_data_e_act_q_clipped_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12 = activated_data_e_act_q_clipped_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13 = activated_data_e_act_q_clipped_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_12 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_12 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_12 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_528 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_529 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_530 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_531 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_532 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_533 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_534 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_535 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_536 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_537 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_538 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_539 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_540 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_541 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_542 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_543 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_544 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_545 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_546 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_547 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_548 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_549 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_550 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_551 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_529 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_552 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_530 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_551; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_553 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_531 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_552; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_554 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_532 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_553; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_555 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_533 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_554; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_556 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_534 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_555; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_557 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_535 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_556; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_558 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_536 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_557; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_559 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_537 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_558; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_560 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_538 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_559; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_561 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_539 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_560; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_562 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_540 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_561; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_563 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_541 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_562; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_564 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_542 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_563; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_565 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_543 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_564; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_566 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_544 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_565; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_567 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_545 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_566; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_568 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_546 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_567; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_569 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_547 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_568; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_570 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_548 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_569; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_571 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_549 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_570; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_12 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_550 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_571; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_24 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_12; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_25 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_24[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_12 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_25, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_60 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_12}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_61 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_12 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_60 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_12}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_62 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_12 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_63 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_62}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_64 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_61} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_63}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_12 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_64[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_24 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_12; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_12 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_12 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_12_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_12 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_12[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_12 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_12; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_98 = activated_data_e_act_q_poly_self_rec_rawIn_12_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_12_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_12_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_12_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_24 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_25 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_12 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_24; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_12_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_12 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_12 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_12_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_25 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_24}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_12_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_48 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_49 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_48}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_50 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_12 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_12 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_12; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_51 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_49, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_50}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_12_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_96 = activated_data_e_act_q_poly_self_rec_rawIn_12_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_97 = activated_data_e_act_q_poly_self_rec_rawIn_12_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_96; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_99 = {_activated_data_e_act_q_poly_self_rec_T_97[2:1], _activated_data_e_act_q_poly_self_rec_T_97[0] | _activated_data_e_act_q_poly_self_rec_T_98}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_100 = {activated_data_e_act_q_poly_self_rec_rawIn_12_sign, _activated_data_e_act_q_poly_self_rec_T_99}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_101 = activated_data_e_act_q_poly_self_rec_rawIn_12_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_102 = {_activated_data_e_act_q_poly_self_rec_T_100, _activated_data_e_act_q_poly_self_rec_T_101}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_103 = activated_data_e_act_q_poly_self_rec_rawIn_12_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_12 = {_activated_data_e_act_q_poly_self_rec_T_102, _activated_data_e_act_q_poly_self_rec_T_103}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_9; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_result_6_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_9 = _activated_data_e_act_q_poly_muladder_9_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_9 = activated_data_e_act_q_poly_result_bits_rawIn_exp_9[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_9 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_9 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_9_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_9 = activated_data_e_act_q_poly_result_bits_rawIn_exp_9[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_9 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_9; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_29; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_9; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_9; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_39; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_9_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_9_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_9_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_9_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_9_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_18 = activated_data_e_act_q_poly_result_bits_rawIn_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_27 = activated_data_e_act_q_poly_result_bits_rawIn_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_19 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_9 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_18; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_9_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_28 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_27; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_29 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_9 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_28; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_9_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_29; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_9 = _activated_data_e_act_q_poly_muladder_9_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_9_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_9; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_9 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_9}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_9_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_9; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_36 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_37 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_36}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_38 = _activated_data_e_act_q_poly_muladder_9_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_39 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_37, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_38}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_9_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_39; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_9 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_9_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_18 = activated_data_e_act_q_poly_result_bits_rawIn_9_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_19 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_18}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_9 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_19[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_18 = activated_data_e_act_q_poly_result_bits_rawIn_9_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_19 = _activated_data_e_act_q_poly_result_bits_denormFract_T_18 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_9; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_9 = _activated_data_e_act_q_poly_result_bits_denormFract_T_19[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_54 = activated_data_e_act_q_poly_result_bits_rawIn_9_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_55 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_54} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_56 = _activated_data_e_act_q_poly_result_bits_expOut_T_55[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_57 = activated_data_e_act_q_poly_result_bits_isSubnormal_9 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_56; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_58 = activated_data_e_act_q_poly_result_bits_rawIn_9_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_9_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_59 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_58}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_9 = _activated_data_e_act_q_poly_result_bits_expOut_T_57 | _activated_data_e_act_q_poly_result_bits_expOut_T_59; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_18 = activated_data_e_act_q_poly_result_bits_rawIn_9_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_19 = activated_data_e_act_q_poly_result_bits_rawIn_9_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_18; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_9 = activated_data_e_act_q_poly_result_bits_isSubnormal_9 ? activated_data_e_act_q_poly_result_bits_denormFract_9 : _activated_data_e_act_q_poly_result_bits_fractOut_T_19; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_9 = {activated_data_e_act_q_poly_result_bits_rawIn_9_sign, activated_data_e_act_q_poly_result_bits_expOut_9}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_9 = {activated_data_e_act_q_poly_result_bits_hi_9, activated_data_e_act_q_poly_result_bits_fractOut_9}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_result_6_bits = _activated_data_e_act_q_poly_result_bits_T_9; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_t_rec_rawIn_7_sign = activated_data_e_act_q_poly_t_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_7 = activated_data_e_act_q_poly_t_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_7 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_308 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_309 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_310 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_311 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_312 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_313 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_314 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_315 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_316 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_317 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_318 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_319 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_320 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_321 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_322 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_323 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_324 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_325 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_326 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_327 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_328 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_329 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_330 = activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_331 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_332 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_333 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_334 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_335 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_336 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_337 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_338 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_339 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_340 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_341 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_342 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_343 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_344 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_345 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_346 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_347 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_348 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_349 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_350 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_351 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_t_rec_rawIn_normDist_7 = _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_act_q_poly_t_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7} << activated_data_e_act_q_poly_t_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_15 = _activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_7 = {_activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_act_q_poly_t_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_36 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_act_q_poly_t_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_37 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_7 = _activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_14 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_t_rec_rawIn_isZero_7 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_7 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_t_rec_rawIn_7_isZero = activated_data_e_act_q_poly_t_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_7 = activated_data_e_act_q_poly_t_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_7 = &_activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_t_rec_T_58 = activated_data_e_act_q_poly_t_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_t_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_t_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_t_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_15 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_7 & _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_t_rec_rawIn_7_isNaN = _activated_data_e_act_q_poly_t_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_7 = activated_data_e_act_q_poly_t_rec_rawIn_isSpecial_7 & activated_data_e_act_q_poly_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_t_rec_rawIn_7_isInf = _activated_data_e_act_q_poly_t_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_t_rec_rawIn_7_sExp = _activated_data_e_act_q_poly_t_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_28 = ~activated_data_e_act_q_poly_t_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_30 = activated_data_e_act_q_poly_t_rec_rawIn_isZeroExpIn_7 ? activated_data_e_act_q_poly_t_rec_rawIn_subnormFract_7 : activated_data_e_act_q_poly_t_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_31 = {_activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_29, _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_t_rec_rawIn_7_sig = _activated_data_e_act_q_poly_t_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_56 = activated_data_e_act_q_poly_t_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_57 = activated_data_e_act_q_poly_t_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_act_q_poly_t_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_t_rec_T_59 = {_activated_data_e_act_q_poly_t_rec_T_57[2:1], _activated_data_e_act_q_poly_t_rec_T_57[0] | _activated_data_e_act_q_poly_t_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_t_rec_T_60 = {activated_data_e_act_q_poly_t_rec_rawIn_7_sign, _activated_data_e_act_q_poly_t_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_t_rec_T_61 = activated_data_e_act_q_poly_t_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_t_rec_T_62 = {_activated_data_e_act_q_poly_t_rec_T_60, _activated_data_e_act_q_poly_t_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_t_rec_T_63 = activated_data_e_act_q_poly_t_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_t_rec_7 = {_activated_data_e_act_q_poly_t_rec_T_62, _activated_data_e_act_q_poly_t_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_13_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_13; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_13 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_13 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_13 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_572 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_573 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_574 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_575 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_576 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_577 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_578 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_579 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_580 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_581 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_582 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_583 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_584 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_585 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_586 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_587 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_588 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_589 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_590 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_591 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_592 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_593 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_594 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_595 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_573 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_596 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_574 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_595; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_597 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_575 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_596; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_598 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_576 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_597; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_599 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_577 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_598; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_600 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_578 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_599; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_601 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_579 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_600; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_602 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_580 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_601; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_603 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_581 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_602; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_604 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_582 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_603; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_605 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_583 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_604; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_606 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_584 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_605; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_607 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_585 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_606; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_608 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_586 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_607; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_609 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_587 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_608; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_610 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_588 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_609; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_611 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_589 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_610; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_612 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_590 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_611; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_613 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_591 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_612; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_614 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_592 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_613; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_615 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_593 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_614; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_13 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_594 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_615; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_26 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_13; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_27 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_26[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_13 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_27, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_65 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_13}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_66 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_13 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_65 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_13}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_67 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_13 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_68 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_67}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_69 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_66} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_68}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_13 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_69[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_26 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_13; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_13 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_13 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_13_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_13 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_13[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_13 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_13; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_106 = activated_data_e_act_q_poly_self_rec_rawIn_13_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_13_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_13_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_13_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_26 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_27 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_13 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_26; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_13_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_13 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_13 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_13_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_27 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_26}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_13_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_52 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_53 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_52}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_54 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_13 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_13 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_13; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_55 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_53, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_54}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_13_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_104 = activated_data_e_act_q_poly_self_rec_rawIn_13_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_105 = activated_data_e_act_q_poly_self_rec_rawIn_13_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_104; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_107 = {_activated_data_e_act_q_poly_self_rec_T_105[2:1], _activated_data_e_act_q_poly_self_rec_T_105[0] | _activated_data_e_act_q_poly_self_rec_T_106}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_108 = {activated_data_e_act_q_poly_self_rec_rawIn_13_sign, _activated_data_e_act_q_poly_self_rec_T_107}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_109 = activated_data_e_act_q_poly_self_rec_rawIn_13_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_110 = {_activated_data_e_act_q_poly_self_rec_T_108, _activated_data_e_act_q_poly_self_rec_T_109}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_111 = activated_data_e_act_q_poly_self_rec_rawIn_13_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_13 = {_activated_data_e_act_q_poly_self_rec_T_110, _activated_data_e_act_q_poly_self_rec_T_111}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_10; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_result_7_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_10 = _activated_data_e_act_q_poly_muladder_10_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_10 = activated_data_e_act_q_poly_result_bits_rawIn_exp_10[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_10 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_10 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_10_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_10 = activated_data_e_act_q_poly_result_bits_rawIn_exp_10[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_10 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_10; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_32; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_10; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_10; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_43; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_10_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_10_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_10_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_10_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_10_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_20 = activated_data_e_act_q_poly_result_bits_rawIn_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_30 = activated_data_e_act_q_poly_result_bits_rawIn_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_21 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_10 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_20; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_10_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_31 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_30; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_32 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_10 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_31; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_10_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_32; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_10 = _activated_data_e_act_q_poly_muladder_10_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_10_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_10; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_10 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_10}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_10_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_10; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_40 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_40}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_42 = _activated_data_e_act_q_poly_muladder_10_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_43 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_41, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_42}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_10_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_43; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_10 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_10_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_20 = activated_data_e_act_q_poly_result_bits_rawIn_10_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_21 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_20}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_10 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_21[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_20 = activated_data_e_act_q_poly_result_bits_rawIn_10_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_21 = _activated_data_e_act_q_poly_result_bits_denormFract_T_20 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_10; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_10 = _activated_data_e_act_q_poly_result_bits_denormFract_T_21[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_60 = activated_data_e_act_q_poly_result_bits_rawIn_10_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_61 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_60} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_62 = _activated_data_e_act_q_poly_result_bits_expOut_T_61[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_63 = activated_data_e_act_q_poly_result_bits_isSubnormal_10 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_62; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_64 = activated_data_e_act_q_poly_result_bits_rawIn_10_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_10_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_65 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_64}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_10 = _activated_data_e_act_q_poly_result_bits_expOut_T_63 | _activated_data_e_act_q_poly_result_bits_expOut_T_65; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_20 = activated_data_e_act_q_poly_result_bits_rawIn_10_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_21 = activated_data_e_act_q_poly_result_bits_rawIn_10_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_20; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_10 = activated_data_e_act_q_poly_result_bits_isSubnormal_10 ? activated_data_e_act_q_poly_result_bits_denormFract_10 : _activated_data_e_act_q_poly_result_bits_fractOut_T_21; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_10 = {activated_data_e_act_q_poly_result_bits_rawIn_10_sign, activated_data_e_act_q_poly_result_bits_expOut_10}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_10 = {activated_data_e_act_q_poly_result_bits_hi_10, activated_data_e_act_q_poly_result_bits_fractOut_10}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_result_7_bits = _activated_data_e_act_q_poly_result_bits_T_10; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_m1_rec_rawIn_sign_3 = activated_data_e_act_q_poly_result_6_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_m1_rec_rawIn_3_sign = activated_data_e_act_q_poly_m1_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_m1_rec_rawIn_expIn_3 = activated_data_e_act_q_poly_result_6_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3 = activated_data_e_act_q_poly_result_6_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_poly_m1_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_132 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_133 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_134 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_135 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_136 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_137 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_138 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_139 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_140 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_141 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_142 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_143 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_144 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_145 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_146 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_147 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_148 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_149 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_150 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_151 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_152 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_153 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_154 = activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_m1_rec_rawIn_normDist_3 = _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_poly_m1_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3} << activated_data_e_act_q_poly_m1_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_poly_m1_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_poly_m1_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_m1_rec_rawIn_isZero_3 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_m1_rec_rawIn_3_isZero = activated_data_e_act_q_poly_m1_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_m1_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_m1_rec_T_26 = activated_data_e_act_q_poly_m1_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_m1_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_m1_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_m1_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_m1_rec_rawIn_3_isNaN = _activated_data_e_act_q_poly_m1_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_m1_rec_rawIn_isSpecial_3 & activated_data_e_act_q_poly_m1_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_m1_rec_rawIn_3_isInf = _activated_data_e_act_q_poly_m1_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_m1_rec_rawIn_3_sExp = _activated_data_e_act_q_poly_m1_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_m1_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_poly_m1_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_poly_m1_rec_rawIn_subnormFract_3 : activated_data_e_act_q_poly_m1_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_m1_rec_rawIn_3_sig = _activated_data_e_act_q_poly_m1_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_24 = activated_data_e_act_q_poly_m1_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_25 = activated_data_e_act_q_poly_m1_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_poly_m1_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_m1_rec_T_27 = {_activated_data_e_act_q_poly_m1_rec_T_25[2:1], _activated_data_e_act_q_poly_m1_rec_T_25[0] | _activated_data_e_act_q_poly_m1_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_m1_rec_T_28 = {activated_data_e_act_q_poly_m1_rec_rawIn_3_sign, _activated_data_e_act_q_poly_m1_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_m1_rec_T_29 = activated_data_e_act_q_poly_m1_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_m1_rec_T_30 = {_activated_data_e_act_q_poly_m1_rec_T_28, _activated_data_e_act_q_poly_m1_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_m1_rec_T_31 = activated_data_e_act_q_poly_m1_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_m1_rec_3 = {_activated_data_e_act_q_poly_m1_rec_T_30, _activated_data_e_act_q_poly_m1_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_m2_rec_rawIn_sign_3 = activated_data_e_act_q_poly_result_7_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_m2_rec_rawIn_3_sign = activated_data_e_act_q_poly_m2_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_m2_rec_rawIn_expIn_3 = activated_data_e_act_q_poly_result_7_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3 = activated_data_e_act_q_poly_result_7_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_poly_m2_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_132 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_133 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_134 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_135 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_136 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_137 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_138 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_139 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_140 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_141 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_142 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_143 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_144 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_145 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_146 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_147 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_148 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_149 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_150 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_151 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_152 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_153 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_154 = activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_m2_rec_rawIn_normDist_3 = _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_poly_m2_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3} << activated_data_e_act_q_poly_m2_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_poly_m2_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_poly_m2_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_m2_rec_rawIn_isZero_3 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_m2_rec_rawIn_3_isZero = activated_data_e_act_q_poly_m2_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_m2_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_m2_rec_T_26 = activated_data_e_act_q_poly_m2_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_m2_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_m2_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_m2_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_m2_rec_rawIn_3_isNaN = _activated_data_e_act_q_poly_m2_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_m2_rec_rawIn_isSpecial_3 & activated_data_e_act_q_poly_m2_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_m2_rec_rawIn_3_isInf = _activated_data_e_act_q_poly_m2_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_m2_rec_rawIn_3_sExp = _activated_data_e_act_q_poly_m2_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_m2_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_poly_m2_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_poly_m2_rec_rawIn_subnormFract_3 : activated_data_e_act_q_poly_m2_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_m2_rec_rawIn_3_sig = _activated_data_e_act_q_poly_m2_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_24 = activated_data_e_act_q_poly_m2_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_25 = activated_data_e_act_q_poly_m2_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_poly_m2_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_m2_rec_T_27 = {_activated_data_e_act_q_poly_m2_rec_T_25[2:1], _activated_data_e_act_q_poly_m2_rec_T_25[0] | _activated_data_e_act_q_poly_m2_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_m2_rec_T_28 = {activated_data_e_act_q_poly_m2_rec_rawIn_3_sign, _activated_data_e_act_q_poly_m2_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_m2_rec_T_29 = activated_data_e_act_q_poly_m2_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_m2_rec_T_30 = {_activated_data_e_act_q_poly_m2_rec_T_28, _activated_data_e_act_q_poly_m2_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_m2_rec_T_31 = activated_data_e_act_q_poly_m2_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_m2_rec_3 = {_activated_data_e_act_q_poly_m2_rec_T_30, _activated_data_e_act_q_poly_m2_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_self_rec_rawIn_14_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_14; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_14 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_14 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_14 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_616 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_617 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_618 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_619 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_620 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_621 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_622 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_623 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_624 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_625 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_626 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_627 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_628 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_629 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_630 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_631 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_632 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_633 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_634 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_635 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_636 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_637 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_638 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_639 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_617 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_640 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_618 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_639; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_641 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_619 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_640; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_642 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_620 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_641; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_643 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_621 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_642; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_644 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_622 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_643; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_645 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_623 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_644; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_646 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_624 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_645; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_647 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_625 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_646; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_648 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_626 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_647; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_649 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_627 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_648; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_650 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_628 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_649; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_651 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_629 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_650; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_652 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_630 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_651; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_653 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_631 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_652; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_654 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_632 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_653; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_655 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_633 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_654; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_656 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_634 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_655; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_657 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_635 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_656; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_658 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_636 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_657; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_659 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_637 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_658; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_14 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_638 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_659; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_28 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_14; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_29 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_28[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_14 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_29, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_70 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_14}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_71 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_14 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_70 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_14}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_72 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_14 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_73 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_72}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_74 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_71} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_73}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_14 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_74[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_28 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_14; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_14 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_14 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_14_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_14 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_14[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_14 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_14; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_114 = activated_data_e_act_q_poly_self_rec_rawIn_14_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_14_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_14_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_14_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_28 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_29 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_14 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_28; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_14_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_14 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_14 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_14_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_29 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_28}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_14_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_56 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_57 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_56}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_58 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_14 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_14 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_14; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_59 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_57, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_58}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_14_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_112 = activated_data_e_act_q_poly_self_rec_rawIn_14_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_113 = activated_data_e_act_q_poly_self_rec_rawIn_14_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_112; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_115 = {_activated_data_e_act_q_poly_self_rec_T_113[2:1], _activated_data_e_act_q_poly_self_rec_T_113[0] | _activated_data_e_act_q_poly_self_rec_T_114}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_116 = {activated_data_e_act_q_poly_self_rec_rawIn_14_sign, _activated_data_e_act_q_poly_self_rec_T_115}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_117 = activated_data_e_act_q_poly_self_rec_rawIn_14_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_118 = {_activated_data_e_act_q_poly_self_rec_T_116, _activated_data_e_act_q_poly_self_rec_T_117}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_119 = activated_data_e_act_q_poly_self_rec_rawIn_14_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_14 = {_activated_data_e_act_q_poly_self_rec_T_118, _activated_data_e_act_q_poly_self_rec_T_119}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_out_3_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_q_poly_out_bits_rawIn_exp_3 = _activated_data_e_act_q_poly_muladder_11_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_out_bits_rawIn_isZero_T_3 = activated_data_e_act_q_poly_out_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_out_bits_rawIn_isZero_3 = _activated_data_e_act_q_poly_out_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_out_bits_rawIn_3_isZero = activated_data_e_act_q_poly_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_out_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_out_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_out_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_out_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_out_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_q_poly_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_9 = activated_data_e_act_q_poly_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_out_bits_rawIn_3_isNaN = _activated_data_e_act_q_poly_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_11 = activated_data_e_act_q_poly_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_out_bits_rawIn_3_isInf = _activated_data_e_act_q_poly_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T_3 = _activated_data_e_act_q_poly_muladder_11_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_out_bits_rawIn_3_sign = _activated_data_e_act_q_poly_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_q_poly_out_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_out_bits_rawIn_3_sExp = _activated_data_e_act_q_poly_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_14 = _activated_data_e_act_q_poly_muladder_11_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_out_bits_rawIn_3_sig = _activated_data_e_act_q_poly_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_out_bits_isSubnormal_3 = $signed(activated_data_e_act_q_poly_out_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_6 = activated_data_e_act_q_poly_out_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_out_bits_denormShiftDist_3 = _activated_data_e_act_q_poly_out_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_out_bits_denormFract_T_6 = activated_data_e_act_q_poly_out_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_out_bits_denormFract_T_7 = _activated_data_e_act_q_poly_out_bits_denormFract_T_6 >> activated_data_e_act_q_poly_out_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_out_bits_denormFract_3 = _activated_data_e_act_q_poly_out_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_18 = activated_data_e_act_q_poly_out_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_out_bits_expOut_T_19 = {1'h0, _activated_data_e_act_q_poly_out_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_20 = _activated_data_e_act_q_poly_out_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_21 = activated_data_e_act_q_poly_out_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_q_poly_out_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_out_bits_expOut_T_22 = activated_data_e_act_q_poly_out_bits_rawIn_3_isNaN | activated_data_e_act_q_poly_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_out_bits_expOut_T_23 = {8{_activated_data_e_act_q_poly_out_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_out_bits_expOut_3 = _activated_data_e_act_q_poly_out_bits_expOut_T_21 | _activated_data_e_act_q_poly_out_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_out_bits_fractOut_T_6 = activated_data_e_act_q_poly_out_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_out_bits_fractOut_T_7 = activated_data_e_act_q_poly_out_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_q_poly_out_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_out_bits_fractOut_3 = activated_data_e_act_q_poly_out_bits_isSubnormal_3 ? activated_data_e_act_q_poly_out_bits_denormFract_3 : _activated_data_e_act_q_poly_out_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_out_bits_hi_3 = {activated_data_e_act_q_poly_out_bits_rawIn_3_sign, activated_data_e_act_q_poly_out_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_out_bits_T_3 = {activated_data_e_act_q_poly_out_bits_hi_3, activated_data_e_act_q_poly_out_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_out_3_bits = _activated_data_e_act_q_poly_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_self_rec_rawIn_sign_15 = activated_data_e_act_q_poly_out_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_self_rec_rawIn_15_sign = activated_data_e_act_q_poly_self_rec_rawIn_sign_15; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_self_rec_rawIn_expIn_15 = activated_data_e_act_q_poly_out_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15 = activated_data_e_act_q_poly_out_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_15 = activated_data_e_act_q_poly_self_rec_rawIn_expIn_15 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_15 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_660 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_661 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_662 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_663 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_664 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_665 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_666 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_667 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_668 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_669 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_670 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_671 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_672 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_673 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_674 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_675 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_676 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_677 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_678 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_679 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_680 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_681 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_682 = activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_683 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_661 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_684 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_662 ? 5'h14 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_683; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_685 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_663 ? 5'h13 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_684; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_686 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_664 ? 5'h12 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_685; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_687 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_665 ? 5'h11 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_686; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_688 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_666 ? 5'h10 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_687; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_689 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_667 ? 5'hF : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_688; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_690 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_668 ? 5'hE : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_689; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_691 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_669 ? 5'hD : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_690; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_692 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_670 ? 5'hC : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_691; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_693 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_671 ? 5'hB : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_692; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_694 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_672 ? 5'hA : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_693; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_695 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_673 ? 5'h9 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_694; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_696 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_674 ? 5'h8 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_695; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_697 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_675 ? 5'h7 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_696; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_698 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_676 ? 5'h6 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_697; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_699 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_677 ? 5'h5 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_698; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_700 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_678 ? 5'h4 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_699; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_701 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_679 ? 5'h3 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_700; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_702 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_680 ? 5'h2 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_701; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_703 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_681 ? 5'h1 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_702; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_self_rec_rawIn_normDist_15 = _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_682 ? 5'h0 : _activated_data_e_act_q_poly_self_rec_rawIn_normDist_T_703; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_30 = {31'h0, activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15} << activated_data_e_act_q_poly_self_rec_rawIn_normDist_15; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_31 = _activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_30[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_15 = {_activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_T_31, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_75 = {4'hF, ~activated_data_e_act_q_poly_self_rec_rawIn_normDist_15}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_76 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_15 ? _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_75 : {1'h0, activated_data_e_act_q_poly_self_rec_rawIn_expIn_15}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_77 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_15 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_78 = {6'h20, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_77}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_79 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_76} + {2'h0, _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_78}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_15 = _activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_T_79[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_30 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_15; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_self_rec_rawIn_isZero_15 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_15 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_self_rec_rawIn_15_isZero = activated_data_e_act_q_poly_self_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_15 = activated_data_e_act_q_poly_self_rec_rawIn_adjustedExp_15[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_15 = &_activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_T_15; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_self_rec_T_122 = activated_data_e_act_q_poly_self_rec_rawIn_15_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_self_rec_rawIn_15_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_self_rec_rawIn_15_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_self_rec_rawIn_15_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_30 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_31 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_15 & _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_30; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_self_rec_rawIn_15_isNaN = _activated_data_e_act_q_poly_self_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_15 = activated_data_e_act_q_poly_self_rec_rawIn_isSpecial_15 & activated_data_e_act_q_poly_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_self_rec_rawIn_15_isInf = _activated_data_e_act_q_poly_self_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_31 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_30}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_self_rec_rawIn_15_sExp = _activated_data_e_act_q_poly_self_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_60 = ~activated_data_e_act_q_poly_self_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_61 = {1'h0, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_60}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_62 = activated_data_e_act_q_poly_self_rec_rawIn_isZeroExpIn_15 ? activated_data_e_act_q_poly_self_rec_rawIn_subnormFract_15 : activated_data_e_act_q_poly_self_rec_rawIn_fractIn_15; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_63 = {_activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_61, _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_62}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_self_rec_rawIn_15_sig = _activated_data_e_act_q_poly_self_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_120 = activated_data_e_act_q_poly_self_rec_rawIn_15_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_121 = activated_data_e_act_q_poly_self_rec_rawIn_15_isZero ? 3'h0 : _activated_data_e_act_q_poly_self_rec_T_120; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_self_rec_T_123 = {_activated_data_e_act_q_poly_self_rec_T_121[2:1], _activated_data_e_act_q_poly_self_rec_T_121[0] | _activated_data_e_act_q_poly_self_rec_T_122}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_self_rec_T_124 = {activated_data_e_act_q_poly_self_rec_rawIn_15_sign, _activated_data_e_act_q_poly_self_rec_T_123}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_self_rec_T_125 = activated_data_e_act_q_poly_self_rec_rawIn_15_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_self_rec_T_126 = {_activated_data_e_act_q_poly_self_rec_T_124, _activated_data_e_act_q_poly_self_rec_T_125}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_self_rec_T_127 = activated_data_e_act_q_poly_self_rec_rawIn_15_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_self_rec_15 = {_activated_data_e_act_q_poly_self_rec_T_126, _activated_data_e_act_q_poly_self_rec_T_127}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_result_bits_T_11; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_3_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_poly_result_bits_rawIn_exp_11 = _activated_data_e_act_q_poly_resizer_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_11 = activated_data_e_act_q_poly_result_bits_rawIn_exp_11[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isZero_11 = _activated_data_e_act_q_poly_result_bits_rawIn_isZero_T_11 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_result_bits_rawIn_11_isZero = activated_data_e_act_q_poly_result_bits_rawIn_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_11 = activated_data_e_act_q_poly_result_bits_rawIn_exp_11[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_11 = &_activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_T_11; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_35; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_11; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_11; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_47; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_result_bits_rawIn_11_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_11_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_result_bits_rawIn_11_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_result_bits_rawIn_11_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_result_bits_rawIn_11_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_22 = activated_data_e_act_q_poly_result_bits_rawIn_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_33 = activated_data_e_act_q_poly_result_bits_rawIn_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_23 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_11 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_22; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_result_bits_rawIn_11_isNaN = _activated_data_e_act_q_poly_result_bits_rawIn_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_34 = ~_activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_33; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_35 = activated_data_e_act_q_poly_result_bits_rawIn_isSpecial_11 & _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_34; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_result_bits_rawIn_11_isInf = _activated_data_e_act_q_poly_result_bits_rawIn_out_isInf_T_35; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_11 = _activated_data_e_act_q_poly_resizer_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_result_bits_rawIn_11_sign = _activated_data_e_act_q_poly_result_bits_rawIn_out_sign_T_11; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_11 = {1'h0, activated_data_e_act_q_poly_result_bits_rawIn_exp_11}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_result_bits_rawIn_11_sExp = _activated_data_e_act_q_poly_result_bits_rawIn_out_sExp_T_11; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_44 = ~activated_data_e_act_q_poly_result_bits_rawIn_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_45 = {1'h0, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_44}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_46 = _activated_data_e_act_q_poly_resizer_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_47 = {_activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_45, _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_46}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_result_bits_rawIn_11_sig = _activated_data_e_act_q_poly_result_bits_rawIn_out_sig_T_47; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_result_bits_isSubnormal_11 = $signed(activated_data_e_act_q_poly_result_bits_rawIn_11_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_22 = activated_data_e_act_q_poly_result_bits_rawIn_11_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_23 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_22}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_result_bits_denormShiftDist_11 = _activated_data_e_act_q_poly_result_bits_denormShiftDist_T_23[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_22 = activated_data_e_act_q_poly_result_bits_rawIn_11_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_result_bits_denormFract_T_23 = _activated_data_e_act_q_poly_result_bits_denormFract_T_22 >> activated_data_e_act_q_poly_result_bits_denormShiftDist_11; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_result_bits_denormFract_11 = _activated_data_e_act_q_poly_result_bits_denormFract_T_23[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_66 = activated_data_e_act_q_poly_result_bits_rawIn_11_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_result_bits_expOut_T_67 = {1'h0, _activated_data_e_act_q_poly_result_bits_expOut_T_66} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_68 = _activated_data_e_act_q_poly_result_bits_expOut_T_67[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_69 = activated_data_e_act_q_poly_result_bits_isSubnormal_11 ? 8'h0 : _activated_data_e_act_q_poly_result_bits_expOut_T_68; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_result_bits_expOut_T_70 = activated_data_e_act_q_poly_result_bits_rawIn_11_isNaN | activated_data_e_act_q_poly_result_bits_rawIn_11_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_result_bits_expOut_T_71 = {8{_activated_data_e_act_q_poly_result_bits_expOut_T_70}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_result_bits_expOut_11 = _activated_data_e_act_q_poly_result_bits_expOut_T_69 | _activated_data_e_act_q_poly_result_bits_expOut_T_71; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_22 = activated_data_e_act_q_poly_result_bits_rawIn_11_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_result_bits_fractOut_T_23 = activated_data_e_act_q_poly_result_bits_rawIn_11_isInf ? 23'h0 : _activated_data_e_act_q_poly_result_bits_fractOut_T_22; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_result_bits_fractOut_11 = activated_data_e_act_q_poly_result_bits_isSubnormal_11 ? activated_data_e_act_q_poly_result_bits_denormFract_11 : _activated_data_e_act_q_poly_result_bits_fractOut_T_23; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_result_bits_hi_11 = {activated_data_e_act_q_poly_result_bits_rawIn_11_sign, activated_data_e_act_q_poly_result_bits_expOut_11}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_result_bits_T_11 = {activated_data_e_act_q_poly_result_bits_hi_11, activated_data_e_act_q_poly_result_bits_fractOut_11}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_3_bits = _activated_data_e_act_q_poly_result_bits_T_11; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_erf_t_rec_rawIn_sign_3 = activated_data_e_act_q_poly_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_t_rec_rawIn_3_sign = activated_data_e_act_q_erf_t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_t_rec_rawIn_expIn_3 = activated_data_e_act_q_poly_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3 = activated_data_e_act_q_poly_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_erf_t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_132 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_133 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_134 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_135 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_136 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_137 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_138 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_139 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_140 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_141 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_142 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_143 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_144 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_145 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_146 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_147 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_148 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_149 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_150 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_151 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_152 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_153 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_154 = activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_t_rec_rawIn_normDist_3 = _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_erf_t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3} << activated_data_e_act_q_erf_t_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_erf_t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_erf_t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_t_rec_rawIn_isZero_3 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_t_rec_rawIn_3_isZero = activated_data_e_act_q_erf_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_erf_t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_t_rec_T_26 = activated_data_e_act_q_erf_t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_t_rec_rawIn_3_isNaN = _activated_data_e_act_q_erf_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_erf_t_rec_rawIn_isSpecial_3 & activated_data_e_act_q_erf_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_t_rec_rawIn_3_isInf = _activated_data_e_act_q_erf_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_t_rec_rawIn_3_sExp = _activated_data_e_act_q_erf_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_erf_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_erf_t_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_erf_t_rec_rawIn_subnormFract_3 : activated_data_e_act_q_erf_t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_t_rec_rawIn_3_sig = _activated_data_e_act_q_erf_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_24 = activated_data_e_act_q_erf_t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_25 = activated_data_e_act_q_erf_t_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_erf_t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_t_rec_T_27 = {_activated_data_e_act_q_erf_t_rec_T_25[2:1], _activated_data_e_act_q_erf_t_rec_T_25[0] | _activated_data_e_act_q_erf_t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_t_rec_T_28 = {activated_data_e_act_q_erf_t_rec_rawIn_3_sign, _activated_data_e_act_q_erf_t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_t_rec_T_29 = activated_data_e_act_q_erf_t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_t_rec_T_30 = {_activated_data_e_act_q_erf_t_rec_T_28, _activated_data_e_act_q_erf_t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_t_rec_T_31 = activated_data_e_act_q_erf_t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_t_rec_3 = {_activated_data_e_act_q_erf_t_rec_T_30, _activated_data_e_act_q_erf_t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_erf_self_rec_rawIn_sign_6 = activated_data_e_act_q_sign_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_self_rec_rawIn_6_sign = activated_data_e_act_q_erf_self_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_self_rec_rawIn_expIn_6 = activated_data_e_act_q_sign_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6 = activated_data_e_act_q_sign_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_q_erf_self_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_264 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_265 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_266 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_267 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_268 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_269 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_270 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_271 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_272 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_273 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_274 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_275 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_276 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_277 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_278 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_279 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_280 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_281 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_282 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_283 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_284 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_285 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_286 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_287 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_288 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_289 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_290 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_291 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_292 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_293 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_294 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_295 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_296 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_297 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_298 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_299 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_300 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_301 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_302 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_303 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_304 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_305 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_306 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_307 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_self_rec_rawIn_normDist_6 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6} << activated_data_e_act_q_erf_self_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_6 = {_activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_q_erf_self_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_q_erf_self_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_6 = _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_12 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_self_rec_rawIn_isZero_6 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_self_rec_rawIn_6_isZero = activated_data_e_act_q_erf_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_6 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_6 = &_activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_self_rec_T_50 = activated_data_e_act_q_erf_self_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_self_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_self_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_self_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_6 & _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_self_rec_rawIn_6_isNaN = _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_6 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_6 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_self_rec_rawIn_6_isInf = _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_self_rec_rawIn_6_sExp = _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_26 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_6 : activated_data_e_act_q_erf_self_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_25, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_self_rec_rawIn_6_sig = _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_48 = activated_data_e_act_q_erf_self_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_49 = activated_data_e_act_q_erf_self_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_q_erf_self_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_51 = {_activated_data_e_act_q_erf_self_rec_T_49[2:1], _activated_data_e_act_q_erf_self_rec_T_49[0] | _activated_data_e_act_q_erf_self_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_self_rec_T_52 = {activated_data_e_act_q_erf_self_rec_rawIn_6_sign, _activated_data_e_act_q_erf_self_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_self_rec_T_53 = activated_data_e_act_q_erf_self_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_self_rec_T_54 = {_activated_data_e_act_q_erf_self_rec_T_52, _activated_data_e_act_q_erf_self_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_self_rec_T_55 = activated_data_e_act_q_erf_self_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_self_rec_6 = {_activated_data_e_act_q_erf_self_rec_T_54, _activated_data_e_act_q_erf_self_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_erf_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_erf_out_3_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_q_erf_out_bits_rawIn_exp_3 = _activated_data_e_act_q_erf_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_erf_out_bits_rawIn_isZero_T_3 = activated_data_e_act_q_erf_out_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_erf_out_bits_rawIn_isZero_3 = _activated_data_e_act_q_erf_out_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_erf_out_bits_rawIn_3_isZero = activated_data_e_act_q_erf_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_T_3 = activated_data_e_act_q_erf_out_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_3 = &_activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_erf_out_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_out_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_erf_out_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_erf_out_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_q_erf_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_9 = activated_data_e_act_q_erf_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_erf_out_bits_rawIn_3_isNaN = _activated_data_e_act_q_erf_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_11 = activated_data_e_act_q_erf_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_erf_out_bits_rawIn_3_isInf = _activated_data_e_act_q_erf_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T_3 = _activated_data_e_act_q_erf_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_erf_out_bits_rawIn_3_sign = _activated_data_e_act_q_erf_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_q_erf_out_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_erf_out_bits_rawIn_3_sExp = _activated_data_e_act_q_erf_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_q_erf_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_14 = _activated_data_e_act_q_erf_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_13, _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_erf_out_bits_rawIn_3_sig = _activated_data_e_act_q_erf_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_erf_out_bits_isSubnormal_3 = $signed(activated_data_e_act_q_erf_out_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_6 = activated_data_e_act_q_erf_out_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_erf_out_bits_denormShiftDist_3 = _activated_data_e_act_q_erf_out_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_erf_out_bits_denormFract_T_6 = activated_data_e_act_q_erf_out_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_erf_out_bits_denormFract_T_7 = _activated_data_e_act_q_erf_out_bits_denormFract_T_6 >> activated_data_e_act_q_erf_out_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_erf_out_bits_denormFract_3 = _activated_data_e_act_q_erf_out_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_18 = activated_data_e_act_q_erf_out_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_erf_out_bits_expOut_T_19 = {1'h0, _activated_data_e_act_q_erf_out_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_20 = _activated_data_e_act_q_erf_out_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_21 = activated_data_e_act_q_erf_out_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_q_erf_out_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_erf_out_bits_expOut_T_22 = activated_data_e_act_q_erf_out_bits_rawIn_3_isNaN | activated_data_e_act_q_erf_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_erf_out_bits_expOut_T_23 = {8{_activated_data_e_act_q_erf_out_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_erf_out_bits_expOut_3 = _activated_data_e_act_q_erf_out_bits_expOut_T_21 | _activated_data_e_act_q_erf_out_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_erf_out_bits_fractOut_T_6 = activated_data_e_act_q_erf_out_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_erf_out_bits_fractOut_T_7 = activated_data_e_act_q_erf_out_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_q_erf_out_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_erf_out_bits_fractOut_3 = activated_data_e_act_q_erf_out_bits_isSubnormal_3 ? activated_data_e_act_q_erf_out_bits_denormFract_3 : _activated_data_e_act_q_erf_out_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_erf_out_bits_hi_3 = {activated_data_e_act_q_erf_out_bits_rawIn_3_sign, activated_data_e_act_q_erf_out_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_erf_out_bits_T_3 = {activated_data_e_act_q_erf_out_bits_hi_3, activated_data_e_act_q_erf_out_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_erf_out_3_bits = _activated_data_e_act_q_erf_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_erf_self_rec_rawIn_sign_7 = activated_data_e_act_q_erf_out_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_erf_self_rec_rawIn_7_sign = activated_data_e_act_q_erf_self_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_erf_self_rec_rawIn_expIn_7 = activated_data_e_act_q_erf_out_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7 = activated_data_e_act_q_erf_out_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_7 = activated_data_e_act_q_erf_self_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_7 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_308 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_309 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_310 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_311 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_312 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_313 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_314 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_315 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_316 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_317 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_318 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_319 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_320 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_321 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_322 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_323 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_324 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_325 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_326 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_327 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_328 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_329 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_330 = activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_331 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_332 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_333 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_334 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_335 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_336 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_337 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_338 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_339 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_340 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_341 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_342 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_343 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_344 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_345 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_346 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_347 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_348 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_349 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_350 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_351 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_erf_self_rec_rawIn_normDist_7 = _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_act_q_erf_self_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7} << activated_data_e_act_q_erf_self_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_15 = _activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_7 = {_activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_act_q_erf_self_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_36 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_act_q_erf_self_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_37 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_7 = _activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_14 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_erf_self_rec_rawIn_isZero_7 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_7 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_erf_self_rec_rawIn_7_isZero = activated_data_e_act_q_erf_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_7 = activated_data_e_act_q_erf_self_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_7 = &_activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_erf_self_rec_T_58 = activated_data_e_act_q_erf_self_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_erf_self_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_erf_self_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_erf_self_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_15 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_7 & _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_erf_self_rec_rawIn_7_isNaN = _activated_data_e_act_q_erf_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_7 = activated_data_e_act_q_erf_self_rec_rawIn_isSpecial_7 & activated_data_e_act_q_erf_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_erf_self_rec_rawIn_7_isInf = _activated_data_e_act_q_erf_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_erf_self_rec_rawIn_7_sExp = _activated_data_e_act_q_erf_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_28 = ~activated_data_e_act_q_erf_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_30 = activated_data_e_act_q_erf_self_rec_rawIn_isZeroExpIn_7 ? activated_data_e_act_q_erf_self_rec_rawIn_subnormFract_7 : activated_data_e_act_q_erf_self_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_31 = {_activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_29, _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_erf_self_rec_rawIn_7_sig = _activated_data_e_act_q_erf_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_56 = activated_data_e_act_q_erf_self_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_57 = activated_data_e_act_q_erf_self_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_act_q_erf_self_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_erf_self_rec_T_59 = {_activated_data_e_act_q_erf_self_rec_T_57[2:1], _activated_data_e_act_q_erf_self_rec_T_57[0] | _activated_data_e_act_q_erf_self_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_erf_self_rec_T_60 = {activated_data_e_act_q_erf_self_rec_rawIn_7_sign, _activated_data_e_act_q_erf_self_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_erf_self_rec_T_61 = activated_data_e_act_q_erf_self_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_erf_self_rec_T_62 = {_activated_data_e_act_q_erf_self_rec_T_60, _activated_data_e_act_q_erf_self_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_erf_self_rec_T_63 = activated_data_e_act_q_erf_self_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_erf_self_rec_7 = {_activated_data_e_act_q_erf_self_rec_T_62, _activated_data_e_act_q_erf_self_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_erf_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_erf_3_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_erf_result_bits_rawIn_exp_3 = _activated_data_e_act_q_erf_resizer_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_erf_result_bits_rawIn_isZero_T_3 = activated_data_e_act_q_erf_result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_erf_result_bits_rawIn_isZero_3 = _activated_data_e_act_q_erf_result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_erf_result_bits_rawIn_3_isZero = activated_data_e_act_q_erf_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_T_3 = activated_data_e_act_q_erf_result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_3 = &_activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_erf_result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_erf_result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_erf_result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_erf_result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_q_erf_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_9 = activated_data_e_act_q_erf_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_erf_result_bits_rawIn_3_isNaN = _activated_data_e_act_q_erf_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_11 = activated_data_e_act_q_erf_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_erf_result_bits_rawIn_3_isInf = _activated_data_e_act_q_erf_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T_3 = _activated_data_e_act_q_erf_resizer_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_erf_result_bits_rawIn_3_sign = _activated_data_e_act_q_erf_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_q_erf_result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_erf_result_bits_rawIn_3_sExp = _activated_data_e_act_q_erf_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_q_erf_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_14 = _activated_data_e_act_q_erf_resizer_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_13, _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_erf_result_bits_rawIn_3_sig = _activated_data_e_act_q_erf_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_erf_result_bits_isSubnormal_3 = $signed(activated_data_e_act_q_erf_result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_6 = activated_data_e_act_q_erf_result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_erf_result_bits_denormShiftDist_3 = _activated_data_e_act_q_erf_result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_erf_result_bits_denormFract_T_6 = activated_data_e_act_q_erf_result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_erf_result_bits_denormFract_T_7 = _activated_data_e_act_q_erf_result_bits_denormFract_T_6 >> activated_data_e_act_q_erf_result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_erf_result_bits_denormFract_3 = _activated_data_e_act_q_erf_result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_18 = activated_data_e_act_q_erf_result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_erf_result_bits_expOut_T_19 = {1'h0, _activated_data_e_act_q_erf_result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_20 = _activated_data_e_act_q_erf_result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_21 = activated_data_e_act_q_erf_result_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_q_erf_result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_erf_result_bits_expOut_T_22 = activated_data_e_act_q_erf_result_bits_rawIn_3_isNaN | activated_data_e_act_q_erf_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_erf_result_bits_expOut_T_23 = {8{_activated_data_e_act_q_erf_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_erf_result_bits_expOut_3 = _activated_data_e_act_q_erf_result_bits_expOut_T_21 | _activated_data_e_act_q_erf_result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_erf_result_bits_fractOut_T_6 = activated_data_e_act_q_erf_result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_erf_result_bits_fractOut_T_7 = activated_data_e_act_q_erf_result_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_q_erf_result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_erf_result_bits_fractOut_3 = activated_data_e_act_q_erf_result_bits_isSubnormal_3 ? activated_data_e_act_q_erf_result_bits_denormFract_3 : _activated_data_e_act_q_erf_result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_erf_result_bits_hi_3 = {activated_data_e_act_q_erf_result_bits_rawIn_3_sign, activated_data_e_act_q_erf_result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_erf_result_bits_T_3 = {activated_data_e_act_q_erf_result_bits_hi_3, activated_data_e_act_q_erf_result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_erf_3_bits = _activated_data_e_act_q_erf_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_t_rec_rawIn_13_sign = activated_data_e_act_t_rec_rawIn_sign_13; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_13 = activated_data_e_act_t_rec_rawIn_expIn_13 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_13 = activated_data_e_act_t_rec_rawIn_fractIn_13 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_t_rec_rawIn_normDist_T_572 = activated_data_e_act_t_rec_rawIn_fractIn_13[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_573 = activated_data_e_act_t_rec_rawIn_fractIn_13[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_574 = activated_data_e_act_t_rec_rawIn_fractIn_13[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_575 = activated_data_e_act_t_rec_rawIn_fractIn_13[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_576 = activated_data_e_act_t_rec_rawIn_fractIn_13[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_577 = activated_data_e_act_t_rec_rawIn_fractIn_13[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_578 = activated_data_e_act_t_rec_rawIn_fractIn_13[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_579 = activated_data_e_act_t_rec_rawIn_fractIn_13[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_580 = activated_data_e_act_t_rec_rawIn_fractIn_13[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_581 = activated_data_e_act_t_rec_rawIn_fractIn_13[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_582 = activated_data_e_act_t_rec_rawIn_fractIn_13[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_583 = activated_data_e_act_t_rec_rawIn_fractIn_13[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_584 = activated_data_e_act_t_rec_rawIn_fractIn_13[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_585 = activated_data_e_act_t_rec_rawIn_fractIn_13[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_586 = activated_data_e_act_t_rec_rawIn_fractIn_13[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_587 = activated_data_e_act_t_rec_rawIn_fractIn_13[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_588 = activated_data_e_act_t_rec_rawIn_fractIn_13[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_589 = activated_data_e_act_t_rec_rawIn_fractIn_13[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_590 = activated_data_e_act_t_rec_rawIn_fractIn_13[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_591 = activated_data_e_act_t_rec_rawIn_fractIn_13[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_592 = activated_data_e_act_t_rec_rawIn_fractIn_13[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_593 = activated_data_e_act_t_rec_rawIn_fractIn_13[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_594 = activated_data_e_act_t_rec_rawIn_fractIn_13[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_595 = _activated_data_e_act_t_rec_rawIn_normDist_T_573 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_596 = _activated_data_e_act_t_rec_rawIn_normDist_T_574 ? 5'h14 : _activated_data_e_act_t_rec_rawIn_normDist_T_595; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_597 = _activated_data_e_act_t_rec_rawIn_normDist_T_575 ? 5'h13 : _activated_data_e_act_t_rec_rawIn_normDist_T_596; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_598 = _activated_data_e_act_t_rec_rawIn_normDist_T_576 ? 5'h12 : _activated_data_e_act_t_rec_rawIn_normDist_T_597; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_599 = _activated_data_e_act_t_rec_rawIn_normDist_T_577 ? 5'h11 : _activated_data_e_act_t_rec_rawIn_normDist_T_598; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_600 = _activated_data_e_act_t_rec_rawIn_normDist_T_578 ? 5'h10 : _activated_data_e_act_t_rec_rawIn_normDist_T_599; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_601 = _activated_data_e_act_t_rec_rawIn_normDist_T_579 ? 5'hF : _activated_data_e_act_t_rec_rawIn_normDist_T_600; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_602 = _activated_data_e_act_t_rec_rawIn_normDist_T_580 ? 5'hE : _activated_data_e_act_t_rec_rawIn_normDist_T_601; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_603 = _activated_data_e_act_t_rec_rawIn_normDist_T_581 ? 5'hD : _activated_data_e_act_t_rec_rawIn_normDist_T_602; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_604 = _activated_data_e_act_t_rec_rawIn_normDist_T_582 ? 5'hC : _activated_data_e_act_t_rec_rawIn_normDist_T_603; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_605 = _activated_data_e_act_t_rec_rawIn_normDist_T_583 ? 5'hB : _activated_data_e_act_t_rec_rawIn_normDist_T_604; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_606 = _activated_data_e_act_t_rec_rawIn_normDist_T_584 ? 5'hA : _activated_data_e_act_t_rec_rawIn_normDist_T_605; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_607 = _activated_data_e_act_t_rec_rawIn_normDist_T_585 ? 5'h9 : _activated_data_e_act_t_rec_rawIn_normDist_T_606; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_608 = _activated_data_e_act_t_rec_rawIn_normDist_T_586 ? 5'h8 : _activated_data_e_act_t_rec_rawIn_normDist_T_607; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_609 = _activated_data_e_act_t_rec_rawIn_normDist_T_587 ? 5'h7 : _activated_data_e_act_t_rec_rawIn_normDist_T_608; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_610 = _activated_data_e_act_t_rec_rawIn_normDist_T_588 ? 5'h6 : _activated_data_e_act_t_rec_rawIn_normDist_T_609; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_611 = _activated_data_e_act_t_rec_rawIn_normDist_T_589 ? 5'h5 : _activated_data_e_act_t_rec_rawIn_normDist_T_610; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_612 = _activated_data_e_act_t_rec_rawIn_normDist_T_590 ? 5'h4 : _activated_data_e_act_t_rec_rawIn_normDist_T_611; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_613 = _activated_data_e_act_t_rec_rawIn_normDist_T_591 ? 5'h3 : _activated_data_e_act_t_rec_rawIn_normDist_T_612; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_614 = _activated_data_e_act_t_rec_rawIn_normDist_T_592 ? 5'h2 : _activated_data_e_act_t_rec_rawIn_normDist_T_613; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_615 = _activated_data_e_act_t_rec_rawIn_normDist_T_593 ? 5'h1 : _activated_data_e_act_t_rec_rawIn_normDist_T_614; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_13 = _activated_data_e_act_t_rec_rawIn_normDist_T_594 ? 5'h0 : _activated_data_e_act_t_rec_rawIn_normDist_T_615; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_26 = {31'h0, activated_data_e_act_t_rec_rawIn_fractIn_13} << activated_data_e_act_t_rec_rawIn_normDist_13; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_27 = _activated_data_e_act_t_rec_rawIn_subnormFract_T_26[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_13 = {_activated_data_e_act_t_rec_rawIn_subnormFract_T_27, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_65 = {4'hF, ~activated_data_e_act_t_rec_rawIn_normDist_13}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_66 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_13 ? _activated_data_e_act_t_rec_rawIn_adjustedExp_T_65 : {1'h0, activated_data_e_act_t_rec_rawIn_expIn_13}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_67 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_13 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_68 = {6'h20, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_67}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_69 = {1'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_66} + {2'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_68}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_13 = _activated_data_e_act_t_rec_rawIn_adjustedExp_T_69[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_26 = activated_data_e_act_t_rec_rawIn_adjustedExp_13; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_t_rec_rawIn_isZero_13 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_13 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_t_rec_rawIn_13_isZero = activated_data_e_act_t_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_13 = activated_data_e_act_t_rec_rawIn_adjustedExp_13[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_t_rec_rawIn_isSpecial_13 = &_activated_data_e_act_t_rec_rawIn_isSpecial_T_13; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_T_106 = activated_data_e_act_t_rec_rawIn_13_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_t_rec_rawIn_13_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_t_rec_rawIn_13_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_t_rec_rawIn_13_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_26 = ~activated_data_e_act_t_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_t_rec_rawIn_out_isNaN_T_27 = activated_data_e_act_t_rec_rawIn_isSpecial_13 & _activated_data_e_act_t_rec_rawIn_out_isNaN_T_26; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_t_rec_rawIn_13_isNaN = _activated_data_e_act_t_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_t_rec_rawIn_out_isInf_T_13 = activated_data_e_act_t_rec_rawIn_isSpecial_13 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_t_rec_rawIn_13_isInf = _activated_data_e_act_t_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_t_rec_rawIn_out_sExp_T_27 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sExp_T_26}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_t_rec_rawIn_13_sExp = _activated_data_e_act_t_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_52 = ~activated_data_e_act_t_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_53 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sig_T_52}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_54 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_13 ? activated_data_e_act_t_rec_rawIn_subnormFract_13 : activated_data_e_act_t_rec_rawIn_fractIn_13; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_t_rec_rawIn_out_sig_T_55 = {_activated_data_e_act_t_rec_rawIn_out_sig_T_53, _activated_data_e_act_t_rec_rawIn_out_sig_T_54}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_t_rec_rawIn_13_sig = _activated_data_e_act_t_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_t_rec_T_104 = activated_data_e_act_t_rec_rawIn_13_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_105 = activated_data_e_act_t_rec_rawIn_13_isZero ? 3'h0 : _activated_data_e_act_t_rec_T_104; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_t_rec_T_107 = {_activated_data_e_act_t_rec_T_105[2:1], _activated_data_e_act_t_rec_T_105[0] | _activated_data_e_act_t_rec_T_106}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_t_rec_T_108 = {activated_data_e_act_t_rec_rawIn_13_sign, _activated_data_e_act_t_rec_T_107}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_t_rec_T_109 = activated_data_e_act_t_rec_rawIn_13_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_t_rec_T_110 = {_activated_data_e_act_t_rec_T_108, _activated_data_e_act_t_rec_T_109}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_t_rec_T_111 = activated_data_e_act_t_rec_rawIn_13_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_t_rec_13 = {_activated_data_e_act_t_rec_T_110, _activated_data_e_act_t_rec_T_111}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_self_rec_rawIn_sign_16 = activated_data_e_act_q_erf_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_16_sign = activated_data_e_act_self_rec_rawIn_sign_16; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_16 = activated_data_e_act_q_erf_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_16 = activated_data_e_act_q_erf_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_16 = activated_data_e_act_self_rec_rawIn_expIn_16 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_16 = activated_data_e_act_self_rec_rawIn_fractIn_16 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_704 = activated_data_e_act_self_rec_rawIn_fractIn_16[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_705 = activated_data_e_act_self_rec_rawIn_fractIn_16[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_706 = activated_data_e_act_self_rec_rawIn_fractIn_16[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_707 = activated_data_e_act_self_rec_rawIn_fractIn_16[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_708 = activated_data_e_act_self_rec_rawIn_fractIn_16[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_709 = activated_data_e_act_self_rec_rawIn_fractIn_16[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_710 = activated_data_e_act_self_rec_rawIn_fractIn_16[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_711 = activated_data_e_act_self_rec_rawIn_fractIn_16[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_712 = activated_data_e_act_self_rec_rawIn_fractIn_16[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_713 = activated_data_e_act_self_rec_rawIn_fractIn_16[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_714 = activated_data_e_act_self_rec_rawIn_fractIn_16[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_715 = activated_data_e_act_self_rec_rawIn_fractIn_16[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_716 = activated_data_e_act_self_rec_rawIn_fractIn_16[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_717 = activated_data_e_act_self_rec_rawIn_fractIn_16[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_718 = activated_data_e_act_self_rec_rawIn_fractIn_16[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_719 = activated_data_e_act_self_rec_rawIn_fractIn_16[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_720 = activated_data_e_act_self_rec_rawIn_fractIn_16[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_721 = activated_data_e_act_self_rec_rawIn_fractIn_16[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_722 = activated_data_e_act_self_rec_rawIn_fractIn_16[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_723 = activated_data_e_act_self_rec_rawIn_fractIn_16[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_724 = activated_data_e_act_self_rec_rawIn_fractIn_16[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_725 = activated_data_e_act_self_rec_rawIn_fractIn_16[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_726 = activated_data_e_act_self_rec_rawIn_fractIn_16[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_727 = _activated_data_e_act_self_rec_rawIn_normDist_T_705 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_728 = _activated_data_e_act_self_rec_rawIn_normDist_T_706 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_727; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_729 = _activated_data_e_act_self_rec_rawIn_normDist_T_707 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_728; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_730 = _activated_data_e_act_self_rec_rawIn_normDist_T_708 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_729; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_731 = _activated_data_e_act_self_rec_rawIn_normDist_T_709 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_730; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_732 = _activated_data_e_act_self_rec_rawIn_normDist_T_710 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_731; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_733 = _activated_data_e_act_self_rec_rawIn_normDist_T_711 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_732; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_734 = _activated_data_e_act_self_rec_rawIn_normDist_T_712 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_733; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_735 = _activated_data_e_act_self_rec_rawIn_normDist_T_713 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_734; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_736 = _activated_data_e_act_self_rec_rawIn_normDist_T_714 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_735; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_737 = _activated_data_e_act_self_rec_rawIn_normDist_T_715 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_736; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_738 = _activated_data_e_act_self_rec_rawIn_normDist_T_716 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_737; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_739 = _activated_data_e_act_self_rec_rawIn_normDist_T_717 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_738; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_740 = _activated_data_e_act_self_rec_rawIn_normDist_T_718 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_739; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_741 = _activated_data_e_act_self_rec_rawIn_normDist_T_719 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_740; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_742 = _activated_data_e_act_self_rec_rawIn_normDist_T_720 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_741; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_743 = _activated_data_e_act_self_rec_rawIn_normDist_T_721 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_742; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_744 = _activated_data_e_act_self_rec_rawIn_normDist_T_722 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_743; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_745 = _activated_data_e_act_self_rec_rawIn_normDist_T_723 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_744; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_746 = _activated_data_e_act_self_rec_rawIn_normDist_T_724 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_745; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_747 = _activated_data_e_act_self_rec_rawIn_normDist_T_725 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_746; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_16 = _activated_data_e_act_self_rec_rawIn_normDist_T_726 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_747; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_32 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_16} << activated_data_e_act_self_rec_rawIn_normDist_16; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_33 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_32[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_16 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_33, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_80 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_16}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_81 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_16 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_80 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_16}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_82 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_16 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_83 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_82}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_84 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_81} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_83}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_16 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_84[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_32 = activated_data_e_act_self_rec_rawIn_adjustedExp_16; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_16 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_16 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_16; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_16_isZero = activated_data_e_act_self_rec_rawIn_isZero_16; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_16 = activated_data_e_act_self_rec_rawIn_adjustedExp_16[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_16 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_16; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_33; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_16; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_130 = activated_data_e_act_self_rec_rawIn_16_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_33; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_67; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_16_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_16_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_16_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_32 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_16; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_33 = activated_data_e_act_self_rec_rawIn_isSpecial_16 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_32; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_16_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_33; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_16 = activated_data_e_act_self_rec_rawIn_isSpecial_16 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_16; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_16_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_16; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_33 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_32}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_16_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_33; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_64 = ~activated_data_e_act_self_rec_rawIn_isZero_16; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_65 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_64}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_66 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_16 ? activated_data_e_act_self_rec_rawIn_subnormFract_16 : activated_data_e_act_self_rec_rawIn_fractIn_16; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_67 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_65, _activated_data_e_act_self_rec_rawIn_out_sig_T_66}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_16_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_67; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_128 = activated_data_e_act_self_rec_rawIn_16_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_129 = activated_data_e_act_self_rec_rawIn_16_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_128; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_131 = {_activated_data_e_act_self_rec_T_129[2:1], _activated_data_e_act_self_rec_T_129[0] | _activated_data_e_act_self_rec_T_130}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_132 = {activated_data_e_act_self_rec_rawIn_16_sign, _activated_data_e_act_self_rec_T_131}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_133 = activated_data_e_act_self_rec_rawIn_16_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_134 = {_activated_data_e_act_self_rec_T_132, _activated_data_e_act_self_rec_T_133}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_135 = activated_data_e_act_self_rec_rawIn_16_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_16 = {_activated_data_e_act_self_rec_T_134, _activated_data_e_act_self_rec_T_135}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_25; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_17_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_13 = _activated_data_e_act_muladder_13_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_13 = activated_data_e_act_result_bits_rawIn_exp_13[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_13 = _activated_data_e_act_result_bits_rawIn_isZero_T_13 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_13_isZero = activated_data_e_act_result_bits_rawIn_isZero_13; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_13 = activated_data_e_act_result_bits_rawIn_exp_13[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_13 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_13; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_27; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_41; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_13; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_13; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_55; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_13_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_13_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_13_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_13_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_13_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_26 = activated_data_e_act_result_bits_rawIn_exp_13[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_39 = activated_data_e_act_result_bits_rawIn_exp_13[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_27 = activated_data_e_act_result_bits_rawIn_isSpecial_13 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_26; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_13_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_27; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_40 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_39; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_41 = activated_data_e_act_result_bits_rawIn_isSpecial_13 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_40; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_13_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_41; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_13 = _activated_data_e_act_muladder_13_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_13_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_13; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_13 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_13}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_13_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_13; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_52 = ~activated_data_e_act_result_bits_rawIn_isZero_13; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_53 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_52}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_54 = _activated_data_e_act_muladder_13_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_55 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_53, _activated_data_e_act_result_bits_rawIn_out_sig_T_54}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_13_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_55; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_13 = $signed(activated_data_e_act_result_bits_rawIn_13_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_26 = activated_data_e_act_result_bits_rawIn_13_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_27 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_26}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_13 = _activated_data_e_act_result_bits_denormShiftDist_T_27[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_26 = activated_data_e_act_result_bits_rawIn_13_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_27 = _activated_data_e_act_result_bits_denormFract_T_26 >> activated_data_e_act_result_bits_denormShiftDist_13; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_13 = _activated_data_e_act_result_bits_denormFract_T_27[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_78 = activated_data_e_act_result_bits_rawIn_13_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_79 = {1'h0, _activated_data_e_act_result_bits_expOut_T_78} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_80 = _activated_data_e_act_result_bits_expOut_T_79[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_81 = activated_data_e_act_result_bits_isSubnormal_13 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_80; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_82 = activated_data_e_act_result_bits_rawIn_13_isNaN | activated_data_e_act_result_bits_rawIn_13_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_83 = {8{_activated_data_e_act_result_bits_expOut_T_82}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_13 = _activated_data_e_act_result_bits_expOut_T_81 | _activated_data_e_act_result_bits_expOut_T_83; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_26 = activated_data_e_act_result_bits_rawIn_13_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_27 = activated_data_e_act_result_bits_rawIn_13_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_26; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_13 = activated_data_e_act_result_bits_isSubnormal_13 ? activated_data_e_act_result_bits_denormFract_13 : _activated_data_e_act_result_bits_fractOut_T_27; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_13 = {activated_data_e_act_result_bits_rawIn_13_sign, activated_data_e_act_result_bits_expOut_13}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_25 = {activated_data_e_act_result_bits_hi_13, activated_data_e_act_result_bits_fractOut_13}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_17_bits = _activated_data_e_act_result_bits_T_25; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_t_rec_rawIn_sign_14 = activated_data_e_act_result_17_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_t_rec_rawIn_14_sign = activated_data_e_act_t_rec_rawIn_sign_14; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_t_rec_rawIn_expIn_14 = activated_data_e_act_result_17_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_t_rec_rawIn_fractIn_14 = activated_data_e_act_result_17_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_t_rec_rawIn_isZeroExpIn_14 = activated_data_e_act_t_rec_rawIn_expIn_14 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_t_rec_rawIn_isZeroFractIn_14 = activated_data_e_act_t_rec_rawIn_fractIn_14 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_t_rec_rawIn_normDist_T_616 = activated_data_e_act_t_rec_rawIn_fractIn_14[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_617 = activated_data_e_act_t_rec_rawIn_fractIn_14[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_618 = activated_data_e_act_t_rec_rawIn_fractIn_14[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_619 = activated_data_e_act_t_rec_rawIn_fractIn_14[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_620 = activated_data_e_act_t_rec_rawIn_fractIn_14[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_621 = activated_data_e_act_t_rec_rawIn_fractIn_14[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_622 = activated_data_e_act_t_rec_rawIn_fractIn_14[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_623 = activated_data_e_act_t_rec_rawIn_fractIn_14[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_624 = activated_data_e_act_t_rec_rawIn_fractIn_14[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_625 = activated_data_e_act_t_rec_rawIn_fractIn_14[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_626 = activated_data_e_act_t_rec_rawIn_fractIn_14[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_627 = activated_data_e_act_t_rec_rawIn_fractIn_14[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_628 = activated_data_e_act_t_rec_rawIn_fractIn_14[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_629 = activated_data_e_act_t_rec_rawIn_fractIn_14[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_630 = activated_data_e_act_t_rec_rawIn_fractIn_14[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_631 = activated_data_e_act_t_rec_rawIn_fractIn_14[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_632 = activated_data_e_act_t_rec_rawIn_fractIn_14[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_633 = activated_data_e_act_t_rec_rawIn_fractIn_14[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_634 = activated_data_e_act_t_rec_rawIn_fractIn_14[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_635 = activated_data_e_act_t_rec_rawIn_fractIn_14[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_636 = activated_data_e_act_t_rec_rawIn_fractIn_14[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_637 = activated_data_e_act_t_rec_rawIn_fractIn_14[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_t_rec_rawIn_normDist_T_638 = activated_data_e_act_t_rec_rawIn_fractIn_14[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_639 = _activated_data_e_act_t_rec_rawIn_normDist_T_617 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_640 = _activated_data_e_act_t_rec_rawIn_normDist_T_618 ? 5'h14 : _activated_data_e_act_t_rec_rawIn_normDist_T_639; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_641 = _activated_data_e_act_t_rec_rawIn_normDist_T_619 ? 5'h13 : _activated_data_e_act_t_rec_rawIn_normDist_T_640; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_642 = _activated_data_e_act_t_rec_rawIn_normDist_T_620 ? 5'h12 : _activated_data_e_act_t_rec_rawIn_normDist_T_641; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_643 = _activated_data_e_act_t_rec_rawIn_normDist_T_621 ? 5'h11 : _activated_data_e_act_t_rec_rawIn_normDist_T_642; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_644 = _activated_data_e_act_t_rec_rawIn_normDist_T_622 ? 5'h10 : _activated_data_e_act_t_rec_rawIn_normDist_T_643; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_645 = _activated_data_e_act_t_rec_rawIn_normDist_T_623 ? 5'hF : _activated_data_e_act_t_rec_rawIn_normDist_T_644; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_646 = _activated_data_e_act_t_rec_rawIn_normDist_T_624 ? 5'hE : _activated_data_e_act_t_rec_rawIn_normDist_T_645; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_647 = _activated_data_e_act_t_rec_rawIn_normDist_T_625 ? 5'hD : _activated_data_e_act_t_rec_rawIn_normDist_T_646; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_648 = _activated_data_e_act_t_rec_rawIn_normDist_T_626 ? 5'hC : _activated_data_e_act_t_rec_rawIn_normDist_T_647; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_649 = _activated_data_e_act_t_rec_rawIn_normDist_T_627 ? 5'hB : _activated_data_e_act_t_rec_rawIn_normDist_T_648; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_650 = _activated_data_e_act_t_rec_rawIn_normDist_T_628 ? 5'hA : _activated_data_e_act_t_rec_rawIn_normDist_T_649; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_651 = _activated_data_e_act_t_rec_rawIn_normDist_T_629 ? 5'h9 : _activated_data_e_act_t_rec_rawIn_normDist_T_650; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_652 = _activated_data_e_act_t_rec_rawIn_normDist_T_630 ? 5'h8 : _activated_data_e_act_t_rec_rawIn_normDist_T_651; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_653 = _activated_data_e_act_t_rec_rawIn_normDist_T_631 ? 5'h7 : _activated_data_e_act_t_rec_rawIn_normDist_T_652; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_654 = _activated_data_e_act_t_rec_rawIn_normDist_T_632 ? 5'h6 : _activated_data_e_act_t_rec_rawIn_normDist_T_653; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_655 = _activated_data_e_act_t_rec_rawIn_normDist_T_633 ? 5'h5 : _activated_data_e_act_t_rec_rawIn_normDist_T_654; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_656 = _activated_data_e_act_t_rec_rawIn_normDist_T_634 ? 5'h4 : _activated_data_e_act_t_rec_rawIn_normDist_T_655; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_657 = _activated_data_e_act_t_rec_rawIn_normDist_T_635 ? 5'h3 : _activated_data_e_act_t_rec_rawIn_normDist_T_656; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_658 = _activated_data_e_act_t_rec_rawIn_normDist_T_636 ? 5'h2 : _activated_data_e_act_t_rec_rawIn_normDist_T_657; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_t_rec_rawIn_normDist_T_659 = _activated_data_e_act_t_rec_rawIn_normDist_T_637 ? 5'h1 : _activated_data_e_act_t_rec_rawIn_normDist_T_658; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_t_rec_rawIn_normDist_14 = _activated_data_e_act_t_rec_rawIn_normDist_T_638 ? 5'h0 : _activated_data_e_act_t_rec_rawIn_normDist_T_659; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_28 = {31'h0, activated_data_e_act_t_rec_rawIn_fractIn_14} << activated_data_e_act_t_rec_rawIn_normDist_14; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_t_rec_rawIn_subnormFract_T_29 = _activated_data_e_act_t_rec_rawIn_subnormFract_T_28[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_t_rec_rawIn_subnormFract_14 = {_activated_data_e_act_t_rec_rawIn_subnormFract_T_29, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_70 = {4'hF, ~activated_data_e_act_t_rec_rawIn_normDist_14}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_71 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_14 ? _activated_data_e_act_t_rec_rawIn_adjustedExp_T_70 : {1'h0, activated_data_e_act_t_rec_rawIn_expIn_14}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_72 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_14 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_73 = {6'h20, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_72}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_t_rec_rawIn_adjustedExp_T_74 = {1'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_71} + {2'h0, _activated_data_e_act_t_rec_rawIn_adjustedExp_T_73}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_t_rec_rawIn_adjustedExp_14 = _activated_data_e_act_t_rec_rawIn_adjustedExp_T_74[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_28 = activated_data_e_act_t_rec_rawIn_adjustedExp_14; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_t_rec_rawIn_isZero_14 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_14 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_t_rec_rawIn_14_isZero = activated_data_e_act_t_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_isSpecial_T_14 = activated_data_e_act_t_rec_rawIn_adjustedExp_14[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_t_rec_rawIn_isSpecial_14 = &_activated_data_e_act_t_rec_rawIn_isSpecial_T_14; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_t_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_t_rec_T_114 = activated_data_e_act_t_rec_rawIn_14_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_t_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_t_rec_rawIn_14_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_t_rec_rawIn_14_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_t_rec_rawIn_14_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_t_rec_rawIn_out_isNaN_T_28 = ~activated_data_e_act_t_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_t_rec_rawIn_out_isNaN_T_29 = activated_data_e_act_t_rec_rawIn_isSpecial_14 & _activated_data_e_act_t_rec_rawIn_out_isNaN_T_28; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_t_rec_rawIn_14_isNaN = _activated_data_e_act_t_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_t_rec_rawIn_out_isInf_T_14 = activated_data_e_act_t_rec_rawIn_isSpecial_14 & activated_data_e_act_t_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_t_rec_rawIn_14_isInf = _activated_data_e_act_t_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_t_rec_rawIn_out_sExp_T_29 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sExp_T_28}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_t_rec_rawIn_14_sExp = _activated_data_e_act_t_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_t_rec_rawIn_out_sig_T_56 = ~activated_data_e_act_t_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_57 = {1'h0, _activated_data_e_act_t_rec_rawIn_out_sig_T_56}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_t_rec_rawIn_out_sig_T_58 = activated_data_e_act_t_rec_rawIn_isZeroExpIn_14 ? activated_data_e_act_t_rec_rawIn_subnormFract_14 : activated_data_e_act_t_rec_rawIn_fractIn_14; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_t_rec_rawIn_out_sig_T_59 = {_activated_data_e_act_t_rec_rawIn_out_sig_T_57, _activated_data_e_act_t_rec_rawIn_out_sig_T_58}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_t_rec_rawIn_14_sig = _activated_data_e_act_t_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_t_rec_T_112 = activated_data_e_act_t_rec_rawIn_14_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_t_rec_T_113 = activated_data_e_act_t_rec_rawIn_14_isZero ? 3'h0 : _activated_data_e_act_t_rec_T_112; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_t_rec_T_115 = {_activated_data_e_act_t_rec_T_113[2:1], _activated_data_e_act_t_rec_T_113[0] | _activated_data_e_act_t_rec_T_114}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_t_rec_T_116 = {activated_data_e_act_t_rec_rawIn_14_sign, _activated_data_e_act_t_rec_T_115}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_t_rec_T_117 = activated_data_e_act_t_rec_rawIn_14_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_t_rec_T_118 = {_activated_data_e_act_t_rec_T_116, _activated_data_e_act_t_rec_T_117}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_t_rec_T_119 = activated_data_e_act_t_rec_rawIn_14_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_t_rec_14 = {_activated_data_e_act_t_rec_T_118, _activated_data_e_act_t_rec_T_119}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_self_rec_rawIn_17_sign = activated_data_e_act_self_rec_rawIn_sign_17; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_17 = activated_data_e_act_self_rec_rawIn_expIn_17 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_17 = activated_data_e_act_self_rec_rawIn_fractIn_17 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_748 = activated_data_e_act_self_rec_rawIn_fractIn_17[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_749 = activated_data_e_act_self_rec_rawIn_fractIn_17[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_750 = activated_data_e_act_self_rec_rawIn_fractIn_17[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_751 = activated_data_e_act_self_rec_rawIn_fractIn_17[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_752 = activated_data_e_act_self_rec_rawIn_fractIn_17[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_753 = activated_data_e_act_self_rec_rawIn_fractIn_17[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_754 = activated_data_e_act_self_rec_rawIn_fractIn_17[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_755 = activated_data_e_act_self_rec_rawIn_fractIn_17[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_756 = activated_data_e_act_self_rec_rawIn_fractIn_17[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_757 = activated_data_e_act_self_rec_rawIn_fractIn_17[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_758 = activated_data_e_act_self_rec_rawIn_fractIn_17[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_759 = activated_data_e_act_self_rec_rawIn_fractIn_17[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_760 = activated_data_e_act_self_rec_rawIn_fractIn_17[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_761 = activated_data_e_act_self_rec_rawIn_fractIn_17[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_762 = activated_data_e_act_self_rec_rawIn_fractIn_17[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_763 = activated_data_e_act_self_rec_rawIn_fractIn_17[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_764 = activated_data_e_act_self_rec_rawIn_fractIn_17[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_765 = activated_data_e_act_self_rec_rawIn_fractIn_17[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_766 = activated_data_e_act_self_rec_rawIn_fractIn_17[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_767 = activated_data_e_act_self_rec_rawIn_fractIn_17[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_768 = activated_data_e_act_self_rec_rawIn_fractIn_17[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_769 = activated_data_e_act_self_rec_rawIn_fractIn_17[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_770 = activated_data_e_act_self_rec_rawIn_fractIn_17[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_771 = _activated_data_e_act_self_rec_rawIn_normDist_T_749 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_772 = _activated_data_e_act_self_rec_rawIn_normDist_T_750 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_771; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_773 = _activated_data_e_act_self_rec_rawIn_normDist_T_751 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_772; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_774 = _activated_data_e_act_self_rec_rawIn_normDist_T_752 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_773; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_775 = _activated_data_e_act_self_rec_rawIn_normDist_T_753 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_774; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_776 = _activated_data_e_act_self_rec_rawIn_normDist_T_754 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_775; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_777 = _activated_data_e_act_self_rec_rawIn_normDist_T_755 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_776; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_778 = _activated_data_e_act_self_rec_rawIn_normDist_T_756 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_777; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_779 = _activated_data_e_act_self_rec_rawIn_normDist_T_757 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_778; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_780 = _activated_data_e_act_self_rec_rawIn_normDist_T_758 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_779; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_781 = _activated_data_e_act_self_rec_rawIn_normDist_T_759 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_780; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_782 = _activated_data_e_act_self_rec_rawIn_normDist_T_760 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_781; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_783 = _activated_data_e_act_self_rec_rawIn_normDist_T_761 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_782; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_784 = _activated_data_e_act_self_rec_rawIn_normDist_T_762 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_783; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_785 = _activated_data_e_act_self_rec_rawIn_normDist_T_763 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_784; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_786 = _activated_data_e_act_self_rec_rawIn_normDist_T_764 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_785; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_787 = _activated_data_e_act_self_rec_rawIn_normDist_T_765 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_786; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_788 = _activated_data_e_act_self_rec_rawIn_normDist_T_766 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_787; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_789 = _activated_data_e_act_self_rec_rawIn_normDist_T_767 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_788; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_790 = _activated_data_e_act_self_rec_rawIn_normDist_T_768 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_789; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_791 = _activated_data_e_act_self_rec_rawIn_normDist_T_769 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_790; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_17 = _activated_data_e_act_self_rec_rawIn_normDist_T_770 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_791; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_34 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_17} << activated_data_e_act_self_rec_rawIn_normDist_17; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_35 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_34[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_17 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_35, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_85 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_17}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_86 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_17 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_85 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_17}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_87 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_17 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_88 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_87}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_89 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_86} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_88}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_17 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_89[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_34 = activated_data_e_act_self_rec_rawIn_adjustedExp_17; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_17 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_17 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_17; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_17_isZero = activated_data_e_act_self_rec_rawIn_isZero_17; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_17 = activated_data_e_act_self_rec_rawIn_adjustedExp_17[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_17 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_17; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_35; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_17; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_138 = activated_data_e_act_self_rec_rawIn_17_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_35; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_71; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_17_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_17_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_17_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_34 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_17; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_35 = activated_data_e_act_self_rec_rawIn_isSpecial_17 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_34; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_17_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_35; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_17 = activated_data_e_act_self_rec_rawIn_isSpecial_17 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_17; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_17_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_17; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_35 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_34}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_17_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_35; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_68 = ~activated_data_e_act_self_rec_rawIn_isZero_17; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_69 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_68}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_70 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_17 ? activated_data_e_act_self_rec_rawIn_subnormFract_17 : activated_data_e_act_self_rec_rawIn_fractIn_17; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_71 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_69, _activated_data_e_act_self_rec_rawIn_out_sig_T_70}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_17_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_71; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_136 = activated_data_e_act_self_rec_rawIn_17_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_137 = activated_data_e_act_self_rec_rawIn_17_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_136; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_139 = {_activated_data_e_act_self_rec_T_137[2:1], _activated_data_e_act_self_rec_T_137[0] | _activated_data_e_act_self_rec_T_138}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_140 = {activated_data_e_act_self_rec_rawIn_17_sign, _activated_data_e_act_self_rec_T_139}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_141 = activated_data_e_act_self_rec_rawIn_17_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_142 = {_activated_data_e_act_self_rec_T_140, _activated_data_e_act_self_rec_T_141}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_143 = activated_data_e_act_self_rec_rawIn_17_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_17 = {_activated_data_e_act_self_rec_T_142, _activated_data_e_act_self_rec_T_143}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_out_3_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_out_bits_rawIn_exp_3 = _activated_data_e_act_muladder_14_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_out_bits_rawIn_isZero_T_3 = activated_data_e_act_out_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_out_bits_rawIn_isZero_3 = _activated_data_e_act_out_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_out_bits_rawIn_3_isZero = activated_data_e_act_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_out_bits_rawIn_isSpecial_T_3 = activated_data_e_act_out_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_out_bits_rawIn_isSpecial_3 = &_activated_data_e_act_out_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_out_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_out_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_out_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_out_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_out_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_9 = activated_data_e_act_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_out_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_out_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_out_bits_rawIn_3_isNaN = _activated_data_e_act_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_out_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_out_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_out_bits_rawIn_out_isInf_T_11 = activated_data_e_act_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_out_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_out_bits_rawIn_3_isInf = _activated_data_e_act_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_out_bits_rawIn_out_sign_T_3 = _activated_data_e_act_muladder_14_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_out_bits_rawIn_3_sign = _activated_data_e_act_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_out_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_out_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_out_bits_rawIn_3_sExp = _activated_data_e_act_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_out_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_out_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_out_bits_rawIn_out_sig_T_14 = _activated_data_e_act_muladder_14_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_out_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_out_bits_rawIn_out_sig_T_13, _activated_data_e_act_out_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_out_bits_rawIn_3_sig = _activated_data_e_act_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_out_bits_isSubnormal_3 = $signed(activated_data_e_act_out_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_out_bits_denormShiftDist_T_6 = activated_data_e_act_out_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_out_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_out_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_out_bits_denormShiftDist_3 = _activated_data_e_act_out_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_out_bits_denormFract_T_6 = activated_data_e_act_out_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_out_bits_denormFract_T_7 = _activated_data_e_act_out_bits_denormFract_T_6 >> activated_data_e_act_out_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_out_bits_denormFract_3 = _activated_data_e_act_out_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_out_bits_expOut_T_18 = activated_data_e_act_out_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_out_bits_expOut_T_19 = {1'h0, _activated_data_e_act_out_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_out_bits_expOut_T_20 = _activated_data_e_act_out_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_out_bits_expOut_T_21 = activated_data_e_act_out_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_out_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_out_bits_expOut_T_22 = activated_data_e_act_out_bits_rawIn_3_isNaN | activated_data_e_act_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_out_bits_expOut_T_23 = {8{_activated_data_e_act_out_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_out_bits_expOut_3 = _activated_data_e_act_out_bits_expOut_T_21 | _activated_data_e_act_out_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_out_bits_fractOut_T_6 = activated_data_e_act_out_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_out_bits_fractOut_T_7 = activated_data_e_act_out_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_out_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_out_bits_fractOut_3 = activated_data_e_act_out_bits_isSubnormal_3 ? activated_data_e_act_out_bits_denormFract_3 : _activated_data_e_act_out_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_out_bits_hi_3 = {activated_data_e_act_out_bits_rawIn_3_sign, activated_data_e_act_out_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_out_bits_T_3 = {activated_data_e_act_out_bits_hi_3, activated_data_e_act_out_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_out_3_bits = _activated_data_e_act_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_self_rec_rawIn_sign_18 = activated_data_e_act_out_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_self_rec_rawIn_18_sign = activated_data_e_act_self_rec_rawIn_sign_18; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_self_rec_rawIn_expIn_18 = activated_data_e_act_out_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_self_rec_rawIn_fractIn_18 = activated_data_e_act_out_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_18 = activated_data_e_act_self_rec_rawIn_expIn_18 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_18 = activated_data_e_act_self_rec_rawIn_fractIn_18 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_792 = activated_data_e_act_self_rec_rawIn_fractIn_18[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_793 = activated_data_e_act_self_rec_rawIn_fractIn_18[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_794 = activated_data_e_act_self_rec_rawIn_fractIn_18[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_795 = activated_data_e_act_self_rec_rawIn_fractIn_18[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_796 = activated_data_e_act_self_rec_rawIn_fractIn_18[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_797 = activated_data_e_act_self_rec_rawIn_fractIn_18[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_798 = activated_data_e_act_self_rec_rawIn_fractIn_18[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_799 = activated_data_e_act_self_rec_rawIn_fractIn_18[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_800 = activated_data_e_act_self_rec_rawIn_fractIn_18[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_801 = activated_data_e_act_self_rec_rawIn_fractIn_18[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_802 = activated_data_e_act_self_rec_rawIn_fractIn_18[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_803 = activated_data_e_act_self_rec_rawIn_fractIn_18[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_804 = activated_data_e_act_self_rec_rawIn_fractIn_18[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_805 = activated_data_e_act_self_rec_rawIn_fractIn_18[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_806 = activated_data_e_act_self_rec_rawIn_fractIn_18[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_807 = activated_data_e_act_self_rec_rawIn_fractIn_18[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_808 = activated_data_e_act_self_rec_rawIn_fractIn_18[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_809 = activated_data_e_act_self_rec_rawIn_fractIn_18[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_810 = activated_data_e_act_self_rec_rawIn_fractIn_18[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_811 = activated_data_e_act_self_rec_rawIn_fractIn_18[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_812 = activated_data_e_act_self_rec_rawIn_fractIn_18[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_813 = activated_data_e_act_self_rec_rawIn_fractIn_18[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_814 = activated_data_e_act_self_rec_rawIn_fractIn_18[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_815 = _activated_data_e_act_self_rec_rawIn_normDist_T_793 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_816 = _activated_data_e_act_self_rec_rawIn_normDist_T_794 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_815; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_817 = _activated_data_e_act_self_rec_rawIn_normDist_T_795 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_816; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_818 = _activated_data_e_act_self_rec_rawIn_normDist_T_796 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_817; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_819 = _activated_data_e_act_self_rec_rawIn_normDist_T_797 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_818; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_820 = _activated_data_e_act_self_rec_rawIn_normDist_T_798 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_819; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_821 = _activated_data_e_act_self_rec_rawIn_normDist_T_799 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_820; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_822 = _activated_data_e_act_self_rec_rawIn_normDist_T_800 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_821; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_823 = _activated_data_e_act_self_rec_rawIn_normDist_T_801 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_822; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_824 = _activated_data_e_act_self_rec_rawIn_normDist_T_802 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_823; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_825 = _activated_data_e_act_self_rec_rawIn_normDist_T_803 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_824; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_826 = _activated_data_e_act_self_rec_rawIn_normDist_T_804 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_825; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_827 = _activated_data_e_act_self_rec_rawIn_normDist_T_805 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_826; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_828 = _activated_data_e_act_self_rec_rawIn_normDist_T_806 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_827; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_829 = _activated_data_e_act_self_rec_rawIn_normDist_T_807 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_828; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_830 = _activated_data_e_act_self_rec_rawIn_normDist_T_808 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_829; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_831 = _activated_data_e_act_self_rec_rawIn_normDist_T_809 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_830; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_832 = _activated_data_e_act_self_rec_rawIn_normDist_T_810 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_831; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_833 = _activated_data_e_act_self_rec_rawIn_normDist_T_811 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_832; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_834 = _activated_data_e_act_self_rec_rawIn_normDist_T_812 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_833; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_835 = _activated_data_e_act_self_rec_rawIn_normDist_T_813 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_834; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_18 = _activated_data_e_act_self_rec_rawIn_normDist_T_814 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_835; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_36 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_18} << activated_data_e_act_self_rec_rawIn_normDist_18; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_37 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_36[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_18 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_37, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_90 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_18}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_91 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_18 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_90 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_18}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_92 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_18 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_93 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_92}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_94 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_91} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_93}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_18 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_94[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_36 = activated_data_e_act_self_rec_rawIn_adjustedExp_18; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_18 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_18 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_18; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_18_isZero = activated_data_e_act_self_rec_rawIn_isZero_18; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_18 = activated_data_e_act_self_rec_rawIn_adjustedExp_18[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_18 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_18; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_37; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_18; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_146 = activated_data_e_act_self_rec_rawIn_18_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_37; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_75; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_18_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_18_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_18_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_36 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_18; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_37 = activated_data_e_act_self_rec_rawIn_isSpecial_18 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_36; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_18_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_37; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_18 = activated_data_e_act_self_rec_rawIn_isSpecial_18 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_18; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_18_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_18; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_37 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_36}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_18_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_37; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_72 = ~activated_data_e_act_self_rec_rawIn_isZero_18; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_73 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_72}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_74 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_18 ? activated_data_e_act_self_rec_rawIn_subnormFract_18 : activated_data_e_act_self_rec_rawIn_fractIn_18; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_75 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_73, _activated_data_e_act_self_rec_rawIn_out_sig_T_74}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_18_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_75; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_144 = activated_data_e_act_self_rec_rawIn_18_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_145 = activated_data_e_act_self_rec_rawIn_18_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_144; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_147 = {_activated_data_e_act_self_rec_T_145[2:1], _activated_data_e_act_self_rec_T_145[0] | _activated_data_e_act_self_rec_T_146}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_148 = {activated_data_e_act_self_rec_rawIn_18_sign, _activated_data_e_act_self_rec_T_147}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_149 = activated_data_e_act_self_rec_rawIn_18_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_150 = {_activated_data_e_act_self_rec_T_148, _activated_data_e_act_self_rec_T_149}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_151 = activated_data_e_act_self_rec_rawIn_18_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_18 = {_activated_data_e_act_self_rec_T_150, _activated_data_e_act_self_rec_T_151}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_26; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_18_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_14 = _activated_data_e_act_resizer_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_14 = activated_data_e_act_result_bits_rawIn_exp_14[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_14 = _activated_data_e_act_result_bits_rawIn_isZero_T_14 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_14_isZero = activated_data_e_act_result_bits_rawIn_isZero_14; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_14 = activated_data_e_act_result_bits_rawIn_exp_14[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_14 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_14; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_29; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_44; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_14; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_14; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_59; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_14_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_14_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_14_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_14_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_14_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_28 = activated_data_e_act_result_bits_rawIn_exp_14[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_42 = activated_data_e_act_result_bits_rawIn_exp_14[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_29 = activated_data_e_act_result_bits_rawIn_isSpecial_14 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_28; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_14_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_29; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_43 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_42; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_44 = activated_data_e_act_result_bits_rawIn_isSpecial_14 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_43; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_14_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_44; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_14 = _activated_data_e_act_resizer_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_14_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_14; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_14 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_14}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_14_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_14; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_56 = ~activated_data_e_act_result_bits_rawIn_isZero_14; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_57 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_56}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_58 = _activated_data_e_act_resizer_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_59 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_57, _activated_data_e_act_result_bits_rawIn_out_sig_T_58}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_14_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_59; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_14 = $signed(activated_data_e_act_result_bits_rawIn_14_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_28 = activated_data_e_act_result_bits_rawIn_14_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_29 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_28}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_14 = _activated_data_e_act_result_bits_denormShiftDist_T_29[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_28 = activated_data_e_act_result_bits_rawIn_14_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_29 = _activated_data_e_act_result_bits_denormFract_T_28 >> activated_data_e_act_result_bits_denormShiftDist_14; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_14 = _activated_data_e_act_result_bits_denormFract_T_29[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_84 = activated_data_e_act_result_bits_rawIn_14_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_85 = {1'h0, _activated_data_e_act_result_bits_expOut_T_84} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_86 = _activated_data_e_act_result_bits_expOut_T_85[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_87 = activated_data_e_act_result_bits_isSubnormal_14 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_86; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_88 = activated_data_e_act_result_bits_rawIn_14_isNaN | activated_data_e_act_result_bits_rawIn_14_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_89 = {8{_activated_data_e_act_result_bits_expOut_T_88}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_14 = _activated_data_e_act_result_bits_expOut_T_87 | _activated_data_e_act_result_bits_expOut_T_89; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_28 = activated_data_e_act_result_bits_rawIn_14_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_29 = activated_data_e_act_result_bits_rawIn_14_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_28; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_14 = activated_data_e_act_result_bits_isSubnormal_14 ? activated_data_e_act_result_bits_denormFract_14 : _activated_data_e_act_result_bits_fractOut_T_29; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_14 = {activated_data_e_act_result_bits_rawIn_14_sign, activated_data_e_act_result_bits_expOut_14}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_26 = {activated_data_e_act_result_bits_hi_14, activated_data_e_act_result_bits_fractOut_14}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_18_bits = _activated_data_e_act_result_bits_T_26; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_self_rec_rawIn_19_sign = activated_data_e_act_self_rec_rawIn_sign_19; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_self_rec_rawIn_isZeroExpIn_19 = activated_data_e_act_self_rec_rawIn_expIn_19 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_self_rec_rawIn_isZeroFractIn_19 = activated_data_e_act_self_rec_rawIn_fractIn_19 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_self_rec_rawIn_normDist_T_836 = activated_data_e_act_self_rec_rawIn_fractIn_19[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_837 = activated_data_e_act_self_rec_rawIn_fractIn_19[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_838 = activated_data_e_act_self_rec_rawIn_fractIn_19[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_839 = activated_data_e_act_self_rec_rawIn_fractIn_19[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_840 = activated_data_e_act_self_rec_rawIn_fractIn_19[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_841 = activated_data_e_act_self_rec_rawIn_fractIn_19[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_842 = activated_data_e_act_self_rec_rawIn_fractIn_19[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_843 = activated_data_e_act_self_rec_rawIn_fractIn_19[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_844 = activated_data_e_act_self_rec_rawIn_fractIn_19[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_845 = activated_data_e_act_self_rec_rawIn_fractIn_19[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_846 = activated_data_e_act_self_rec_rawIn_fractIn_19[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_847 = activated_data_e_act_self_rec_rawIn_fractIn_19[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_848 = activated_data_e_act_self_rec_rawIn_fractIn_19[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_849 = activated_data_e_act_self_rec_rawIn_fractIn_19[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_850 = activated_data_e_act_self_rec_rawIn_fractIn_19[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_851 = activated_data_e_act_self_rec_rawIn_fractIn_19[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_852 = activated_data_e_act_self_rec_rawIn_fractIn_19[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_853 = activated_data_e_act_self_rec_rawIn_fractIn_19[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_854 = activated_data_e_act_self_rec_rawIn_fractIn_19[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_855 = activated_data_e_act_self_rec_rawIn_fractIn_19[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_856 = activated_data_e_act_self_rec_rawIn_fractIn_19[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_857 = activated_data_e_act_self_rec_rawIn_fractIn_19[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_self_rec_rawIn_normDist_T_858 = activated_data_e_act_self_rec_rawIn_fractIn_19[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_859 = _activated_data_e_act_self_rec_rawIn_normDist_T_837 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_860 = _activated_data_e_act_self_rec_rawIn_normDist_T_838 ? 5'h14 : _activated_data_e_act_self_rec_rawIn_normDist_T_859; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_861 = _activated_data_e_act_self_rec_rawIn_normDist_T_839 ? 5'h13 : _activated_data_e_act_self_rec_rawIn_normDist_T_860; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_862 = _activated_data_e_act_self_rec_rawIn_normDist_T_840 ? 5'h12 : _activated_data_e_act_self_rec_rawIn_normDist_T_861; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_863 = _activated_data_e_act_self_rec_rawIn_normDist_T_841 ? 5'h11 : _activated_data_e_act_self_rec_rawIn_normDist_T_862; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_864 = _activated_data_e_act_self_rec_rawIn_normDist_T_842 ? 5'h10 : _activated_data_e_act_self_rec_rawIn_normDist_T_863; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_865 = _activated_data_e_act_self_rec_rawIn_normDist_T_843 ? 5'hF : _activated_data_e_act_self_rec_rawIn_normDist_T_864; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_866 = _activated_data_e_act_self_rec_rawIn_normDist_T_844 ? 5'hE : _activated_data_e_act_self_rec_rawIn_normDist_T_865; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_867 = _activated_data_e_act_self_rec_rawIn_normDist_T_845 ? 5'hD : _activated_data_e_act_self_rec_rawIn_normDist_T_866; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_868 = _activated_data_e_act_self_rec_rawIn_normDist_T_846 ? 5'hC : _activated_data_e_act_self_rec_rawIn_normDist_T_867; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_869 = _activated_data_e_act_self_rec_rawIn_normDist_T_847 ? 5'hB : _activated_data_e_act_self_rec_rawIn_normDist_T_868; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_870 = _activated_data_e_act_self_rec_rawIn_normDist_T_848 ? 5'hA : _activated_data_e_act_self_rec_rawIn_normDist_T_869; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_871 = _activated_data_e_act_self_rec_rawIn_normDist_T_849 ? 5'h9 : _activated_data_e_act_self_rec_rawIn_normDist_T_870; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_872 = _activated_data_e_act_self_rec_rawIn_normDist_T_850 ? 5'h8 : _activated_data_e_act_self_rec_rawIn_normDist_T_871; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_873 = _activated_data_e_act_self_rec_rawIn_normDist_T_851 ? 5'h7 : _activated_data_e_act_self_rec_rawIn_normDist_T_872; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_874 = _activated_data_e_act_self_rec_rawIn_normDist_T_852 ? 5'h6 : _activated_data_e_act_self_rec_rawIn_normDist_T_873; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_875 = _activated_data_e_act_self_rec_rawIn_normDist_T_853 ? 5'h5 : _activated_data_e_act_self_rec_rawIn_normDist_T_874; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_876 = _activated_data_e_act_self_rec_rawIn_normDist_T_854 ? 5'h4 : _activated_data_e_act_self_rec_rawIn_normDist_T_875; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_877 = _activated_data_e_act_self_rec_rawIn_normDist_T_855 ? 5'h3 : _activated_data_e_act_self_rec_rawIn_normDist_T_876; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_878 = _activated_data_e_act_self_rec_rawIn_normDist_T_856 ? 5'h2 : _activated_data_e_act_self_rec_rawIn_normDist_T_877; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_self_rec_rawIn_normDist_T_879 = _activated_data_e_act_self_rec_rawIn_normDist_T_857 ? 5'h1 : _activated_data_e_act_self_rec_rawIn_normDist_T_878; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_self_rec_rawIn_normDist_19 = _activated_data_e_act_self_rec_rawIn_normDist_T_858 ? 5'h0 : _activated_data_e_act_self_rec_rawIn_normDist_T_879; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_38 = {31'h0, activated_data_e_act_self_rec_rawIn_fractIn_19} << activated_data_e_act_self_rec_rawIn_normDist_19; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_self_rec_rawIn_subnormFract_T_39 = _activated_data_e_act_self_rec_rawIn_subnormFract_T_38[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_self_rec_rawIn_subnormFract_19 = {_activated_data_e_act_self_rec_rawIn_subnormFract_T_39, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_95 = {4'hF, ~activated_data_e_act_self_rec_rawIn_normDist_19}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_96 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_19 ? _activated_data_e_act_self_rec_rawIn_adjustedExp_T_95 : {1'h0, activated_data_e_act_self_rec_rawIn_expIn_19}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_97 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_19 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_98 = {6'h20, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_97}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_self_rec_rawIn_adjustedExp_T_99 = {1'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_96} + {2'h0, _activated_data_e_act_self_rec_rawIn_adjustedExp_T_98}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_self_rec_rawIn_adjustedExp_19 = _activated_data_e_act_self_rec_rawIn_adjustedExp_T_99[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_38 = activated_data_e_act_self_rec_rawIn_adjustedExp_19; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_self_rec_rawIn_isZero_19 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_19 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_19; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_self_rec_rawIn_19_isZero = activated_data_e_act_self_rec_rawIn_isZero_19; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_isSpecial_T_19 = activated_data_e_act_self_rec_rawIn_adjustedExp_19[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_self_rec_rawIn_isSpecial_19 = &_activated_data_e_act_self_rec_rawIn_isSpecial_T_19; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_39; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_self_rec_rawIn_out_isInf_T_19; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_self_rec_T_154 = activated_data_e_act_self_rec_rawIn_19_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_self_rec_rawIn_out_sExp_T_39; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_79; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_self_rec_rawIn_19_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_self_rec_rawIn_19_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_self_rec_rawIn_19_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_self_rec_rawIn_out_isNaN_T_38 = ~activated_data_e_act_self_rec_rawIn_isZeroFractIn_19; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_self_rec_rawIn_out_isNaN_T_39 = activated_data_e_act_self_rec_rawIn_isSpecial_19 & _activated_data_e_act_self_rec_rawIn_out_isNaN_T_38; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_self_rec_rawIn_19_isNaN = _activated_data_e_act_self_rec_rawIn_out_isNaN_T_39; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_self_rec_rawIn_out_isInf_T_19 = activated_data_e_act_self_rec_rawIn_isSpecial_19 & activated_data_e_act_self_rec_rawIn_isZeroFractIn_19; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_self_rec_rawIn_19_isInf = _activated_data_e_act_self_rec_rawIn_out_isInf_T_19; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_self_rec_rawIn_out_sExp_T_39 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sExp_T_38}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_self_rec_rawIn_19_sExp = _activated_data_e_act_self_rec_rawIn_out_sExp_T_39; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_self_rec_rawIn_out_sig_T_76 = ~activated_data_e_act_self_rec_rawIn_isZero_19; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_77 = {1'h0, _activated_data_e_act_self_rec_rawIn_out_sig_T_76}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_self_rec_rawIn_out_sig_T_78 = activated_data_e_act_self_rec_rawIn_isZeroExpIn_19 ? activated_data_e_act_self_rec_rawIn_subnormFract_19 : activated_data_e_act_self_rec_rawIn_fractIn_19; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_self_rec_rawIn_out_sig_T_79 = {_activated_data_e_act_self_rec_rawIn_out_sig_T_77, _activated_data_e_act_self_rec_rawIn_out_sig_T_78}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_self_rec_rawIn_19_sig = _activated_data_e_act_self_rec_rawIn_out_sig_T_79; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_self_rec_T_152 = activated_data_e_act_self_rec_rawIn_19_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_self_rec_T_153 = activated_data_e_act_self_rec_rawIn_19_isZero ? 3'h0 : _activated_data_e_act_self_rec_T_152; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_self_rec_T_155 = {_activated_data_e_act_self_rec_T_153[2:1], _activated_data_e_act_self_rec_T_153[0] | _activated_data_e_act_self_rec_T_154}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_self_rec_T_156 = {activated_data_e_act_self_rec_rawIn_19_sign, _activated_data_e_act_self_rec_T_155}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_self_rec_T_157 = activated_data_e_act_self_rec_rawIn_19_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_self_rec_T_158 = {_activated_data_e_act_self_rec_T_156, _activated_data_e_act_self_rec_T_157}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_self_rec_T_159 = activated_data_e_act_self_rec_rawIn_19_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_self_rec_19 = {_activated_data_e_act_self_rec_T_158, _activated_data_e_act_self_rec_T_159}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_result_bits_T_27; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_result_19_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_result_bits_rawIn_exp_15 = _activated_data_e_act_muladder_15_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_result_bits_rawIn_isZero_T_15 = activated_data_e_act_result_bits_rawIn_exp_15[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_result_bits_rawIn_isZero_15 = _activated_data_e_act_result_bits_rawIn_isZero_T_15 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_result_bits_rawIn_15_isZero = activated_data_e_act_result_bits_rawIn_isZero_15; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_result_bits_rawIn_isSpecial_T_15 = activated_data_e_act_result_bits_rawIn_exp_15[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_result_bits_rawIn_isSpecial_15 = &_activated_data_e_act_result_bits_rawIn_isSpecial_T_15; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_31; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_47; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_result_bits_rawIn_out_sign_T_15; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_result_bits_rawIn_out_sExp_T_15; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_63; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_result_bits_rawIn_15_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_15_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_result_bits_rawIn_15_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_result_bits_rawIn_15_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_result_bits_rawIn_15_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_result_bits_rawIn_out_isNaN_T_30 = activated_data_e_act_result_bits_rawIn_exp_15[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_45 = activated_data_e_act_result_bits_rawIn_exp_15[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_result_bits_rawIn_out_isNaN_T_31 = activated_data_e_act_result_bits_rawIn_isSpecial_15 & _activated_data_e_act_result_bits_rawIn_out_isNaN_T_30; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_result_bits_rawIn_15_isNaN = _activated_data_e_act_result_bits_rawIn_out_isNaN_T_31; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_result_bits_rawIn_out_isInf_T_46 = ~_activated_data_e_act_result_bits_rawIn_out_isInf_T_45; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_result_bits_rawIn_out_isInf_T_47 = activated_data_e_act_result_bits_rawIn_isSpecial_15 & _activated_data_e_act_result_bits_rawIn_out_isInf_T_46; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_result_bits_rawIn_15_isInf = _activated_data_e_act_result_bits_rawIn_out_isInf_T_47; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_result_bits_rawIn_out_sign_T_15 = _activated_data_e_act_muladder_15_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_result_bits_rawIn_15_sign = _activated_data_e_act_result_bits_rawIn_out_sign_T_15; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_result_bits_rawIn_out_sExp_T_15 = {1'h0, activated_data_e_act_result_bits_rawIn_exp_15}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_result_bits_rawIn_15_sExp = _activated_data_e_act_result_bits_rawIn_out_sExp_T_15; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_result_bits_rawIn_out_sig_T_60 = ~activated_data_e_act_result_bits_rawIn_isZero_15; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_61 = {1'h0, _activated_data_e_act_result_bits_rawIn_out_sig_T_60}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_result_bits_rawIn_out_sig_T_62 = _activated_data_e_act_muladder_15_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_result_bits_rawIn_out_sig_T_63 = {_activated_data_e_act_result_bits_rawIn_out_sig_T_61, _activated_data_e_act_result_bits_rawIn_out_sig_T_62}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_result_bits_rawIn_15_sig = _activated_data_e_act_result_bits_rawIn_out_sig_T_63; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_result_bits_isSubnormal_15 = $signed(activated_data_e_act_result_bits_rawIn_15_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_result_bits_denormShiftDist_T_30 = activated_data_e_act_result_bits_rawIn_15_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_result_bits_denormShiftDist_T_31 = 6'h1 - {1'h0, _activated_data_e_act_result_bits_denormShiftDist_T_30}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_result_bits_denormShiftDist_15 = _activated_data_e_act_result_bits_denormShiftDist_T_31[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_30 = activated_data_e_act_result_bits_rawIn_15_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_result_bits_denormFract_T_31 = _activated_data_e_act_result_bits_denormFract_T_30 >> activated_data_e_act_result_bits_denormShiftDist_15; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_result_bits_denormFract_15 = _activated_data_e_act_result_bits_denormFract_T_31[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_90 = activated_data_e_act_result_bits_rawIn_15_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_result_bits_expOut_T_91 = {1'h0, _activated_data_e_act_result_bits_expOut_T_90} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_result_bits_expOut_T_92 = _activated_data_e_act_result_bits_expOut_T_91[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_result_bits_expOut_T_93 = activated_data_e_act_result_bits_isSubnormal_15 ? 8'h0 : _activated_data_e_act_result_bits_expOut_T_92; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_result_bits_expOut_T_94 = activated_data_e_act_result_bits_rawIn_15_isNaN | activated_data_e_act_result_bits_rawIn_15_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_result_bits_expOut_T_95 = {8{_activated_data_e_act_result_bits_expOut_T_94}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_result_bits_expOut_15 = _activated_data_e_act_result_bits_expOut_T_93 | _activated_data_e_act_result_bits_expOut_T_95; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_30 = activated_data_e_act_result_bits_rawIn_15_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_result_bits_fractOut_T_31 = activated_data_e_act_result_bits_rawIn_15_isInf ? 23'h0 : _activated_data_e_act_result_bits_fractOut_T_30; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_result_bits_fractOut_15 = activated_data_e_act_result_bits_isSubnormal_15 ? activated_data_e_act_result_bits_denormFract_15 : _activated_data_e_act_result_bits_fractOut_T_31; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_result_bits_hi_15 = {activated_data_e_act_result_bits_rawIn_15_sign, activated_data_e_act_result_bits_expOut_15}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_result_bits_T_27 = {activated_data_e_act_result_bits_hi_15, activated_data_e_act_result_bits_fractOut_15}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_result_19_bits = _activated_data_e_act_result_bits_T_27; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_neg_q_iexp_t_sgn_3 = activated_data_e_act_result_19_bits[31]; // @[Arithmetic.scala:426:26, :432:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_sign_6 = activated_data_e_act_result_19_bits[31]; // @[rawFloatFromFN.scala:44:18] wire _activated_data_e_act_neg_q_iexp_neg_t_T_12 = ~activated_data_e_act_neg_q_iexp_t_sgn_3; // @[Arithmetic.scala:432:27, :433:25] wire [30:0] _activated_data_e_act_neg_q_iexp_neg_t_T_13 = activated_data_e_act_result_19_bits[30:0]; // @[Arithmetic.scala:426:26, :433:39] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_T_14 = {_activated_data_e_act_neg_q_iexp_neg_t_T_12, _activated_data_e_act_neg_q_iexp_neg_t_T_13}; // @[Arithmetic.scala:433:{24,25,39}] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_WIRE_3 = _activated_data_e_act_neg_q_iexp_neg_t_T_14; // @[Arithmetic.scala:433:{24,65}] wire [31:0] _activated_data_e_act_neg_q_iexp_neg_t_T_15; // @[Arithmetic.scala:433:65] wire [31:0] activated_data_e_act_neg_q_iexp_neg_t_3_bits; // @[Arithmetic.scala:433:65] assign _activated_data_e_act_neg_q_iexp_neg_t_T_15 = _activated_data_e_act_neg_q_iexp_neg_t_WIRE_3; // @[Arithmetic.scala:433:65] assign activated_data_e_act_neg_q_iexp_neg_t_3_bits = _activated_data_e_act_neg_q_iexp_neg_t_T_15; // @[Arithmetic.scala:433:65] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_sign_3 = activated_data_e_act_neg_q_iexp_neg_t_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_sign = activated_data_e_act_neg_q_iexp_t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn_3 = activated_data_e_act_neg_q_iexp_neg_t_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3 = activated_data_e_act_neg_q_iexp_neg_t_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_132 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_133 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_134 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_135 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_136 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_137 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_138 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_139 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_140 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_141 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_142 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_143 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_144 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_145 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_146 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_147 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_148 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_149 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_150 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_151 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_152 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_153 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_154 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_155 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_156 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_157 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_158 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_159 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_160 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_161 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_162 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_163 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_164 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_165 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_166 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_167 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_168 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_169 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_170 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_171 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_172 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_173 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_174 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_175 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_3 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3} << activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_3 = {_activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_neg_q_iexp_t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_3 = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_6 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_3 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_isZero = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_T_3 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_3 = &_activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_neg_q_iexp_t_rec_T_26 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_3 & _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_isNaN = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T_3 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isSpecial_3 & activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_isInf = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_sExp = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_14 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_neg_q_iexp_t_rec_rawIn_subnormFract_3 : activated_data_e_act_neg_q_iexp_t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_13, _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_sig = _activated_data_e_act_neg_q_iexp_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_24 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_25 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_neg_q_iexp_t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_neg_q_iexp_t_rec_T_27 = {_activated_data_e_act_neg_q_iexp_t_rec_T_25[2:1], _activated_data_e_act_neg_q_iexp_t_rec_T_25[0] | _activated_data_e_act_neg_q_iexp_t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_neg_q_iexp_t_rec_T_28 = {activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_sign, _activated_data_e_act_neg_q_iexp_t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_neg_q_iexp_t_rec_T_29 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_neg_q_iexp_t_rec_T_30 = {_activated_data_e_act_neg_q_iexp_t_rec_T_28, _activated_data_e_act_neg_q_iexp_t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_neg_q_iexp_t_rec_T_31 = activated_data_e_act_neg_q_iexp_t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_neg_q_iexp_t_rec_3 = {_activated_data_e_act_neg_q_iexp_t_rec_T_30, _activated_data_e_act_neg_q_iexp_t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_neg_q_iexp_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_neg_q_iexp_3_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_3 = _activated_data_e_act_neg_q_iexp_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_T_3 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_3 = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_isZero = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_T_3 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_3 = &_activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_9 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_isNaN = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_11 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_isInf = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T_3 = _activated_data_e_act_neg_q_iexp_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sign = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_neg_q_iexp_result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sExp = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_neg_q_iexp_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_14 = _activated_data_e_act_neg_q_iexp_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_13, _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sig = _activated_data_e_act_neg_q_iexp_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_neg_q_iexp_result_bits_isSubnormal_3 = $signed(activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_6 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_3 = _activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_6 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_7 = _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_6 >> activated_data_e_act_neg_q_iexp_result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_neg_q_iexp_result_bits_denormFract_3 = _activated_data_e_act_neg_q_iexp_result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_18 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_19 = {1'h0, _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_20 = _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_21 = activated_data_e_act_neg_q_iexp_result_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_22 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_isNaN | activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_23 = {8{_activated_data_e_act_neg_q_iexp_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_neg_q_iexp_result_bits_expOut_3 = _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_21 | _activated_data_e_act_neg_q_iexp_result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_6 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_7 = activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_neg_q_iexp_result_bits_fractOut_3 = activated_data_e_act_neg_q_iexp_result_bits_isSubnormal_3 ? activated_data_e_act_neg_q_iexp_result_bits_denormFract_3 : _activated_data_e_act_neg_q_iexp_result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_neg_q_iexp_result_bits_hi_3 = {activated_data_e_act_neg_q_iexp_result_bits_rawIn_3_sign, activated_data_e_act_neg_q_iexp_result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_neg_q_iexp_result_bits_T_3 = {activated_data_e_act_neg_q_iexp_result_bits_hi_3, activated_data_e_act_neg_q_iexp_result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_neg_q_iexp_3_bits = _activated_data_e_act_neg_q_iexp_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_z_iexp_t_rec_rawIn_3_sign = activated_data_e_act_z_iexp_t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_z_iexp_t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_132 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_133 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_134 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_135 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_136 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_137 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_138 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_139 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_140 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_141 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_142 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_143 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_144 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_145 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_146 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_147 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_148 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_149 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_150 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_151 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_152 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_153 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_154 = activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_155 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_156 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_157 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_158 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_159 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_160 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_161 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_162 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_163 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_164 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_165 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_166 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_167 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_168 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_169 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_170 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_171 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_172 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_173 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_174 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_175 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_z_iexp_t_rec_rawIn_normDist_3 = _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_z_iexp_t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3} << activated_data_e_act_z_iexp_t_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_3 = {_activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_z_iexp_t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_z_iexp_t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_3 = _activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_6 = activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_z_iexp_t_rec_rawIn_isZero_3 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_z_iexp_t_rec_rawIn_3_isZero = activated_data_e_act_z_iexp_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_T_3 = activated_data_e_act_z_iexp_t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_3 = &_activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_z_iexp_t_rec_T_26 = activated_data_e_act_z_iexp_t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_z_iexp_t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_z_iexp_t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_z_iexp_t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_3 & _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_z_iexp_t_rec_rawIn_3_isNaN = _activated_data_e_act_z_iexp_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T_3 = activated_data_e_act_z_iexp_t_rec_rawIn_isSpecial_3 & activated_data_e_act_z_iexp_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_z_iexp_t_rec_rawIn_3_isInf = _activated_data_e_act_z_iexp_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_z_iexp_t_rec_rawIn_3_sExp = _activated_data_e_act_z_iexp_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_z_iexp_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_14 = activated_data_e_act_z_iexp_t_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_z_iexp_t_rec_rawIn_subnormFract_3 : activated_data_e_act_z_iexp_t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_13, _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_z_iexp_t_rec_rawIn_3_sig = _activated_data_e_act_z_iexp_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_24 = activated_data_e_act_z_iexp_t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_25 = activated_data_e_act_z_iexp_t_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_z_iexp_t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_z_iexp_t_rec_T_27 = {_activated_data_e_act_z_iexp_t_rec_T_25[2:1], _activated_data_e_act_z_iexp_t_rec_T_25[0] | _activated_data_e_act_z_iexp_t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_z_iexp_t_rec_T_28 = {activated_data_e_act_z_iexp_t_rec_rawIn_3_sign, _activated_data_e_act_z_iexp_t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_z_iexp_t_rec_T_29 = activated_data_e_act_z_iexp_t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_z_iexp_t_rec_T_30 = {_activated_data_e_act_z_iexp_t_rec_T_28, _activated_data_e_act_z_iexp_t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_z_iexp_t_rec_T_31 = activated_data_e_act_z_iexp_t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_z_iexp_t_rec_3 = {_activated_data_e_act_z_iexp_t_rec_T_30, _activated_data_e_act_z_iexp_t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_z_iexp_self_rec_rawIn_sign_3 = activated_data_e_act_neg_q_iexp_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_z_iexp_self_rec_rawIn_3_sign = activated_data_e_act_z_iexp_self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_z_iexp_self_rec_rawIn_expIn_3 = activated_data_e_act_neg_q_iexp_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3 = activated_data_e_act_neg_q_iexp_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_z_iexp_self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_132 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_133 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_134 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_135 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_136 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_137 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_138 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_139 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_140 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_141 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_142 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_143 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_144 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_145 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_146 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_147 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_148 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_149 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_150 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_151 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_152 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_153 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_154 = activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_155 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_156 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_157 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_158 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_159 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_160 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_161 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_162 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_163 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_164 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_165 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_166 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_167 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_168 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_169 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_170 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_171 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_172 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_173 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_174 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_175 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_z_iexp_self_rec_rawIn_normDist_3 = _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_z_iexp_self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3} << activated_data_e_act_z_iexp_self_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_3 = {_activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_z_iexp_self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_z_iexp_self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_3 = _activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_6 = activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_z_iexp_self_rec_rawIn_isZero_3 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_z_iexp_self_rec_rawIn_3_isZero = activated_data_e_act_z_iexp_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_T_3 = activated_data_e_act_z_iexp_self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_3 = &_activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_z_iexp_self_rec_T_26 = activated_data_e_act_z_iexp_self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_z_iexp_self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_z_iexp_self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_z_iexp_self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_3 & _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_z_iexp_self_rec_rawIn_3_isNaN = _activated_data_e_act_z_iexp_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T_3 = activated_data_e_act_z_iexp_self_rec_rawIn_isSpecial_3 & activated_data_e_act_z_iexp_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_z_iexp_self_rec_rawIn_3_isInf = _activated_data_e_act_z_iexp_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_z_iexp_self_rec_rawIn_3_sExp = _activated_data_e_act_z_iexp_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_z_iexp_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_14 = activated_data_e_act_z_iexp_self_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_z_iexp_self_rec_rawIn_subnormFract_3 : activated_data_e_act_z_iexp_self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_13, _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_z_iexp_self_rec_rawIn_3_sig = _activated_data_e_act_z_iexp_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_24 = activated_data_e_act_z_iexp_self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_25 = activated_data_e_act_z_iexp_self_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_z_iexp_self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_z_iexp_self_rec_T_27 = {_activated_data_e_act_z_iexp_self_rec_T_25[2:1], _activated_data_e_act_z_iexp_self_rec_T_25[0] | _activated_data_e_act_z_iexp_self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_z_iexp_self_rec_T_28 = {activated_data_e_act_z_iexp_self_rec_rawIn_3_sign, _activated_data_e_act_z_iexp_self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_z_iexp_self_rec_T_29 = activated_data_e_act_z_iexp_self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_z_iexp_self_rec_T_30 = {_activated_data_e_act_z_iexp_self_rec_T_28, _activated_data_e_act_z_iexp_self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_z_iexp_self_rec_T_31 = activated_data_e_act_z_iexp_self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_z_iexp_self_rec_3 = {_activated_data_e_act_z_iexp_self_rec_T_30, _activated_data_e_act_z_iexp_self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_z_iexp_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_z_iexp_out_3_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_act_z_iexp_out_bits_rawIn_exp_3 = _activated_data_e_act_z_iexp_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_z_iexp_out_bits_rawIn_isZero_T_3 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_z_iexp_out_bits_rawIn_isZero_3 = _activated_data_e_act_z_iexp_out_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_z_iexp_out_bits_rawIn_3_isZero = activated_data_e_act_z_iexp_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_T_3 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_3 = &_activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_z_iexp_out_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_z_iexp_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_z_iexp_out_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_z_iexp_out_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_z_iexp_out_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_9 = activated_data_e_act_z_iexp_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_z_iexp_out_bits_rawIn_3_isNaN = _activated_data_e_act_z_iexp_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_11 = activated_data_e_act_z_iexp_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_z_iexp_out_bits_rawIn_3_isInf = _activated_data_e_act_z_iexp_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T_3 = _activated_data_e_act_z_iexp_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_z_iexp_out_bits_rawIn_3_sign = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_z_iexp_out_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_z_iexp_out_bits_rawIn_3_sExp = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_z_iexp_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_14 = _activated_data_e_act_z_iexp_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_13, _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_z_iexp_out_bits_rawIn_3_sig = _activated_data_e_act_z_iexp_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_z_iexp_out_bits_isSubnormal_3 = $signed(activated_data_e_act_z_iexp_out_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_6 = activated_data_e_act_z_iexp_out_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_z_iexp_out_bits_denormShiftDist_3 = _activated_data_e_act_z_iexp_out_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_z_iexp_out_bits_denormFract_T_6 = activated_data_e_act_z_iexp_out_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_z_iexp_out_bits_denormFract_T_7 = _activated_data_e_act_z_iexp_out_bits_denormFract_T_6 >> activated_data_e_act_z_iexp_out_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_z_iexp_out_bits_denormFract_3 = _activated_data_e_act_z_iexp_out_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_18 = activated_data_e_act_z_iexp_out_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_19 = {1'h0, _activated_data_e_act_z_iexp_out_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_20 = _activated_data_e_act_z_iexp_out_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_21 = activated_data_e_act_z_iexp_out_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_z_iexp_out_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_z_iexp_out_bits_expOut_T_22 = activated_data_e_act_z_iexp_out_bits_rawIn_3_isNaN | activated_data_e_act_z_iexp_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_z_iexp_out_bits_expOut_T_23 = {8{_activated_data_e_act_z_iexp_out_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_z_iexp_out_bits_expOut_3 = _activated_data_e_act_z_iexp_out_bits_expOut_T_21 | _activated_data_e_act_z_iexp_out_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_z_iexp_out_bits_fractOut_T_6 = activated_data_e_act_z_iexp_out_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_z_iexp_out_bits_fractOut_T_7 = activated_data_e_act_z_iexp_out_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_z_iexp_out_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_z_iexp_out_bits_fractOut_3 = activated_data_e_act_z_iexp_out_bits_isSubnormal_3 ? activated_data_e_act_z_iexp_out_bits_denormFract_3 : _activated_data_e_act_z_iexp_out_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_z_iexp_out_bits_hi_3 = {activated_data_e_act_z_iexp_out_bits_rawIn_3_sign, activated_data_e_act_z_iexp_out_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_z_iexp_out_bits_T_3 = {activated_data_e_act_z_iexp_out_bits_hi_3, activated_data_e_act_z_iexp_out_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_z_iexp_out_3_bits = _activated_data_e_act_z_iexp_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [15:0] _activated_data_e_act_z_iexp_T_6 = activated_data_e_act_z_iexp_out_3_bits[31:16]; // @[Arithmetic.scala:350:23] wire [31:0] _activated_data_e_act_z_iexp_T_7; // @[AccumulatorScale.scala:398:67] wire [31:0] activated_data_e_act_z_iexp_3_bits; // @[AccumulatorScale.scala:398:67] assign _activated_data_e_act_z_iexp_T_7 = _activated_data_e_act_z_iexp_WIRE_3; // @[AccumulatorScale.scala:398:67] assign _activated_data_e_act_z_iexp_WIRE_3 = {16'h0, _activated_data_e_act_z_iexp_T_6}; // @[AccumulatorScale.scala:398:{54,67}] assign activated_data_e_act_z_iexp_3_bits = _activated_data_e_act_z_iexp_T_7; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_87_bits; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_3_bits; // @[AccumulatorScale.scala:399:32] wire _activated_data_e_act_z_iexp_saturated_T_66 = activated_data_e_act_z_iexp_3_bits[5]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_67 = activated_data_e_act_z_iexp_3_bits[6]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_68 = activated_data_e_act_z_iexp_3_bits[7]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_69 = activated_data_e_act_z_iexp_3_bits[8]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_70 = activated_data_e_act_z_iexp_3_bits[9]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_71 = activated_data_e_act_z_iexp_3_bits[10]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_72 = activated_data_e_act_z_iexp_3_bits[11]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_73 = activated_data_e_act_z_iexp_3_bits[12]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_74 = activated_data_e_act_z_iexp_3_bits[13]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_75 = activated_data_e_act_z_iexp_3_bits[14]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_76 = activated_data_e_act_z_iexp_3_bits[15]; // @[AccumulatorScale.scala:398:67, :400:59] wire _activated_data_e_act_z_iexp_saturated_T_77 = _activated_data_e_act_z_iexp_saturated_T_66 | _activated_data_e_act_z_iexp_saturated_T_67; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_78 = _activated_data_e_act_z_iexp_saturated_T_77 | _activated_data_e_act_z_iexp_saturated_T_68; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_79 = _activated_data_e_act_z_iexp_saturated_T_78 | _activated_data_e_act_z_iexp_saturated_T_69; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_80 = _activated_data_e_act_z_iexp_saturated_T_79 | _activated_data_e_act_z_iexp_saturated_T_70; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_81 = _activated_data_e_act_z_iexp_saturated_T_80 | _activated_data_e_act_z_iexp_saturated_T_71; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_82 = _activated_data_e_act_z_iexp_saturated_T_81 | _activated_data_e_act_z_iexp_saturated_T_72; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_83 = _activated_data_e_act_z_iexp_saturated_T_82 | _activated_data_e_act_z_iexp_saturated_T_73; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_84 = _activated_data_e_act_z_iexp_saturated_T_83 | _activated_data_e_act_z_iexp_saturated_T_74; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_85 = _activated_data_e_act_z_iexp_saturated_T_84 | _activated_data_e_act_z_iexp_saturated_T_75; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_86 = _activated_data_e_act_z_iexp_saturated_T_85 | _activated_data_e_act_z_iexp_saturated_T_76; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_87_bits = _activated_data_e_act_z_iexp_saturated_T_86 ? 32'h20 : activated_data_e_act_z_iexp_3_bits; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_3_bits = _activated_data_e_act_z_iexp_saturated_T_87_bits; // @[AccumulatorScale.scala:399:32, :400:28] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_sign_3 = activated_data_e_act_z_iexp_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_3_sign = activated_data_e_act_qp_iexp_m1_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn_3 = activated_data_e_act_z_iexp_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3 = activated_data_e_act_z_iexp_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_132 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_133 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_134 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_135 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_136 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_137 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_138 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_139 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_140 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_141 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_142 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_143 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_144 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_145 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_146 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_147 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_148 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_149 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_150 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_151 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_152 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_153 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_154 = activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_155 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_156 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_157 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_158 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_159 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_160 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_161 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_162 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_163 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_164 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_165 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_166 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_167 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_168 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_169 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_170 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_171 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_172 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_173 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_174 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_175 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_3 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3} << activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_3 = {_activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_qp_iexp_m1_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_qp_iexp_m1_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_3 = _activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_6 = activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_3 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_3_isZero = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_T_3 = activated_data_e_act_qp_iexp_m1_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_3 = &_activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_m1_rec_T_26 = activated_data_e_act_qp_iexp_m1_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_m1_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_m1_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_3 & _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_3_isNaN = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T_3 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isSpecial_3 & activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_3_isInf = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_3_sExp = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_qp_iexp_m1_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_14 = activated_data_e_act_qp_iexp_m1_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_qp_iexp_m1_rec_rawIn_subnormFract_3 : activated_data_e_act_qp_iexp_m1_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_13, _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_m1_rec_rawIn_3_sig = _activated_data_e_act_qp_iexp_m1_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_24 = activated_data_e_act_qp_iexp_m1_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_25 = activated_data_e_act_qp_iexp_m1_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_m1_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_m1_rec_T_27 = {_activated_data_e_act_qp_iexp_m1_rec_T_25[2:1], _activated_data_e_act_qp_iexp_m1_rec_T_25[0] | _activated_data_e_act_qp_iexp_m1_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_m1_rec_T_28 = {activated_data_e_act_qp_iexp_m1_rec_rawIn_3_sign, _activated_data_e_act_qp_iexp_m1_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_m1_rec_T_29 = activated_data_e_act_qp_iexp_m1_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_m1_rec_T_30 = {_activated_data_e_act_qp_iexp_m1_rec_T_28, _activated_data_e_act_qp_iexp_m1_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_m1_rec_T_31 = activated_data_e_act_qp_iexp_m1_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_m1_rec_3 = {_activated_data_e_act_qp_iexp_m1_rec_T_30, _activated_data_e_act_qp_iexp_m1_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_3_sign = activated_data_e_act_qp_iexp_m2_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_132 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_133 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_134 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_135 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_136 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_137 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_138 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_139 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_140 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_141 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_142 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_143 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_144 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_145 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_146 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_147 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_148 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_149 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_150 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_151 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_152 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_153 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_154 = activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_155 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_156 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_157 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_158 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_159 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_160 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_161 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_162 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_163 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_164 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_165 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_166 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_167 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_168 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_169 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_170 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_171 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_172 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_173 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_174 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_175 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_3 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3} << activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_3 = {_activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_qp_iexp_m2_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_qp_iexp_m2_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_3 = _activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_6 = activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_3 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_3_isZero = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_T_3 = activated_data_e_act_qp_iexp_m2_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_3 = &_activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_m2_rec_T_26 = activated_data_e_act_qp_iexp_m2_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_m2_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_m2_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_3 & _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_3_isNaN = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T_3 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isSpecial_3 & activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_3_isInf = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_3_sExp = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_qp_iexp_m2_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_14 = activated_data_e_act_qp_iexp_m2_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_qp_iexp_m2_rec_rawIn_subnormFract_3 : activated_data_e_act_qp_iexp_m2_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_13, _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_m2_rec_rawIn_3_sig = _activated_data_e_act_qp_iexp_m2_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_24 = activated_data_e_act_qp_iexp_m2_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_25 = activated_data_e_act_qp_iexp_m2_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_m2_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_m2_rec_T_27 = {_activated_data_e_act_qp_iexp_m2_rec_T_25[2:1], _activated_data_e_act_qp_iexp_m2_rec_T_25[0] | _activated_data_e_act_qp_iexp_m2_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_m2_rec_T_28 = {activated_data_e_act_qp_iexp_m2_rec_rawIn_3_sign, _activated_data_e_act_qp_iexp_m2_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_m2_rec_T_29 = activated_data_e_act_qp_iexp_m2_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_m2_rec_T_30 = {_activated_data_e_act_qp_iexp_m2_rec_T_28, _activated_data_e_act_qp_iexp_m2_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_m2_rec_T_31 = activated_data_e_act_qp_iexp_m2_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_m2_rec_3 = {_activated_data_e_act_qp_iexp_m2_rec_T_30, _activated_data_e_act_qp_iexp_m2_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_qp_iexp_self_rec_rawIn_6_sign = activated_data_e_act_qp_iexp_self_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_6 = activated_data_e_act_result_19_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6 = activated_data_e_act_result_19_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_264 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_265 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_266 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_267 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_268 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_269 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_270 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_271 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_272 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_273 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_274 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_275 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_276 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_277 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_278 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_279 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_280 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_281 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_282 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_283 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_284 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_285 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_286 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_287 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_288 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_289 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_290 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_291 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_292 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_293 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_294 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_295 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_296 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_297 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_298 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_299 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_300 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_301 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_302 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_303 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_304 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_305 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_306 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_307 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_6 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6} << activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_6 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_6 = _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_12 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_6 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_6_isZero = activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_6 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_6 = &_activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_self_rec_T_50 = activated_data_e_act_qp_iexp_self_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_self_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_self_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_6 & _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_6_isNaN = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_6 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_6 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_self_rec_rawIn_6_isInf = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_6_sExp = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_26 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_6 : activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_25, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_6_sig = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_48 = activated_data_e_act_qp_iexp_self_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_49 = activated_data_e_act_qp_iexp_self_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_self_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_51 = {_activated_data_e_act_qp_iexp_self_rec_T_49[2:1], _activated_data_e_act_qp_iexp_self_rec_T_49[0] | _activated_data_e_act_qp_iexp_self_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_self_rec_T_52 = {activated_data_e_act_qp_iexp_self_rec_rawIn_6_sign, _activated_data_e_act_qp_iexp_self_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_self_rec_T_53 = activated_data_e_act_qp_iexp_self_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_T_54 = {_activated_data_e_act_qp_iexp_self_rec_T_52, _activated_data_e_act_qp_iexp_self_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_T_55 = activated_data_e_act_qp_iexp_self_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_self_rec_6 = {_activated_data_e_act_qp_iexp_self_rec_T_54, _activated_data_e_act_qp_iexp_self_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_qp_iexp_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_qp_iexp_out_3_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_qp_iexp_out_bits_rawIn_exp_3 = _activated_data_e_act_qp_iexp_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_T_3 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_3 = _activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_qp_iexp_out_bits_rawIn_3_isZero = activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_T_3 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_3 = &_activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_qp_iexp_out_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_out_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_qp_iexp_out_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_qp_iexp_out_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_9 = activated_data_e_act_qp_iexp_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_3_isNaN = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_11 = activated_data_e_act_qp_iexp_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_3_isInf = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T_3 = _activated_data_e_act_qp_iexp_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_qp_iexp_out_bits_rawIn_3_sign = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_qp_iexp_out_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_qp_iexp_out_bits_rawIn_3_sExp = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_qp_iexp_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_14 = _activated_data_e_act_qp_iexp_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_13, _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_qp_iexp_out_bits_rawIn_3_sig = _activated_data_e_act_qp_iexp_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_qp_iexp_out_bits_isSubnormal_3 = $signed(activated_data_e_act_qp_iexp_out_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_6 = activated_data_e_act_qp_iexp_out_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_qp_iexp_out_bits_denormShiftDist_3 = _activated_data_e_act_qp_iexp_out_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_qp_iexp_out_bits_denormFract_T_6 = activated_data_e_act_qp_iexp_out_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_qp_iexp_out_bits_denormFract_T_7 = _activated_data_e_act_qp_iexp_out_bits_denormFract_T_6 >> activated_data_e_act_qp_iexp_out_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_qp_iexp_out_bits_denormFract_3 = _activated_data_e_act_qp_iexp_out_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_18 = activated_data_e_act_qp_iexp_out_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_19 = {1'h0, _activated_data_e_act_qp_iexp_out_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_20 = _activated_data_e_act_qp_iexp_out_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_21 = activated_data_e_act_qp_iexp_out_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_qp_iexp_out_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_qp_iexp_out_bits_expOut_T_22 = activated_data_e_act_qp_iexp_out_bits_rawIn_3_isNaN | activated_data_e_act_qp_iexp_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_qp_iexp_out_bits_expOut_T_23 = {8{_activated_data_e_act_qp_iexp_out_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_qp_iexp_out_bits_expOut_3 = _activated_data_e_act_qp_iexp_out_bits_expOut_T_21 | _activated_data_e_act_qp_iexp_out_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_fractOut_T_6 = activated_data_e_act_qp_iexp_out_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_qp_iexp_out_bits_fractOut_T_7 = activated_data_e_act_qp_iexp_out_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_qp_iexp_out_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_qp_iexp_out_bits_fractOut_3 = activated_data_e_act_qp_iexp_out_bits_isSubnormal_3 ? activated_data_e_act_qp_iexp_out_bits_denormFract_3 : _activated_data_e_act_qp_iexp_out_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_qp_iexp_out_bits_hi_3 = {activated_data_e_act_qp_iexp_out_bits_rawIn_3_sign, activated_data_e_act_qp_iexp_out_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_qp_iexp_out_bits_T_3 = {activated_data_e_act_qp_iexp_out_bits_hi_3, activated_data_e_act_qp_iexp_out_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_qp_iexp_out_3_bits = _activated_data_e_act_qp_iexp_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_qp_iexp_self_rec_rawIn_sign_7 = activated_data_e_act_qp_iexp_out_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_qp_iexp_self_rec_rawIn_7_sign = activated_data_e_act_qp_iexp_self_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_7 = activated_data_e_act_qp_iexp_out_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7 = activated_data_e_act_qp_iexp_out_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_7 = activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_7 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_308 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_309 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_310 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_311 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_312 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_313 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_314 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_315 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_316 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_317 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_318 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_319 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_320 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_321 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_322 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_323 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_324 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_325 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_326 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_327 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_328 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_329 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_330 = activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_331 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_332 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_333 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_334 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_335 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_336 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_337 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_338 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_339 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_340 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_341 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_342 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_343 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_344 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_345 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_346 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_347 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_348 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_349 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_350 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_351 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_7 = _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7} << activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_15 = _activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_7 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_act_qp_iexp_self_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_36 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_act_qp_iexp_self_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_37 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_7 = _activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_14 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_7 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_7 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_qp_iexp_self_rec_rawIn_7_isZero = activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_7 = activated_data_e_act_qp_iexp_self_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_7 = &_activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_qp_iexp_self_rec_T_58 = activated_data_e_act_qp_iexp_self_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_qp_iexp_self_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_qp_iexp_self_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_qp_iexp_self_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_15 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_7 & _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_7_isNaN = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_7 = activated_data_e_act_qp_iexp_self_rec_rawIn_isSpecial_7 & activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_qp_iexp_self_rec_rawIn_7_isInf = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_7_sExp = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_28 = ~activated_data_e_act_qp_iexp_self_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_30 = activated_data_e_act_qp_iexp_self_rec_rawIn_isZeroExpIn_7 ? activated_data_e_act_qp_iexp_self_rec_rawIn_subnormFract_7 : activated_data_e_act_qp_iexp_self_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_31 = {_activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_29, _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_qp_iexp_self_rec_rawIn_7_sig = _activated_data_e_act_qp_iexp_self_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_56 = activated_data_e_act_qp_iexp_self_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_57 = activated_data_e_act_qp_iexp_self_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_act_qp_iexp_self_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_qp_iexp_self_rec_T_59 = {_activated_data_e_act_qp_iexp_self_rec_T_57[2:1], _activated_data_e_act_qp_iexp_self_rec_T_57[0] | _activated_data_e_act_qp_iexp_self_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_qp_iexp_self_rec_T_60 = {activated_data_e_act_qp_iexp_self_rec_rawIn_7_sign, _activated_data_e_act_qp_iexp_self_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_qp_iexp_self_rec_T_61 = activated_data_e_act_qp_iexp_self_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_qp_iexp_self_rec_T_62 = {_activated_data_e_act_qp_iexp_self_rec_T_60, _activated_data_e_act_qp_iexp_self_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_qp_iexp_self_rec_T_63 = activated_data_e_act_qp_iexp_self_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_qp_iexp_self_rec_7 = {_activated_data_e_act_qp_iexp_self_rec_T_62, _activated_data_e_act_qp_iexp_self_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_qp_iexp_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_qp_iexp_3_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_qp_iexp_result_bits_rawIn_exp_3 = _activated_data_e_act_qp_iexp_resizer_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_T_3 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_3 = _activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_qp_iexp_result_bits_rawIn_3_isZero = activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_T_3 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_3 = &_activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_qp_iexp_result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_qp_iexp_result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_qp_iexp_result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_qp_iexp_result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_9 = activated_data_e_act_qp_iexp_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_3_isNaN = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_11 = activated_data_e_act_qp_iexp_result_bits_rawIn_isSpecial_3 & _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_3_isInf = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T_3 = _activated_data_e_act_qp_iexp_resizer_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_qp_iexp_result_bits_rawIn_3_sign = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_qp_iexp_result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_qp_iexp_result_bits_rawIn_3_sExp = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_qp_iexp_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_14 = _activated_data_e_act_qp_iexp_resizer_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_13, _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_qp_iexp_result_bits_rawIn_3_sig = _activated_data_e_act_qp_iexp_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_qp_iexp_result_bits_isSubnormal_3 = $signed(activated_data_e_act_qp_iexp_result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_6 = activated_data_e_act_qp_iexp_result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_qp_iexp_result_bits_denormShiftDist_3 = _activated_data_e_act_qp_iexp_result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_qp_iexp_result_bits_denormFract_T_6 = activated_data_e_act_qp_iexp_result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_qp_iexp_result_bits_denormFract_T_7 = _activated_data_e_act_qp_iexp_result_bits_denormFract_T_6 >> activated_data_e_act_qp_iexp_result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_qp_iexp_result_bits_denormFract_3 = _activated_data_e_act_qp_iexp_result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_18 = activated_data_e_act_qp_iexp_result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_19 = {1'h0, _activated_data_e_act_qp_iexp_result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_20 = _activated_data_e_act_qp_iexp_result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_21 = activated_data_e_act_qp_iexp_result_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_qp_iexp_result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_qp_iexp_result_bits_expOut_T_22 = activated_data_e_act_qp_iexp_result_bits_rawIn_3_isNaN | activated_data_e_act_qp_iexp_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_qp_iexp_result_bits_expOut_T_23 = {8{_activated_data_e_act_qp_iexp_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_qp_iexp_result_bits_expOut_3 = _activated_data_e_act_qp_iexp_result_bits_expOut_T_21 | _activated_data_e_act_qp_iexp_result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_fractOut_T_6 = activated_data_e_act_qp_iexp_result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_qp_iexp_result_bits_fractOut_T_7 = activated_data_e_act_qp_iexp_result_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_qp_iexp_result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_qp_iexp_result_bits_fractOut_3 = activated_data_e_act_qp_iexp_result_bits_isSubnormal_3 ? activated_data_e_act_qp_iexp_result_bits_denormFract_3 : _activated_data_e_act_qp_iexp_result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_qp_iexp_result_bits_hi_3 = {activated_data_e_act_qp_iexp_result_bits_rawIn_3_sign, activated_data_e_act_qp_iexp_result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_qp_iexp_result_bits_T_3 = {activated_data_e_act_qp_iexp_result_bits_hi_3, activated_data_e_act_qp_iexp_result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_qp_iexp_3_bits = _activated_data_e_act_qp_iexp_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_sign = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_6 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_6 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_264 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_265 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_266 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_267 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_268 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_269 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_270 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_271 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_272 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_273 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_274 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_275 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_276 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_277 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_278 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_279 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_280 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_281 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_282 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_283 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_284 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_285 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_286 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_287 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_288 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_289 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_290 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_291 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_292 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_293 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_294 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_295 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_296 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_297 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_298 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_299 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_300 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_301 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_302 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_303 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_304 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_305 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_306 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_307 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_6 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6} << activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_13 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_6 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_31 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_32 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_6 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_12 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_6 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_6 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_isZero = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_6 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_6 = &_activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_t_rec_T_50 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_13 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_6 & _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_isNaN = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_6 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_6 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_isInf = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_sExp = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_24 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_26 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_6 ? activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_6 : activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_27 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_25, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_sig = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_48 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_49 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_t_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_51 = {_activated_data_e_act_q_poly_iexp_t_rec_T_49[2:1], _activated_data_e_act_q_poly_iexp_t_rec_T_49[0] | _activated_data_e_act_q_poly_iexp_t_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_t_rec_T_52 = {activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_sign, _activated_data_e_act_q_poly_iexp_t_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_t_rec_T_53 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_T_54 = {_activated_data_e_act_q_poly_iexp_t_rec_T_52, _activated_data_e_act_q_poly_iexp_t_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_T_55 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_t_rec_6 = {_activated_data_e_act_q_poly_iexp_t_rec_T_54, _activated_data_e_act_q_poly_iexp_t_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_12 = activated_data_e_act_qp_iexp_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_13 = activated_data_e_act_qp_iexp_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_12; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_12 = activated_data_e_act_qp_iexp_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_13 = activated_data_e_act_qp_iexp_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12 = activated_data_e_act_qp_iexp_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13 = activated_data_e_act_qp_iexp_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_12 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_12 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_12 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_528 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_529 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_530 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_531 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_532 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_533 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_534 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_535 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_536 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_537 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_538 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_539 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_540 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_541 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_542 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_543 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_544 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_545 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_546 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_547 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_548 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_549 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_550 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_551 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_529 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_552 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_530 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_551; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_553 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_531 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_552; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_554 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_532 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_553; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_555 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_533 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_554; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_556 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_534 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_555; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_557 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_535 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_556; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_558 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_536 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_557; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_559 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_537 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_558; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_560 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_538 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_559; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_561 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_539 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_560; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_562 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_540 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_561; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_563 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_541 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_562; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_564 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_542 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_563; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_565 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_543 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_564; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_566 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_544 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_565; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_567 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_545 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_566; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_568 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_546 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_567; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_569 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_547 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_568; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_570 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_548 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_569; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_571 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_549 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_570; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_12 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_550 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_571; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_24 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_12; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_25 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_24[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_12 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_25, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_60 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_12}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_61 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_12 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_60 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_12}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_62 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_12 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_63 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_62}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_64 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_61} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_63}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_12 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_64[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_24 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_12; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_12 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_12 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_12 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_12[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_12 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_12; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_98 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_24 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_25 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_12 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_24; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_12 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_12 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_25 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_24}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_48 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_49 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_48}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_50 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_12 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_12 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_12; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_51 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_49, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_50}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_96 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_97 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_96; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_99 = {_activated_data_e_act_q_poly_iexp_self_rec_T_97[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_97[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_98}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_100 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_99}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_101 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_102 = {_activated_data_e_act_q_poly_iexp_self_rec_T_100, _activated_data_e_act_q_poly_iexp_self_rec_T_101}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_103 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_12_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_12 = {_activated_data_e_act_q_poly_iexp_self_rec_T_102, _activated_data_e_act_q_poly_iexp_self_rec_T_103}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_9; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_result_6_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_9 = _activated_data_e_act_q_poly_iexp_muladder_9_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_9 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_9[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_9 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_9 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_9 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_9[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_9 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_9; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_29; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_9; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_9; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_39; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_18 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_27 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_19 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_9 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_18; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_28 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_27; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_29 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_9 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_28; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_29; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_9 = _activated_data_e_act_q_poly_iexp_muladder_9_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_9; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_9 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_9}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_9; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_36 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_37 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_36}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_38 = _activated_data_e_act_q_poly_iexp_muladder_9_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_39 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_37, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_38}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_39; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_9 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_18 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_19 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_18}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_9 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_19[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_18 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_19 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_18 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_9; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_9 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_19[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_54 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_55 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_54} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_56 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_55[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_57 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_9 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_56; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_58 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_59 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_58}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_9 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_57 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_59; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_18 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_19 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_18; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_9 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_9 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_9 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_19; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_9 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_9_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_9}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_9 = {activated_data_e_act_q_poly_iexp_result_bits_hi_9, activated_data_e_act_q_poly_iexp_result_bits_fractOut_9}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_result_6_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_9; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_sign = activated_data_e_act_q_poly_iexp_t_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_7 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_7 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_308 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_309 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_310 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_311 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_312 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_313 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_314 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_315 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_316 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_317 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_318 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_319 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_320 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_321 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_322 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_323 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_324 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_325 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_326 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_327 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_328 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_329 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_330 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_331 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_332 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_333 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_334 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_335 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_336 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_337 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_338 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_339 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_340 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_341 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_342 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_343 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_344 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_345 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_346 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_347 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_348 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_349 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_350 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_351 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_7 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7} << activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_15 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_7 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_36 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_act_q_poly_iexp_t_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_37 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_7 = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_14 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_7 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_7 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_isZero = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_7 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_7 = &_activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_t_rec_T_58 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_15 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_7 & _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_isNaN = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_7 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isSpecial_7 & activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_isInf = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_sExp = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_28 = ~activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_30 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_isZeroExpIn_7 ? activated_data_e_act_q_poly_iexp_t_rec_rawIn_subnormFract_7 : activated_data_e_act_q_poly_iexp_t_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_31 = {_activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_29, _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_sig = _activated_data_e_act_q_poly_iexp_t_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_56 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_57 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_t_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_t_rec_T_59 = {_activated_data_e_act_q_poly_iexp_t_rec_T_57[2:1], _activated_data_e_act_q_poly_iexp_t_rec_T_57[0] | _activated_data_e_act_q_poly_iexp_t_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_t_rec_T_60 = {activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_sign, _activated_data_e_act_q_poly_iexp_t_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_t_rec_T_61 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_t_rec_T_62 = {_activated_data_e_act_q_poly_iexp_t_rec_T_60, _activated_data_e_act_q_poly_iexp_t_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_t_rec_T_63 = activated_data_e_act_q_poly_iexp_t_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_t_rec_7 = {_activated_data_e_act_q_poly_iexp_t_rec_T_62, _activated_data_e_act_q_poly_iexp_t_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_13; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_13 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_13 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_13 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_572 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_573 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_574 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_575 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_576 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_577 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_578 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_579 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_580 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_581 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_582 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_583 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_584 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_585 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_586 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_587 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_588 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_589 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_590 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_591 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_592 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_593 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_594 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_595 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_573 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_596 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_574 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_595; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_597 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_575 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_596; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_598 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_576 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_597; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_599 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_577 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_598; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_600 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_578 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_599; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_601 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_579 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_600; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_602 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_580 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_601; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_603 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_581 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_602; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_604 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_582 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_603; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_605 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_583 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_604; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_606 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_584 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_605; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_607 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_585 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_606; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_608 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_586 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_607; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_609 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_587 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_608; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_610 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_588 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_609; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_611 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_589 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_610; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_612 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_590 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_611; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_613 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_591 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_612; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_614 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_592 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_613; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_615 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_593 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_614; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_13 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_594 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_615; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_26 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_13; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_27 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_26[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_13 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_27, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_65 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_13}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_66 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_13 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_65 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_13}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_67 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_13 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_68 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_67}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_69 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_66} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_68}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_13 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_69[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_26 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_13; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_13 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_13 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_13 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_13[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_13 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_13; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_106 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_26 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_27 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_13 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_26; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_13 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_13 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_27 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_26}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_52 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_53 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_52}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_54 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_13 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_13 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_13; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_55 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_53, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_54}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_104 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_105 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_104; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_107 = {_activated_data_e_act_q_poly_iexp_self_rec_T_105[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_105[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_106}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_108 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_107}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_109 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_110 = {_activated_data_e_act_q_poly_iexp_self_rec_T_108, _activated_data_e_act_q_poly_iexp_self_rec_T_109}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_111 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_13_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_13 = {_activated_data_e_act_q_poly_iexp_self_rec_T_110, _activated_data_e_act_q_poly_iexp_self_rec_T_111}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_10; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_result_7_bits; // @[Arithmetic.scala:426:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_10 = _activated_data_e_act_q_poly_iexp_muladder_10_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_10 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_10[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_10 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_10 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_10 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_10[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_10 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_10; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_32; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_10; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_10; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_43; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_20 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_30 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_21 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_10 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_20; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_31 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_30; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_32 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_10 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_31; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_32; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_10 = _activated_data_e_act_q_poly_iexp_muladder_10_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_10; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_10 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_10}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_10; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_40 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_40}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_42 = _activated_data_e_act_q_poly_iexp_muladder_10_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_43 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_41, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_42}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_43; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_10 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_20 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_21 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_20}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_10 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_21[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_20 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_21 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_20 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_10; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_10 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_21[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_60 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_61 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_60} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_62 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_61[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_63 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_10 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_62; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_64 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_65 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_64}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_10 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_63 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_65; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_20 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_21 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_20; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_10 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_10 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_10 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_21; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_10 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_10_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_10}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_10 = {activated_data_e_act_q_poly_iexp_result_bits_hi_10, activated_data_e_act_q_poly_iexp_result_bits_fractOut_10}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_result_7_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_10; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sign_3 = activated_data_e_act_q_poly_iexp_result_6_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_sign = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn_3 = activated_data_e_act_q_poly_iexp_result_6_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3 = activated_data_e_act_q_poly_iexp_result_6_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_132 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_133 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_134 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_135 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_136 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_137 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_138 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_139 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_140 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_141 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_142 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_143 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_144 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_145 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_146 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_147 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_148 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_149 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_150 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_151 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_152 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_153 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_154 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_3 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3} << activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_poly_iexp_m1_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_3 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_isZero = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_m1_rec_T_26 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_isNaN = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isSpecial_3 & activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_isInf = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_sExp = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_poly_iexp_m1_rec_rawIn_subnormFract_3 : activated_data_e_act_q_poly_iexp_m1_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_sig = _activated_data_e_act_q_poly_iexp_m1_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_24 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_25 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_m1_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_27 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_25[2:1], _activated_data_e_act_q_poly_iexp_m1_rec_T_25[0] | _activated_data_e_act_q_poly_iexp_m1_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_28 = {activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_sign, _activated_data_e_act_q_poly_iexp_m1_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_29 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_30 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_28, _activated_data_e_act_q_poly_iexp_m1_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_m1_rec_T_31 = activated_data_e_act_q_poly_iexp_m1_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_m1_rec_3 = {_activated_data_e_act_q_poly_iexp_m1_rec_T_30, _activated_data_e_act_q_poly_iexp_m1_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sign_3 = activated_data_e_act_q_poly_iexp_result_7_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_sign = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn_3 = activated_data_e_act_q_poly_iexp_result_7_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3 = activated_data_e_act_q_poly_iexp_result_7_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_3 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_3 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_132 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_133 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_134 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_135 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_136 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_137 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_138 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_139 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_140 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_141 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_142 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_143 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_144 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_145 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_146 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_147 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_148 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_149 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_150 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_151 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_152 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_153 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_154 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_155 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_156 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_157 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_158 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_159 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_160 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_161 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_162 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_163 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_164 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_165 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_166 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_167 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_168 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_169 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_170 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_171 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_172 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_173 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_174 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_175 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_3 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3} << activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_7 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_3 = {_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_16 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_act_q_poly_iexp_m2_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_17 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_3 = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_6 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_3 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_3 & activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_isZero = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_m2_rec_T_26 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_isNaN = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T_3 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isSpecial_3 & activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_isInf = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_sExp = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_14 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_isZeroExpIn_3 ? activated_data_e_act_q_poly_iexp_m2_rec_rawIn_subnormFract_3 : activated_data_e_act_q_poly_iexp_m2_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_sig = _activated_data_e_act_q_poly_iexp_m2_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_24 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_25 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_m2_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_27 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_25[2:1], _activated_data_e_act_q_poly_iexp_m2_rec_T_25[0] | _activated_data_e_act_q_poly_iexp_m2_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_28 = {activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_sign, _activated_data_e_act_q_poly_iexp_m2_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_29 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_30 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_28, _activated_data_e_act_q_poly_iexp_m2_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_m2_rec_T_31 = activated_data_e_act_q_poly_iexp_m2_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_m2_rec_3 = {_activated_data_e_act_q_poly_iexp_m2_rec_T_30, _activated_data_e_act_q_poly_iexp_m2_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_14; // @[rawFloatFromFN.scala:44:18, :63:19] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_14 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_14 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_14 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_616 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_617 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_618 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_619 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_620 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_621 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_622 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_623 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_624 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_625 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_626 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_627 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_628 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_629 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_630 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_631 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_632 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_633 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_634 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_635 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_636 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_637 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_638 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_639 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_617 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_640 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_618 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_639; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_641 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_619 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_640; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_642 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_620 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_641; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_643 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_621 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_642; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_644 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_622 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_643; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_645 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_623 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_644; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_646 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_624 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_645; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_647 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_625 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_646; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_648 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_626 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_647; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_649 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_627 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_648; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_650 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_628 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_649; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_651 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_629 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_650; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_652 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_630 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_651; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_653 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_631 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_652; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_654 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_632 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_653; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_655 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_633 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_654; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_656 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_634 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_655; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_657 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_635 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_656; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_658 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_636 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_657; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_659 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_637 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_658; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_14 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_638 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_659; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_28 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_14; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_29 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_28[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_14 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_29, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_70 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_14}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_71 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_14 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_70 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_14}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_72 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_14 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_73 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_72}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_74 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_71} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_73}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_14 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_74[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_28 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_14; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_14 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_14 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_14 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_14[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_14 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_14; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_114 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_28 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_29 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_14 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_28; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_14 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_14 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_29 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_28}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_56 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_57 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_56}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_58 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_14 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_14 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_14; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_59 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_57, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_58}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_112 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_113 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_112; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_115 = {_activated_data_e_act_q_poly_iexp_self_rec_T_113[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_113[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_114}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_116 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_115}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_117 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_118 = {_activated_data_e_act_q_poly_iexp_self_rec_T_116, _activated_data_e_act_q_poly_iexp_self_rec_T_117}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_119 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_14_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_14 = {_activated_data_e_act_q_poly_iexp_self_rec_T_118, _activated_data_e_act_q_poly_iexp_self_rec_T_119}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_out_3_bits; // @[Arithmetic.scala:387:23] wire [8:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_3 = _activated_data_e_act_q_poly_iexp_muladder_11_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_T_3 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_3 = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_isZero = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_T_3 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_3 = &_activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_6 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_9 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_7 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_isNaN = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_11 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_isSpecial_3 & _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_isInf = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T_3 = _activated_data_e_act_q_poly_iexp_muladder_11_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sign = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_act_q_poly_iexp_out_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sExp = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_12 = ~activated_data_e_act_q_poly_iexp_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_14 = _activated_data_e_act_q_poly_iexp_muladder_11_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_15 = {_activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_13, _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sig = _activated_data_e_act_q_poly_iexp_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_out_bits_isSubnormal_3 = $signed(activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_6 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_3 = _activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_6 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_7 = _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_6 >> activated_data_e_act_q_poly_iexp_out_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_out_bits_denormFract_3 = _activated_data_e_act_q_poly_iexp_out_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_18 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_19 = {1'h0, _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_20 = _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_21 = activated_data_e_act_q_poly_iexp_out_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_22 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_isNaN | activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_23 = {8{_activated_data_e_act_q_poly_iexp_out_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_out_bits_expOut_3 = _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_21 | _activated_data_e_act_q_poly_iexp_out_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_6 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_7 = activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_out_bits_fractOut_3 = activated_data_e_act_q_poly_iexp_out_bits_isSubnormal_3 ? activated_data_e_act_q_poly_iexp_out_bits_denormFract_3 : _activated_data_e_act_q_poly_iexp_out_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_out_bits_hi_3 = {activated_data_e_act_q_poly_iexp_out_bits_rawIn_3_sign, activated_data_e_act_q_poly_iexp_out_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_out_bits_T_3 = {activated_data_e_act_q_poly_iexp_out_bits_hi_3, activated_data_e_act_q_poly_iexp_out_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_out_3_bits = _activated_data_e_act_q_poly_iexp_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_15 = activated_data_e_act_q_poly_iexp_out_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_sign = activated_data_e_act_q_poly_iexp_self_rec_rawIn_sign_15; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_15 = activated_data_e_act_q_poly_iexp_out_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15 = activated_data_e_act_q_poly_iexp_out_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_15 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_15 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_15 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_660 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_661 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_662 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_663 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_664 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_665 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_666 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_667 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_668 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_669 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_670 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_671 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_672 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_673 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_674 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_675 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_676 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_677 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_678 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_679 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_680 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_681 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_682 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_683 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_661 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_684 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_662 ? 5'h14 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_683; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_685 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_663 ? 5'h13 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_684; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_686 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_664 ? 5'h12 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_685; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_687 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_665 ? 5'h11 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_686; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_688 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_666 ? 5'h10 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_687; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_689 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_667 ? 5'hF : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_688; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_690 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_668 ? 5'hE : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_689; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_691 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_669 ? 5'hD : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_690; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_692 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_670 ? 5'hC : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_691; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_693 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_671 ? 5'hB : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_692; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_694 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_672 ? 5'hA : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_693; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_695 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_673 ? 5'h9 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_694; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_696 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_674 ? 5'h8 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_695; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_697 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_675 ? 5'h7 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_696; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_698 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_676 ? 5'h6 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_697; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_699 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_677 ? 5'h5 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_698; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_700 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_678 ? 5'h4 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_699; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_701 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_679 ? 5'h3 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_700; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_702 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_680 ? 5'h2 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_701; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_703 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_681 ? 5'h1 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_702; // @[Mux.scala:50:70] wire [4:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_15 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_682 ? 5'h0 : _activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_T_703; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_30 = {31'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15} << activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_15; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_31 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_30[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_15 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_T_31, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_75 = {4'hF, ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_normDist_15}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_76 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_15 ? _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_75 : {1'h0, activated_data_e_act_q_poly_iexp_self_rec_rawIn_expIn_15}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_77 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_15 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_78 = {6'h20, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_77}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_79 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_76} + {2'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_78}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_15 = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_T_79[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_30 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_15; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_15 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_15 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_isZero = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_15 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_adjustedExp_15[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_15 = &_activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_T_15; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_act_q_poly_iexp_self_rec_T_122 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_30 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_31 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_15 & _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_30; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_isNaN = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_15 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isSpecial_15 & activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_isInf = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_31 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_30}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_sExp = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_60 = ~activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_61 = {1'h0, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_60}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_62 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_isZeroExpIn_15 ? activated_data_e_act_q_poly_iexp_self_rec_rawIn_subnormFract_15 : activated_data_e_act_q_poly_iexp_self_rec_rawIn_fractIn_15; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_63 = {_activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_61, _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_62}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_sig = _activated_data_e_act_q_poly_iexp_self_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_120 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_121 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_isZero ? 3'h0 : _activated_data_e_act_q_poly_iexp_self_rec_T_120; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_act_q_poly_iexp_self_rec_T_123 = {_activated_data_e_act_q_poly_iexp_self_rec_T_121[2:1], _activated_data_e_act_q_poly_iexp_self_rec_T_121[0] | _activated_data_e_act_q_poly_iexp_self_rec_T_122}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_act_q_poly_iexp_self_rec_T_124 = {activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_sign, _activated_data_e_act_q_poly_iexp_self_rec_T_123}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_act_q_poly_iexp_self_rec_T_125 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_act_q_poly_iexp_self_rec_T_126 = {_activated_data_e_act_q_poly_iexp_self_rec_T_124, _activated_data_e_act_q_poly_iexp_self_rec_T_125}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_act_q_poly_iexp_self_rec_T_127 = activated_data_e_act_q_poly_iexp_self_rec_rawIn_15_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_act_q_poly_iexp_self_rec_15 = {_activated_data_e_act_q_poly_iexp_self_rec_T_126, _activated_data_e_act_q_poly_iexp_self_rec_T_127}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_act_q_poly_iexp_result_bits_T_11; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_act_q_poly_iexp_3_bits; // @[Arithmetic.scala:491:26] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_11 = _activated_data_e_act_q_poly_iexp_resizer_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_11 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_11[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_11 = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_T_11 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_isZero = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_11 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_11[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_11 = &_activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_T_11; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_35; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_11; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_11; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_47; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_22 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_33 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_23 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_11 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_22; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_isNaN = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_34 = ~_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_33; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_35 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_isSpecial_11 & _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_34; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_isInf = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_isInf_T_35; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_11 = _activated_data_e_act_q_poly_iexp_resizer_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sign = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sign_T_11; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_11 = {1'h0, activated_data_e_act_q_poly_iexp_result_bits_rawIn_exp_11}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sExp = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sExp_T_11; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_44 = ~activated_data_e_act_q_poly_iexp_result_bits_rawIn_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_45 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_44}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_46 = _activated_data_e_act_q_poly_iexp_resizer_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_47 = {_activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_45, _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_46}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sig = _activated_data_e_act_q_poly_iexp_result_bits_rawIn_out_sig_T_47; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_11 = $signed(activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_22 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_23 = 6'h1 - {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_22}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_11 = _activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_T_23[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_22 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_23 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_22 >> activated_data_e_act_q_poly_iexp_result_bits_denormShiftDist_11; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_denormFract_11 = _activated_data_e_act_q_poly_iexp_result_bits_denormFract_T_23[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_66 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_67 = {1'h0, _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_66} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_68 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_67[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_69 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_11 ? 8'h0 : _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_68; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_70 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_isNaN | activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_71 = {8{_activated_data_e_act_q_poly_iexp_result_bits_expOut_T_70}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_act_q_poly_iexp_result_bits_expOut_11 = _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_69 | _activated_data_e_act_q_poly_iexp_result_bits_expOut_T_71; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_22 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_23 = activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_isInf ? 23'h0 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_22; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_act_q_poly_iexp_result_bits_fractOut_11 = activated_data_e_act_q_poly_iexp_result_bits_isSubnormal_11 ? activated_data_e_act_q_poly_iexp_result_bits_denormFract_11 : _activated_data_e_act_q_poly_iexp_result_bits_fractOut_T_23; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_act_q_poly_iexp_result_bits_hi_11 = {activated_data_e_act_q_poly_iexp_result_bits_rawIn_11_sign, activated_data_e_act_q_poly_iexp_result_bits_expOut_11}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_act_q_poly_iexp_result_bits_T_11 = {activated_data_e_act_q_poly_iexp_result_bits_hi_11, activated_data_e_act_q_poly_iexp_result_bits_fractOut_11}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_act_q_poly_iexp_3_bits = _activated_data_e_act_q_poly_iexp_result_bits_T_11; // @[fNFromRecFN.scala:66:12] wire [31:0] _activated_data_e_act_T_59 = activated_data_e_act_q_poly_iexp_3_bits >> activated_data_e_act_z_iexp_saturated_3_bits; // @[Arithmetic.scala:491:26] wire [31:0] _activated_data_e_act_WIRE_7 = _activated_data_e_act_T_59; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_T_60; // @[AccumulatorScale.scala:405:65] assign _activated_data_e_act_T_60 = _activated_data_e_act_WIRE_7; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_WIRE_6_bits = _activated_data_e_act_T_60; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_62_bits = _activated_data_e_act_T_61_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_63_bits = _activated_data_e_act_T_62_bits; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_3_bits = _activated_data_e_act_T_49 ? activated_data_e_act_result_15_bits : _activated_data_e_act_T_63_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_38_bits = _activated_data_e_scaled_T_37_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_15 = _activated_data_e_scaled_T_38_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_39; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_39 = _activated_data_e_scaled_WIRE_15; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_14_bits = _activated_data_e_scaled_T_39; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_t_rec_rawIn_sign_3 = _activated_data_e_scaled_WIRE_14_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_t_rec_rawIn_3_sign = activated_data_e_scaled_t_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_t_rec_rawIn_expIn_3 = _activated_data_e_scaled_WIRE_14_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_t_rec_rawIn_fractIn_3 = _activated_data_e_scaled_WIRE_14_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_3 = activated_data_e_scaled_t_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_3 = activated_data_e_scaled_t_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_132 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_133 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_134 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_135 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_136 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_137 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_138 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_139 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_140 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_141 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_142 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_143 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_144 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_145 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_146 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_147 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_148 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_149 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_150 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_151 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_152 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_153 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_t_rec_rawIn_normDist_T_154 = activated_data_e_scaled_t_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_155 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_156 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_157 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_158 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_159 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_160 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_161 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_scaled_t_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_162 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_scaled_t_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_163 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_scaled_t_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_164 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_scaled_t_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_165 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_scaled_t_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_166 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_scaled_t_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_167 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_168 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_169 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_170 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_171 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_172 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_173 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_174 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_t_rec_rawIn_normDist_T_175 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_t_rec_rawIn_normDist_3 = _activated_data_e_scaled_t_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_scaled_t_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_t_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_scaled_t_rec_rawIn_fractIn_3} << activated_data_e_scaled_t_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_t_rec_rawIn_subnormFract_T_7 = _activated_data_e_scaled_t_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_t_rec_rawIn_subnormFract_3 = {_activated_data_e_scaled_t_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_scaled_t_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_16 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_scaled_t_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_17 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_scaled_t_rec_rawIn_adjustedExp_3 = _activated_data_e_scaled_t_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_6 = activated_data_e_scaled_t_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_t_rec_rawIn_isZero_3 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_3 & activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_t_rec_rawIn_3_isZero = activated_data_e_scaled_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_isSpecial_T_3 = activated_data_e_scaled_t_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_t_rec_rawIn_isSpecial_3 = &_activated_data_e_scaled_t_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_t_rec_T_26 = activated_data_e_scaled_t_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_t_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_t_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_t_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_7 = activated_data_e_scaled_t_rec_rawIn_isSpecial_3 & _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_t_rec_rawIn_3_isNaN = _activated_data_e_scaled_t_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_t_rec_rawIn_out_isInf_T_3 = activated_data_e_scaled_t_rec_rawIn_isSpecial_3 & activated_data_e_scaled_t_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_t_rec_rawIn_3_isInf = _activated_data_e_scaled_t_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_t_rec_rawIn_3_sExp = _activated_data_e_scaled_t_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_t_rec_rawIn_out_sig_T_12 = ~activated_data_e_scaled_t_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_scaled_t_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_t_rec_rawIn_out_sig_T_14 = activated_data_e_scaled_t_rec_rawIn_isZeroExpIn_3 ? activated_data_e_scaled_t_rec_rawIn_subnormFract_3 : activated_data_e_scaled_t_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_t_rec_rawIn_out_sig_T_15 = {_activated_data_e_scaled_t_rec_rawIn_out_sig_T_13, _activated_data_e_scaled_t_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_t_rec_rawIn_3_sig = _activated_data_e_scaled_t_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_t_rec_T_24 = activated_data_e_scaled_t_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_t_rec_T_25 = activated_data_e_scaled_t_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_scaled_t_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_t_rec_T_27 = {_activated_data_e_scaled_t_rec_T_25[2:1], _activated_data_e_scaled_t_rec_T_25[0] | _activated_data_e_scaled_t_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_t_rec_T_28 = {activated_data_e_scaled_t_rec_rawIn_3_sign, _activated_data_e_scaled_t_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_t_rec_T_29 = activated_data_e_scaled_t_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_t_rec_T_30 = {_activated_data_e_scaled_t_rec_T_28, _activated_data_e_scaled_t_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_t_rec_T_31 = activated_data_e_scaled_t_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_t_rec_3 = {_activated_data_e_scaled_t_rec_T_30, _activated_data_e_scaled_t_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire activated_data_e_scaled_self_rec_rawIn_sign_3 = activated_data_e_act_3_bits[31]; // @[Mux.scala:126:16] wire activated_data_e_scaled_self_rec_rawIn_3_sign = activated_data_e_scaled_self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_self_rec_rawIn_expIn_3 = activated_data_e_act_3_bits[30:23]; // @[Mux.scala:126:16] wire [22:0] activated_data_e_scaled_self_rec_rawIn_fractIn_3 = activated_data_e_act_3_bits[22:0]; // @[Mux.scala:126:16] wire activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_3 = activated_data_e_scaled_self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_3 = activated_data_e_scaled_self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_132 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_133 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_134 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_135 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_136 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_137 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_138 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_139 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_140 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_141 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_142 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_143 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_144 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_145 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_146 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_147 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_148 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_149 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_150 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_151 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_152 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_153 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_self_rec_rawIn_normDist_T_154 = activated_data_e_scaled_self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_155 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_156 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_157 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_158 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_159 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_160 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_161 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_scaled_self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_162 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_scaled_self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_163 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_scaled_self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_164 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_scaled_self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_165 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_scaled_self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_166 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_scaled_self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_167 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_168 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_169 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_170 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_171 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_172 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_173 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_174 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_self_rec_rawIn_normDist_T_175 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_self_rec_rawIn_normDist_3 = _activated_data_e_scaled_self_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_scaled_self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_self_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_scaled_self_rec_rawIn_fractIn_3} << activated_data_e_scaled_self_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_self_rec_rawIn_subnormFract_T_7 = _activated_data_e_scaled_self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_self_rec_rawIn_subnormFract_3 = {_activated_data_e_scaled_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_scaled_self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_16 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_scaled_self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_17 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_scaled_self_rec_rawIn_adjustedExp_3 = _activated_data_e_scaled_self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_6 = activated_data_e_scaled_self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_self_rec_rawIn_isZero_3 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_3 & activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_self_rec_rawIn_3_isZero = activated_data_e_scaled_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_isSpecial_T_3 = activated_data_e_scaled_self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_self_rec_rawIn_isSpecial_3 = &_activated_data_e_scaled_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_self_rec_T_26 = activated_data_e_scaled_self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_7 = activated_data_e_scaled_self_rec_rawIn_isSpecial_3 & _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_self_rec_rawIn_3_isNaN = _activated_data_e_scaled_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_self_rec_rawIn_out_isInf_T_3 = activated_data_e_scaled_self_rec_rawIn_isSpecial_3 & activated_data_e_scaled_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_self_rec_rawIn_3_isInf = _activated_data_e_scaled_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_self_rec_rawIn_3_sExp = _activated_data_e_scaled_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_self_rec_rawIn_out_sig_T_12 = ~activated_data_e_scaled_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_scaled_self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_self_rec_rawIn_out_sig_T_14 = activated_data_e_scaled_self_rec_rawIn_isZeroExpIn_3 ? activated_data_e_scaled_self_rec_rawIn_subnormFract_3 : activated_data_e_scaled_self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_self_rec_rawIn_out_sig_T_15 = {_activated_data_e_scaled_self_rec_rawIn_out_sig_T_13, _activated_data_e_scaled_self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_self_rec_rawIn_3_sig = _activated_data_e_scaled_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_self_rec_T_24 = activated_data_e_scaled_self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_self_rec_T_25 = activated_data_e_scaled_self_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_scaled_self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_self_rec_T_27 = {_activated_data_e_scaled_self_rec_T_25[2:1], _activated_data_e_scaled_self_rec_T_25[0] | _activated_data_e_scaled_self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_self_rec_T_28 = {activated_data_e_scaled_self_rec_rawIn_3_sign, _activated_data_e_scaled_self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_self_rec_T_29 = activated_data_e_scaled_self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_self_rec_T_30 = {_activated_data_e_scaled_self_rec_T_28, _activated_data_e_scaled_self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_self_rec_T_31 = activated_data_e_scaled_self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_self_rec_3 = {_activated_data_e_scaled_self_rec_T_30, _activated_data_e_scaled_self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_scaled_3_bits; // @[Arithmetic.scala:350:23] wire [8:0] activated_data_e_scaled_out_bits_rawIn_exp_3 = _activated_data_e_scaled_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_out_bits_rawIn_isZero_T_3 = activated_data_e_scaled_out_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_out_bits_rawIn_isZero_3 = _activated_data_e_scaled_out_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_out_bits_rawIn_3_isZero = activated_data_e_scaled_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_out_bits_rawIn_isSpecial_T_3 = activated_data_e_scaled_out_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_out_bits_rawIn_isSpecial_3 = &_activated_data_e_scaled_out_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_out_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_out_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_out_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_out_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_6 = activated_data_e_scaled_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_9 = activated_data_e_scaled_out_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_7 = activated_data_e_scaled_out_bits_rawIn_isSpecial_3 & _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_out_bits_rawIn_3_isNaN = _activated_data_e_scaled_out_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_scaled_out_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_11 = activated_data_e_scaled_out_bits_rawIn_isSpecial_3 & _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_out_bits_rawIn_3_isInf = _activated_data_e_scaled_out_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_out_bits_rawIn_out_sign_T_3 = _activated_data_e_scaled_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_out_bits_rawIn_3_sign = _activated_data_e_scaled_out_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_out_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_scaled_out_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_out_bits_rawIn_3_sExp = _activated_data_e_scaled_out_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_out_bits_rawIn_out_sig_T_12 = ~activated_data_e_scaled_out_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_scaled_out_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_out_bits_rawIn_out_sig_T_14 = _activated_data_e_scaled_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_out_bits_rawIn_out_sig_T_15 = {_activated_data_e_scaled_out_bits_rawIn_out_sig_T_13, _activated_data_e_scaled_out_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_out_bits_rawIn_3_sig = _activated_data_e_scaled_out_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_scaled_out_bits_isSubnormal_3 = $signed(activated_data_e_scaled_out_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_scaled_out_bits_denormShiftDist_T_6 = activated_data_e_scaled_out_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_scaled_out_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_scaled_out_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_scaled_out_bits_denormShiftDist_3 = _activated_data_e_scaled_out_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_scaled_out_bits_denormFract_T_6 = activated_data_e_scaled_out_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_scaled_out_bits_denormFract_T_7 = _activated_data_e_scaled_out_bits_denormFract_T_6 >> activated_data_e_scaled_out_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_scaled_out_bits_denormFract_3 = _activated_data_e_scaled_out_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_18 = activated_data_e_scaled_out_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_scaled_out_bits_expOut_T_19 = {1'h0, _activated_data_e_scaled_out_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_20 = _activated_data_e_scaled_out_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_21 = activated_data_e_scaled_out_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_scaled_out_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_scaled_out_bits_expOut_T_22 = activated_data_e_scaled_out_bits_rawIn_3_isNaN | activated_data_e_scaled_out_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_scaled_out_bits_expOut_T_23 = {8{_activated_data_e_scaled_out_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_scaled_out_bits_expOut_3 = _activated_data_e_scaled_out_bits_expOut_T_21 | _activated_data_e_scaled_out_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_scaled_out_bits_fractOut_T_6 = activated_data_e_scaled_out_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_scaled_out_bits_fractOut_T_7 = activated_data_e_scaled_out_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_scaled_out_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_scaled_out_bits_fractOut_3 = activated_data_e_scaled_out_bits_isSubnormal_3 ? activated_data_e_scaled_out_bits_denormFract_3 : _activated_data_e_scaled_out_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_scaled_out_bits_hi_3 = {activated_data_e_scaled_out_bits_rawIn_3_sign, activated_data_e_scaled_out_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_scaled_out_bits_T_3 = {activated_data_e_scaled_out_bits_hi_3, activated_data_e_scaled_out_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_scaled_3_bits = _activated_data_e_scaled_out_bits_T_3; // @[fNFromRecFN.scala:66:12] wire activated_data_e_clipped_self_rec_rawIn_sign_3 = activated_data_e_scaled_3_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_clipped_self_rec_rawIn_3_sign = activated_data_e_clipped_self_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_clipped_self_rec_rawIn_expIn_3 = activated_data_e_scaled_3_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_clipped_self_rec_rawIn_fractIn_3 = activated_data_e_scaled_3_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_3 = activated_data_e_clipped_self_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_3 = activated_data_e_clipped_self_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_132 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_133 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_134 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_135 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_136 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_137 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_138 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_139 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_140 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_141 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_142 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_143 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_144 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_145 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_146 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_147 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_148 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_149 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_150 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_151 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_152 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_153 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_clipped_self_rec_rawIn_normDist_T_154 = activated_data_e_clipped_self_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_155 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_156 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_157 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_158 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_159 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_160 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_161 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_clipped_self_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_162 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_clipped_self_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_163 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_clipped_self_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_164 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_clipped_self_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_165 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_clipped_self_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_166 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_clipped_self_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_167 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_168 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_169 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_170 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_171 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_172 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_173 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_174 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_clipped_self_rec_rawIn_normDist_T_175 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_clipped_self_rec_rawIn_normDist_3 = _activated_data_e_clipped_self_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_clipped_self_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_clipped_self_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_clipped_self_rec_rawIn_fractIn_3} << activated_data_e_clipped_self_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_clipped_self_rec_rawIn_subnormFract_T_7 = _activated_data_e_clipped_self_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_clipped_self_rec_rawIn_subnormFract_3 = {_activated_data_e_clipped_self_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_clipped_self_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_16 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_clipped_self_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_17 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9, :61:32, :70:16] wire [8:0] activated_data_e_clipped_self_rec_rawIn_adjustedExp_3 = _activated_data_e_clipped_self_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_6 = activated_data_e_clipped_self_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_clipped_self_rec_rawIn_isZero_3 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_3 & activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_clipped_self_rec_rawIn_3_isZero = activated_data_e_clipped_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_isSpecial_T_3 = activated_data_e_clipped_self_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_clipped_self_rec_rawIn_isSpecial_3 = &_activated_data_e_clipped_self_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_clipped_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_clipped_self_rec_T_26 = activated_data_e_clipped_self_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_clipped_self_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_clipped_self_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_clipped_self_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_7 = activated_data_e_clipped_self_rec_rawIn_isSpecial_3 & _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_clipped_self_rec_rawIn_3_isNaN = _activated_data_e_clipped_self_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_clipped_self_rec_rawIn_out_isInf_T_3 = activated_data_e_clipped_self_rec_rawIn_isSpecial_3 & activated_data_e_clipped_self_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_clipped_self_rec_rawIn_3_isInf = _activated_data_e_clipped_self_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_clipped_self_rec_rawIn_3_sExp = _activated_data_e_clipped_self_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_clipped_self_rec_rawIn_out_sig_T_12 = ~activated_data_e_clipped_self_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_clipped_self_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_clipped_self_rec_rawIn_out_sig_T_14 = activated_data_e_clipped_self_rec_rawIn_isZeroExpIn_3 ? activated_data_e_clipped_self_rec_rawIn_subnormFract_3 : activated_data_e_clipped_self_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_clipped_self_rec_rawIn_out_sig_T_15 = {_activated_data_e_clipped_self_rec_rawIn_out_sig_T_13, _activated_data_e_clipped_self_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_clipped_self_rec_rawIn_3_sig = _activated_data_e_clipped_self_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_clipped_self_rec_T_24 = activated_data_e_clipped_self_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_clipped_self_rec_T_25 = activated_data_e_clipped_self_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_clipped_self_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_clipped_self_rec_T_27 = {_activated_data_e_clipped_self_rec_T_25[2:1], _activated_data_e_clipped_self_rec_T_25[0] | _activated_data_e_clipped_self_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_clipped_self_rec_T_28 = {activated_data_e_clipped_self_rec_rawIn_3_sign, _activated_data_e_clipped_self_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_clipped_self_rec_T_29 = activated_data_e_clipped_self_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_clipped_self_rec_T_30 = {_activated_data_e_clipped_self_rec_T_28, _activated_data_e_clipped_self_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_clipped_self_rec_T_31 = activated_data_e_clipped_self_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_clipped_self_rec_3 = {_activated_data_e_clipped_self_rec_T_30, _activated_data_e_clipped_self_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_clipped_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_e_clipped_3_bits; // @[Arithmetic.scala:505:26] wire [31:0] _activated_data_WIRE_3_0_bits = activated_data_e_clipped_3_bits; // @[Arithmetic.scala:505:26] wire [8:0] activated_data_e_clipped_result_bits_rawIn_exp_3 = _activated_data_e_clipped_resizer_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_clipped_result_bits_rawIn_isZero_T_3 = activated_data_e_clipped_result_bits_rawIn_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_clipped_result_bits_rawIn_isZero_3 = _activated_data_e_clipped_result_bits_rawIn_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_clipped_result_bits_rawIn_3_isZero = activated_data_e_clipped_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_clipped_result_bits_rawIn_isSpecial_T_3 = activated_data_e_clipped_result_bits_rawIn_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_clipped_result_bits_rawIn_isSpecial_3 = &_activated_data_e_clipped_result_bits_rawIn_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_clipped_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_clipped_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_clipped_result_bits_rawIn_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_clipped_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_clipped_result_bits_rawIn_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_clipped_result_bits_rawIn_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_clipped_result_bits_rawIn_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_6 = activated_data_e_clipped_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_9 = activated_data_e_clipped_result_bits_rawIn_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_7 = activated_data_e_clipped_result_bits_rawIn_isSpecial_3 & _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_clipped_result_bits_rawIn_3_isNaN = _activated_data_e_clipped_result_bits_rawIn_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_10 = ~_activated_data_e_clipped_result_bits_rawIn_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_11 = activated_data_e_clipped_result_bits_rawIn_isSpecial_3 & _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_clipped_result_bits_rawIn_3_isInf = _activated_data_e_clipped_result_bits_rawIn_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_clipped_result_bits_rawIn_out_sign_T_3 = _activated_data_e_clipped_resizer_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_clipped_result_bits_rawIn_3_sign = _activated_data_e_clipped_result_bits_rawIn_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_clipped_result_bits_rawIn_out_sExp_T_3 = {1'h0, activated_data_e_clipped_result_bits_rawIn_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_clipped_result_bits_rawIn_3_sExp = _activated_data_e_clipped_result_bits_rawIn_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_clipped_result_bits_rawIn_out_sig_T_12 = ~activated_data_e_clipped_result_bits_rawIn_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_clipped_result_bits_rawIn_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_clipped_result_bits_rawIn_out_sig_T_14 = _activated_data_e_clipped_resizer_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_clipped_result_bits_rawIn_out_sig_T_15 = {_activated_data_e_clipped_result_bits_rawIn_out_sig_T_13, _activated_data_e_clipped_result_bits_rawIn_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_clipped_result_bits_rawIn_3_sig = _activated_data_e_clipped_result_bits_rawIn_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire activated_data_e_clipped_result_bits_isSubnormal_3 = $signed(activated_data_e_clipped_result_bits_rawIn_3_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _activated_data_e_clipped_result_bits_denormShiftDist_T_6 = activated_data_e_clipped_result_bits_rawIn_3_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _activated_data_e_clipped_result_bits_denormShiftDist_T_7 = 6'h1 - {1'h0, _activated_data_e_clipped_result_bits_denormShiftDist_T_6}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] activated_data_e_clipped_result_bits_denormShiftDist_3 = _activated_data_e_clipped_result_bits_denormShiftDist_T_7[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _activated_data_e_clipped_result_bits_denormFract_T_6 = activated_data_e_clipped_result_bits_rawIn_3_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _activated_data_e_clipped_result_bits_denormFract_T_7 = _activated_data_e_clipped_result_bits_denormFract_T_6 >> activated_data_e_clipped_result_bits_denormShiftDist_3; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] activated_data_e_clipped_result_bits_denormFract_3 = _activated_data_e_clipped_result_bits_denormFract_T_7[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_18 = activated_data_e_clipped_result_bits_rawIn_3_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _activated_data_e_clipped_result_bits_expOut_T_19 = {1'h0, _activated_data_e_clipped_result_bits_expOut_T_18} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_20 = _activated_data_e_clipped_result_bits_expOut_T_19[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_21 = activated_data_e_clipped_result_bits_isSubnormal_3 ? 8'h0 : _activated_data_e_clipped_result_bits_expOut_T_20; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _activated_data_e_clipped_result_bits_expOut_T_22 = activated_data_e_clipped_result_bits_rawIn_3_isNaN | activated_data_e_clipped_result_bits_rawIn_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _activated_data_e_clipped_result_bits_expOut_T_23 = {8{_activated_data_e_clipped_result_bits_expOut_T_22}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] activated_data_e_clipped_result_bits_expOut_3 = _activated_data_e_clipped_result_bits_expOut_T_21 | _activated_data_e_clipped_result_bits_expOut_T_23; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _activated_data_e_clipped_result_bits_fractOut_T_6 = activated_data_e_clipped_result_bits_rawIn_3_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _activated_data_e_clipped_result_bits_fractOut_T_7 = activated_data_e_clipped_result_bits_rawIn_3_isInf ? 23'h0 : _activated_data_e_clipped_result_bits_fractOut_T_6; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] activated_data_e_clipped_result_bits_fractOut_3 = activated_data_e_clipped_result_bits_isSubnormal_3 ? activated_data_e_clipped_result_bits_denormFract_3 : _activated_data_e_clipped_result_bits_fractOut_T_7; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] activated_data_e_clipped_result_bits_hi_3 = {activated_data_e_clipped_result_bits_rawIn_3_sign, activated_data_e_clipped_result_bits_expOut_3}; // @[rawFloatFromRecFN.scala:55:23] assign _activated_data_e_clipped_result_bits_T_3 = {activated_data_e_clipped_result_bits_hi_3, activated_data_e_clipped_result_bits_fractOut_3}; // @[fNFromRecFN.scala:62:16, :66:12] assign activated_data_e_clipped_3_bits = _activated_data_e_clipped_result_bits_T_3; // @[fNFromRecFN.scala:66:12] wire [31:0] activated_data_3_0_bits = _activated_data_WIRE_3_0_bits; // @[AccumulatorScale.scala:116:{33,55}] wire [31:0] in_bits_resp_data_0_0_bits = activated_data_0_0_bits; // @[AccumulatorScale.scala:116:33, :139:18] wire [31:0] in_bits_resp_data_1_0_bits = activated_data_1_0_bits; // @[AccumulatorScale.scala:116:33, :139:18] wire [31:0] in_bits_resp_data_2_0_bits = activated_data_2_0_bits; // @[AccumulatorScale.scala:116:33, :139:18] wire [31:0] in_bits_resp_data_3_0_bits = activated_data_3_0_bits; // @[AccumulatorScale.scala:116:33, :139:18] assign io_in_ready_0 = in_ready; // @[AccumulatorScale.scala:88:7, :139:18] INToRecFN_i1_e8_s24 activated_data_e_act_in_to_rec_fn (); // @[Arithmetic.scala:400:34] RecFNToRecFN_12 activated_data_e_act_t_resizer (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24 activated_data_e_act_muladder ( // @[Arithmetic.scala:416:30] .io_c (activated_data_e_act_self_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_13 activated_data_e_act_q_sign_t_resizer ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_sign_t_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_sign_t_resizer_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_4 activated_data_e_act_q_sign_comparator ( // @[Arithmetic.scala:475:32] .io_b (_activated_data_e_act_q_sign_t_resizer_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_sign_comparator_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_1 activated_data_e_act_q_sign_in_to_rec_fn (); // @[Arithmetic.scala:400:34] RecFNToRecFN_14 activated_data_e_act_q_sign_t_resizer_1 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_1 activated_data_e_act_q_sign_muladder (); // @[Arithmetic.scala:416:30] RecFNToRecFN_15 activated_data_e_act_q_abs_t_resizer ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_abs_t_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_abs_t_resizer_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_5 activated_data_e_act_q_abs_comparator ( // @[Arithmetic.scala:475:32] .io_b (_activated_data_e_act_q_abs_t_resizer_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_abs_comparator_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_2 activated_data_e_act_q_abs_in_to_rec_fn (); // @[Arithmetic.scala:400:34] RecFNToRecFN_16 activated_data_e_act_q_abs_t_resizer_1 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_abs_t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_abs_t_resizer_1_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_2 activated_data_e_act_q_abs_muladder ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_abs_t_resizer_1_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_abs_muladder_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_3 activated_data_e_act_q_clipped_in_to_rec_fn (); // @[Arithmetic.scala:400:34] RecFNToRecFN_17 activated_data_e_act_q_clipped_t_resizer ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_clipped_t_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_3 activated_data_e_act_q_clipped_muladder ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_clipped_t_resizer_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_clipped_muladder_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_18 activated_data_e_act_q_clipped_t_resizer_1 ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_clipped_t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_1_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_6 activated_data_e_act_q_clipped_comparator ( // @[Arithmetic.scala:475:32] .io_a (activated_data_e_act_q_clipped_self_rec_1), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_q_clipped_t_resizer_1_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_clipped_comparator_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_4 activated_data_e_act_q_clipped_in_to_rec_fn_1 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_19 activated_data_e_act_q_clipped_t_resizer_2 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_clipped_t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_2_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_4 activated_data_e_act_q_clipped_muladder_1 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_clipped_t_resizer_2_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_clipped_muladder_1_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_5 activated_data_e_act_q_poly_in_to_rec_fn (); // @[Arithmetic.scala:400:34] RecFNToRecFN_20 activated_data_e_act_q_poly_t_resizer ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_t_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_t_resizer_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_5 activated_data_e_act_q_poly_muladder ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_t_resizer_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_self_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_6 activated_data_e_act_q_poly_in_to_rec_fn_1 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_21 activated_data_e_act_q_poly_t_resizer_1 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_t_resizer_1_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_6 activated_data_e_act_q_poly_muladder_1 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_t_resizer_1_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_self_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_1_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_22 activated_data_e_act_q_poly_m1_resizer ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_q_poly_m1_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_m1_resizer_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_23 activated_data_e_act_q_poly_m2_resizer ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_q_poly_m2_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_m2_resizer_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_7 activated_data_e_act_q_poly_muladder_2 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_q_poly_m1_resizer_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_q_poly_m2_resizer_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_q_poly_self_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_2_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_24 activated_data_e_act_q_poly_resizer ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_poly_self_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_resizer_io_out) ); // @[Arithmetic.scala:486:29] RecFNToRecFN_25 activated_data_e_act_q_erf_t_resizer ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_q_erf_t_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_erf_t_resizer_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_8 activated_data_e_act_q_erf_muladder ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_q_erf_self_rec), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_q_erf_t_resizer_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_q_erf_muladder_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_26 activated_data_e_act_q_erf_resizer ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_erf_self_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_erf_resizer_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_7 activated_data_e_act_in_to_rec_fn_1 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_27 activated_data_e_act_t_resizer_1 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_t_resizer_1_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_8 activated_data_e_act_muladder_1 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_t_resizer_1_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_self_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_1_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_28 activated_data_e_act_t_resizer_2 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_t_resizer_2_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_9 activated_data_e_act_muladder_2 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_self_rec_2), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_t_resizer_2_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_muladder_2_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_29 activated_data_e_act_resizer ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_self_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_resizer_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_8 activated_data_e_act_in_to_rec_fn_2 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_30 activated_data_e_act_t_resizer_3 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_9 activated_data_e_act_muladder_3 ( // @[Arithmetic.scala:416:30] .io_c (activated_data_e_act_self_rec_4), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_3_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_9 activated_data_e_act_neg_q_iexp_in_to_rec_fn (); // @[Arithmetic.scala:400:34] RecFNToRecFN_31 activated_data_e_act_neg_q_iexp_t_resizer ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_neg_q_iexp_t_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_neg_q_iexp_t_resizer_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_10 activated_data_e_act_neg_q_iexp_muladder ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_neg_q_iexp_t_resizer_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_neg_q_iexp_muladder_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_32 activated_data_e_act_z_iexp_t_resizer ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_z_iexp_t_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_z_iexp_t_resizer_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_10 activated_data_e_act_z_iexp_muladder ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_z_iexp_self_rec), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_z_iexp_t_resizer_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_z_iexp_muladder_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_33 activated_data_e_act_qp_iexp_m1_resizer ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_qp_iexp_m1_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_m1_resizer_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_34 activated_data_e_act_qp_iexp_m2_resizer ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_qp_iexp_m2_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_m2_resizer_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_11 activated_data_e_act_qp_iexp_muladder ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_qp_iexp_m1_resizer_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_qp_iexp_m2_resizer_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_qp_iexp_self_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_muladder_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_35 activated_data_e_act_qp_iexp_resizer ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_qp_iexp_self_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_resizer_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_10 activated_data_e_act_q_poly_iexp_in_to_rec_fn (); // @[Arithmetic.scala:400:34] RecFNToRecFN_36 activated_data_e_act_q_poly_iexp_t_resizer ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_iexp_t_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_t_resizer_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_12 activated_data_e_act_q_poly_iexp_muladder ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_iexp_t_resizer_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_iexp_self_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_11 activated_data_e_act_q_poly_iexp_in_to_rec_fn_1 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_37 activated_data_e_act_q_poly_iexp_t_resizer_1 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_iexp_t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_t_resizer_1_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_13 activated_data_e_act_q_poly_iexp_muladder_1 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_iexp_t_resizer_1_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_iexp_self_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_1_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_38 activated_data_e_act_q_poly_iexp_m1_resizer ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_q_poly_iexp_m1_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_m1_resizer_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_39 activated_data_e_act_q_poly_iexp_m2_resizer ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_q_poly_iexp_m2_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_m2_resizer_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_14 activated_data_e_act_q_poly_iexp_muladder_2 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_q_poly_iexp_m1_resizer_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_q_poly_iexp_m2_resizer_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_q_poly_iexp_self_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_2_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_40 activated_data_e_act_q_poly_iexp_resizer ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_poly_iexp_self_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_resizer_io_out) ); // @[Arithmetic.scala:486:29] RecFNToRecFN_41 activated_data_e_scaled_t_resizer ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_scaled_t_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_t_resizer_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_11 activated_data_e_scaled_muladder ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_scaled_self_rec), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_scaled_t_resizer_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_scaled_muladder_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_42 activated_data_e_clipped_resizer ( // @[Arithmetic.scala:500:29] .io_in (activated_data_e_clipped_self_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_clipped_resizer_io_out) ); // @[Arithmetic.scala:500:29] INToRecFN_i1_e8_s24_12 activated_data_e_act_in_to_rec_fn_3 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_43 activated_data_e_act_t_resizer_4 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_15 activated_data_e_act_muladder_4 ( // @[Arithmetic.scala:416:30] .io_c (activated_data_e_act_self_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_4_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_44 activated_data_e_act_q_sign_t_resizer_2 ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_sign_t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_sign_t_resizer_2_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_7 activated_data_e_act_q_sign_comparator_1 ( // @[Arithmetic.scala:475:32] .io_b (_activated_data_e_act_q_sign_t_resizer_2_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_sign_comparator_1_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_13 activated_data_e_act_q_sign_in_to_rec_fn_1 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_45 activated_data_e_act_q_sign_t_resizer_3 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_16 activated_data_e_act_q_sign_muladder_1 (); // @[Arithmetic.scala:416:30] RecFNToRecFN_46 activated_data_e_act_q_abs_t_resizer_2 ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_abs_t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_abs_t_resizer_2_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_8 activated_data_e_act_q_abs_comparator_1 ( // @[Arithmetic.scala:475:32] .io_b (_activated_data_e_act_q_abs_t_resizer_2_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_abs_comparator_1_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_14 activated_data_e_act_q_abs_in_to_rec_fn_1 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_47 activated_data_e_act_q_abs_t_resizer_3 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_abs_t_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_abs_t_resizer_3_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_17 activated_data_e_act_q_abs_muladder_1 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_abs_t_resizer_3_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_abs_muladder_1_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_15 activated_data_e_act_q_clipped_in_to_rec_fn_2 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_48 activated_data_e_act_q_clipped_t_resizer_3 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_clipped_t_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_3_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_18 activated_data_e_act_q_clipped_muladder_2 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_clipped_t_resizer_3_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_clipped_muladder_2_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_49 activated_data_e_act_q_clipped_t_resizer_4 ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_clipped_t_rec_4), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_4_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_9 activated_data_e_act_q_clipped_comparator_1 ( // @[Arithmetic.scala:475:32] .io_a (activated_data_e_act_q_clipped_self_rec_4), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_q_clipped_t_resizer_4_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_clipped_comparator_1_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_16 activated_data_e_act_q_clipped_in_to_rec_fn_3 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_50 activated_data_e_act_q_clipped_t_resizer_5 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_clipped_t_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_5_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_19 activated_data_e_act_q_clipped_muladder_3 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_clipped_t_resizer_5_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_clipped_muladder_3_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_17 activated_data_e_act_q_poly_in_to_rec_fn_2 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_51 activated_data_e_act_q_poly_t_resizer_2 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_t_resizer_2_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_20 activated_data_e_act_q_poly_muladder_3 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_t_resizer_2_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_self_rec_4), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_3_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_18 activated_data_e_act_q_poly_in_to_rec_fn_3 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_52 activated_data_e_act_q_poly_t_resizer_3 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_t_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_t_resizer_3_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_21 activated_data_e_act_q_poly_muladder_4 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_t_resizer_3_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_self_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_4_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_53 activated_data_e_act_q_poly_m1_resizer_1 ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_q_poly_m1_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_m1_resizer_1_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_54 activated_data_e_act_q_poly_m2_resizer_1 ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_q_poly_m2_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_m2_resizer_1_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_22 activated_data_e_act_q_poly_muladder_5 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_q_poly_m1_resizer_1_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_q_poly_m2_resizer_1_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_q_poly_self_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_5_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_55 activated_data_e_act_q_poly_resizer_1 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_poly_self_rec_7), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_resizer_1_io_out) ); // @[Arithmetic.scala:486:29] RecFNToRecFN_56 activated_data_e_act_q_erf_t_resizer_1 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_q_erf_t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_erf_t_resizer_1_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_12 activated_data_e_act_q_erf_muladder_1 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_q_erf_self_rec_2), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_q_erf_t_resizer_1_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_q_erf_muladder_1_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_57 activated_data_e_act_q_erf_resizer_1 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_erf_self_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_erf_resizer_1_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_19 activated_data_e_act_in_to_rec_fn_4 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_58 activated_data_e_act_t_resizer_5 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_t_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_t_resizer_5_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_23 activated_data_e_act_muladder_5 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_t_resizer_5_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_self_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_5_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_59 activated_data_e_act_t_resizer_6 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_t_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_t_resizer_6_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_13 activated_data_e_act_muladder_6 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_self_rec_7), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_t_resizer_6_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_muladder_6_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_60 activated_data_e_act_resizer_1 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_self_rec_8), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_resizer_1_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_20 activated_data_e_act_in_to_rec_fn_5 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_61 activated_data_e_act_t_resizer_7 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_24 activated_data_e_act_muladder_7 ( // @[Arithmetic.scala:416:30] .io_c (activated_data_e_act_self_rec_9), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_7_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_21 activated_data_e_act_neg_q_iexp_in_to_rec_fn_1 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_62 activated_data_e_act_neg_q_iexp_t_resizer_1 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_neg_q_iexp_t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_neg_q_iexp_t_resizer_1_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_25 activated_data_e_act_neg_q_iexp_muladder_1 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_neg_q_iexp_t_resizer_1_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_neg_q_iexp_muladder_1_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_63 activated_data_e_act_z_iexp_t_resizer_1 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_z_iexp_t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_z_iexp_t_resizer_1_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_14 activated_data_e_act_z_iexp_muladder_1 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_z_iexp_self_rec_1), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_z_iexp_t_resizer_1_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_z_iexp_muladder_1_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_64 activated_data_e_act_qp_iexp_m1_resizer_1 ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_qp_iexp_m1_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_m1_resizer_1_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_65 activated_data_e_act_qp_iexp_m2_resizer_1 ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_qp_iexp_m2_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_m2_resizer_1_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_26 activated_data_e_act_qp_iexp_muladder_1 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_qp_iexp_m1_resizer_1_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_qp_iexp_m2_resizer_1_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_qp_iexp_self_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_muladder_1_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_66 activated_data_e_act_qp_iexp_resizer_1 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_qp_iexp_self_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_resizer_1_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_22 activated_data_e_act_q_poly_iexp_in_to_rec_fn_2 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_67 activated_data_e_act_q_poly_iexp_t_resizer_2 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_iexp_t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_t_resizer_2_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_27 activated_data_e_act_q_poly_iexp_muladder_3 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_iexp_t_resizer_2_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_iexp_self_rec_4), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_3_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_23 activated_data_e_act_q_poly_iexp_in_to_rec_fn_3 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_68 activated_data_e_act_q_poly_iexp_t_resizer_3 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_iexp_t_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_t_resizer_3_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_28 activated_data_e_act_q_poly_iexp_muladder_4 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_iexp_t_resizer_3_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_iexp_self_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_4_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_69 activated_data_e_act_q_poly_iexp_m1_resizer_1 ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_q_poly_iexp_m1_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_m1_resizer_1_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_70 activated_data_e_act_q_poly_iexp_m2_resizer_1 ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_q_poly_iexp_m2_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_m2_resizer_1_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_29 activated_data_e_act_q_poly_iexp_muladder_5 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_q_poly_iexp_m1_resizer_1_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_q_poly_iexp_m2_resizer_1_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_q_poly_iexp_self_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_5_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_71 activated_data_e_act_q_poly_iexp_resizer_1 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_poly_iexp_self_rec_7), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_resizer_1_io_out) ); // @[Arithmetic.scala:486:29] RecFNToRecFN_72 activated_data_e_scaled_t_resizer_1 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_scaled_t_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_t_resizer_1_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_15 activated_data_e_scaled_muladder_1 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_scaled_self_rec_1), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_scaled_t_resizer_1_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_scaled_muladder_1_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_73 activated_data_e_clipped_resizer_1 ( // @[Arithmetic.scala:500:29] .io_in (activated_data_e_clipped_self_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_clipped_resizer_1_io_out) ); // @[Arithmetic.scala:500:29] INToRecFN_i1_e8_s24_24 activated_data_e_act_in_to_rec_fn_6 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_74 activated_data_e_act_t_resizer_8 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_30 activated_data_e_act_muladder_8 ( // @[Arithmetic.scala:416:30] .io_c (activated_data_e_act_self_rec_10), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_8_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_75 activated_data_e_act_q_sign_t_resizer_4 ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_sign_t_rec_4), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_sign_t_resizer_4_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_10 activated_data_e_act_q_sign_comparator_2 ( // @[Arithmetic.scala:475:32] .io_b (_activated_data_e_act_q_sign_t_resizer_4_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_sign_comparator_2_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_25 activated_data_e_act_q_sign_in_to_rec_fn_2 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_76 activated_data_e_act_q_sign_t_resizer_5 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_31 activated_data_e_act_q_sign_muladder_2 (); // @[Arithmetic.scala:416:30] RecFNToRecFN_77 activated_data_e_act_q_abs_t_resizer_4 ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_abs_t_rec_4), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_abs_t_resizer_4_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_11 activated_data_e_act_q_abs_comparator_2 ( // @[Arithmetic.scala:475:32] .io_b (_activated_data_e_act_q_abs_t_resizer_4_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_abs_comparator_2_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_26 activated_data_e_act_q_abs_in_to_rec_fn_2 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_78 activated_data_e_act_q_abs_t_resizer_5 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_abs_t_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_abs_t_resizer_5_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_32 activated_data_e_act_q_abs_muladder_2 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_abs_t_resizer_5_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_abs_muladder_2_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_27 activated_data_e_act_q_clipped_in_to_rec_fn_4 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_79 activated_data_e_act_q_clipped_t_resizer_6 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_clipped_t_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_6_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_33 activated_data_e_act_q_clipped_muladder_4 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_clipped_t_resizer_6_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_clipped_muladder_4_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_80 activated_data_e_act_q_clipped_t_resizer_7 ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_clipped_t_rec_7), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_7_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_12 activated_data_e_act_q_clipped_comparator_2 ( // @[Arithmetic.scala:475:32] .io_a (activated_data_e_act_q_clipped_self_rec_7), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_q_clipped_t_resizer_7_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_clipped_comparator_2_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_28 activated_data_e_act_q_clipped_in_to_rec_fn_5 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_81 activated_data_e_act_q_clipped_t_resizer_8 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_clipped_t_rec_8), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_8_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_34 activated_data_e_act_q_clipped_muladder_5 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_clipped_t_resizer_8_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_clipped_muladder_5_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_29 activated_data_e_act_q_poly_in_to_rec_fn_4 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_82 activated_data_e_act_q_poly_t_resizer_4 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_t_rec_4), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_t_resizer_4_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_35 activated_data_e_act_q_poly_muladder_6 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_t_resizer_4_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_self_rec_8), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_6_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_30 activated_data_e_act_q_poly_in_to_rec_fn_5 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_83 activated_data_e_act_q_poly_t_resizer_5 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_t_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_t_resizer_5_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_36 activated_data_e_act_q_poly_muladder_7 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_t_resizer_5_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_self_rec_9), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_7_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_84 activated_data_e_act_q_poly_m1_resizer_2 ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_q_poly_m1_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_m1_resizer_2_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_85 activated_data_e_act_q_poly_m2_resizer_2 ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_q_poly_m2_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_m2_resizer_2_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_37 activated_data_e_act_q_poly_muladder_8 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_q_poly_m1_resizer_2_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_q_poly_m2_resizer_2_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_q_poly_self_rec_10), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_8_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_86 activated_data_e_act_q_poly_resizer_2 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_poly_self_rec_11), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_resizer_2_io_out) ); // @[Arithmetic.scala:486:29] RecFNToRecFN_87 activated_data_e_act_q_erf_t_resizer_2 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_q_erf_t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_erf_t_resizer_2_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_16 activated_data_e_act_q_erf_muladder_2 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_q_erf_self_rec_4), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_q_erf_t_resizer_2_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_q_erf_muladder_2_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_88 activated_data_e_act_q_erf_resizer_2 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_erf_self_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_erf_resizer_2_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_31 activated_data_e_act_in_to_rec_fn_7 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_89 activated_data_e_act_t_resizer_9 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_t_rec_9), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_t_resizer_9_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_38 activated_data_e_act_muladder_9 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_t_resizer_9_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_self_rec_11), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_9_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_90 activated_data_e_act_t_resizer_10 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_t_rec_10), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_t_resizer_10_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_17 activated_data_e_act_muladder_10 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_self_rec_12), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_t_resizer_10_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_muladder_10_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_91 activated_data_e_act_resizer_2 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_self_rec_13), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_resizer_2_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_32 activated_data_e_act_in_to_rec_fn_8 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_92 activated_data_e_act_t_resizer_11 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_39 activated_data_e_act_muladder_11 ( // @[Arithmetic.scala:416:30] .io_c (activated_data_e_act_self_rec_14), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_11_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_33 activated_data_e_act_neg_q_iexp_in_to_rec_fn_2 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_93 activated_data_e_act_neg_q_iexp_t_resizer_2 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_neg_q_iexp_t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_neg_q_iexp_t_resizer_2_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_40 activated_data_e_act_neg_q_iexp_muladder_2 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_neg_q_iexp_t_resizer_2_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_neg_q_iexp_muladder_2_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_94 activated_data_e_act_z_iexp_t_resizer_2 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_z_iexp_t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_z_iexp_t_resizer_2_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_18 activated_data_e_act_z_iexp_muladder_2 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_z_iexp_self_rec_2), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_z_iexp_t_resizer_2_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_z_iexp_muladder_2_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_95 activated_data_e_act_qp_iexp_m1_resizer_2 ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_qp_iexp_m1_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_m1_resizer_2_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_96 activated_data_e_act_qp_iexp_m2_resizer_2 ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_qp_iexp_m2_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_m2_resizer_2_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_41 activated_data_e_act_qp_iexp_muladder_2 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_qp_iexp_m1_resizer_2_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_qp_iexp_m2_resizer_2_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_qp_iexp_self_rec_4), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_muladder_2_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_97 activated_data_e_act_qp_iexp_resizer_2 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_qp_iexp_self_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_resizer_2_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_34 activated_data_e_act_q_poly_iexp_in_to_rec_fn_4 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_98 activated_data_e_act_q_poly_iexp_t_resizer_4 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_iexp_t_rec_4), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_t_resizer_4_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_42 activated_data_e_act_q_poly_iexp_muladder_6 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_iexp_t_resizer_4_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_iexp_self_rec_8), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_6_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_35 activated_data_e_act_q_poly_iexp_in_to_rec_fn_5 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_99 activated_data_e_act_q_poly_iexp_t_resizer_5 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_iexp_t_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_t_resizer_5_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_43 activated_data_e_act_q_poly_iexp_muladder_7 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_iexp_t_resizer_5_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_iexp_self_rec_9), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_7_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_100 activated_data_e_act_q_poly_iexp_m1_resizer_2 ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_q_poly_iexp_m1_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_m1_resizer_2_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_101 activated_data_e_act_q_poly_iexp_m2_resizer_2 ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_q_poly_iexp_m2_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_m2_resizer_2_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_44 activated_data_e_act_q_poly_iexp_muladder_8 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_q_poly_iexp_m1_resizer_2_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_q_poly_iexp_m2_resizer_2_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_q_poly_iexp_self_rec_10), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_8_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_102 activated_data_e_act_q_poly_iexp_resizer_2 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_poly_iexp_self_rec_11), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_resizer_2_io_out) ); // @[Arithmetic.scala:486:29] RecFNToRecFN_103 activated_data_e_scaled_t_resizer_2 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_scaled_t_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_t_resizer_2_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_19 activated_data_e_scaled_muladder_2 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_scaled_self_rec_2), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_scaled_t_resizer_2_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_scaled_muladder_2_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_104 activated_data_e_clipped_resizer_2 ( // @[Arithmetic.scala:500:29] .io_in (activated_data_e_clipped_self_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_clipped_resizer_2_io_out) ); // @[Arithmetic.scala:500:29] INToRecFN_i1_e8_s24_36 activated_data_e_act_in_to_rec_fn_9 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_105 activated_data_e_act_t_resizer_12 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_45 activated_data_e_act_muladder_12 ( // @[Arithmetic.scala:416:30] .io_c (activated_data_e_act_self_rec_15), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_12_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_106 activated_data_e_act_q_sign_t_resizer_6 ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_sign_t_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_sign_t_resizer_6_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_13 activated_data_e_act_q_sign_comparator_3 ( // @[Arithmetic.scala:475:32] .io_b (_activated_data_e_act_q_sign_t_resizer_6_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_sign_comparator_3_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_37 activated_data_e_act_q_sign_in_to_rec_fn_3 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_107 activated_data_e_act_q_sign_t_resizer_7 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_46 activated_data_e_act_q_sign_muladder_3 (); // @[Arithmetic.scala:416:30] RecFNToRecFN_108 activated_data_e_act_q_abs_t_resizer_6 ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_abs_t_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_abs_t_resizer_6_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_14 activated_data_e_act_q_abs_comparator_3 ( // @[Arithmetic.scala:475:32] .io_b (_activated_data_e_act_q_abs_t_resizer_6_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_abs_comparator_3_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_38 activated_data_e_act_q_abs_in_to_rec_fn_3 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_109 activated_data_e_act_q_abs_t_resizer_7 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_abs_t_rec_7), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_abs_t_resizer_7_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_47 activated_data_e_act_q_abs_muladder_3 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_abs_t_resizer_7_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_abs_muladder_3_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_39 activated_data_e_act_q_clipped_in_to_rec_fn_6 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_110 activated_data_e_act_q_clipped_t_resizer_9 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_clipped_t_rec_9), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_9_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_48 activated_data_e_act_q_clipped_muladder_6 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_clipped_t_resizer_9_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_clipped_muladder_6_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_111 activated_data_e_act_q_clipped_t_resizer_10 ( // @[Arithmetic.scala:469:31] .io_in (activated_data_e_act_q_clipped_t_rec_10), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_10_io_out) ); // @[Arithmetic.scala:469:31] CompareRecFN_15 activated_data_e_act_q_clipped_comparator_3 ( // @[Arithmetic.scala:475:32] .io_a (activated_data_e_act_q_clipped_self_rec_10), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_q_clipped_t_resizer_10_io_out), // @[Arithmetic.scala:469:31] .io_gt (_activated_data_e_act_q_clipped_comparator_3_io_gt) ); // @[Arithmetic.scala:475:32] INToRecFN_i1_e8_s24_40 activated_data_e_act_q_clipped_in_to_rec_fn_7 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_112 activated_data_e_act_q_clipped_t_resizer_11 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_clipped_t_rec_11), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_clipped_t_resizer_11_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_49 activated_data_e_act_q_clipped_muladder_7 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_clipped_t_resizer_11_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_q_clipped_muladder_7_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_41 activated_data_e_act_q_poly_in_to_rec_fn_6 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_113 activated_data_e_act_q_poly_t_resizer_6 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_t_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_t_resizer_6_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_50 activated_data_e_act_q_poly_muladder_9 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_t_resizer_6_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_self_rec_12), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_9_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_42 activated_data_e_act_q_poly_in_to_rec_fn_7 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_114 activated_data_e_act_q_poly_t_resizer_7 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_t_rec_7), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_t_resizer_7_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_51 activated_data_e_act_q_poly_muladder_10 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_t_resizer_7_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_self_rec_13), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_10_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_115 activated_data_e_act_q_poly_m1_resizer_3 ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_q_poly_m1_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_m1_resizer_3_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_116 activated_data_e_act_q_poly_m2_resizer_3 ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_q_poly_m2_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_m2_resizer_3_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_52 activated_data_e_act_q_poly_muladder_11 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_q_poly_m1_resizer_3_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_q_poly_m2_resizer_3_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_q_poly_self_rec_14), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_muladder_11_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_117 activated_data_e_act_q_poly_resizer_3 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_poly_self_rec_15), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_resizer_3_io_out) ); // @[Arithmetic.scala:486:29] RecFNToRecFN_118 activated_data_e_act_q_erf_t_resizer_3 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_q_erf_t_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_erf_t_resizer_3_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_20 activated_data_e_act_q_erf_muladder_3 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_q_erf_self_rec_6), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_q_erf_t_resizer_3_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_q_erf_muladder_3_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_119 activated_data_e_act_q_erf_resizer_3 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_erf_self_rec_7), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_erf_resizer_3_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_43 activated_data_e_act_in_to_rec_fn_10 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_120 activated_data_e_act_t_resizer_13 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_t_rec_13), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_t_resizer_13_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_53 activated_data_e_act_muladder_13 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_t_resizer_13_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_self_rec_16), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_13_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_121 activated_data_e_act_t_resizer_14 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_t_rec_14), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_t_resizer_14_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_21 activated_data_e_act_muladder_14 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_self_rec_17), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_t_resizer_14_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_muladder_14_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_122 activated_data_e_act_resizer_3 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_self_rec_18), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_resizer_3_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_44 activated_data_e_act_in_to_rec_fn_11 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_123 activated_data_e_act_t_resizer_15 (); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_54 activated_data_e_act_muladder_15 ( // @[Arithmetic.scala:416:30] .io_c (activated_data_e_act_self_rec_19), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_muladder_15_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_45 activated_data_e_act_neg_q_iexp_in_to_rec_fn_3 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_124 activated_data_e_act_neg_q_iexp_t_resizer_3 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_neg_q_iexp_t_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_neg_q_iexp_t_resizer_3_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_55 activated_data_e_act_neg_q_iexp_muladder_3 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_neg_q_iexp_t_resizer_3_io_out), // @[Arithmetic.scala:409:31] .io_out (_activated_data_e_act_neg_q_iexp_muladder_3_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_125 activated_data_e_act_z_iexp_t_resizer_3 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_act_z_iexp_t_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_z_iexp_t_resizer_3_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_22 activated_data_e_act_z_iexp_muladder_3 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_act_z_iexp_self_rec_3), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_act_z_iexp_t_resizer_3_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_act_z_iexp_muladder_3_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_126 activated_data_e_act_qp_iexp_m1_resizer_3 ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_qp_iexp_m1_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_m1_resizer_3_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_127 activated_data_e_act_qp_iexp_m2_resizer_3 ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_qp_iexp_m2_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_m2_resizer_3_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_56 activated_data_e_act_qp_iexp_muladder_3 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_qp_iexp_m1_resizer_3_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_qp_iexp_m2_resizer_3_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_qp_iexp_self_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_muladder_3_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_128 activated_data_e_act_qp_iexp_resizer_3 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_qp_iexp_self_rec_7), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_qp_iexp_resizer_3_io_out) ); // @[Arithmetic.scala:486:29] INToRecFN_i1_e8_s24_46 activated_data_e_act_q_poly_iexp_in_to_rec_fn_6 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_129 activated_data_e_act_q_poly_iexp_t_resizer_6 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_iexp_t_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_t_resizer_6_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_57 activated_data_e_act_q_poly_iexp_muladder_9 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_iexp_t_resizer_6_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_iexp_self_rec_12), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_9_io_out) ); // @[Arithmetic.scala:416:30] INToRecFN_i1_e8_s24_47 activated_data_e_act_q_poly_iexp_in_to_rec_fn_7 (); // @[Arithmetic.scala:400:34] RecFNToRecFN_130 activated_data_e_act_q_poly_iexp_t_resizer_7 ( // @[Arithmetic.scala:409:31] .io_in (activated_data_e_act_q_poly_iexp_t_rec_7), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_t_resizer_7_io_out) ); // @[Arithmetic.scala:409:31] MulAddRecFN_e8_s24_58 activated_data_e_act_q_poly_iexp_muladder_10 ( // @[Arithmetic.scala:416:30] .io_a (_activated_data_e_act_q_poly_iexp_t_resizer_7_io_out), // @[Arithmetic.scala:409:31] .io_c (activated_data_e_act_q_poly_iexp_self_rec_13), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_10_io_out) ); // @[Arithmetic.scala:416:30] RecFNToRecFN_131 activated_data_e_act_q_poly_iexp_m1_resizer_3 ( // @[Arithmetic.scala:362:32] .io_in (activated_data_e_act_q_poly_iexp_m1_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_m1_resizer_3_io_out) ); // @[Arithmetic.scala:362:32] RecFNToRecFN_132 activated_data_e_act_q_poly_iexp_m2_resizer_3 ( // @[Arithmetic.scala:369:32] .io_in (activated_data_e_act_q_poly_iexp_m2_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_m2_resizer_3_io_out) ); // @[Arithmetic.scala:369:32] MulAddRecFN_e8_s24_59 activated_data_e_act_q_poly_iexp_muladder_11 ( // @[Arithmetic.scala:376:30] .io_a (_activated_data_e_act_q_poly_iexp_m1_resizer_3_io_out), // @[Arithmetic.scala:362:32] .io_b (_activated_data_e_act_q_poly_iexp_m2_resizer_3_io_out), // @[Arithmetic.scala:369:32] .io_c (activated_data_e_act_q_poly_iexp_self_rec_14), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_muladder_11_io_out) ); // @[Arithmetic.scala:376:30] RecFNToRecFN_133 activated_data_e_act_q_poly_iexp_resizer_3 ( // @[Arithmetic.scala:486:29] .io_in (activated_data_e_act_q_poly_iexp_self_rec_15), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_act_q_poly_iexp_resizer_3_io_out) ); // @[Arithmetic.scala:486:29] RecFNToRecFN_134 activated_data_e_scaled_t_resizer_3 ( // @[Arithmetic.scala:336:32] .io_in (activated_data_e_scaled_t_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_t_resizer_3_io_out) ); // @[Arithmetic.scala:336:32] MulRecFN_23 activated_data_e_scaled_muladder_3 ( // @[Arithmetic.scala:342:30] .io_a (activated_data_e_scaled_self_rec_3), // @[recFNFromFN.scala:50:41] .io_b (_activated_data_e_scaled_t_resizer_3_io_out), // @[Arithmetic.scala:336:32] .io_out (_activated_data_e_scaled_muladder_3_io_out) ); // @[Arithmetic.scala:342:30] RecFNToRecFN_135 activated_data_e_clipped_resizer_3 ( // @[Arithmetic.scala:500:29] .io_in (activated_data_e_clipped_self_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_clipped_resizer_3_io_out) ); // @[Arithmetic.scala:500:29] Pipeline_10 pipe_out_p ( // @[Pipeline.scala:75:19] .clock (clock), .reset (reset), .io_in_ready (in_ready), .io_in_valid (in_valid), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_0_0_bits (in_bits_resp_data_0_0_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_1_0_bits (in_bits_resp_data_1_0_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_2_0_bits (in_bits_resp_data_2_0_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_3_0_bits (in_bits_resp_data_3_0_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_fromDMA (in_bits_resp_fromDMA), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_scale_bits (in_bits_resp_scale_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_igelu_qb_bits (in_bits_resp_igelu_qb_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_igelu_qc_bits (in_bits_resp_igelu_qc_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_iexp_qln2_bits (in_bits_resp_iexp_qln2_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_iexp_qln2_inv_bits (in_bits_resp_iexp_qln2_inv_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_act (in_bits_resp_act), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_acc_bank_id (in_bits_resp_acc_bank_id), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_0_0_bits (in_bits_full_data_0_0_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_1_0_bits (in_bits_full_data_1_0_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_2_0_bits (in_bits_full_data_2_0_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_3_0_bits (in_bits_full_data_3_0_bits), // @[AccumulatorScale.scala:139:18] .io_out_ready (out_ready), // @[AccumulatorScale.scala:104:17] .io_out_valid (out_valid), .io_out_bits_resp_data_0_0_bits (out_bits_data_0_0_bits), .io_out_bits_resp_data_1_0_bits (out_bits_data_1_0_bits), .io_out_bits_resp_data_2_0_bits (out_bits_data_2_0_bits), .io_out_bits_resp_data_3_0_bits (out_bits_data_3_0_bits), .io_out_bits_resp_fromDMA (out_bits_fromDMA), .io_out_bits_resp_acc_bank_id (out_bits_acc_bank_id), .io_out_bits_full_data_0_0_bits (out_bits_full_data_0_0_bits), .io_out_bits_full_data_1_0_bits (out_bits_full_data_1_0_bits), .io_out_bits_full_data_2_0_bits (out_bits_full_data_2_0_bits), .io_out_bits_full_data_3_0_bits (out_bits_full_data_3_0_bits) ); // @[Pipeline.scala:75:19] assign io_in_ready = io_in_ready_0; // @[AccumulatorScale.scala:88:7] assign io_out_valid = io_out_valid_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_0_0_bits = io_out_bits_full_data_0_0_bits_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_1_0_bits = io_out_bits_full_data_1_0_bits_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_2_0_bits = io_out_bits_full_data_2_0_bits_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_3_0_bits = io_out_bits_full_data_3_0_bits_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_0_0_bits = io_out_bits_data_0_0_bits_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_1_0_bits = io_out_bits_data_1_0_bits_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_2_0_bits = io_out_bits_data_2_0_bits_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_3_0_bits = io_out_bits_data_3_0_bits_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_acc_bank_id = io_out_bits_acc_bank_id_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_fromDMA = io_out_bits_fromDMA_0; // @[AccumulatorScale.scala:88:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w4_d3_i0_35( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_319 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_320 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_321 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_322 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_50( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }
module IntSyncCrossingSource_n1x2_2( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] input auto_in_1, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_1 // @[LazyModuleImp.scala:107:25] ); wire [1:0] _reg_io_q; // @[AsyncResetReg.scala:86:21] wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire auto_in_1_0 = auto_in_1; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeIn_1 = auto_in_1_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire nodeOut_sync_1; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] wire auto_out_sync_1_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9] assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21] AsyncResetRegVec_w2_i0_2 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d ({nodeIn_1, nodeIn_0}), // @[Crossing.scala:45:36] .io_q (_reg_io_q) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundRawFNToRecFN_e5_s11_7( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_7 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File fpu.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ package boom.v3.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile.FPConstants._ import freechips.rocketchip.tile.{FPUCtrlSigs, HasFPUParameters} import freechips.rocketchip.tile import freechips.rocketchip.rocket import freechips.rocketchip.util.uintToBitPat import boom.v3.common._ import boom.v3.util.{ImmGenRm, ImmGenTyp} /** * FP Decoder for the FPU * * TODO get rid of this decoder and move into the Decode stage? Or the RRd stage? * most of these signals are already created, just need to be translated * to the Rocket FPU-speak */ class UOPCodeFPUDecoder(implicit p: Parameters) extends BoomModule with HasFPUParameters { val io = IO(new Bundle { val uopc = Input(Bits(UOPC_SZ.W)) val sigs = Output(new FPUCtrlSigs()) }) // TODO change N,Y,X to BitPat("b1"), BitPat("b0"), and BitPat("b?") val N = false.B val Y = true.B val X = false.B val default: List[BitPat] = List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X) val f_table: Array[(BitPat, List[BitPat])] = // Note: not all of these signals are used or necessary, but we're // constrained by the need to fit the rocket.FPU units' ctrl signals. // swap12 fma // | swap32 | div // | | typeTagIn | | sqrt // ldst | | | typeTagOut | | wflags // | wen | | | | from_int | | | // | | ren1 | | | | | to_int | | | // | | | ren2 | | | | | | fastpipe | // | | | | ren3 | | | | | | | | | | // | | | | | | | | | | | | | | | | Array( BitPat(uopFCLASS_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N), BitPat(uopFMV_W_X) -> List(X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N), BitPat(uopFMV_X_W) -> List(X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N), BitPat(uopFCVT_S_X) -> List(X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y), BitPat(uopFCVT_X_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y), BitPat(uopCMPR_S) -> List(X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y), BitPat(uopFSGNJ_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N), BitPat(uopFMINMAX_S)-> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y), BitPat(uopFADD_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), BitPat(uopFSUB_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y), BitPat(uopFMUL_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFNMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y), BitPat(uopFNMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y) ) val d_table: Array[(BitPat, List[BitPat])] = Array( BitPat(uopFCLASS_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), BitPat(uopFMV_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N), BitPat(uopFMV_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N), BitPat(uopFCVT_S_D) -> List(X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y), BitPat(uopFCVT_D_S) -> List(X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y), BitPat(uopFCVT_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y), BitPat(uopFCVT_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y), BitPat(uopCMPR_D) -> List(X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y), BitPat(uopFSGNJ_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N), BitPat(uopFMINMAX_D)-> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y), BitPat(uopFADD_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), BitPat(uopFSUB_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y), BitPat(uopFMUL_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFNMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y), BitPat(uopFNMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y) ) // val insns = fLen match { // case 32 => f_table // case 64 => f_table ++ d_table // } val insns = f_table ++ d_table val decoder = rocket.DecodeLogic(io.uopc, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags) sigs zip decoder map {case(s,d) => s := d} s.vec := false.B } /** * FP fused multiple add decoder for the FPU */ class FMADecoder extends Module { val io = IO(new Bundle { val uopc = Input(UInt(UOPC_SZ.W)) val cmd = Output(UInt(2.W)) }) val default: List[BitPat] = List(BitPat("b??")) val table: Array[(BitPat, List[BitPat])] = Array( BitPat(uopFADD_S) -> List(BitPat("b00")), BitPat(uopFSUB_S) -> List(BitPat("b01")), BitPat(uopFMUL_S) -> List(BitPat("b00")), BitPat(uopFMADD_S) -> List(BitPat("b00")), BitPat(uopFMSUB_S) -> List(BitPat("b01")), BitPat(uopFNMADD_S) -> List(BitPat("b11")), BitPat(uopFNMSUB_S) -> List(BitPat("b10")), BitPat(uopFADD_D) -> List(BitPat("b00")), BitPat(uopFSUB_D) -> List(BitPat("b01")), BitPat(uopFMUL_D) -> List(BitPat("b00")), BitPat(uopFMADD_D) -> List(BitPat("b00")), BitPat(uopFMSUB_D) -> List(BitPat("b01")), BitPat(uopFNMADD_D) -> List(BitPat("b11")), BitPat(uopFNMSUB_D) -> List(BitPat("b10")) ) val decoder = rocket.DecodeLogic(io.uopc, default, table) val (cmd: UInt) :: Nil = decoder io.cmd := cmd } /** * Bundle representing data to be sent to the FPU */ class FpuReq()(implicit p: Parameters) extends BoomBundle { val uop = new MicroOp() val rs1_data = Bits(65.W) val rs2_data = Bits(65.W) val rs3_data = Bits(65.W) val fcsr_rm = Bits(tile.FPConstants.RM_SZ.W) } /** * FPU unit that wraps the RocketChip FPU units (which in turn wrap hardfloat) */ class FPU(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters { val io = IO(new Bundle { val req = Flipped(new ValidIO(new FpuReq)) val resp = new ValidIO(new ExeUnitResp(65)) }) io.resp.bits := DontCare // all FP units are padded out to the same latency for easy scheduling of the write port val fpu_latency = dfmaLatency val io_req = io.req.bits val fp_decoder = Module(new UOPCodeFPUDecoder) fp_decoder.io.uopc := io_req.uop.uopc val fp_ctrl = fp_decoder.io.sigs val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io_req.fcsr_rm, ImmGenRm(io_req.uop.imm_packed)) def fuInput(minT: Option[tile.FType]): tile.FPInput = { val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, minT) req.in2 := unbox(io_req.rs2_data, tag, minT) req.in3 := unbox(io_req.rs3_data, tag, minT) when (fp_ctrl.swap23) { req.in3 := req.in2 } req.typ := ImmGenTyp(io_req.uop.imm_packed) req.fmt := Mux(tag === S, 0.U, 1.U) // TODO support Zfh and avoid special-case below when (io_req.uop.uopc === uopFMV_X_W) { req.fmt := 0.U } val fma_decoder = Module(new FMADecoder) fma_decoder.io.uopc := io_req.uop.uopc req.fmaCmd := fma_decoder.io.cmd // ex_reg_inst(3,2) | (!fp_ctrl.ren3 && ex_reg_inst(27)) req } val dfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.D)) dfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === D) dfma.io.in.bits := fuInput(Some(dfma.t)) val sfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.S)) sfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === S) sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new tile.FPToInt) fpiu.io.in.valid := io.req.valid && (fp_ctrl.toint || (fp_ctrl.fastpipe && fp_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) val fpiu_out = Pipe(RegNext(fpiu.io.in.valid && !fp_ctrl.fastpipe), fpiu.io.out.bits, fpu_latency-1) val fpiu_result = Wire(new tile.FPResult) fpiu_result.data := fpiu_out.bits.toint fpiu_result.exc := fpiu_out.bits.exc val fpmu = Module(new tile.FPToFP(fpu_latency)) // latency 2 for rocket fpmu.io.in.valid := io.req.valid && fp_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val fpmu_double = Pipe(io.req.valid && fp_ctrl.fastpipe, fp_ctrl.typeTagOut === D, fpu_latency).bits // Response (all FP units have been padded out to the same latency) io.resp.valid := fpiu_out.valid || fpmu.io.out.valid || sfma.io.out.valid || dfma.io.out.valid val fpu_out_data = Mux(dfma.io.out.valid, box(dfma.io.out.bits.data, true.B), Mux(sfma.io.out.valid, box(sfma.io.out.bits.data, false.B), Mux(fpiu_out.valid, fpiu_result.data, box(fpmu.io.out.bits.data, fpmu_double)))) val fpu_out_exc = Mux(dfma.io.out.valid, dfma.io.out.bits.exc, Mux(sfma.io.out.valid, sfma.io.out.bits.exc, Mux(fpiu_out.valid, fpiu_result.exc, fpmu.io.out.bits.exc))) io.resp.bits.data := fpu_out_data io.resp.bits.fflags.valid := io.resp.valid io.resp.bits.fflags.bits.flags := fpu_out_exc }
module UOPCodeFPUDecoder_1( // @[fpu.scala:27:7] input clock, // @[fpu.scala:27:7] input reset, // @[fpu.scala:27:7] input [6:0] io_uopc, // @[fpu.scala:29:14] output io_sigs_ldst, // @[fpu.scala:29:14] output io_sigs_wen, // @[fpu.scala:29:14] output io_sigs_ren1, // @[fpu.scala:29:14] output io_sigs_ren2, // @[fpu.scala:29:14] output io_sigs_ren3, // @[fpu.scala:29:14] output io_sigs_swap12, // @[fpu.scala:29:14] output io_sigs_swap23, // @[fpu.scala:29:14] output [1:0] io_sigs_typeTagIn, // @[fpu.scala:29:14] output [1:0] io_sigs_typeTagOut, // @[fpu.scala:29:14] output io_sigs_fromint, // @[fpu.scala:29:14] output io_sigs_toint, // @[fpu.scala:29:14] output io_sigs_fastpipe, // @[fpu.scala:29:14] output io_sigs_fma, // @[fpu.scala:29:14] output io_sigs_div, // @[fpu.scala:29:14] output io_sigs_sqrt, // @[fpu.scala:29:14] output io_sigs_wflags // @[fpu.scala:29:14] ); wire [6:0] io_uopc_0 = io_uopc; // @[fpu.scala:27:7] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = 2'h0; // @[pla.scala:102:36] wire io_sigs_vec = 1'h0; // @[fpu.scala:27:7] wire [6:0] decoder_decoded_plaInput = io_uopc_0; // @[pla.scala:77:22] wire decoder_0; // @[Decode.scala:50:77] wire decoder_1; // @[Decode.scala:50:77] wire decoder_2; // @[Decode.scala:50:77] wire decoder_3; // @[Decode.scala:50:77] wire decoder_4; // @[Decode.scala:50:77] wire decoder_5; // @[Decode.scala:50:77] wire decoder_6; // @[Decode.scala:50:77] wire decoder_9; // @[Decode.scala:50:77] wire decoder_10; // @[Decode.scala:50:77] wire decoder_11; // @[Decode.scala:50:77] wire decoder_12; // @[Decode.scala:50:77] wire decoder_13; // @[Decode.scala:50:77] wire decoder_14; // @[Decode.scala:50:77] wire decoder_15; // @[Decode.scala:50:77] wire io_sigs_ldst_0; // @[fpu.scala:27:7] wire io_sigs_wen_0; // @[fpu.scala:27:7] wire io_sigs_ren1_0; // @[fpu.scala:27:7] wire io_sigs_ren2_0; // @[fpu.scala:27:7] wire io_sigs_ren3_0; // @[fpu.scala:27:7] wire io_sigs_swap12_0; // @[fpu.scala:27:7] wire io_sigs_swap23_0; // @[fpu.scala:27:7] wire [1:0] io_sigs_typeTagIn_0; // @[fpu.scala:27:7] wire [1:0] io_sigs_typeTagOut_0; // @[fpu.scala:27:7] wire io_sigs_fromint_0; // @[fpu.scala:27:7] wire io_sigs_toint_0; // @[fpu.scala:27:7] wire io_sigs_fastpipe_0; // @[fpu.scala:27:7] wire io_sigs_fma_0; // @[fpu.scala:27:7] wire io_sigs_div_0; // @[fpu.scala:27:7] wire io_sigs_sqrt_0; // @[fpu.scala:27:7] wire io_sigs_wflags_0; // @[fpu.scala:27:7] wire [6:0] decoder_decoded_invInputs = ~decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [15:0] decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [15:0] decoder_decoded; // @[pla.scala:81:23] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T = {decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_17_2 = &_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_1, decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_1 = {decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_22_2 = &_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_8 = decoder_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_2 = {decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_2 = {decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_4_2 = &_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_3 = {decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_16_2 = &_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_2_2 = &_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_5 = {decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_5 = {decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_10_2 = &_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, decoder_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _decoder_decoded_andMatrixOutputs_T_6 = {decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_6_2 = &_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_7 = {decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_7 = {decoder_decoded_andMatrixOutputs_hi_7, decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_14_2 = &_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_8 = {decoder_decoded_andMatrixOutputs_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_8 = {decoder_decoded_andMatrixOutputs_hi_8, decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_34_2 = &_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_9 = {decoder_decoded_andMatrixOutputs_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_9 = {decoder_decoded_andMatrixOutputs_hi_9, decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_28_2 = &_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_10 = {decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_10 = {decoder_decoded_andMatrixOutputs_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_10 = {decoder_decoded_andMatrixOutputs_hi_10, decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_21_2 = &_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] _decoder_decoded_andMatrixOutputs_T_11 = {decoder_decoded_andMatrixOutputs_hi_11, decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_1_2 = &_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, decoder_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_12 = {decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_12 = {decoder_decoded_andMatrixOutputs_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_12 = {decoder_decoded_andMatrixOutputs_hi_12, decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_32_2 = &_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] _decoder_decoded_andMatrixOutputs_T_13 = {decoder_decoded_andMatrixOutputs_hi_13, decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_19_2 = &_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _decoder_decoded_andMatrixOutputs_T_14 = {decoder_decoded_andMatrixOutputs_hi_14, decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_7_2 = &_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _decoder_decoded_andMatrixOutputs_T_15 = {decoder_decoded_andMatrixOutputs_hi_15, decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_26_2 = &_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_16 = {decoder_decoded_andMatrixOutputs_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:90:45, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_16 = {decoder_decoded_andMatrixOutputs_hi_16, decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_12_2 = &_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [3:0] _decoder_decoded_andMatrixOutputs_T_17 = {decoder_decoded_andMatrixOutputs_hi_17, decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_5_2 = &_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, decoder_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_18 = {decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_18 = {decoder_decoded_andMatrixOutputs_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_18 = {decoder_decoded_andMatrixOutputs_hi_18, decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_27_2 = &_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_19 = {decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_19 = {decoder_decoded_andMatrixOutputs_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_19 = {decoder_decoded_andMatrixOutputs_hi_19, decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_15_2 = &_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_20 = {decoder_decoded_andMatrixOutputs_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_20 = {decoder_decoded_andMatrixOutputs_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_20 = {decoder_decoded_andMatrixOutputs_hi_20, decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_24_2 = &_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, decoder_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_21 = {decoder_decoded_andMatrixOutputs_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_21 = {decoder_decoded_andMatrixOutputs_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_21 = {decoder_decoded_andMatrixOutputs_hi_21, decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_29_2 = &_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_22 = {decoder_decoded_andMatrixOutputs_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:90:45, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_22 = {decoder_decoded_andMatrixOutputs_hi_22, decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_33_2 = &_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_23 = {decoder_decoded_andMatrixOutputs_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_23 = {decoder_decoded_andMatrixOutputs_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_23 = {decoder_decoded_andMatrixOutputs_hi_23, decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_9_2 = &_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_18, decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_24 = {decoder_decoded_andMatrixOutputs_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_24 = {decoder_decoded_andMatrixOutputs_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_24 = {decoder_decoded_andMatrixOutputs_hi_24, decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_25_2 = &_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, decoder_decoded_andMatrixOutputs_andMatrixInput_3_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [3:0] _decoder_decoded_andMatrixOutputs_T_25 = {decoder_decoded_andMatrixOutputs_hi_25, decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_18_2 = &_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_26 = {decoder_decoded_andMatrixOutputs_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_26 = {decoder_decoded_andMatrixOutputs_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_26 = {decoder_decoded_andMatrixOutputs_hi_26, decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_11_2 = &_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_27 = {decoder_decoded_andMatrixOutputs_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_27 = {decoder_decoded_andMatrixOutputs_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_27 = {decoder_decoded_andMatrixOutputs_hi_27, decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_35_2 = &_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_21, decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_28 = {decoder_decoded_andMatrixOutputs_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_28 = {decoder_decoded_andMatrixOutputs_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_28 = {decoder_decoded_andMatrixOutputs_hi_28, decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_0_2 = &_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_29, decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_29 = {decoder_decoded_andMatrixOutputs_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_29 = {decoder_decoded_andMatrixOutputs_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_29 = {decoder_decoded_andMatrixOutputs_hi_29, decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_31_2 = &_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_30 = {decoder_decoded_andMatrixOutputs_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_30 = {decoder_decoded_andMatrixOutputs_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_30 = {decoder_decoded_andMatrixOutputs_hi_30, decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_3_2 = &_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_31 = {decoder_decoded_andMatrixOutputs_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_31 = {decoder_decoded_andMatrixOutputs_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_31 = {decoder_decoded_andMatrixOutputs_hi_31, decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_8_2 = &_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_32 = {decoder_decoded_andMatrixOutputs_hi_32, decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_20_2 = &_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, decoder_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_33 = {decoder_decoded_andMatrixOutputs_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_33 = {decoder_decoded_andMatrixOutputs_hi_33, decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_23_2 = &_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, decoder_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_34 = {decoder_decoded_andMatrixOutputs_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_34 = {decoder_decoded_andMatrixOutputs_hi_34, decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_30_2 = &_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_35 = {decoder_decoded_andMatrixOutputs_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_35 = {decoder_decoded_andMatrixOutputs_hi_35, decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_13_2 = &_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi = {decoder_decoded_andMatrixOutputs_33_2, decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo = {decoder_decoded_orMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi = {decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi = {decoder_decoded_orMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _decoder_decoded_orMatrixOutputs_T = {decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_1 = |_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {decoder_decoded_andMatrixOutputs_8_2, decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_1 = _GEN; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_4 = _GEN; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_2 = _GEN; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_9_2, decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _decoder_decoded_orMatrixOutputs_T_2 = {decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_3 = |_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _decoder_decoded_orMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_34_2, decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_5 = |_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] _decoder_decoded_orMatrixOutputs_T_6 = {decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_7 = |_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo = {decoder_decoded_andMatrixOutputs_23_2, decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_2 = {decoder_decoded_orMatrixOutputs_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo = {decoder_decoded_andMatrixOutputs_28_2, decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi = {decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_1 = {decoder_decoded_orMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_2 = {decoder_decoded_orMatrixOutputs_hi_hi_1, decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [8:0] _decoder_decoded_orMatrixOutputs_T_9 = {decoder_decoded_orMatrixOutputs_hi_2, decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_10 = |_decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_1 = {decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi = {decoder_decoded_andMatrixOutputs_24_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_2 = {decoder_decoded_orMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_3 = {decoder_decoded_orMatrixOutputs_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_32_2, decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_16_2, decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_2 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] _decoder_decoded_orMatrixOutputs_T_11 = {decoder_decoded_orMatrixOutputs_hi_3, decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_12 = |_decoder_decoded_orMatrixOutputs_T_11; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_hi_4 = {decoder_decoded_andMatrixOutputs_25_2, decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _decoder_decoded_orMatrixOutputs_T_13 = {decoder_decoded_orMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_14 = |_decoder_decoded_orMatrixOutputs_T_13; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_hi_5 = {decoder_decoded_andMatrixOutputs_31_2, decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _decoder_decoded_orMatrixOutputs_T_15 = {decoder_decoded_orMatrixOutputs_hi_5, decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_16 = |_decoder_decoded_orMatrixOutputs_T_15; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_3 = {decoder_decoded_andMatrixOutputs_18_2, decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_5 = {decoder_decoded_orMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_3 = {decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_6 = {decoder_decoded_orMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _decoder_decoded_orMatrixOutputs_T_17 = {decoder_decoded_orMatrixOutputs_hi_6, decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_18 = |_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_4 = {decoder_decoded_andMatrixOutputs_26_2, decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_6 = {decoder_decoded_orMatrixOutputs_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_4 = {decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] _decoder_decoded_orMatrixOutputs_T_19 = {decoder_decoded_orMatrixOutputs_hi_7, decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_20 = |_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo = {1'h0, _decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi = {_decoder_decoded_orMatrixOutputs_T_3, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_3 = {decoder_decoded_orMatrixOutputs_lo_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo = {_decoder_decoded_orMatrixOutputs_T_7, _decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {_decoder_decoded_orMatrixOutputs_T_10, _decoder_decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_5 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_1, decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [7:0] decoder_decoded_orMatrixOutputs_lo_7 = {decoder_decoded_orMatrixOutputs_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo = {_decoder_decoded_orMatrixOutputs_T_14, _decoder_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi = {_decoder_decoded_orMatrixOutputs_T_16, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_3 = {decoder_decoded_orMatrixOutputs_hi_lo_hi, decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo = {_decoder_decoded_orMatrixOutputs_T_20, _decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_5 = {2'h0, decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36] wire [7:0] decoder_decoded_orMatrixOutputs_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:102:36] wire [15:0] decoder_decoded_orMatrixOutputs = {decoder_decoded_orMatrixOutputs_hi_8, decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:102:36] wire _decoder_decoded_invMatrixOutputs_T = decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_1 = decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_2 = decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_3 = decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_4 = decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_5 = decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_6 = decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_7 = decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_8 = decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_9 = decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_10 = decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_11 = decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_12 = decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_13 = decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_14 = decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_15 = decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_lo = {_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_hi = {_decoder_decoded_invMatrixOutputs_T_3, _decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoder_decoded_invMatrixOutputs_lo_lo = {decoder_decoded_invMatrixOutputs_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_lo = {_decoder_decoded_invMatrixOutputs_T_5, _decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_hi = {_decoder_decoded_invMatrixOutputs_T_7, _decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [3:0] decoder_decoded_invMatrixOutputs_lo_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [7:0] decoder_decoded_invMatrixOutputs_lo = {decoder_decoded_invMatrixOutputs_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_lo = {_decoder_decoded_invMatrixOutputs_T_9, _decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_hi = {_decoder_decoded_invMatrixOutputs_T_11, _decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [3:0] decoder_decoded_invMatrixOutputs_hi_lo = {decoder_decoded_invMatrixOutputs_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_lo = {_decoder_decoded_invMatrixOutputs_T_13, _decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_15, _decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [3:0] decoder_decoded_invMatrixOutputs_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [7:0] decoder_decoded_invMatrixOutputs_hi = {decoder_decoded_invMatrixOutputs_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoder_decoded_invMatrixOutputs = {decoder_decoded_invMatrixOutputs_hi, decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoder_decoded = decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoder_0 = decoder_decoded[15]; // @[pla.scala:81:23] assign io_sigs_ldst_0 = decoder_0; // @[Decode.scala:50:77] assign decoder_1 = decoder_decoded[14]; // @[pla.scala:81:23] assign io_sigs_wen_0 = decoder_1; // @[Decode.scala:50:77] assign decoder_2 = decoder_decoded[13]; // @[pla.scala:81:23] assign io_sigs_ren1_0 = decoder_2; // @[Decode.scala:50:77] assign decoder_3 = decoder_decoded[12]; // @[pla.scala:81:23] assign io_sigs_ren2_0 = decoder_3; // @[Decode.scala:50:77] assign decoder_4 = decoder_decoded[11]; // @[pla.scala:81:23] assign io_sigs_ren3_0 = decoder_4; // @[Decode.scala:50:77] assign decoder_5 = decoder_decoded[10]; // @[pla.scala:81:23] assign io_sigs_swap12_0 = decoder_5; // @[Decode.scala:50:77] assign decoder_6 = decoder_decoded[9]; // @[pla.scala:81:23] assign io_sigs_swap23_0 = decoder_6; // @[Decode.scala:50:77] wire decoder_7 = decoder_decoded[8]; // @[pla.scala:81:23] wire decoder_8 = decoder_decoded[7]; // @[pla.scala:81:23] assign decoder_9 = decoder_decoded[6]; // @[pla.scala:81:23] assign io_sigs_fromint_0 = decoder_9; // @[Decode.scala:50:77] assign decoder_10 = decoder_decoded[5]; // @[pla.scala:81:23] assign io_sigs_toint_0 = decoder_10; // @[Decode.scala:50:77] assign decoder_11 = decoder_decoded[4]; // @[pla.scala:81:23] assign io_sigs_fastpipe_0 = decoder_11; // @[Decode.scala:50:77] assign decoder_12 = decoder_decoded[3]; // @[pla.scala:81:23] assign io_sigs_fma_0 = decoder_12; // @[Decode.scala:50:77] assign decoder_13 = decoder_decoded[2]; // @[pla.scala:81:23] assign io_sigs_div_0 = decoder_13; // @[Decode.scala:50:77] assign decoder_14 = decoder_decoded[1]; // @[pla.scala:81:23] assign io_sigs_sqrt_0 = decoder_14; // @[Decode.scala:50:77] assign decoder_15 = decoder_decoded[0]; // @[pla.scala:81:23] assign io_sigs_wflags_0 = decoder_15; // @[Decode.scala:50:77] assign io_sigs_typeTagIn_0 = {1'h0, decoder_7}; // @[Decode.scala:50:77] assign io_sigs_typeTagOut_0 = {1'h0, decoder_8}; // @[Decode.scala:50:77] assign io_sigs_ldst = io_sigs_ldst_0; // @[fpu.scala:27:7] assign io_sigs_wen = io_sigs_wen_0; // @[fpu.scala:27:7] assign io_sigs_ren1 = io_sigs_ren1_0; // @[fpu.scala:27:7] assign io_sigs_ren2 = io_sigs_ren2_0; // @[fpu.scala:27:7] assign io_sigs_ren3 = io_sigs_ren3_0; // @[fpu.scala:27:7] assign io_sigs_swap12 = io_sigs_swap12_0; // @[fpu.scala:27:7] assign io_sigs_swap23 = io_sigs_swap23_0; // @[fpu.scala:27:7] assign io_sigs_typeTagIn = io_sigs_typeTagIn_0; // @[fpu.scala:27:7] assign io_sigs_typeTagOut = io_sigs_typeTagOut_0; // @[fpu.scala:27:7] assign io_sigs_fromint = io_sigs_fromint_0; // @[fpu.scala:27:7] assign io_sigs_toint = io_sigs_toint_0; // @[fpu.scala:27:7] assign io_sigs_fastpipe = io_sigs_fastpipe_0; // @[fpu.scala:27:7] assign io_sigs_fma = io_sigs_fma_0; // @[fpu.scala:27:7] assign io_sigs_div = io_sigs_div_0; // @[fpu.scala:27:7] assign io_sigs_sqrt = io_sigs_sqrt_0; // @[fpu.scala:27:7] assign io_sigs_wflags = io_sigs_wflags_0; // @[fpu.scala:27:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_241( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_445 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_165( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLBuffer_a32d64s4k7z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [6:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [6:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [6:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_16 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s4k7z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s4k7z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File tage.scala: package boom.v4.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f2_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)*l, histLength)-1, i*l) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val us = SyncReadMem(nRows, Vec(bankWidth*2, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) us.suggestName(s"tage_u_${histLength}") table.suggestName(s"tage_table_${histLength}") val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry)) val s2_req_rus = Wire(Vec(bankWidth*2, Bool())) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f2_resp(w).valid := s2_req_rhits(w) io.f2_resp(w).bits.u := Cat(s2_req_rus(w*2+1), s2_req_rus(w*2)) io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val clear_u_mask = VecInit((0 until bankWidth*2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) val wen = WireInit(doing_reset || io.update_mask.reduce(_||_)) val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid) when (RegNext(wen) && singlePorted.B) { s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry)) } .otherwise { s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry))) } when (wen) { val widx = Mux(doing_reset, reset_idx, update_idx) val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))) val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt) table.write(widx, wdata, wmask.asBools) } val update_u_mask = VecInit((0 until bankWidth*2) map {i => io.update_u_mask(i / 2)}) val update_u_wen = WireInit(doing_reset || doing_clear_u || update_u_mask.reduce(_||_)) val u_rdata = if (singlePorted) { us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid) } else { us.read(s1_hashed_idx, io.f1_req_valid) } s2_req_rus := u_rdata when (update_u_wen) { val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx)) val wdata = Mux(doing_reset || doing_clear_u, VecInit(0.U((bankWidth*2).W).asBools), VecInit(io.update_u.asUInt.asBools)) val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt)) us.write(widx, wdata, wmask.asBools) } val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_||_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag } when (io.update_mask.reduce(_||_)) { when (wrbypass_hits.reduce(_||_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048, singlePorted: Boolean = false ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc)) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f2_resps = VecInit(tables.map(_.io.f2_resp)) val f3_resps = RegNext(f2_resps) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var s2_provided = false.B var s2_provider = 0.U var s2_alt_provided = false.B var s2_alt_provider = 0.U for (i <- 0 until tageNTables) { val hit = f2_resps(i)(w).valid s2_alt_provided = s2_alt_provided || (s2_provided && hit) s2_provided = s2_provided || hit s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider) s2_provider = Mux(hit, i.U, s2_provider) } val s3_provided = RegNext(s2_provided) val s3_provider = RegNext(s2_provider) val s3_alt_provided = RegNext(s2_alt_provided) val s3_alt_provider = RegNext(s2_alt_provider) val prov = RegNext(f2_resps(s2_provider)(w).bits) val alt = RegNext(f2_resps(s2_alt_provider)(w).bits) io.resp.f3(w).taken := Mux(s3_provided, Mux(prov.ctr === 3.U || prov.ctr === 4.U, Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken), prov.ctr(2)), io.resp_in(0).f3(w).taken ) f3_meta.provider(w).valid := s3_provided f3_meta.provider(w).bits := s3_provider f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken f3_meta.provider_u(w) := prov.u f3_meta.provider_ctr(w) := prov.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }
module TageTable_10( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f2_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14] output io_f2_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14] output io_f2_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14] output io_f2_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire [51:0] _tage_table_32_R0_data; // @[tage.scala:90:27] wire [7:0] _tage_u_32_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26] wire [12:0] _wdata_WIRE_0 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_1 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_2 = 13'h0; // @[tage.scala:130:41] wire [12:0] _wdata_WIRE_3 = 13'h0; // @[tage.scala:130:41] wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34] wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58] wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34] wire s2_req_rhits_0; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_1; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_2; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_3; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34] wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26] wire [7:0] _reset_idx_T = _GEN + {7'h0, doing_reset}; // @[tage.scala:72:28, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [6:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2 = io_f1_req_ghist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3 = io_f1_req_ghist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [3:0] idx_history_hist_chunks_4 = io_f1_req_ghist_0[31:28]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_1 = _idx_history_T ^ idx_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_2 = _idx_history_T_1 ^ idx_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history = {_idx_history_T_2[6:4], _idx_history_T_2[3:0] ^ idx_history_hist_chunks_4}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:149:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[10:4] ^ idx_history}; // @[frontend.scala:149:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99] wire [6:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12] wire [8:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2 = io_f1_req_ghist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [4:0] tag_history_hist_chunks_3 = io_f1_req_ghist_0[31:27]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_1 = _tag_history_T ^ tag_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history = {_tag_history_T_1[8:5], _tag_history_T_1[4:0] ^ tag_history_hist_chunks_3}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_1 = {_tag_T[28:9], _tag_T[8:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] s1_tag = _tag_T_1[8:0]; // @[tage.scala:62:{50,64}] wire wdata_1_0; // @[tage.scala:145:20] wire wdata_1_1; // @[tage.scala:145:20] wire wdata_1_2; // @[tage.scala:145:20] wire wdata_1_3; // @[tage.scala:145:20] wire wdata_1_4; // @[tage.scala:145:20] wire wdata_1_5; // @[tage.scala:145:20] wire wdata_1_6; // @[tage.scala:145:20] wire wdata_1_7; // @[tage.scala:145:20] wire s2_req_rus_0 = _tage_u_32_R0_data[0]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_1 = _tage_u_32_R0_data[1]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_2 = _tage_u_32_R0_data[2]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_3 = _tage_u_32_R0_data[3]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_4 = _tage_u_32_R0_data[4]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_5 = _tage_u_32_R0_data[5]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_6 = _tage_u_32_R0_data[6]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_7 = _tage_u_32_R0_data[7]; // @[tage.scala:89:27, :99:24] wire [12:0] wdata_0; // @[tage.scala:130:20] wire [12:0] wdata_1; // @[tage.scala:130:20] wire [12:0] wdata_2; // @[tage.scala:130:20] wire [12:0] wdata_3; // @[tage.scala:130:20] reg [8:0] s2_tag; // @[tage.scala:96:29] assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26] wire s2_req_rtage_0_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_0_tag; // @[tage.scala:98:26] wire s2_req_rtage_1_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_1_tag; // @[tage.scala:98:26] wire s2_req_rtage_2_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_2_tag; // @[tage.scala:98:26] wire s2_req_rtage_3_valid; // @[tage.scala:98:26] wire [8:0] s2_req_rtage_3_tag; // @[tage.scala:98:26] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29] assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29] assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29] assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29] assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31] wire _clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31, :114:31] wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}] wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}] wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109] wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109] wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109] wire [6:0] idx_history_hist_chunks_0_1 = io_update_hist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1_1 = io_update_hist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2_1 = io_update_hist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3_1 = io_update_hist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [3:0] idx_history_hist_chunks_4_1 = io_update_hist_0[31:28]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T_3 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_4 = _idx_history_T_3 ^ idx_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_5 = _idx_history_T_4 ^ idx_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history_1 = {_idx_history_T_5[6:4], _idx_history_T_5[3:0] ^ idx_history_hist_chunks_4_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:149:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[10:4] ^ idx_history_1}; // @[frontend.scala:149:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [8:0] tag_history_hist_chunks_0_1 = io_update_hist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1_1 = io_update_hist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2_1 = io_update_hist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [4:0] tag_history_hist_chunks_3_1 = io_update_hist_0[31:27]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T_2 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_3 = _tag_history_T_2 ^ tag_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history_1 = {_tag_history_T_3[8:5], _tag_history_T_3[4:0] ^ tag_history_hist_chunks_3_1}; // @[tage.scala:53:11, :55:25] wire [28:0] _tag_T_3 = {_tag_T_2[28:9], _tag_T_2[8:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] update_tag = _tag_T_3[8:0]; // @[tage.scala:62:{50,64}] wire [8:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [8:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26] wire _wen_T = io_update_mask_0_0 | io_update_mask_1_0; // @[tage.scala:24:7, :121:60] wire _wen_T_1 = _wen_T | io_update_mask_2_0; // @[tage.scala:24:7, :121:60] wire _wen_T_2 = _wen_T_1 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60] wire _wen_T_3 = doing_reset | _wen_T_2; // @[tage.scala:72:28, :121:{34,60}] wire wen = _wen_T_3; // @[tage.scala:121:{21,34}] reg REG; // @[tage.scala:123:16] assign s2_req_rtage_0_ctr = _tage_table_32_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_tag = _tage_table_32_R0_data[11:3]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_valid = _tage_table_32_R0_data[12]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_ctr = _tage_table_32_R0_data[15:13]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_tag = _tage_table_32_R0_data[24:16]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_valid = _tage_table_32_R0_data[25]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_ctr = _tage_table_32_R0_data[28:26]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_tag = _tage_table_32_R0_data[37:29]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_valid = _tage_table_32_R0_data[38]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_ctr = _tage_table_32_R0_data[41:39]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_tag = _tage_table_32_R0_data[50:42]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_valid = _tage_table_32_R0_data[51]; // @[tage.scala:90:27, :98:26, :126:49] wire [6:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19] wire [9:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}] wire [9:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114] wire [12:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}] assign wdata_0 = doing_reset ? 13'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}] assign wdata_1 = doing_reset ? 13'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}] assign wdata_2 = doing_reset ? 13'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}] assign wdata_3 = doing_reset ? 13'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}] wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70] wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70] wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70] wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}] wire _GEN_0 = doing_reset | doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43] wire _update_u_wen_T; // @[tage.scala:136:43] assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43] wire _wdata_T_4; // @[tage.scala:145:33] assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33] wire _update_u_wen_T_1 = update_u_mask_0 | update_u_mask_1; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_2 = _update_u_wen_T_1 | update_u_mask_2; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_3 = _update_u_wen_T_2 | update_u_mask_3; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_4 = _update_u_wen_T_3 | update_u_mask_4; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_5 = _update_u_wen_T_4 | update_u_mask_5; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_6 = _update_u_wen_T_5 | update_u_mask_6; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_7 = _update_u_wen_T_6 | update_u_mask_7; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_8 = _update_u_wen_T | _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}] wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}] wire [7:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47] wire [7:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}] wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110] wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110] wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110] wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}] wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}] wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}] wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}] wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}] wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}] wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}] wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}] assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}] assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}] assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}] assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}] assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}] assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}] assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}] assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}] wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106] wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106] wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106] wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}] wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}] reg [8:0] wrbypass_tags_0; // @[tage.scala:154:29] reg [8:0] wrbypass_tags_1; // @[tage.scala:154:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:155:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:155:29] reg [2:0] wrbypass_0_0; // @[tage.scala:156:29] reg [2:0] wrbypass_0_1; // @[tage.scala:156:29] reg [2:0] wrbypass_0_2; // @[tage.scala:156:29] reg [2:0] wrbypass_0_3; // @[tage.scala:156:29] reg [2:0] wrbypass_1_0; // @[tage.scala:156:29] reg [2:0] wrbypass_1_1; // @[tage.scala:156:29] reg [2:0] wrbypass_1_2; // @[tage.scala:156:29] reg [2:0] wrbypass_1_3; // @[tage.scala:156:29] reg wrbypass_enq_idx; // @[tage.scala:157:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:159:33, :164:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}] wire _T_31 = _wen_T | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_31 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] wire _GEN_15 = ~_T_31 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_31 | wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39] end else // @[tage.scala:157:33, :180:38, :181:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29] REG <= wen; // @[tage.scala:121:21, :123:16] if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29] if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29] if (~_T_31 | _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] end else begin // @[tage.scala:156:29, :180:38, :181:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end always @(posedge) tage_u_32_0 tage_u_32 ( // @[tage.scala:89:27] .R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_u_32_R0_data), .W0_addr (widx_1[6:0]), // @[tage.scala:144:19, :147:13] .W0_en (update_u_wen), // @[tage.scala:136:30] .W0_clk (clock), .W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20] .W0_mask (wmask_1) // @[tage.scala:146:20] ); // @[tage.scala:89:27] tage_table_32_0 tage_table_32 ( // @[tage.scala:90:27] .R0_addr (_rdata_WIRE), // @[tage.scala:122:99] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_table_32_R0_data), .W0_addr (widx), // @[tage.scala:129:19] .W0_en (wen), // @[tage.scala:121:21] .W0_clk (clock), .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20] .W0_mask (wmask) // @[tage.scala:131:20] ); // @[tage.scala:90:27] assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_5( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_94 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_54 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_56 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_62 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_68 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_74 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_57 = _source_ok_T_56 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_69 = _source_ok_T_68 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_75 = _source_ok_T_74 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_79; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_80 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_86 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_92 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_81 = _source_ok_T_80 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_87 = _source_ok_T_86 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_93 = _source_ok_T_92 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_95 = _source_ok_T_93; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_97 = _source_ok_T_95 & _source_ok_T_96; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire _source_ok_T_99 = io_in_d_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_99; // @[Parameters.scala:1138:31] wire _source_ok_T_100 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_109 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1458 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1458; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1458; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1531 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1531; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1531; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1531; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1384 = _T_1458 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1384 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1384 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1384 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1384 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1384 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1430 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1430 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1399 = _T_1531 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1399 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1399 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1399 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1502 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1502 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1484 = _T_1531 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1484 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1484 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1484 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module IntSyncSyncCrossingSink_n0x0_9(); // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_91( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File VectorUnit.scala: package shuttle.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import shuttle.dmem._ abstract class ShuttleVectorUnit(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { val module: ShuttleVectorUnitModuleImp val tlNode: TLNode = TLIdentityNode() val atlNode: TLNode = TLIdentityNode() val sgNode: Option[TLNode] = tileParams.asInstanceOf[ShuttleTileParams].sgtcm.map { _ => TLIdentityNode() } } class ShuttleVectorUnitModuleImp(outer: ShuttleVectorUnit) extends LazyModuleImp(outer) with HasCoreParameters { val io = IO(new ShuttleVectorCoreIO) val io_sg_base = IO(Input(UInt(coreMaxAddrBits.W))) val sgSize = outer.tileParams.asInstanceOf[ShuttleTileParams].sgtcm.map(_.size) } class ShuttleVectorCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val status = Input(new MStatus) val satp = Input(new PTBR) val ex = new Bundle { val valid = Input(Bool()) val uop = Input(new ShuttleUOP) val vconfig = Input(new VConfig) val vstart = Input(UInt(log2Ceil(maxVLMax).W)) val ready = Output(Bool()) val fire = Input(Bool()) } val mem = new Bundle { val kill = Input(Bool()) val tlb_req = Decoupled(new ShuttleDTLBReq(3)) val tlb_resp = Input(new ShuttleDTLBResp) val frs1 = Input(UInt(fLen.W)) } val com = new Bundle { val store_pending = Input(Bool()) val retire_late = Output(Bool()) val inst = Output(UInt(32.W)) val rob_should_wb = Output(Bool()) // debug val rob_should_wb_fp = Output(Bool()) // debug val pc = Output(UInt(vaddrBitsExtended.W)) val xcpt = Output(Bool()) val cause = Output(UInt(log2Ceil(Causes.all.max).W)) val tval = Output(UInt(coreMaxAddrBits.W)) val vxrm = Input(UInt(2.W)) val frm = Input(UInt(3.W)) val scalar_check = Flipped(Decoupled(new Bundle { val addr = UInt(paddrBits.W) val size = UInt(2.W) val store = Bool() })) val internal_replay = Output(Bool()) val block_all = Output(Bool()) } def wb = com val resp = Decoupled(new Bundle { val fp = Bool() val size = UInt(2.W) val rd = UInt(5.W) val data = UInt((xLen max fLen).W) }) val set_vstart = Valid(UInt(log2Ceil(maxVLMax).W)) val set_vxsat = Output(Bool()) val set_vconfig = Valid(new VConfig) val set_fflags = Valid(UInt(5.W)) val trap_check_busy = Output(Bool()) val backend_busy = Output(Bool()) } File Integration.scala: package saturn.shuttle import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.diplomacy._ import saturn.common._ import saturn.backend.{VectorBackend} import saturn.mem.{TLSplitInterface, SGTLInterface, VectorMemUnit} import saturn.frontend.{VectorDispatcher} import shuttle.common._ class SaturnShuttleUnit(implicit p: Parameters) extends ShuttleVectorUnit()(p) with HasVectorParams with HasCoreParameters { assert(!vParams.useScalarFPFMA && !vParams.useScalarFPMisc) if (vParams.useScalarFPFMA) { require(coreParams.fpu.get.dfmaLatency == vParams.fmaPipeDepth - 1) } val tl_if = LazyModule(new TLSplitInterface) atlNode := TLBuffer(vParams.tlBuffer) := TLWidthWidget(dLenB) := tl_if.node val sg_if = sgNode.map { n => val sg_if = LazyModule(new SGTLInterface) n :=* sg_if.node sg_if } override lazy val module = new SaturnShuttleImpl class SaturnShuttleImpl extends ShuttleVectorUnitModuleImp(this) with HasVectorParams with HasCoreParameters { val dis = Module(new VectorDispatcher) val scalar_arb = Module(new Arbiter(new ScalarWrite, 2)) val vfu = Module(new SaturnShuttleFrontend(sgSize, tl_if.edge)) val vu = Module(new VectorBackend) val vmu = Module(new VectorMemUnit(sgSize)) sg_if.foreach { sg => sg.module.io.vec <> vmu.io.sgmem.get } dis.io.issue <> vfu.io.issue vfu.io.core <> io vfu.io.sg_base := io_sg_base vu.io.index_access <> vfu.io.index_access vu.io.mask_access <> vfu.io.mask_access vu.io.vmu <> vmu.io.vu vu.io.vat_tail := dis.io.vat_tail vu.io.vat_head := dis.io.vat_head vu.io.dis <> dis.io.dis dis.io.vat_release := vu.io.vat_release vmu.io.enq <> dis.io.mem vmu.io.scalar_check <> vfu.io.scalar_check io.backend_busy := vu.io.busy || tl_if.module.io.mem_busy || sg_if.map(_.module.io.mem_busy).getOrElse(false.B) || vmu.io.busy io.set_vxsat := vu.io.set_vxsat io.set_fflags := vu.io.set_fflags scalar_arb.io.in(0) <> vu.io.scalar_resp scalar_arb.io.in(1) <> dis.io.scalar_resp io.resp <> Queue(scalar_arb.io.out) tl_if.module.io.vec <> vmu.io.dmem vu.io.fp_req.ready := false.B vu.io.fp_resp.valid := false.B vu.io.fp_resp.bits := DontCare } }
module SaturnShuttleUnit( // @[Integration.scala:35:9] input clock, // @[Integration.scala:35:9] input reset, // @[Integration.scala:35:9] input auto_atl_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_atl_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_atl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_atl_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_atl_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_atl_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_atl_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_atl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_atl_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_atl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_atl_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_atl_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_atl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_atl_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_atl_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_atl_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_atl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_atl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_atl_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_atl_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input [1:0] io_status_prv, // @[VectorUnit.scala:20:14] input io_ex_valid, // @[VectorUnit.scala:20:14] input [31:0] io_ex_uop_inst, // @[VectorUnit.scala:20:14] input [39:0] io_ex_uop_pc, // @[VectorUnit.scala:20:14] input [63:0] io_ex_uop_rs1_data, // @[VectorUnit.scala:20:14] input [63:0] io_ex_uop_rs2_data, // @[VectorUnit.scala:20:14] input [8:0] io_ex_vconfig_vl, // @[VectorUnit.scala:20:14] input io_ex_vconfig_vtype_vill, // @[VectorUnit.scala:20:14] input [54:0] io_ex_vconfig_vtype_reserved, // @[VectorUnit.scala:20:14] input io_ex_vconfig_vtype_vma, // @[VectorUnit.scala:20:14] input io_ex_vconfig_vtype_vta, // @[VectorUnit.scala:20:14] input [2:0] io_ex_vconfig_vtype_vsew, // @[VectorUnit.scala:20:14] input io_ex_vconfig_vtype_vlmul_sign, // @[VectorUnit.scala:20:14] input [1:0] io_ex_vconfig_vtype_vlmul_mag, // @[VectorUnit.scala:20:14] input [7:0] io_ex_vstart, // @[VectorUnit.scala:20:14] output io_ex_ready, // @[VectorUnit.scala:20:14] input io_ex_fire, // @[VectorUnit.scala:20:14] input io_mem_kill, // @[VectorUnit.scala:20:14] input io_mem_tlb_req_ready, // @[VectorUnit.scala:20:14] output io_mem_tlb_req_valid, // @[VectorUnit.scala:20:14] output [39:0] io_mem_tlb_req_bits_vaddr, // @[VectorUnit.scala:20:14] output [1:0] io_mem_tlb_req_bits_size, // @[VectorUnit.scala:20:14] output [4:0] io_mem_tlb_req_bits_cmd, // @[VectorUnit.scala:20:14] output [1:0] io_mem_tlb_req_bits_prv, // @[VectorUnit.scala:20:14] input io_mem_tlb_resp_miss, // @[VectorUnit.scala:20:14] input [31:0] io_mem_tlb_resp_paddr, // @[VectorUnit.scala:20:14] input io_mem_tlb_resp_pf_ld, // @[VectorUnit.scala:20:14] input io_mem_tlb_resp_pf_st, // @[VectorUnit.scala:20:14] input io_mem_tlb_resp_ae_ld, // @[VectorUnit.scala:20:14] input io_mem_tlb_resp_ae_st, // @[VectorUnit.scala:20:14] input io_mem_tlb_resp_ma_ld, // @[VectorUnit.scala:20:14] input io_mem_tlb_resp_ma_st, // @[VectorUnit.scala:20:14] input [63:0] io_mem_frs1, // @[VectorUnit.scala:20:14] input io_wb_store_pending, // @[VectorUnit.scala:20:14] output io_wb_retire_late, // @[VectorUnit.scala:20:14] output [39:0] io_wb_pc, // @[VectorUnit.scala:20:14] output io_wb_xcpt, // @[VectorUnit.scala:20:14] output [4:0] io_wb_cause, // @[VectorUnit.scala:20:14] output [39:0] io_wb_tval, // @[VectorUnit.scala:20:14] input [1:0] io_wb_vxrm, // @[VectorUnit.scala:20:14] input [2:0] io_wb_frm, // @[VectorUnit.scala:20:14] output io_wb_scalar_check_ready, // @[VectorUnit.scala:20:14] input [31:0] io_wb_scalar_check_bits_addr, // @[VectorUnit.scala:20:14] input io_wb_scalar_check_bits_store, // @[VectorUnit.scala:20:14] output io_wb_internal_replay, // @[VectorUnit.scala:20:14] output io_wb_block_all, // @[VectorUnit.scala:20:14] input io_resp_ready, // @[VectorUnit.scala:20:14] output io_resp_valid, // @[VectorUnit.scala:20:14] output io_resp_bits_fp, // @[VectorUnit.scala:20:14] output [1:0] io_resp_bits_size, // @[VectorUnit.scala:20:14] output [4:0] io_resp_bits_rd, // @[VectorUnit.scala:20:14] output [63:0] io_resp_bits_data, // @[VectorUnit.scala:20:14] output io_set_vstart_valid, // @[VectorUnit.scala:20:14] output [7:0] io_set_vstart_bits, // @[VectorUnit.scala:20:14] output io_set_vxsat, // @[VectorUnit.scala:20:14] output io_set_vconfig_valid, // @[VectorUnit.scala:20:14] output [8:0] io_set_vconfig_bits_vl, // @[VectorUnit.scala:20:14] output io_set_vconfig_bits_vtype_vill, // @[VectorUnit.scala:20:14] output [54:0] io_set_vconfig_bits_vtype_reserved, // @[VectorUnit.scala:20:14] output io_set_vconfig_bits_vtype_vma, // @[VectorUnit.scala:20:14] output io_set_vconfig_bits_vtype_vta, // @[VectorUnit.scala:20:14] output [2:0] io_set_vconfig_bits_vtype_vsew, // @[VectorUnit.scala:20:14] output io_set_vconfig_bits_vtype_vlmul_sign, // @[VectorUnit.scala:20:14] output [1:0] io_set_vconfig_bits_vtype_vlmul_mag, // @[VectorUnit.scala:20:14] output io_set_fflags_valid, // @[VectorUnit.scala:20:14] output [4:0] io_set_fflags_bits, // @[VectorUnit.scala:20:14] output io_trap_check_busy, // @[VectorUnit.scala:20:14] output io_backend_busy // @[VectorUnit.scala:20:14] ); wire _io_resp_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _vmu_io_enq_ready; // @[Integration.scala:41:21] wire _vmu_io_dmem_load_req_valid; // @[Integration.scala:41:21] wire [39:0] _vmu_io_dmem_load_req_bits_addr; // @[Integration.scala:41:21] wire [3:0] _vmu_io_dmem_load_req_bits_tag; // @[Integration.scala:41:21] wire _vmu_io_dmem_store_req_valid; // @[Integration.scala:41:21] wire [39:0] _vmu_io_dmem_store_req_bits_addr; // @[Integration.scala:41:21] wire [127:0] _vmu_io_dmem_store_req_bits_data; // @[Integration.scala:41:21] wire [15:0] _vmu_io_dmem_store_req_bits_mask; // @[Integration.scala:41:21] wire [3:0] _vmu_io_dmem_store_req_bits_tag; // @[Integration.scala:41:21] wire _vmu_io_scalar_check_conflict; // @[Integration.scala:41:21] wire _vmu_io_vu_lresp_valid; // @[Integration.scala:41:21] wire [127:0] _vmu_io_vu_lresp_bits_data; // @[Integration.scala:41:21] wire [15:0] _vmu_io_vu_lresp_bits_debug_id; // @[Integration.scala:41:21] wire _vmu_io_vu_sdata_ready; // @[Integration.scala:41:21] wire _vmu_io_vu_mask_pop_valid; // @[Integration.scala:41:21] wire _vmu_io_vu_index_pop_valid; // @[Integration.scala:41:21] wire [3:0] _vmu_io_vu_index_pop_bits_tail; // @[Integration.scala:41:21] wire _vmu_io_busy; // @[Integration.scala:41:21] wire _vu_io_dis_ready; // @[Integration.scala:40:20] wire _vu_io_vmu_lresp_ready; // @[Integration.scala:40:20] wire _vu_io_vmu_sdata_valid; // @[Integration.scala:40:20] wire [127:0] _vu_io_vmu_sdata_bits_stdata; // @[Integration.scala:40:20] wire [15:0] _vu_io_vmu_sdata_bits_stmask; // @[Integration.scala:40:20] wire [15:0] _vu_io_vmu_sdata_bits_debug_id; // @[Integration.scala:40:20] wire _vu_io_vmu_mask_pop_ready; // @[Integration.scala:40:20] wire _vu_io_vmu_mask_data_0; // @[Integration.scala:40:20] wire _vu_io_vmu_index_pop_ready; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_0; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_1; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_2; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_3; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_4; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_5; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_6; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_7; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_8; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_9; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_10; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_11; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_12; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_13; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_14; // @[Integration.scala:40:20] wire [7:0] _vu_io_vmu_index_data_15; // @[Integration.scala:40:20] wire _vu_io_busy; // @[Integration.scala:40:20] wire _vu_io_index_access_ready; // @[Integration.scala:40:20] wire [63:0] _vu_io_index_access_idx; // @[Integration.scala:40:20] wire _vu_io_mask_access_ready; // @[Integration.scala:40:20] wire _vu_io_mask_access_mask; // @[Integration.scala:40:20] wire _vu_io_scalar_resp_valid; // @[Integration.scala:40:20] wire [63:0] _vu_io_scalar_resp_bits_data; // @[Integration.scala:40:20] wire _vu_io_scalar_resp_bits_fp; // @[Integration.scala:40:20] wire [1:0] _vu_io_scalar_resp_bits_size; // @[Integration.scala:40:20] wire [4:0] _vu_io_scalar_resp_bits_rd; // @[Integration.scala:40:20] wire _vu_io_vat_release_0_valid; // @[Integration.scala:40:20] wire [4:0] _vu_io_vat_release_0_bits; // @[Integration.scala:40:20] wire _vu_io_vat_release_1_valid; // @[Integration.scala:40:20] wire [4:0] _vu_io_vat_release_1_bits; // @[Integration.scala:40:20] wire _vu_io_vat_release_2_valid; // @[Integration.scala:40:20] wire [4:0] _vu_io_vat_release_2_bits; // @[Integration.scala:40:20] wire _vu_io_vat_release_3_valid; // @[Integration.scala:40:20] wire [4:0] _vu_io_vat_release_3_bits; // @[Integration.scala:40:20] wire _vfu_io_issue_valid; // @[Integration.scala:39:21] wire [31:0] _vfu_io_issue_bits_bits; // @[Integration.scala:39:21] wire [8:0] _vfu_io_issue_bits_vconfig_vl; // @[Integration.scala:39:21] wire [2:0] _vfu_io_issue_bits_vconfig_vtype_vsew; // @[Integration.scala:39:21] wire _vfu_io_issue_bits_vconfig_vtype_vlmul_sign; // @[Integration.scala:39:21] wire [1:0] _vfu_io_issue_bits_vconfig_vtype_vlmul_mag; // @[Integration.scala:39:21] wire [7:0] _vfu_io_issue_bits_vstart; // @[Integration.scala:39:21] wire [2:0] _vfu_io_issue_bits_segstart; // @[Integration.scala:39:21] wire [2:0] _vfu_io_issue_bits_segend; // @[Integration.scala:39:21] wire [63:0] _vfu_io_issue_bits_rs1_data; // @[Integration.scala:39:21] wire [63:0] _vfu_io_issue_bits_rs2_data; // @[Integration.scala:39:21] wire [19:0] _vfu_io_issue_bits_page; // @[Integration.scala:39:21] wire [2:0] _vfu_io_issue_bits_rm; // @[Integration.scala:39:21] wire [1:0] _vfu_io_issue_bits_emul; // @[Integration.scala:39:21] wire [1:0] _vfu_io_issue_bits_mop; // @[Integration.scala:39:21] wire _vfu_io_index_access_valid; // @[Integration.scala:39:21] wire [4:0] _vfu_io_index_access_vrs; // @[Integration.scala:39:21] wire [8:0] _vfu_io_index_access_eidx; // @[Integration.scala:39:21] wire [1:0] _vfu_io_index_access_eew; // @[Integration.scala:39:21] wire _vfu_io_mask_access_valid; // @[Integration.scala:39:21] wire [8:0] _vfu_io_mask_access_eidx; // @[Integration.scala:39:21] wire [39:0] _vfu_io_scalar_check_addr; // @[Integration.scala:39:21] wire _vfu_io_scalar_check_store; // @[Integration.scala:39:21] wire _scalar_arb_io_in_0_ready; // @[Integration.scala:38:28] wire _scalar_arb_io_in_1_ready; // @[Integration.scala:38:28] wire _scalar_arb_io_out_valid; // @[Integration.scala:38:28] wire [63:0] _scalar_arb_io_out_bits_data; // @[Integration.scala:38:28] wire _scalar_arb_io_out_bits_fp; // @[Integration.scala:38:28] wire [1:0] _scalar_arb_io_out_bits_size; // @[Integration.scala:38:28] wire [4:0] _scalar_arb_io_out_bits_rd; // @[Integration.scala:38:28] wire _dis_io_issue_ready; // @[Integration.scala:37:21] wire _dis_io_mem_valid; // @[Integration.scala:37:21] wire [15:0] _dis_io_mem_bits_debug_id; // @[Integration.scala:37:21] wire [11:0] _dis_io_mem_bits_base_offset; // @[Integration.scala:37:21] wire [19:0] _dis_io_mem_bits_page; // @[Integration.scala:37:21] wire [11:0] _dis_io_mem_bits_stride; // @[Integration.scala:37:21] wire [2:0] _dis_io_mem_bits_segstart; // @[Integration.scala:37:21] wire [2:0] _dis_io_mem_bits_segend; // @[Integration.scala:37:21] wire [7:0] _dis_io_mem_bits_vstart; // @[Integration.scala:37:21] wire [8:0] _dis_io_mem_bits_vl; // @[Integration.scala:37:21] wire [1:0] _dis_io_mem_bits_mop; // @[Integration.scala:37:21] wire _dis_io_mem_bits_vm; // @[Integration.scala:37:21] wire [2:0] _dis_io_mem_bits_nf; // @[Integration.scala:37:21] wire [1:0] _dis_io_mem_bits_idx_size; // @[Integration.scala:37:21] wire [1:0] _dis_io_mem_bits_elem_size; // @[Integration.scala:37:21] wire _dis_io_mem_bits_whole_reg; // @[Integration.scala:37:21] wire _dis_io_mem_bits_store; // @[Integration.scala:37:21] wire _dis_io_dis_valid; // @[Integration.scala:37:21] wire [31:0] _dis_io_dis_bits_bits; // @[Integration.scala:37:21] wire [8:0] _dis_io_dis_bits_vconfig_vl; // @[Integration.scala:37:21] wire [2:0] _dis_io_dis_bits_vconfig_vtype_vsew; // @[Integration.scala:37:21] wire _dis_io_dis_bits_vconfig_vtype_vlmul_sign; // @[Integration.scala:37:21] wire [1:0] _dis_io_dis_bits_vconfig_vtype_vlmul_mag; // @[Integration.scala:37:21] wire [7:0] _dis_io_dis_bits_vstart; // @[Integration.scala:37:21] wire [2:0] _dis_io_dis_bits_segstart; // @[Integration.scala:37:21] wire [2:0] _dis_io_dis_bits_segend; // @[Integration.scala:37:21] wire [63:0] _dis_io_dis_bits_rs1_data; // @[Integration.scala:37:21] wire [4:0] _dis_io_dis_bits_vat; // @[Integration.scala:37:21] wire [2:0] _dis_io_dis_bits_rm; // @[Integration.scala:37:21] wire [1:0] _dis_io_dis_bits_emul; // @[Integration.scala:37:21] wire [15:0] _dis_io_dis_bits_debug_id; // @[Integration.scala:37:21] wire [1:0] _dis_io_dis_bits_mop; // @[Integration.scala:37:21] wire _dis_io_scalar_resp_valid; // @[Integration.scala:37:21] wire [63:0] _dis_io_scalar_resp_bits_data; // @[Integration.scala:37:21] wire [4:0] _dis_io_scalar_resp_bits_rd; // @[Integration.scala:37:21] wire [4:0] _dis_io_vat_head; // @[Integration.scala:37:21] wire [4:0] _dis_io_vat_tail; // @[Integration.scala:37:21] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [4:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [127:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _tl_if_auto_arb_anon_out_a_valid; // @[Integration.scala:25:25] wire [2:0] _tl_if_auto_arb_anon_out_a_bits_opcode; // @[Integration.scala:25:25] wire [3:0] _tl_if_auto_arb_anon_out_a_bits_size; // @[Integration.scala:25:25] wire [4:0] _tl_if_auto_arb_anon_out_a_bits_source; // @[Integration.scala:25:25] wire [31:0] _tl_if_auto_arb_anon_out_a_bits_address; // @[Integration.scala:25:25] wire [15:0] _tl_if_auto_arb_anon_out_a_bits_mask; // @[Integration.scala:25:25] wire [127:0] _tl_if_auto_arb_anon_out_a_bits_data; // @[Integration.scala:25:25] wire _tl_if_auto_arb_anon_out_d_ready; // @[Integration.scala:25:25] wire _tl_if_io_vec_load_req_ready; // @[Integration.scala:25:25] wire _tl_if_io_vec_load_resp_valid; // @[Integration.scala:25:25] wire [127:0] _tl_if_io_vec_load_resp_bits_data; // @[Integration.scala:25:25] wire [3:0] _tl_if_io_vec_load_resp_bits_tag; // @[Integration.scala:25:25] wire _tl_if_io_vec_store_req_ready; // @[Integration.scala:25:25] wire _tl_if_io_vec_store_ack_valid; // @[Integration.scala:25:25] wire [3:0] _tl_if_io_vec_store_ack_bits_tag; // @[Integration.scala:25:25] wire _tl_if_io_mem_busy; // @[Integration.scala:25:25] TLSplitInterface tl_if ( // @[Integration.scala:25:25] .clock (clock), .reset (reset), .auto_arb_anon_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_arb_anon_out_a_valid (_tl_if_auto_arb_anon_out_a_valid), .auto_arb_anon_out_a_bits_opcode (_tl_if_auto_arb_anon_out_a_bits_opcode), .auto_arb_anon_out_a_bits_size (_tl_if_auto_arb_anon_out_a_bits_size), .auto_arb_anon_out_a_bits_source (_tl_if_auto_arb_anon_out_a_bits_source), .auto_arb_anon_out_a_bits_address (_tl_if_auto_arb_anon_out_a_bits_address), .auto_arb_anon_out_a_bits_mask (_tl_if_auto_arb_anon_out_a_bits_mask), .auto_arb_anon_out_a_bits_data (_tl_if_auto_arb_anon_out_a_bits_data), .auto_arb_anon_out_d_ready (_tl_if_auto_arb_anon_out_d_ready), .auto_arb_anon_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_arb_anon_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28] .io_vec_load_req_ready (_tl_if_io_vec_load_req_ready), .io_vec_load_req_valid (_vmu_io_dmem_load_req_valid), // @[Integration.scala:41:21] .io_vec_load_req_bits_addr (_vmu_io_dmem_load_req_bits_addr), // @[Integration.scala:41:21] .io_vec_load_req_bits_tag (_vmu_io_dmem_load_req_bits_tag), // @[Integration.scala:41:21] .io_vec_load_resp_valid (_tl_if_io_vec_load_resp_valid), .io_vec_load_resp_bits_data (_tl_if_io_vec_load_resp_bits_data), .io_vec_load_resp_bits_tag (_tl_if_io_vec_load_resp_bits_tag), .io_vec_store_req_ready (_tl_if_io_vec_store_req_ready), .io_vec_store_req_valid (_vmu_io_dmem_store_req_valid), // @[Integration.scala:41:21] .io_vec_store_req_bits_addr (_vmu_io_dmem_store_req_bits_addr), // @[Integration.scala:41:21] .io_vec_store_req_bits_data (_vmu_io_dmem_store_req_bits_data), // @[Integration.scala:41:21] .io_vec_store_req_bits_mask (_vmu_io_dmem_store_req_bits_mask), // @[Integration.scala:41:21] .io_vec_store_req_bits_tag (_vmu_io_dmem_store_req_bits_tag), // @[Integration.scala:41:21] .io_vec_store_ack_valid (_tl_if_io_vec_store_ack_valid), .io_vec_store_ack_bits_tag (_tl_if_io_vec_store_ack_bits_tag), .io_mem_busy (_tl_if_io_mem_busy) ); // @[Integration.scala:25:25] TLBuffer_a32d128s5k4z4u buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_tl_if_auto_arb_anon_out_a_valid), // @[Integration.scala:25:25] .auto_in_a_bits_opcode (_tl_if_auto_arb_anon_out_a_bits_opcode), // @[Integration.scala:25:25] .auto_in_a_bits_size (_tl_if_auto_arb_anon_out_a_bits_size), // @[Integration.scala:25:25] .auto_in_a_bits_source (_tl_if_auto_arb_anon_out_a_bits_source), // @[Integration.scala:25:25] .auto_in_a_bits_address (_tl_if_auto_arb_anon_out_a_bits_address), // @[Integration.scala:25:25] .auto_in_a_bits_mask (_tl_if_auto_arb_anon_out_a_bits_mask), // @[Integration.scala:25:25] .auto_in_a_bits_data (_tl_if_auto_arb_anon_out_a_bits_data), // @[Integration.scala:25:25] .auto_in_d_ready (_tl_if_auto_arb_anon_out_d_ready), // @[Integration.scala:25:25] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (auto_atl_out_a_ready), .auto_out_a_valid (auto_atl_out_a_valid), .auto_out_a_bits_opcode (auto_atl_out_a_bits_opcode), .auto_out_a_bits_param (auto_atl_out_a_bits_param), .auto_out_a_bits_size (auto_atl_out_a_bits_size), .auto_out_a_bits_source (auto_atl_out_a_bits_source), .auto_out_a_bits_address (auto_atl_out_a_bits_address), .auto_out_a_bits_mask (auto_atl_out_a_bits_mask), .auto_out_a_bits_data (auto_atl_out_a_bits_data), .auto_out_a_bits_corrupt (auto_atl_out_a_bits_corrupt), .auto_out_d_ready (auto_atl_out_d_ready), .auto_out_d_valid (auto_atl_out_d_valid), .auto_out_d_bits_opcode (auto_atl_out_d_bits_opcode), .auto_out_d_bits_param (auto_atl_out_d_bits_param), .auto_out_d_bits_size (auto_atl_out_d_bits_size), .auto_out_d_bits_source (auto_atl_out_d_bits_source), .auto_out_d_bits_sink (auto_atl_out_d_bits_sink), .auto_out_d_bits_denied (auto_atl_out_d_bits_denied), .auto_out_d_bits_data (auto_atl_out_d_bits_data), .auto_out_d_bits_corrupt (auto_atl_out_d_bits_corrupt) ); // @[Buffer.scala:75:28] VectorDispatcher dis ( // @[Integration.scala:37:21] .clock (clock), .reset (reset), .io_issue_ready (_dis_io_issue_ready), .io_issue_valid (_vfu_io_issue_valid), // @[Integration.scala:39:21] .io_issue_bits_bits (_vfu_io_issue_bits_bits), // @[Integration.scala:39:21] .io_issue_bits_vconfig_vl (_vfu_io_issue_bits_vconfig_vl), // @[Integration.scala:39:21] .io_issue_bits_vconfig_vtype_vsew (_vfu_io_issue_bits_vconfig_vtype_vsew), // @[Integration.scala:39:21] .io_issue_bits_vconfig_vtype_vlmul_sign (_vfu_io_issue_bits_vconfig_vtype_vlmul_sign), // @[Integration.scala:39:21] .io_issue_bits_vconfig_vtype_vlmul_mag (_vfu_io_issue_bits_vconfig_vtype_vlmul_mag), // @[Integration.scala:39:21] .io_issue_bits_vstart (_vfu_io_issue_bits_vstart), // @[Integration.scala:39:21] .io_issue_bits_segstart (_vfu_io_issue_bits_segstart), // @[Integration.scala:39:21] .io_issue_bits_segend (_vfu_io_issue_bits_segend), // @[Integration.scala:39:21] .io_issue_bits_rs1_data (_vfu_io_issue_bits_rs1_data), // @[Integration.scala:39:21] .io_issue_bits_rs2_data (_vfu_io_issue_bits_rs2_data), // @[Integration.scala:39:21] .io_issue_bits_page (_vfu_io_issue_bits_page), // @[Integration.scala:39:21] .io_issue_bits_rm (_vfu_io_issue_bits_rm), // @[Integration.scala:39:21] .io_issue_bits_emul (_vfu_io_issue_bits_emul), // @[Integration.scala:39:21] .io_issue_bits_mop (_vfu_io_issue_bits_mop), // @[Integration.scala:39:21] .io_mem_ready (_vmu_io_enq_ready), // @[Integration.scala:41:21] .io_mem_valid (_dis_io_mem_valid), .io_mem_bits_debug_id (_dis_io_mem_bits_debug_id), .io_mem_bits_base_offset (_dis_io_mem_bits_base_offset), .io_mem_bits_page (_dis_io_mem_bits_page), .io_mem_bits_stride (_dis_io_mem_bits_stride), .io_mem_bits_segstart (_dis_io_mem_bits_segstart), .io_mem_bits_segend (_dis_io_mem_bits_segend), .io_mem_bits_vstart (_dis_io_mem_bits_vstart), .io_mem_bits_vl (_dis_io_mem_bits_vl), .io_mem_bits_mop (_dis_io_mem_bits_mop), .io_mem_bits_vm (_dis_io_mem_bits_vm), .io_mem_bits_nf (_dis_io_mem_bits_nf), .io_mem_bits_idx_size (_dis_io_mem_bits_idx_size), .io_mem_bits_elem_size (_dis_io_mem_bits_elem_size), .io_mem_bits_whole_reg (_dis_io_mem_bits_whole_reg), .io_mem_bits_store (_dis_io_mem_bits_store), .io_dis_ready (_vu_io_dis_ready), // @[Integration.scala:40:20] .io_dis_valid (_dis_io_dis_valid), .io_dis_bits_bits (_dis_io_dis_bits_bits), .io_dis_bits_vconfig_vl (_dis_io_dis_bits_vconfig_vl), .io_dis_bits_vconfig_vtype_vsew (_dis_io_dis_bits_vconfig_vtype_vsew), .io_dis_bits_vconfig_vtype_vlmul_sign (_dis_io_dis_bits_vconfig_vtype_vlmul_sign), .io_dis_bits_vconfig_vtype_vlmul_mag (_dis_io_dis_bits_vconfig_vtype_vlmul_mag), .io_dis_bits_vstart (_dis_io_dis_bits_vstart), .io_dis_bits_segstart (_dis_io_dis_bits_segstart), .io_dis_bits_segend (_dis_io_dis_bits_segend), .io_dis_bits_rs1_data (_dis_io_dis_bits_rs1_data), .io_dis_bits_vat (_dis_io_dis_bits_vat), .io_dis_bits_rm (_dis_io_dis_bits_rm), .io_dis_bits_emul (_dis_io_dis_bits_emul), .io_dis_bits_debug_id (_dis_io_dis_bits_debug_id), .io_dis_bits_mop (_dis_io_dis_bits_mop), .io_scalar_resp_ready (_scalar_arb_io_in_1_ready), // @[Integration.scala:38:28] .io_scalar_resp_valid (_dis_io_scalar_resp_valid), .io_scalar_resp_bits_data (_dis_io_scalar_resp_bits_data), .io_scalar_resp_bits_rd (_dis_io_scalar_resp_bits_rd), .io_vat_release_0_valid (_vu_io_vat_release_0_valid), // @[Integration.scala:40:20] .io_vat_release_0_bits (_vu_io_vat_release_0_bits), // @[Integration.scala:40:20] .io_vat_release_1_valid (_vu_io_vat_release_1_valid), // @[Integration.scala:40:20] .io_vat_release_1_bits (_vu_io_vat_release_1_bits), // @[Integration.scala:40:20] .io_vat_release_2_valid (_vu_io_vat_release_2_valid), // @[Integration.scala:40:20] .io_vat_release_2_bits (_vu_io_vat_release_2_bits), // @[Integration.scala:40:20] .io_vat_release_3_valid (_vu_io_vat_release_3_valid), // @[Integration.scala:40:20] .io_vat_release_3_bits (_vu_io_vat_release_3_bits), // @[Integration.scala:40:20] .io_vat_head (_dis_io_vat_head), .io_vat_tail (_dis_io_vat_tail) ); // @[Integration.scala:37:21] Arbiter2_ScalarWrite scalar_arb ( // @[Integration.scala:38:28] .io_in_0_ready (_scalar_arb_io_in_0_ready), .io_in_0_valid (_vu_io_scalar_resp_valid), // @[Integration.scala:40:20] .io_in_0_bits_data (_vu_io_scalar_resp_bits_data), // @[Integration.scala:40:20] .io_in_0_bits_fp (_vu_io_scalar_resp_bits_fp), // @[Integration.scala:40:20] .io_in_0_bits_size (_vu_io_scalar_resp_bits_size), // @[Integration.scala:40:20] .io_in_0_bits_rd (_vu_io_scalar_resp_bits_rd), // @[Integration.scala:40:20] .io_in_1_ready (_scalar_arb_io_in_1_ready), .io_in_1_valid (_dis_io_scalar_resp_valid), // @[Integration.scala:37:21] .io_in_1_bits_data (_dis_io_scalar_resp_bits_data), // @[Integration.scala:37:21] .io_in_1_bits_size (2'h3), // @[Integration.scala:37:21, :38:28] .io_in_1_bits_rd (_dis_io_scalar_resp_bits_rd), // @[Integration.scala:37:21] .io_out_ready (_io_resp_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_out_valid (_scalar_arb_io_out_valid), .io_out_bits_data (_scalar_arb_io_out_bits_data), .io_out_bits_fp (_scalar_arb_io_out_bits_fp), .io_out_bits_size (_scalar_arb_io_out_bits_size), .io_out_bits_rd (_scalar_arb_io_out_bits_rd) ); // @[Integration.scala:38:28] SaturnShuttleFrontend vfu ( // @[Integration.scala:39:21] .clock (clock), .reset (reset), .io_core_status_prv (io_status_prv), .io_core_ex_valid (io_ex_valid), .io_core_ex_uop_inst (io_ex_uop_inst), .io_core_ex_uop_pc (io_ex_uop_pc), .io_core_ex_uop_rs1_data (io_ex_uop_rs1_data), .io_core_ex_uop_rs2_data (io_ex_uop_rs2_data), .io_core_ex_vconfig_vl (io_ex_vconfig_vl), .io_core_ex_vconfig_vtype_vill (io_ex_vconfig_vtype_vill), .io_core_ex_vconfig_vtype_reserved (io_ex_vconfig_vtype_reserved), .io_core_ex_vconfig_vtype_vma (io_ex_vconfig_vtype_vma), .io_core_ex_vconfig_vtype_vta (io_ex_vconfig_vtype_vta), .io_core_ex_vconfig_vtype_vsew (io_ex_vconfig_vtype_vsew), .io_core_ex_vconfig_vtype_vlmul_sign (io_ex_vconfig_vtype_vlmul_sign), .io_core_ex_vconfig_vtype_vlmul_mag (io_ex_vconfig_vtype_vlmul_mag), .io_core_ex_vstart (io_ex_vstart), .io_core_ex_ready (io_ex_ready), .io_core_ex_fire (io_ex_fire), .io_core_mem_kill (io_mem_kill), .io_core_mem_tlb_req_ready (io_mem_tlb_req_ready), .io_core_mem_tlb_req_valid (io_mem_tlb_req_valid), .io_core_mem_tlb_req_bits_vaddr (io_mem_tlb_req_bits_vaddr), .io_core_mem_tlb_req_bits_size (io_mem_tlb_req_bits_size), .io_core_mem_tlb_req_bits_cmd (io_mem_tlb_req_bits_cmd), .io_core_mem_tlb_req_bits_prv (io_mem_tlb_req_bits_prv), .io_core_mem_tlb_resp_miss (io_mem_tlb_resp_miss), .io_core_mem_tlb_resp_paddr (io_mem_tlb_resp_paddr), .io_core_mem_tlb_resp_pf_ld (io_mem_tlb_resp_pf_ld), .io_core_mem_tlb_resp_pf_st (io_mem_tlb_resp_pf_st), .io_core_mem_tlb_resp_ae_ld (io_mem_tlb_resp_ae_ld), .io_core_mem_tlb_resp_ae_st (io_mem_tlb_resp_ae_st), .io_core_mem_tlb_resp_ma_ld (io_mem_tlb_resp_ma_ld), .io_core_mem_tlb_resp_ma_st (io_mem_tlb_resp_ma_st), .io_core_mem_frs1 (io_mem_frs1), .io_core_wb_store_pending (io_wb_store_pending), .io_core_wb_retire_late (io_wb_retire_late), .io_core_wb_pc (io_wb_pc), .io_core_wb_xcpt (io_wb_xcpt), .io_core_wb_cause (io_wb_cause), .io_core_wb_tval (io_wb_tval), .io_core_wb_vxrm (io_wb_vxrm), .io_core_wb_frm (io_wb_frm), .io_core_wb_scalar_check_ready (io_wb_scalar_check_ready), .io_core_wb_scalar_check_bits_addr (io_wb_scalar_check_bits_addr), .io_core_wb_scalar_check_bits_store (io_wb_scalar_check_bits_store), .io_core_wb_internal_replay (io_wb_internal_replay), .io_core_wb_block_all (io_wb_block_all), .io_core_set_vstart_valid (io_set_vstart_valid), .io_core_set_vstart_bits (io_set_vstart_bits), .io_core_set_vconfig_valid (io_set_vconfig_valid), .io_core_set_vconfig_bits_vl (io_set_vconfig_bits_vl), .io_core_set_vconfig_bits_vtype_vill (io_set_vconfig_bits_vtype_vill), .io_core_set_vconfig_bits_vtype_reserved (io_set_vconfig_bits_vtype_reserved), .io_core_set_vconfig_bits_vtype_vma (io_set_vconfig_bits_vtype_vma), .io_core_set_vconfig_bits_vtype_vta (io_set_vconfig_bits_vtype_vta), .io_core_set_vconfig_bits_vtype_vsew (io_set_vconfig_bits_vtype_vsew), .io_core_set_vconfig_bits_vtype_vlmul_sign (io_set_vconfig_bits_vtype_vlmul_sign), .io_core_set_vconfig_bits_vtype_vlmul_mag (io_set_vconfig_bits_vtype_vlmul_mag), .io_core_trap_check_busy (io_trap_check_busy), .io_issue_ready (_dis_io_issue_ready), // @[Integration.scala:37:21] .io_issue_valid (_vfu_io_issue_valid), .io_issue_bits_bits (_vfu_io_issue_bits_bits), .io_issue_bits_vconfig_vl (_vfu_io_issue_bits_vconfig_vl), .io_issue_bits_vconfig_vtype_vsew (_vfu_io_issue_bits_vconfig_vtype_vsew), .io_issue_bits_vconfig_vtype_vlmul_sign (_vfu_io_issue_bits_vconfig_vtype_vlmul_sign), .io_issue_bits_vconfig_vtype_vlmul_mag (_vfu_io_issue_bits_vconfig_vtype_vlmul_mag), .io_issue_bits_vstart (_vfu_io_issue_bits_vstart), .io_issue_bits_segstart (_vfu_io_issue_bits_segstart), .io_issue_bits_segend (_vfu_io_issue_bits_segend), .io_issue_bits_rs1_data (_vfu_io_issue_bits_rs1_data), .io_issue_bits_rs2_data (_vfu_io_issue_bits_rs2_data), .io_issue_bits_page (_vfu_io_issue_bits_page), .io_issue_bits_rm (_vfu_io_issue_bits_rm), .io_issue_bits_emul (_vfu_io_issue_bits_emul), .io_issue_bits_mop (_vfu_io_issue_bits_mop), .io_index_access_ready (_vu_io_index_access_ready), // @[Integration.scala:40:20] .io_index_access_valid (_vfu_io_index_access_valid), .io_index_access_vrs (_vfu_io_index_access_vrs), .io_index_access_eidx (_vfu_io_index_access_eidx), .io_index_access_eew (_vfu_io_index_access_eew), .io_index_access_idx (_vu_io_index_access_idx), // @[Integration.scala:40:20] .io_mask_access_ready (_vu_io_mask_access_ready), // @[Integration.scala:40:20] .io_mask_access_valid (_vfu_io_mask_access_valid), .io_mask_access_eidx (_vfu_io_mask_access_eidx), .io_mask_access_mask (_vu_io_mask_access_mask), // @[Integration.scala:40:20] .io_scalar_check_addr (_vfu_io_scalar_check_addr), .io_scalar_check_store (_vfu_io_scalar_check_store), .io_scalar_check_conflict (_vmu_io_scalar_check_conflict) // @[Integration.scala:41:21] ); // @[Integration.scala:39:21] VectorBackend vu ( // @[Integration.scala:40:20] .clock (clock), .reset (reset), .io_dis_ready (_vu_io_dis_ready), .io_dis_valid (_dis_io_dis_valid), // @[Integration.scala:37:21] .io_dis_bits_bits (_dis_io_dis_bits_bits), // @[Integration.scala:37:21] .io_dis_bits_vconfig_vl (_dis_io_dis_bits_vconfig_vl), // @[Integration.scala:37:21] .io_dis_bits_vconfig_vtype_vsew (_dis_io_dis_bits_vconfig_vtype_vsew), // @[Integration.scala:37:21] .io_dis_bits_vconfig_vtype_vlmul_sign (_dis_io_dis_bits_vconfig_vtype_vlmul_sign), // @[Integration.scala:37:21] .io_dis_bits_vconfig_vtype_vlmul_mag (_dis_io_dis_bits_vconfig_vtype_vlmul_mag), // @[Integration.scala:37:21] .io_dis_bits_vstart (_dis_io_dis_bits_vstart), // @[Integration.scala:37:21] .io_dis_bits_segstart (_dis_io_dis_bits_segstart), // @[Integration.scala:37:21] .io_dis_bits_segend (_dis_io_dis_bits_segend), // @[Integration.scala:37:21] .io_dis_bits_rs1_data (_dis_io_dis_bits_rs1_data), // @[Integration.scala:37:21] .io_dis_bits_vat (_dis_io_dis_bits_vat), // @[Integration.scala:37:21] .io_dis_bits_rm (_dis_io_dis_bits_rm), // @[Integration.scala:37:21] .io_dis_bits_emul (_dis_io_dis_bits_emul), // @[Integration.scala:37:21] .io_dis_bits_debug_id (_dis_io_dis_bits_debug_id), // @[Integration.scala:37:21] .io_dis_bits_mop (_dis_io_dis_bits_mop), // @[Integration.scala:37:21] .io_vmu_lresp_ready (_vu_io_vmu_lresp_ready), .io_vmu_lresp_valid (_vmu_io_vu_lresp_valid), // @[Integration.scala:41:21] .io_vmu_lresp_bits_data (_vmu_io_vu_lresp_bits_data), // @[Integration.scala:41:21] .io_vmu_lresp_bits_debug_id (_vmu_io_vu_lresp_bits_debug_id), // @[Integration.scala:41:21] .io_vmu_sdata_ready (_vmu_io_vu_sdata_ready), // @[Integration.scala:41:21] .io_vmu_sdata_valid (_vu_io_vmu_sdata_valid), .io_vmu_sdata_bits_stdata (_vu_io_vmu_sdata_bits_stdata), .io_vmu_sdata_bits_stmask (_vu_io_vmu_sdata_bits_stmask), .io_vmu_sdata_bits_debug_id (_vu_io_vmu_sdata_bits_debug_id), .io_vmu_mask_pop_ready (_vu_io_vmu_mask_pop_ready), .io_vmu_mask_pop_valid (_vmu_io_vu_mask_pop_valid), // @[Integration.scala:41:21] .io_vmu_mask_data_0 (_vu_io_vmu_mask_data_0), .io_vmu_index_pop_ready (_vu_io_vmu_index_pop_ready), .io_vmu_index_pop_valid (_vmu_io_vu_index_pop_valid), // @[Integration.scala:41:21] .io_vmu_index_pop_bits_tail (_vmu_io_vu_index_pop_bits_tail), // @[Integration.scala:41:21] .io_vmu_index_data_0 (_vu_io_vmu_index_data_0), .io_vmu_index_data_1 (_vu_io_vmu_index_data_1), .io_vmu_index_data_2 (_vu_io_vmu_index_data_2), .io_vmu_index_data_3 (_vu_io_vmu_index_data_3), .io_vmu_index_data_4 (_vu_io_vmu_index_data_4), .io_vmu_index_data_5 (_vu_io_vmu_index_data_5), .io_vmu_index_data_6 (_vu_io_vmu_index_data_6), .io_vmu_index_data_7 (_vu_io_vmu_index_data_7), .io_vmu_index_data_8 (_vu_io_vmu_index_data_8), .io_vmu_index_data_9 (_vu_io_vmu_index_data_9), .io_vmu_index_data_10 (_vu_io_vmu_index_data_10), .io_vmu_index_data_11 (_vu_io_vmu_index_data_11), .io_vmu_index_data_12 (_vu_io_vmu_index_data_12), .io_vmu_index_data_13 (_vu_io_vmu_index_data_13), .io_vmu_index_data_14 (_vu_io_vmu_index_data_14), .io_vmu_index_data_15 (_vu_io_vmu_index_data_15), .io_busy (_vu_io_busy), .io_index_access_ready (_vu_io_index_access_ready), .io_index_access_valid (_vfu_io_index_access_valid), // @[Integration.scala:39:21] .io_index_access_vrs (_vfu_io_index_access_vrs), // @[Integration.scala:39:21] .io_index_access_eidx (_vfu_io_index_access_eidx), // @[Integration.scala:39:21] .io_index_access_eew (_vfu_io_index_access_eew), // @[Integration.scala:39:21] .io_index_access_idx (_vu_io_index_access_idx), .io_mask_access_ready (_vu_io_mask_access_ready), .io_mask_access_valid (_vfu_io_mask_access_valid), // @[Integration.scala:39:21] .io_mask_access_eidx (_vfu_io_mask_access_eidx), // @[Integration.scala:39:21] .io_mask_access_mask (_vu_io_mask_access_mask), .io_scalar_resp_ready (_scalar_arb_io_in_0_ready), // @[Integration.scala:38:28] .io_scalar_resp_valid (_vu_io_scalar_resp_valid), .io_scalar_resp_bits_data (_vu_io_scalar_resp_bits_data), .io_scalar_resp_bits_fp (_vu_io_scalar_resp_bits_fp), .io_scalar_resp_bits_size (_vu_io_scalar_resp_bits_size), .io_scalar_resp_bits_rd (_vu_io_scalar_resp_bits_rd), .io_set_vxsat (io_set_vxsat), .io_set_fflags_valid (io_set_fflags_valid), .io_set_fflags_bits (io_set_fflags_bits), .io_vat_tail (_dis_io_vat_tail), // @[Integration.scala:37:21] .io_vat_head (_dis_io_vat_head), // @[Integration.scala:37:21] .io_vat_release_0_valid (_vu_io_vat_release_0_valid), .io_vat_release_0_bits (_vu_io_vat_release_0_bits), .io_vat_release_1_valid (_vu_io_vat_release_1_valid), .io_vat_release_1_bits (_vu_io_vat_release_1_bits), .io_vat_release_2_valid (_vu_io_vat_release_2_valid), .io_vat_release_2_bits (_vu_io_vat_release_2_bits), .io_vat_release_3_valid (_vu_io_vat_release_3_valid), .io_vat_release_3_bits (_vu_io_vat_release_3_bits) ); // @[Integration.scala:40:20] VectorMemUnit vmu ( // @[Integration.scala:41:21] .clock (clock), .reset (reset), .io_enq_ready (_vmu_io_enq_ready), .io_enq_valid (_dis_io_mem_valid), // @[Integration.scala:37:21] .io_enq_bits_debug_id (_dis_io_mem_bits_debug_id), // @[Integration.scala:37:21] .io_enq_bits_base_offset (_dis_io_mem_bits_base_offset), // @[Integration.scala:37:21] .io_enq_bits_page (_dis_io_mem_bits_page), // @[Integration.scala:37:21] .io_enq_bits_stride (_dis_io_mem_bits_stride), // @[Integration.scala:37:21] .io_enq_bits_segstart (_dis_io_mem_bits_segstart), // @[Integration.scala:37:21] .io_enq_bits_segend (_dis_io_mem_bits_segend), // @[Integration.scala:37:21] .io_enq_bits_vstart (_dis_io_mem_bits_vstart), // @[Integration.scala:37:21] .io_enq_bits_vl (_dis_io_mem_bits_vl), // @[Integration.scala:37:21] .io_enq_bits_mop (_dis_io_mem_bits_mop), // @[Integration.scala:37:21] .io_enq_bits_vm (_dis_io_mem_bits_vm), // @[Integration.scala:37:21] .io_enq_bits_nf (_dis_io_mem_bits_nf), // @[Integration.scala:37:21] .io_enq_bits_idx_size (_dis_io_mem_bits_idx_size), // @[Integration.scala:37:21] .io_enq_bits_elem_size (_dis_io_mem_bits_elem_size), // @[Integration.scala:37:21] .io_enq_bits_whole_reg (_dis_io_mem_bits_whole_reg), // @[Integration.scala:37:21] .io_enq_bits_store (_dis_io_mem_bits_store), // @[Integration.scala:37:21] .io_dmem_load_req_ready (_tl_if_io_vec_load_req_ready), // @[Integration.scala:25:25] .io_dmem_load_req_valid (_vmu_io_dmem_load_req_valid), .io_dmem_load_req_bits_addr (_vmu_io_dmem_load_req_bits_addr), .io_dmem_load_req_bits_tag (_vmu_io_dmem_load_req_bits_tag), .io_dmem_load_resp_valid (_tl_if_io_vec_load_resp_valid), // @[Integration.scala:25:25] .io_dmem_load_resp_bits_data (_tl_if_io_vec_load_resp_bits_data), // @[Integration.scala:25:25] .io_dmem_load_resp_bits_tag (_tl_if_io_vec_load_resp_bits_tag), // @[Integration.scala:25:25] .io_dmem_store_req_ready (_tl_if_io_vec_store_req_ready), // @[Integration.scala:25:25] .io_dmem_store_req_valid (_vmu_io_dmem_store_req_valid), .io_dmem_store_req_bits_addr (_vmu_io_dmem_store_req_bits_addr), .io_dmem_store_req_bits_data (_vmu_io_dmem_store_req_bits_data), .io_dmem_store_req_bits_mask (_vmu_io_dmem_store_req_bits_mask), .io_dmem_store_req_bits_tag (_vmu_io_dmem_store_req_bits_tag), .io_dmem_store_ack_valid (_tl_if_io_vec_store_ack_valid), // @[Integration.scala:25:25] .io_dmem_store_ack_bits_tag (_tl_if_io_vec_store_ack_bits_tag), // @[Integration.scala:25:25] .io_scalar_check_addr (_vfu_io_scalar_check_addr), // @[Integration.scala:39:21] .io_scalar_check_store (_vfu_io_scalar_check_store), // @[Integration.scala:39:21] .io_scalar_check_conflict (_vmu_io_scalar_check_conflict), .io_vu_lresp_ready (_vu_io_vmu_lresp_ready), // @[Integration.scala:40:20] .io_vu_lresp_valid (_vmu_io_vu_lresp_valid), .io_vu_lresp_bits_data (_vmu_io_vu_lresp_bits_data), .io_vu_lresp_bits_debug_id (_vmu_io_vu_lresp_bits_debug_id), .io_vu_sdata_ready (_vmu_io_vu_sdata_ready), .io_vu_sdata_valid (_vu_io_vmu_sdata_valid), // @[Integration.scala:40:20] .io_vu_sdata_bits_stdata (_vu_io_vmu_sdata_bits_stdata), // @[Integration.scala:40:20] .io_vu_sdata_bits_stmask (_vu_io_vmu_sdata_bits_stmask), // @[Integration.scala:40:20] .io_vu_sdata_bits_debug_id (_vu_io_vmu_sdata_bits_debug_id), // @[Integration.scala:40:20] .io_vu_mask_pop_ready (_vu_io_vmu_mask_pop_ready), // @[Integration.scala:40:20] .io_vu_mask_pop_valid (_vmu_io_vu_mask_pop_valid), .io_vu_mask_data_0 (_vu_io_vmu_mask_data_0), // @[Integration.scala:40:20] .io_vu_index_pop_ready (_vu_io_vmu_index_pop_ready), // @[Integration.scala:40:20] .io_vu_index_pop_valid (_vmu_io_vu_index_pop_valid), .io_vu_index_pop_bits_tail (_vmu_io_vu_index_pop_bits_tail), .io_vu_index_data_0 (_vu_io_vmu_index_data_0), // @[Integration.scala:40:20] .io_vu_index_data_1 (_vu_io_vmu_index_data_1), // @[Integration.scala:40:20] .io_vu_index_data_2 (_vu_io_vmu_index_data_2), // @[Integration.scala:40:20] .io_vu_index_data_3 (_vu_io_vmu_index_data_3), // @[Integration.scala:40:20] .io_vu_index_data_4 (_vu_io_vmu_index_data_4), // @[Integration.scala:40:20] .io_vu_index_data_5 (_vu_io_vmu_index_data_5), // @[Integration.scala:40:20] .io_vu_index_data_6 (_vu_io_vmu_index_data_6), // @[Integration.scala:40:20] .io_vu_index_data_7 (_vu_io_vmu_index_data_7), // @[Integration.scala:40:20] .io_vu_index_data_8 (_vu_io_vmu_index_data_8), // @[Integration.scala:40:20] .io_vu_index_data_9 (_vu_io_vmu_index_data_9), // @[Integration.scala:40:20] .io_vu_index_data_10 (_vu_io_vmu_index_data_10), // @[Integration.scala:40:20] .io_vu_index_data_11 (_vu_io_vmu_index_data_11), // @[Integration.scala:40:20] .io_vu_index_data_12 (_vu_io_vmu_index_data_12), // @[Integration.scala:40:20] .io_vu_index_data_13 (_vu_io_vmu_index_data_13), // @[Integration.scala:40:20] .io_vu_index_data_14 (_vu_io_vmu_index_data_14), // @[Integration.scala:40:20] .io_vu_index_data_15 (_vu_io_vmu_index_data_15), // @[Integration.scala:40:20] .io_busy (_vmu_io_busy) ); // @[Integration.scala:41:21] Queue2_ScalarWrite io_resp_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_io_resp_q_io_enq_ready), .io_enq_valid (_scalar_arb_io_out_valid), // @[Integration.scala:38:28] .io_enq_bits_data (_scalar_arb_io_out_bits_data), // @[Integration.scala:38:28] .io_enq_bits_fp (_scalar_arb_io_out_bits_fp), // @[Integration.scala:38:28] .io_enq_bits_size (_scalar_arb_io_out_bits_size), // @[Integration.scala:38:28] .io_enq_bits_rd (_scalar_arb_io_out_bits_rd), // @[Integration.scala:38:28] .io_deq_ready (io_resp_ready), .io_deq_valid (io_resp_valid), .io_deq_bits_data (io_resp_bits_data), .io_deq_bits_fp (io_resp_bits_fp), .io_deq_bits_size (io_resp_bits_size), .io_deq_bits_rd (io_resp_bits_rd) ); // @[Decoupled.scala:362:21] assign io_backend_busy = _vu_io_busy | _tl_if_io_mem_busy | _vmu_io_busy; // @[Integration.scala:25:25, :35:9, :40:20, :41:21, :62:{37,119}] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_114( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_194 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_385( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_129 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }
module dataMems_118( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module Router_24( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_4_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_4_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_4_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_4_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_4_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_4_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_4_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_4_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_4_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_4_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_4_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_4_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_4_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_4_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_4_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_4_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_4_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_4_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_4_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_4_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_4_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_4_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_4_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_4_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_4_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_7; // @[Router.scala:136:32] wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_4_0_valid; // @[Router.scala:131:24] wire _switch_io_out_4_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_4_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_4_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_4_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_4_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_4_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_4_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_4_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_4_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_3_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_4_to_30_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_30_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_27_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_25_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_22_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_10_io_channel_status_7_occupied; // @[Router.scala:122:13] wire [2:0] _input_unit_4_from_30_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_4_from_30_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_4_from_30_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_4_from_30_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_4_from_30_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_4_from_30_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_4_from_30_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_4_from_30_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_4_from_30_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_4_from_30_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_4_from_30_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_4_from_30_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_4_from_30_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_4_from_30_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_27_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_27_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_27_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_27_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_27_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_27_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_3_from_27_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_3_from_27_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_27_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_27_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_27_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_27_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_27_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_27_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_25_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_25_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_25_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_25_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_25_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_25_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_25_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_25_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_25_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_25_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_25_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_25_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_25_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_25_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_22_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_22_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_22_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_22_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_22_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_22_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_22_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_22_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_22_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_22_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_22_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_22_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_22_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_22_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_10_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_10_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_10_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_10_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_10_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_10_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_10_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_10_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_10_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_10_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_10_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_10_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_10_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_10_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_10_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_22_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_25_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _input_unit_3_from_27_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_4_ready & _input_unit_4_from_30_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_4_0_4_0; // @[Router.scala:178:14] reg REG_4_0_3_0; // @[Router.scala:178:14] reg REG_4_0_2_0; // @[Router.scala:178:14] reg REG_4_0_1_0; // @[Router.scala:178:14] reg REG_4_0_0_0; // @[Router.scala:178:14] reg REG_3_0_4_0; // @[Router.scala:178:14] reg REG_3_0_3_0; // @[Router.scala:178:14] reg REG_3_0_2_0; // @[Router.scala:178:14] reg REG_3_0_1_0; // @[Router.scala:178:14] reg REG_3_0_0_0; // @[Router.scala:178:14] reg REG_2_0_4_0; // @[Router.scala:178:14] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_4_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_4_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid || io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 || nBanks == 2 || nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }
module RegisterReadXbar_1( // @[RegisterFile.scala:27:7] output io_in_0_req_ready, // @[RegisterFile.scala:28:14] input io_in_0_req_valid, // @[RegisterFile.scala:28:14] input [5:0] io_in_0_req_bits_eg, // @[RegisterFile.scala:28:14] input io_in_0_req_bits_oldest, // @[RegisterFile.scala:28:14] output [63:0] io_in_0_resp, // @[RegisterFile.scala:28:14] input io_out_0_req_ready, // @[RegisterFile.scala:28:14] output io_out_0_req_valid, // @[RegisterFile.scala:28:14] output [5:0] io_out_0_req_bits_eg, // @[RegisterFile.scala:28:14] input [63:0] io_out_0_resp, // @[RegisterFile.scala:28:14] input io_out_1_req_ready, // @[RegisterFile.scala:28:14] output io_out_1_req_valid, // @[RegisterFile.scala:28:14] output [5:0] io_out_1_req_bits_eg, // @[RegisterFile.scala:28:14] input [63:0] io_out_1_resp // @[RegisterFile.scala:28:14] ); wire _arbs_1_io_in_0_ready; // @[RegisterFile.scala:33:38] wire _arbs_0_io_in_0_ready; // @[RegisterFile.scala:33:38] wire [5:0] arbs_1_io_in_0_bits_eg = {1'h0, io_in_0_req_bits_eg[5:1]}; // @[RegisterFile.scala:44:{32,56}] OldestRRArbiter_2 arbs_0 ( // @[RegisterFile.scala:33:38] .io_in_0_ready (_arbs_0_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & ~(io_in_0_req_bits_eg[0])), // @[RegisterFile.scala:41:82, :43:{52,63}] .io_in_0_bits_eg (arbs_1_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_out_ready (io_out_0_req_ready), .io_out_valid (io_out_0_req_valid), .io_out_bits_eg (io_out_0_req_bits_eg) ); // @[RegisterFile.scala:33:38] OldestRRArbiter_2 arbs_1 ( // @[RegisterFile.scala:33:38] .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (io_in_0_req_valid & io_in_0_req_bits_eg[0]), // @[RegisterFile.scala:41:82, :43:52] .io_in_0_bits_eg (arbs_1_io_in_0_bits_eg), // @[RegisterFile.scala:44:32] .io_in_0_bits_oldest (io_in_0_req_bits_oldest), .io_out_ready (io_out_1_req_ready), .io_out_valid (io_out_1_req_valid), .io_out_bits_eg (io_out_1_req_bits_eg) ); // @[RegisterFile.scala:33:38] assign io_in_0_req_ready = ~(io_in_0_req_bits_eg[0]) & _arbs_0_io_in_0_ready | io_in_0_req_bits_eg[0] & _arbs_1_io_in_0_ready; // @[Mux.scala:30:73] assign io_in_0_resp = (io_in_0_req_bits_eg[0] ? 64'h0 : io_out_0_resp) | (io_in_0_req_bits_eg[0] ? io_out_1_resp : 64'h0); // @[Mux.scala:30:73] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }
module IssueSlot_84( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_429( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_173 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_36( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [9:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [9:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_117 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_123 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_129 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_165 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_167 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_171 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_173 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_177 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_179 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_183 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_185 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_189 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_191 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_195 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_197 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_201 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_203 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_207 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_209 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_213 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_215 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_219 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_221 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_225 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_227 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_231 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_233 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_237 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_239 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_243 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_245 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_249 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_251 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_255 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_257 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_261 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_263 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_267 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_269 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_273 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_275 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_279 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_281 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_285 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_287 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_291 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_293 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [9:0] _c_first_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_first_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_first_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_first_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_set_wo_ready_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_set_wo_ready_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_opcodes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_opcodes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_sizes_set_interm_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_sizes_set_interm_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_opcodes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_opcodes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_sizes_set_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_sizes_set_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_probe_ack_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_probe_ack_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _c_probe_ack_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _c_probe_ack_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_1_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_2_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_3_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [9:0] _same_cycle_resp_WIRE_4_bits_source = 10'h0; // @[Bundles.scala:265:74] wire [9:0] _same_cycle_resp_WIRE_5_bits_source = 10'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [8195:0] _c_sizes_set_T_1 = 8196'h0; // @[Monitor.scala:768:52] wire [12:0] _c_opcodes_set_T = 13'h0; // @[Monitor.scala:767:79] wire [12:0] _c_sizes_set_T = 13'h0; // @[Monitor.scala:768:77] wire [8194:0] _c_opcodes_set_T_1 = 8195'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1023:0] _c_set_wo_ready_T = 1024'h1; // @[OneHot.scala:58:35] wire [1023:0] _c_set_T = 1024'h1; // @[OneHot.scala:58:35] wire [4103:0] c_sizes_set = 4104'h0; // @[Monitor.scala:741:34] wire [2051:0] c_opcodes_set = 2052'h0; // @[Monitor.scala:740:34] wire [512:0] c_set = 513'h0; // @[Monitor.scala:738:34] wire [512:0] c_set_wo_ready = 513'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [9:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_77 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_78 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_79 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_80 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_81 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_82 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_83 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_84 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_85 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_86 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_87 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_88 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_89 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_90 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_91 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_92 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_93 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_94 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_95 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_96 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_97 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_98 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_99 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_100 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_101 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_102 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_103 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_104 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_105 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_106 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_107 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_108 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_109 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_110 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_111 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_112 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_113 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_114 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_115 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_116 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_117 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_118 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_119 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_120 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_121 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_122 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_123 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_124 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_125 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_126 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_127 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_128 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_129 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_130 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_131 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_132 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_133 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_134 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_135 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_136 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_137 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_138 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_139 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_140 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_141 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_142 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_143 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_144 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_145 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_146 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_147 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_148 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_149 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_150 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_151 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_152 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_153 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_154 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_155 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_156 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_157 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_158 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_159 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_160 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_161 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_162 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_163 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_164 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_165 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_166 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_167 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_168 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_169 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_170 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_171 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_172 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_173 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_174 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_175 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_176 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_177 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_178 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_179 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_180 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_181 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_182 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_183 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_184 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_185 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_186 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_187 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_188 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_189 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_190 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_191 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_192 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_193 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_194 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_195 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_196 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_197 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_198 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_199 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_200 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_201 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_202 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_203 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_204 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_205 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_206 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_207 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_208 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_209 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_210 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_211 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_212 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_213 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_214 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_215 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_216 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_217 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_218 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_219 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_220 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_221 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_222 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_223 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_224 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_225 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_226 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_227 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_228 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_229 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_230 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_231 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_232 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_233 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_234 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_235 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_236 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_237 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_238 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_239 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_240 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _uncommonBits_T_241 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_22 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_23 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_24 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_25 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_26 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_27 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_28 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_29 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_30 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_31 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_32 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_33 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_34 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_35 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_36 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_37 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_38 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_39 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_40 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_41 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_42 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [9:0] _source_ok_uncommonBits_T_43 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [7:0] _source_ok_T_1 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_7 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_13 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_19 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_25 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_31 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_73 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_79 = io_in_a_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 8'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 8'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 8'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 8'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 8'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 8'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_61 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_67 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_103 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_109 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_115 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_121 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_127 = io_in_a_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_9 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_10 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_11 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_12 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_74 = _source_ok_T_73 == 8'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_13 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 8'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_14 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_15 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_16 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_17 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_18 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_18 = _source_ok_uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_110 = _source_ok_T_109 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_19 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_19 = _source_ok_uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_116 = _source_ok_T_115 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_118 = _source_ok_T_116; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_20 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_20 = _source_ok_uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_122 = _source_ok_T_121 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_124 = _source_ok_T_122; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_21 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_21 = _source_ok_uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_128 = _source_ok_T_127 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_130 = _source_ok_T_128; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_22 = _source_ok_T_132; // @[Parameters.scala:1138:31] wire _source_ok_T_133 = io_in_a_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_133; // @[Parameters.scala:1138:31] wire _source_ok_T_134 = io_in_a_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_134; // @[Parameters.scala:1138:31] wire _source_ok_T_135 = io_in_a_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_135; // @[Parameters.scala:1138:31] wire _source_ok_T_136 = io_in_a_bits_source_0 == 10'h200; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_136; // @[Parameters.scala:1138:31] wire _source_ok_T_137 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_156 = _source_ok_T_155 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_157 = _source_ok_T_156 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_158 = _source_ok_T_157 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_159 = _source_ok_T_158 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_160 = _source_ok_T_159 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_161 = _source_ok_T_160 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_161 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_72 = _uncommonBits_T_72[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_73 = _uncommonBits_T_73[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_74 = _uncommonBits_T_74[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_75 = _uncommonBits_T_75[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_76 = _uncommonBits_T_76[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_77 = _uncommonBits_T_77[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_80 = _uncommonBits_T_80[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_81 = _uncommonBits_T_81[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_82 = _uncommonBits_T_82[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_83 = _uncommonBits_T_83[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_84 = _uncommonBits_T_84[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_85 = _uncommonBits_T_85[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_86 = _uncommonBits_T_86[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_87 = _uncommonBits_T_87[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_89 = _uncommonBits_T_89[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_94 = _uncommonBits_T_94[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_95 = _uncommonBits_T_95[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_96 = _uncommonBits_T_96[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_97 = _uncommonBits_T_97[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_98 = _uncommonBits_T_98[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_99 = _uncommonBits_T_99[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_100 = _uncommonBits_T_100[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_101 = _uncommonBits_T_101[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_102 = _uncommonBits_T_102[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_103 = _uncommonBits_T_103[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_104 = _uncommonBits_T_104[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_105 = _uncommonBits_T_105[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_106 = _uncommonBits_T_106[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_107 = _uncommonBits_T_107[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_108 = _uncommonBits_T_108[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_109 = _uncommonBits_T_109[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_110 = _uncommonBits_T_110[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_111 = _uncommonBits_T_111[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_112 = _uncommonBits_T_112[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_113 = _uncommonBits_T_113[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_114 = _uncommonBits_T_114[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_115 = _uncommonBits_T_115[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_116 = _uncommonBits_T_116[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_117 = _uncommonBits_T_117[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_118 = _uncommonBits_T_118[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_119 = _uncommonBits_T_119[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_120 = _uncommonBits_T_120[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_121 = _uncommonBits_T_121[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_122 = _uncommonBits_T_122[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_123 = _uncommonBits_T_123[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_124 = _uncommonBits_T_124[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_125 = _uncommonBits_T_125[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_126 = _uncommonBits_T_126[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_127 = _uncommonBits_T_127[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_128 = _uncommonBits_T_128[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_129 = _uncommonBits_T_129[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_130 = _uncommonBits_T_130[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_131 = _uncommonBits_T_131[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_132 = _uncommonBits_T_132[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_133 = _uncommonBits_T_133[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_134 = _uncommonBits_T_134[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_135 = _uncommonBits_T_135[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_136 = _uncommonBits_T_136[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_137 = _uncommonBits_T_137[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_138 = _uncommonBits_T_138[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_139 = _uncommonBits_T_139[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_140 = _uncommonBits_T_140[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_141 = _uncommonBits_T_141[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_142 = _uncommonBits_T_142[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_143 = _uncommonBits_T_143[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_144 = _uncommonBits_T_144[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_145 = _uncommonBits_T_145[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_146 = _uncommonBits_T_146[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_147 = _uncommonBits_T_147[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_148 = _uncommonBits_T_148[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_149 = _uncommonBits_T_149[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_150 = _uncommonBits_T_150[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_151 = _uncommonBits_T_151[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_152 = _uncommonBits_T_152[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_153 = _uncommonBits_T_153[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_154 = _uncommonBits_T_154[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_155 = _uncommonBits_T_155[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_156 = _uncommonBits_T_156[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_157 = _uncommonBits_T_157[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_158 = _uncommonBits_T_158[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_159 = _uncommonBits_T_159[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_160 = _uncommonBits_T_160[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_161 = _uncommonBits_T_161[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_162 = _uncommonBits_T_162[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_163 = _uncommonBits_T_163[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_164 = _uncommonBits_T_164[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_165 = _uncommonBits_T_165[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_166 = _uncommonBits_T_166[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_167 = _uncommonBits_T_167[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_168 = _uncommonBits_T_168[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_169 = _uncommonBits_T_169[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_170 = _uncommonBits_T_170[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_171 = _uncommonBits_T_171[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_172 = _uncommonBits_T_172[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_173 = _uncommonBits_T_173[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_174 = _uncommonBits_T_174[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_175 = _uncommonBits_T_175[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_176 = _uncommonBits_T_176[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_177 = _uncommonBits_T_177[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_178 = _uncommonBits_T_178[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_179 = _uncommonBits_T_179[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_180 = _uncommonBits_T_180[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_181 = _uncommonBits_T_181[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_182 = _uncommonBits_T_182[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_183 = _uncommonBits_T_183[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_184 = _uncommonBits_T_184[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_185 = _uncommonBits_T_185[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_186 = _uncommonBits_T_186[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_187 = _uncommonBits_T_187[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_188 = _uncommonBits_T_188[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_189 = _uncommonBits_T_189[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_190 = _uncommonBits_T_190[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_191 = _uncommonBits_T_191[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_192 = _uncommonBits_T_192[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_193 = _uncommonBits_T_193[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_194 = _uncommonBits_T_194[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_195 = _uncommonBits_T_195[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_196 = _uncommonBits_T_196[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_197 = _uncommonBits_T_197[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_198 = _uncommonBits_T_198[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_199 = _uncommonBits_T_199[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_200 = _uncommonBits_T_200[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_201 = _uncommonBits_T_201[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_202 = _uncommonBits_T_202[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_203 = _uncommonBits_T_203[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_204 = _uncommonBits_T_204[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_205 = _uncommonBits_T_205[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_206 = _uncommonBits_T_206[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_207 = _uncommonBits_T_207[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_208 = _uncommonBits_T_208[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_209 = _uncommonBits_T_209[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_210 = _uncommonBits_T_210[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_211 = _uncommonBits_T_211[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_212 = _uncommonBits_T_212[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_213 = _uncommonBits_T_213[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_214 = _uncommonBits_T_214[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_215 = _uncommonBits_T_215[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_216 = _uncommonBits_T_216[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_217 = _uncommonBits_T_217[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_218 = _uncommonBits_T_218[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_219 = _uncommonBits_T_219[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_220 = _uncommonBits_T_220[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_221 = _uncommonBits_T_221[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_222 = _uncommonBits_T_222[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_223 = _uncommonBits_T_223[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_224 = _uncommonBits_T_224[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_225 = _uncommonBits_T_225[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_226 = _uncommonBits_T_226[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_227 = _uncommonBits_T_227[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_228 = _uncommonBits_T_228[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_229 = _uncommonBits_T_229[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_230 = _uncommonBits_T_230[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_231 = _uncommonBits_T_231[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_232 = _uncommonBits_T_232[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_233 = _uncommonBits_T_233[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_234 = _uncommonBits_T_234[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_235 = _uncommonBits_T_235[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_236 = _uncommonBits_T_236[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_237 = _uncommonBits_T_237[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_238 = _uncommonBits_T_238[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_239 = _uncommonBits_T_239[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_240 = _uncommonBits_T_240[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_241 = _uncommonBits_T_241[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_162 = io_in_d_bits_source_0 == 10'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_162; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_22 = _source_ok_uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [7:0] _source_ok_T_163 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_169 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_175 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_181 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_187 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_193 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_235 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire [7:0] _source_ok_T_241 = io_in_d_bits_source_0[9:2]; // @[Monitor.scala:36:7] wire _source_ok_T_164 = _source_ok_T_163 == 8'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_166 = _source_ok_T_164; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_168 = _source_ok_T_166; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_168; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_23 = _source_ok_uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_170 = _source_ok_T_169 == 8'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_172 = _source_ok_T_170; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_174 = _source_ok_T_172; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_174; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_24 = _source_ok_uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_176 = _source_ok_T_175 == 8'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_178 = _source_ok_T_176; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_180 = _source_ok_T_178; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_180; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_25 = _source_ok_uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_182 = _source_ok_T_181 == 8'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_184 = _source_ok_T_182; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_186 = _source_ok_T_184; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_186; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_26 = _source_ok_uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_188 = _source_ok_T_187 == 8'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_190 = _source_ok_T_188; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_192 = _source_ok_T_190; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_192; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_27 = _source_ok_uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_194 = _source_ok_T_193 == 8'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_196 = _source_ok_T_194; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_198 = _source_ok_T_196; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_198; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_28 = _source_ok_uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_199 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_205 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_211 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_217 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_223 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_229 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_247 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_253 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_259 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_265 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_271 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_277 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_283 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_289 = io_in_d_bits_source_0[9:5]; // @[Monitor.scala:36:7] wire _source_ok_T_200 = _source_ok_T_199 == 5'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_202 = _source_ok_T_200; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_204 = _source_ok_T_202; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_204; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_29 = _source_ok_uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_206 = _source_ok_T_205 == 5'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_208 = _source_ok_T_206; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_210 = _source_ok_T_208; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_210; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_30 = _source_ok_uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_212 = _source_ok_T_211 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_214 = _source_ok_T_212; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_216 = _source_ok_T_214; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_9 = _source_ok_T_216; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_31 = _source_ok_uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_218 = _source_ok_T_217 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_220 = _source_ok_T_218; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_222 = _source_ok_T_220; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_10 = _source_ok_T_222; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_32 = _source_ok_uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_224 = _source_ok_T_223 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_226 = _source_ok_T_224; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_228 = _source_ok_T_226; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_11 = _source_ok_T_228; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_33 = _source_ok_uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_230 = _source_ok_T_229 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_232 = _source_ok_T_230; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_234 = _source_ok_T_232; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_12 = _source_ok_T_234; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_34 = _source_ok_uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_236 = _source_ok_T_235 == 8'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_238 = _source_ok_T_236; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_240 = _source_ok_T_238; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_13 = _source_ok_T_240; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_35 = _source_ok_uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_242 = _source_ok_T_241 == 8'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_244 = _source_ok_T_242; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_246 = _source_ok_T_244; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_14 = _source_ok_T_246; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_36 = _source_ok_uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_248 = _source_ok_T_247 == 5'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_250 = _source_ok_T_248; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_252 = _source_ok_T_250; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_15 = _source_ok_T_252; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_37 = _source_ok_uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_254 = _source_ok_T_253 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_256 = _source_ok_T_254; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_258 = _source_ok_T_256; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_16 = _source_ok_T_258; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_38 = _source_ok_uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_260 = _source_ok_T_259 == 5'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_262 = _source_ok_T_260; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_264 = _source_ok_T_262; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_17 = _source_ok_T_264; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_39 = _source_ok_uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_266 = _source_ok_T_265 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_268 = _source_ok_T_266; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_270 = _source_ok_T_268; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_18 = _source_ok_T_270; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_40 = _source_ok_uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_272 = _source_ok_T_271 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_274 = _source_ok_T_272; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_276 = _source_ok_T_274; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_19 = _source_ok_T_276; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_41 = _source_ok_uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_278 = _source_ok_T_277 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_280 = _source_ok_T_278; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_282 = _source_ok_T_280; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_20 = _source_ok_T_282; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_42 = _source_ok_uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_284 = _source_ok_T_283 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_286 = _source_ok_T_284; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_288 = _source_ok_T_286; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_21 = _source_ok_T_288; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_43 = _source_ok_uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_290 = _source_ok_T_289 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_292 = _source_ok_T_290; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_294 = _source_ok_T_292; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_22 = _source_ok_T_294; // @[Parameters.scala:1138:31] wire _source_ok_T_295 = io_in_d_bits_source_0 == 10'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_295; // @[Parameters.scala:1138:31] wire _source_ok_T_296 = io_in_d_bits_source_0 == 10'h1E1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_296; // @[Parameters.scala:1138:31] wire _source_ok_T_297 = io_in_d_bits_source_0 == 10'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_297; // @[Parameters.scala:1138:31] wire _source_ok_T_298 = io_in_d_bits_source_0 == 10'h200; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_298; // @[Parameters.scala:1138:31] wire _source_ok_T_299 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_300 = _source_ok_T_299 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_301 = _source_ok_T_300 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_302 = _source_ok_T_301 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_303 = _source_ok_T_302 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_304 = _source_ok_T_303 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_305 = _source_ok_T_304 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_306 = _source_ok_T_305 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_307 = _source_ok_T_306 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_308 = _source_ok_T_307 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_309 = _source_ok_T_308 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_310 = _source_ok_T_309 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_311 = _source_ok_T_310 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_312 = _source_ok_T_311 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_313 = _source_ok_T_312 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_314 = _source_ok_T_313 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_315 = _source_ok_T_314 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_316 = _source_ok_T_315 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_317 = _source_ok_T_316 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_318 = _source_ok_T_317 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_319 = _source_ok_T_318 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_320 = _source_ok_T_319 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_321 = _source_ok_T_320 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_322 = _source_ok_T_321 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_323 = _source_ok_T_322 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_323 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _T_3103 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_3103; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_3103; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_3176 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_3176; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_3176; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_3176; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4103:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [512:0] a_set; // @[Monitor.scala:626:34] wire [512:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [2051:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4103:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [12:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [12:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [12:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [12:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [12:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [2051:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [2051:0] _a_opcode_lookup_T_6 = {2048'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [2051:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [12:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [12:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [12:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [12:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [12:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [4103:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4103:0] _a_size_lookup_T_6 = {4096'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [4103:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4103:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1023:0] _GEN_3 = 1024'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [1023:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1023:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_3029 = _T_3103 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_3029 ? _a_set_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_3029 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_3029 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [12:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8194:0] _a_opcodes_set_T_1 = {8191'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_3029 ? _a_opcodes_set_T_1[2051:0] : 2052'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [12:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [8195:0] _a_sizes_set_T_1 = {8191'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_3029 ? _a_sizes_set_T_1[4103:0] : 4104'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [512:0] d_clr; // @[Monitor.scala:664:34] wire [512:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [2051:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4103:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_3075 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1023:0] _GEN_5 = 1024'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [1023:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_3075 & ~d_release_ack ? _d_clr_wo_ready_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_3044 = _T_3176 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_3044 ? _d_clr_T[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [8206:0] _d_opcodes_clr_T_5 = 8207'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_3044 ? _d_opcodes_clr_T_5[2051:0] : 2052'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [8206:0] _d_sizes_clr_T_5 = 8207'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_3044 ? _d_sizes_clr_T_5[4103:0] : 4104'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [512:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [512:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [512:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [2051:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [2051:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [2051:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4103:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4103:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4103:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [512:0] inflight_1; // @[Monitor.scala:726:35] wire [512:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [2051:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [2051:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4103:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4103:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [2051:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [2051:0] _c_opcode_lookup_T_6 = {2048'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [2051:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[2051:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4103:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4103:0] _c_size_lookup_T_6 = {4096'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [4103:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4103:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [512:0] d_clr_1; // @[Monitor.scala:774:34] wire [512:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [2051:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4103:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_3147 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_3147 & d_release_ack_1 ? _d_clr_wo_ready_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35] wire _T_3129 = _T_3176 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_3129 ? _d_clr_T_1[512:0] : 513'h0; // @[OneHot.scala:58:35] wire [8206:0] _d_opcodes_clr_T_11 = 8207'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_3129 ? _d_opcodes_clr_T_11[2051:0] : 2052'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [8206:0] _d_sizes_clr_T_11 = 8207'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_3129 ? _d_sizes_clr_T_11[4103:0] : 4104'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 10'h0; // @[Monitor.scala:36:7, :795:113] wire [512:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [512:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [2051:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [2051:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4103:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4103:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Repeater.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{Decoupled, DecoupledIO} // A Repeater passes its input to its output, unless repeat is asserted. // When repeat is asserted, the Repeater copies the input and repeats it next cycle. class Repeater[T <: Data](gen: T) extends Module { override def desiredName = s"Repeater_${gen.typeName}" val io = IO( new Bundle { val repeat = Input(Bool()) val full = Output(Bool()) val enq = Flipped(Decoupled(gen.cloneType)) val deq = Decoupled(gen.cloneType) } ) val full = RegInit(false.B) val saved = Reg(gen.cloneType) // When !full, a repeater is pass-through io.deq.valid := io.enq.valid || full io.enq.ready := io.deq.ready && !full io.deq.bits := Mux(full, saved, io.enq.bits) io.full := full when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits } when (io.deq.fire && !io.repeat) { full := false.B } } object Repeater { def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = { val repeater = Module(new Repeater(chiselTypeOf(enq.bits))) repeater.io.repeat := repeat repeater.io.enq <> enq repeater.io.deq } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLWidthWidget32( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [7:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [7:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71] wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24] wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24] wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25] wire [1:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30] assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}] wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53] assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71] wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}] wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46] reg [1:0] count; // @[WidthWidget.scala:40:27] wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}] wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}] wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56] wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}] wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24] wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_2 = enable_2 | _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_3 = enable_3 | _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24] reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 2'h0; // @[WidthWidget.scala:105:26] count <= 2'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88] anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88] end always @(posedge) TLMonitor_2 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a29d256s8k1z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to Chisel by Andrew Waterman). Copyright 2019, 2020 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1)) }) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf) val notNaN_isInfOut = io.a.isInf || io.b.isInf val notNaN_isZeroOut = io.a.isZero || io.b.isZero val notNaN_signOut = io.a.sign ^ io.b.sign val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0) /*------------------------------------------------------------------------ *------------------------------------------------------------------------*/ io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc io.rawOut.isInf := notNaN_isInfOut io.rawOut.isZero := notNaN_isZeroOut io.rawOut.sExp := common_sExpOut io.rawOut.isNaN := io.a.isNaN || io.b.isNaN io.rawOut.sign := notNaN_signOut io.rawOut.sig := common_sigOut } class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(new RawFloat(expWidth, sigWidth)) val b = Input(new RawFloat(expWidth, sigWidth)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth)) mulFullRaw.io.a := io.a mulFullRaw.io.b := io.b io.invalidExc := mulFullRaw.io.invalidExc io.rawOut := mulFullRaw.io.rawOut io.rawOut.sig := { val sig = mulFullRaw.io.rawOut.sig Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR) } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val a = Input(UInt((expWidth + sigWidth + 1).W)) val b = Input(UInt((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(Bool()) val out = Output(UInt((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(UInt(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulRawFN = Module(new MulRawFN(expWidth, sigWidth)) mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a) mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulRawFN.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }
module MulRawFN_16( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_16 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module InputUnit_14( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_10, // @[InputUnit.scala:170:14] input io_out_credit_available_0_11, // @[InputUnit.scala:170:14] input io_out_credit_available_0_14, // @[InputUnit.scala:170:14] input io_out_credit_available_0_15, // @[InputUnit.scala:170:14] input io_out_credit_available_0_18, // @[InputUnit.scala:170:14] input io_out_credit_available_0_19, // @[InputUnit.scala:170:14] input io_out_credit_available_0_20, // @[InputUnit.scala:170:14] input io_out_credit_available_0_21, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [5:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [4:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [5:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [5:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [21:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [21:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_21; // @[InputUnit.scala:266:32] wire vcalloc_vals_20; // @[InputUnit.scala:266:32] wire vcalloc_vals_17; // @[InputUnit.scala:266:32] wire vcalloc_vals_16; // @[InputUnit.scala:266:32] wire vcalloc_vals_13; // @[InputUnit.scala:266:32] wire vcalloc_vals_12; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_12_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_13_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_16_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_17_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_20_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_21_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [21:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_12_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_13_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_16_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_17_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_20_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_21_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [4:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_10_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_10_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_10_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_11_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_11_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_11_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_12_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_12_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_12_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_12_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_13_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_13_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_13_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_13_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_14_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_14_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_14_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_15_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_15_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_15_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_16_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_16_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_16_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_16_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_17_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_17_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_17_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_17_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_18_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_18_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_18_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_19_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_19_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_19_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_20_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_20_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_20_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_20_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_21_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_21_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_21_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_21_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_12_g; // @[InputUnit.scala:192:19] reg states_12_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_12_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [3:0] states_12_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_12_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_12_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_12_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_12_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_13_g; // @[InputUnit.scala:192:19] reg states_13_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_13_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [3:0] states_13_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_13_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_13_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_13_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_13_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_16_g; // @[InputUnit.scala:192:19] reg states_16_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_16_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [3:0] states_16_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_16_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_16_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_16_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_16_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_17_g; // @[InputUnit.scala:192:19] reg states_17_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_17_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [3:0] states_17_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_17_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_17_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_17_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_17_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_20_g; // @[InputUnit.scala:192:19] reg states_20_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_20_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [3:0] states_20_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_20_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_20_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_20_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_20_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_21_g; // @[InputUnit.scala:192:19] reg states_21_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_21_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [3:0] states_21_flow_vnet_id; // @[InputUnit.scala:192:19] reg [5:0] states_21_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_21_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [5:0] states_21_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_21_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_12_valid = states_12_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_13_valid = states_13_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_16_valid = states_16_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_17_valid = states_17_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_20_valid = states_20_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_21_valid = states_21_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [21:0] mask; // @[InputUnit.scala:250:21] wire [21:0] _vcalloc_filter_T_3 = {vcalloc_vals_21, vcalloc_vals_20, 2'h0, vcalloc_vals_17, vcalloc_vals_16, 2'h0, vcalloc_vals_13, vcalloc_vals_12, 12'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [43:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 44'h1 : _vcalloc_filter_T_3[1] ? 44'h2 : _vcalloc_filter_T_3[2] ? 44'h4 : _vcalloc_filter_T_3[3] ? 44'h8 : _vcalloc_filter_T_3[4] ? 44'h10 : _vcalloc_filter_T_3[5] ? 44'h20 : _vcalloc_filter_T_3[6] ? 44'h40 : _vcalloc_filter_T_3[7] ? 44'h80 : _vcalloc_filter_T_3[8] ? 44'h100 : _vcalloc_filter_T_3[9] ? 44'h200 : _vcalloc_filter_T_3[10] ? 44'h400 : _vcalloc_filter_T_3[11] ? 44'h800 : _vcalloc_filter_T_3[12] ? 44'h1000 : _vcalloc_filter_T_3[13] ? 44'h2000 : _vcalloc_filter_T_3[14] ? 44'h4000 : _vcalloc_filter_T_3[15] ? 44'h8000 : _vcalloc_filter_T_3[16] ? 44'h10000 : _vcalloc_filter_T_3[17] ? 44'h20000 : _vcalloc_filter_T_3[18] ? 44'h40000 : _vcalloc_filter_T_3[19] ? 44'h80000 : _vcalloc_filter_T_3[20] ? 44'h100000 : _vcalloc_filter_T_3[21] ? 44'h200000 : vcalloc_vals_12 ? 44'h400000000 : vcalloc_vals_13 ? 44'h800000000 : vcalloc_vals_16 ? 44'h4000000000 : vcalloc_vals_17 ? 44'h8000000000 : vcalloc_vals_20 ? 44'h40000000000 : {vcalloc_vals_21, 43'h0}; // @[OneHot.scala:85:71] wire [21:0] vcalloc_sel = vcalloc_filter[21:0] | vcalloc_filter[43:22]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_12 | vcalloc_vals_13 | vcalloc_vals_16 | vcalloc_vals_17 | vcalloc_vals_20 | vcalloc_vals_21; // @[package.scala:81:59] assign vcalloc_vals_12 = states_12_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_13 = states_13_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_16 = states_16_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_17 = states_17_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_20 = states_20_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_21 = states_21_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[12]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[13]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[16]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[17]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[20]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[21]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File Directory.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import MetaData._ import chisel3.experimental.dataview._ import freechips.rocketchip.util.DescribedSRAM class DirectoryEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val dirty = Bool() // true => TRUNK or TIP val state = UInt(params.stateBits.W) val clients = UInt(params.clientBits.W) val tag = UInt(params.tagBits.W) } class DirectoryWrite(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val way = UInt(params.wayBits.W) val data = new DirectoryEntry(params) } class DirectoryRead(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) } class DirectoryResult(params: InclusiveCacheParameters) extends DirectoryEntry(params) { val hit = Bool() val way = UInt(params.wayBits.W) } class Directory(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val write = Flipped(Decoupled(new DirectoryWrite(params))) val read = Flipped(Valid(new DirectoryRead(params))) // sees same-cycle write val result = Valid(new DirectoryResult(params)) val ready = Bool() // reset complete; can enable access }) val codeBits = new DirectoryEntry(params).getWidth val cc_dir = DescribedSRAM( name = "cc_dir", desc = "Directory RAM", size = params.cache.sets, data = Vec(params.cache.ways, UInt(codeBits.W)) ) val write = Queue(io.write, 1) // must inspect contents => max size 1 // a flow Q creates a WaR hazard... this MIGHT not cause a problem // a pipe Q causes combinational loop through the scheduler // Wiping the Directory with 0s on reset has ultimate priority val wipeCount = RegInit(0.U((params.setBits + 1).W)) val wipeOff = RegNext(false.B, true.B) // don't wipe tags during reset val wipeDone = wipeCount(params.setBits) val wipeSet = wipeCount(params.setBits - 1,0) io.ready := wipeDone when (!wipeDone && !wipeOff) { wipeCount := wipeCount + 1.U } assert (wipeDone || !io.read.valid) // Be explicit for dumb 1-port inference val ren = io.read.valid val wen = (!wipeDone && !wipeOff) || write.valid assert (!io.read.valid || wipeDone) require (codeBits <= 256) write.ready := !io.read.valid when (!ren && wen) { cc_dir.write( Mux(wipeDone, write.bits.set, wipeSet), VecInit.fill(params.cache.ways) { Mux(wipeDone, write.bits.data.asUInt, 0.U) }, UIntToOH(write.bits.way, params.cache.ways).asBools.map(_ || !wipeDone)) } val ren1 = RegInit(false.B) val ren2 = if (params.micro.dirReg) RegInit(false.B) else ren1 ren2 := ren1 ren1 := ren val bypass_valid = params.dirReg(write.valid) val bypass = params.dirReg(write.bits, ren1 && write.valid) val regout = params.dirReg(cc_dir.read(io.read.bits.set, ren), ren1) val tag = params.dirReg(RegEnable(io.read.bits.tag, ren), ren1) val set = params.dirReg(RegEnable(io.read.bits.set, ren), ren1) // Compute the victim way in case of an evicition val victimLFSR = random.LFSR(width = 16, params.dirReg(ren))(InclusiveCacheParameters.lfsrBits-1, 0) val victimSums = Seq.tabulate(params.cache.ways) { i => ((1 << InclusiveCacheParameters.lfsrBits)*i / params.cache.ways).U } val victimLTE = Cat(victimSums.map { _ <= victimLFSR }.reverse) val victimSimp = Cat(0.U(1.W), victimLTE(params.cache.ways-1, 1), 1.U(1.W)) val victimWayOH = victimSimp(params.cache.ways-1,0) & ~(victimSimp >> 1) val victimWay = OHToUInt(victimWayOH) assert (!ren2 || victimLTE(0) === 1.U) assert (!ren2 || ((victimSimp >> 1) & ~victimSimp) === 0.U) // monotone assert (!ren2 || PopCount(victimWayOH) === 1.U) val setQuash = bypass_valid && bypass.set === set val tagMatch = bypass.data.tag === tag val wayMatch = bypass.way === victimWay val ways = regout.map(d => d.asTypeOf(new DirectoryEntry(params))) val hits = Cat(ways.zipWithIndex.map { case (w, i) => w.tag === tag && w.state =/= INVALID && (!setQuash || i.U =/= bypass.way) }.reverse) val hit = hits.orR io.result.valid := ren2 io.result.bits.viewAsSupertype(chiselTypeOf(bypass.data)) := Mux(hit, Mux1H(hits, ways), Mux(setQuash && (tagMatch || wayMatch), bypass.data, Mux1H(victimWayOH, ways))) io.result.bits.hit := hit || (setQuash && tagMatch && bypass.data.state =/= INVALID) io.result.bits.way := Mux(hit, OHToUInt(hits), Mux(setQuash && tagMatch, bypass.way, victimWay)) params.ccover(ren2 && setQuash && tagMatch, "DIRECTORY_HIT_BYPASS", "Bypassing write to a directory hit") params.ccover(ren2 && setQuash && !tagMatch && wayMatch, "DIRECTORY_EVICT_BYPASS", "Bypassing a write to a directory eviction") def json: String = s"""{"clients":${params.clientBits},"mem":"${cc_dir.pathName}","clean":"${wipeDone.pathName}"}""" } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } }
module Directory( // @[Directory.scala:56:7] input clock, // @[Directory.scala:56:7] input reset, // @[Directory.scala:56:7] output io_write_ready, // @[Directory.scala:58:14] input io_write_valid, // @[Directory.scala:58:14] input [9:0] io_write_bits_set, // @[Directory.scala:58:14] input [2:0] io_write_bits_way, // @[Directory.scala:58:14] input io_write_bits_data_dirty, // @[Directory.scala:58:14] input [1:0] io_write_bits_data_state, // @[Directory.scala:58:14] input [1:0] io_write_bits_data_clients, // @[Directory.scala:58:14] input [12:0] io_write_bits_data_tag, // @[Directory.scala:58:14] input io_read_valid, // @[Directory.scala:58:14] input [9:0] io_read_bits_set, // @[Directory.scala:58:14] input [12:0] io_read_bits_tag, // @[Directory.scala:58:14] output io_result_bits_dirty, // @[Directory.scala:58:14] output [1:0] io_result_bits_state, // @[Directory.scala:58:14] output [1:0] io_result_bits_clients, // @[Directory.scala:58:14] output [12:0] io_result_bits_tag, // @[Directory.scala:58:14] output io_result_bits_hit, // @[Directory.scala:58:14] output [2:0] io_result_bits_way, // @[Directory.scala:58:14] output io_ready // @[Directory.scala:58:14] ); wire cc_dir_MPORT_mask_7; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_6; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_5; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_4; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_3; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_2; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_1; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_0; // @[Directory.scala:100:65] wire [17:0] _T_31; // @[Directory.scala:99:44] wire [17:0] _T_29; // @[Directory.scala:99:44] wire [17:0] _T_27; // @[Directory.scala:99:44] wire [17:0] _T_25; // @[Directory.scala:99:44] wire [17:0] _T_23; // @[Directory.scala:99:44] wire [17:0] _T_21; // @[Directory.scala:99:44] wire [17:0] _T_19; // @[Directory.scala:99:44] wire [17:0] _T_17; // @[Directory.scala:99:44] wire [9:0] cc_dir_MPORT_addr; // @[Directory.scala:98:10] wire cc_dir_MPORT_en; // @[Directory.scala:96:14] wire _victimLFSR_prng_io_out_0; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_1; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_2; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_3; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_4; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_5; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_6; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_7; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_8; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_9; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_10; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_11; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_12; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_13; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_14; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_15; // @[PRNG.scala:91:22] wire _write_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [9:0] _write_q_io_deq_bits_set; // @[Decoupled.scala:362:21] wire [2:0] _write_q_io_deq_bits_way; // @[Decoupled.scala:362:21] wire _write_q_io_deq_bits_data_dirty; // @[Decoupled.scala:362:21] wire [1:0] _write_q_io_deq_bits_data_state; // @[Decoupled.scala:362:21] wire [1:0] _write_q_io_deq_bits_data_clients; // @[Decoupled.scala:362:21] wire [12:0] _write_q_io_deq_bits_data_tag; // @[Decoupled.scala:362:21] wire [143:0] _cc_dir_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_write_valid_0 = io_write_valid; // @[Directory.scala:56:7] wire [9:0] io_write_bits_set_0 = io_write_bits_set; // @[Directory.scala:56:7] wire [2:0] io_write_bits_way_0 = io_write_bits_way; // @[Directory.scala:56:7] wire io_write_bits_data_dirty_0 = io_write_bits_data_dirty; // @[Directory.scala:56:7] wire [1:0] io_write_bits_data_state_0 = io_write_bits_data_state; // @[Directory.scala:56:7] wire [1:0] io_write_bits_data_clients_0 = io_write_bits_data_clients; // @[Directory.scala:56:7] wire [12:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[Directory.scala:56:7] wire io_read_valid_0 = io_read_valid; // @[Directory.scala:56:7] wire [9:0] io_read_bits_set_0 = io_read_bits_set; // @[Directory.scala:56:7] wire [12:0] io_read_bits_tag_0 = io_read_bits_tag; // @[Directory.scala:56:7] wire _victimLTE_T = 1'h1; // @[Directory.scala:117:43] wire [9:0] _regout_WIRE = io_read_bits_set_0; // @[Directory.scala:56:7, :110:41] wire _view__T_139_dirty; // @[Directory.scala:136:67] wire [1:0] _view__T_139_state; // @[Directory.scala:136:67] wire [1:0] _view__T_139_clients; // @[Directory.scala:136:67] wire [12:0] _view__T_139_tag; // @[Directory.scala:136:67] wire _io_result_bits_hit_T_3; // @[Directory.scala:137:29] wire [2:0] _io_result_bits_way_T_9; // @[Directory.scala:138:28] wire wipeDone; // @[Directory.scala:81:27] wire io_write_ready_0; // @[Directory.scala:56:7] wire io_result_bits_dirty_0; // @[Directory.scala:56:7] wire [1:0] io_result_bits_state_0; // @[Directory.scala:56:7] wire [1:0] io_result_bits_clients_0; // @[Directory.scala:56:7] wire [12:0] io_result_bits_tag_0; // @[Directory.scala:56:7] wire io_result_bits_hit_0; // @[Directory.scala:56:7] wire [2:0] io_result_bits_way_0; // @[Directory.scala:56:7] wire io_result_valid; // @[Directory.scala:56:7] wire io_ready_0; // @[Directory.scala:56:7] wire [17:0] _ways_WIRE = _cc_dir_RW0_rdata[17:0]; // @[DescribedSRAM.scala:17:26] wire [17:0] _ways_WIRE_1 = _cc_dir_RW0_rdata[35:18]; // @[DescribedSRAM.scala:17:26] wire [17:0] _ways_WIRE_2 = _cc_dir_RW0_rdata[53:36]; // @[DescribedSRAM.scala:17:26] wire [17:0] _ways_WIRE_3 = _cc_dir_RW0_rdata[71:54]; // @[DescribedSRAM.scala:17:26] wire [17:0] _ways_WIRE_4 = _cc_dir_RW0_rdata[89:72]; // @[DescribedSRAM.scala:17:26] wire [17:0] _ways_WIRE_5 = _cc_dir_RW0_rdata[107:90]; // @[DescribedSRAM.scala:17:26] wire [17:0] _ways_WIRE_6 = _cc_dir_RW0_rdata[125:108]; // @[DescribedSRAM.scala:17:26] wire [17:0] _ways_WIRE_7 = _cc_dir_RW0_rdata[143:126]; // @[DescribedSRAM.scala:17:26] reg [10:0] wipeCount; // @[Directory.scala:79:26] reg wipeOff; // @[Directory.scala:80:24] assign wipeDone = wipeCount[10]; // @[Directory.scala:79:26, :81:27] assign io_ready_0 = wipeDone; // @[Directory.scala:56:7, :81:27] wire [9:0] wipeSet = wipeCount[9:0]; // @[Directory.scala:79:26, :82:26] wire _wen_T_1 = ~wipeOff; // @[Directory.scala:80:24, :85:22, :90:27] wire [11:0] _wipeCount_T = {1'h0, wipeCount} + 12'h1; // @[Directory.scala:79:26, :85:57] wire [10:0] _wipeCount_T_1 = _wipeCount_T[10:0]; // @[Directory.scala:85:57] wire _wen_T = ~wipeDone; // @[Directory.scala:81:27, :85:9, :90:14] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Directory.scala:90:{14,24,27}] wire wen = _wen_T_2 | _write_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _q_io_deq_ready_T = ~io_read_valid_0; // @[Directory.scala:56:7, :86:23, :95:18] assign cc_dir_MPORT_en = ~io_read_valid_0 & wen; // @[Directory.scala:56:7, :86:23, :90:37, :96:14] assign cc_dir_MPORT_addr = wipeDone ? _write_q_io_deq_bits_set : wipeSet; // @[Decoupled.scala:362:21] wire [14:0] _GEN = {_write_q_io_deq_bits_data_clients, _write_q_io_deq_bits_data_tag}; // @[Decoupled.scala:362:21] wire [14:0] lo; // @[Directory.scala:99:71] assign lo = _GEN; // @[Directory.scala:99:71] wire [14:0] lo_1; // @[Directory.scala:99:71] assign lo_1 = _GEN; // @[Directory.scala:99:71] wire [14:0] lo_2; // @[Directory.scala:99:71] assign lo_2 = _GEN; // @[Directory.scala:99:71] wire [14:0] lo_3; // @[Directory.scala:99:71] assign lo_3 = _GEN; // @[Directory.scala:99:71] wire [14:0] lo_4; // @[Directory.scala:99:71] assign lo_4 = _GEN; // @[Directory.scala:99:71] wire [14:0] lo_5; // @[Directory.scala:99:71] assign lo_5 = _GEN; // @[Directory.scala:99:71] wire [14:0] lo_6; // @[Directory.scala:99:71] assign lo_6 = _GEN; // @[Directory.scala:99:71] wire [14:0] lo_7; // @[Directory.scala:99:71] assign lo_7 = _GEN; // @[Directory.scala:99:71] wire [2:0] _GEN_0 = {_write_q_io_deq_bits_data_dirty, _write_q_io_deq_bits_data_state}; // @[Decoupled.scala:362:21] wire [2:0] hi; // @[Directory.scala:99:71] assign hi = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_1; // @[Directory.scala:99:71] assign hi_1 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_2; // @[Directory.scala:99:71] assign hi_2 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_3; // @[Directory.scala:99:71] assign hi_3 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_4; // @[Directory.scala:99:71] assign hi_4 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_5; // @[Directory.scala:99:71] assign hi_5 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_6; // @[Directory.scala:99:71] assign hi_6 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_7; // @[Directory.scala:99:71] assign hi_7 = _GEN_0; // @[Directory.scala:99:71] assign _T_17 = wipeDone ? {hi, lo} : 18'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_19 = wipeDone ? {hi_1, lo_1} : 18'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_21 = wipeDone ? {hi_2, lo_2} : 18'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_23 = wipeDone ? {hi_3, lo_3} : 18'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_25 = wipeDone ? {hi_4, lo_4} : 18'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_27 = wipeDone ? {hi_5, lo_5} : 18'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_29 = wipeDone ? {hi_6, lo_6} : 18'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_31 = wipeDone ? {hi_7, lo_7} : 18'h0; // @[Directory.scala:81:27, :99:{44,71}] wire [2:0] shiftAmount; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_0 = shiftAmount == 3'h0 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_1 = shiftAmount == 3'h1 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_2 = shiftAmount == 3'h2 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_3 = shiftAmount == 3'h3 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_4 = shiftAmount == 3'h4 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_5 = shiftAmount == 3'h5 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_6 = shiftAmount == 3'h6 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_7 = (&shiftAmount) | ~wipeDone; // @[OneHot.scala:64:49] reg ren1; // @[Directory.scala:103:21] assign io_result_valid = ren1; // @[Directory.scala:56:7, :103:21] wire _bypass_T = ren1 & _write_q_io_deq_valid; // @[Decoupled.scala:362:21] reg [12:0] tag; // @[Directory.scala:111:36] reg [9:0] set; // @[Directory.scala:112:36] wire [1:0] victimLFSR_lo_lo_lo = {_victimLFSR_prng_io_out_1, _victimLFSR_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_lo_lo_hi = {_victimLFSR_prng_io_out_3, _victimLFSR_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_lo_lo = {victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_lo_hi_lo = {_victimLFSR_prng_io_out_5, _victimLFSR_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_lo_hi_hi = {_victimLFSR_prng_io_out_7, _victimLFSR_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_lo_hi = {victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] victimLFSR_lo = {victimLFSR_lo_hi, victimLFSR_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_hi_lo_lo = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_hi_lo_hi = {_victimLFSR_prng_io_out_11, _victimLFSR_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_hi_lo = {victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_hi_hi_lo = {_victimLFSR_prng_io_out_13, _victimLFSR_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_hi_hi_hi = {_victimLFSR_prng_io_out_15, _victimLFSR_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_hi_hi = {victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] victimLFSR_hi = {victimLFSR_hi_hi, victimLFSR_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] _victimLFSR_T = {victimLFSR_hi, victimLFSR_lo}; // @[PRNG.scala:95:17] wire [9:0] victimLFSR = _victimLFSR_T[9:0]; // @[PRNG.scala:95:17] wire _victimLTE_T_1 = |(victimLFSR[9:7]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_2 = |(victimLFSR[9:8]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_3 = victimLFSR > 10'h17F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_4 = victimLFSR[9]; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_5 = victimLFSR > 10'h27F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_6 = victimLFSR > 10'h2FF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_7 = victimLFSR > 10'h37F; // @[Directory.scala:115:63, :117:43] wire [1:0] victimLTE_lo_lo = {_victimLTE_T_1, 1'h1}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_lo_hi = {_victimLTE_T_3, _victimLTE_T_2}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_lo = {victimLTE_lo_hi, victimLTE_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_hi_lo = {_victimLTE_T_5, _victimLTE_T_4}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_hi_hi = {_victimLTE_T_7, _victimLTE_T_6}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_hi = {victimLTE_hi_hi, victimLTE_hi_lo}; // @[Directory.scala:117:23] wire [7:0] victimLTE = {victimLTE_hi, victimLTE_lo}; // @[Directory.scala:117:23] wire [6:0] _victimSimp_T = victimLTE[7:1]; // @[Directory.scala:117:23, :118:43] wire [7:0] victimSimp_hi = {1'h0, _victimSimp_T}; // @[Directory.scala:118:{23,43}] wire [8:0] victimSimp = {victimSimp_hi, 1'h1}; // @[Directory.scala:118:23] wire [7:0] _victimWayOH_T = victimSimp[7:0]; // @[Directory.scala:118:23, :119:31] wire [7:0] _victimWayOH_T_1 = victimSimp[8:1]; // @[Directory.scala:118:23, :119:70] wire [7:0] _victimWayOH_T_2 = ~_victimWayOH_T_1; // @[Directory.scala:119:{57,70}] wire [7:0] victimWayOH = _victimWayOH_T & _victimWayOH_T_2; // @[Directory.scala:119:{31,55,57}] wire [3:0] victimWay_hi = victimWayOH[7:4]; // @[OneHot.scala:30:18] wire [3:0] victimWay_lo = victimWayOH[3:0]; // @[OneHot.scala:31:18] wire _victimWay_T = |victimWay_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _victimWay_T_1 = victimWay_hi | victimWay_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] victimWay_hi_1 = _victimWay_T_1[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] victimWay_lo_1 = _victimWay_T_1[1:0]; // @[OneHot.scala:31:18, :32:28] wire _victimWay_T_2 = |victimWay_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _victimWay_T_3 = victimWay_hi_1 | victimWay_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _victimWay_T_4 = _victimWay_T_3[1]; // @[OneHot.scala:32:28] wire [1:0] _victimWay_T_5 = {_victimWay_T_2, _victimWay_T_4}; // @[OneHot.scala:32:{10,14}] wire [2:0] victimWay = {_victimWay_T, _victimWay_T_5}; // @[OneHot.scala:32:{10,14}] wire _view__T_70 = victimWayOH[0]; // @[Mux.scala:32:36] wire _view__T_71 = victimWayOH[1]; // @[Mux.scala:32:36] wire _view__T_72 = victimWayOH[2]; // @[Mux.scala:32:36] wire _view__T_73 = victimWayOH[3]; // @[Mux.scala:32:36] wire _view__T_74 = victimWayOH[4]; // @[Mux.scala:32:36] wire _view__T_75 = victimWayOH[5]; // @[Mux.scala:32:36] wire _view__T_76 = victimWayOH[6]; // @[Mux.scala:32:36] wire _view__T_77 = victimWayOH[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_382( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_126 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module MSHR_4( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 7'h40; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 7'h40; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]